2-Port PCI-to-PCI Bridge REVISION 1.00 2380 Bering Drive, Jo
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PI7C8152
2-Port PCI-to-PCI Bridge
REVISION 1.00
2380 Bering Drive, Jose, 95131 Telephone: 1-877-PERICOM, (1-877-737-4266) Fax: 408-435-1100 Email: solutions@pericom.com Internet: http://www.pericom.com
PI7C8152 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
LIFE SUPPORT POLICY Pericom Semiconductor Corporation's products authorized critical components life support devices systems unless specific written agreement pertaining such intended executed between manufacturer officer PSC. Life support devices system devices systems which: intended surgical implant into body Support sustain life whose failure perform, when properly used accordance with instructions provided labeling, reasonably expected result significant injury user. critical component component life support device system whose failure perform reasonably expected cause failure life support device system, affect safety effectiveness. Pericom Semiconductor Corporation reserves right make changes products specifications time, without notice, order improve design performance supply best possible product. Pericom Semiconductor does assume responsibility circuitry described other than circuitry embodied Pericom Semiconductor product. Company makes representations that circuitry described herein free from patent infringement other rights third parties which result from use. license granted implication otherwise under patent, patent rights other rights, Pericom Semiconductor Corporation. other trademarks their respective companies.
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REVISION HISTORY
Date 8/28/02 10/3/02 11/1/02 Revision Number 0.01 0.02 1.00 Description First draft datasheet Corrections First release datasheet Added further descriptions SCAN_EN SCAN_TM_L Removed values Power Consumption Revised values delay between P_CLK S_CLKOUT
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TABLE CONTENTS
INTRODUCTION SIGNAL DEFINITIONS SIGNAL TYPES SIGNALS 2.2.1 PRIMARY INTERFACE SIGNALS 2.2.3 CLOCK SIGNALS 2.2.4 MISCELLANEOUS SIGNALS. 2.2.5 POWER GROUND. LIST 160-PIN MQFP. OPERATION TYPES TRANSACTIONS. SINGLE ADDRESS PHASE DUAL ADDRESS PHASE DEVICE SELECT (DEVSEL_L) GENERATION DATA PHASE WRITE TRANSACTIONS 3.6.1 MEMORY WRITE TRANSACTIONS.10 3.6.2 MEMORY WRITE INVALIDATE 3.6.3 DELAYED WRITE TRANSACTIONS.11 3.6.4 WRITE TRANSACTION ADDRESS BOUNDARIES.12 3.6.5 BUFFERING MULTIPLE WRITE TRANSACTIONS.12 3.6.6 FAST BACK-TO-BACK WRITE TRANSACTIONS READ TRANSACTIONS 3.7.1 PREFETCHABLE READ TRANSACTIONS.13 3.7.2 NON-PREFETCHABLE READ TRANSACTIONS.13 3.7.3 READ PREFETCH ADDRESS BOUNDARIES 3.7.4 DELAYED READ REQUESTS 3.7.5 DELAYED READ COMPLETION TARGET 3.7.6 DELAYED READ COMPLETION INITIATOR BUS.15 3.7.7 FAST BACK-TO-BACK READ TRANSACTION CONFIGURATION TRANSACTIONS 3.8.1 TYPE ACCESS PI7C8152 3.8.2 TYPE TYPE CONVERSION 3.8.3 TYPE TYPE FORWARDING.19 3.8.4 SPECIAL CYCLES.20 TRANSACTION TERMINATION 3.9.1 MASTER TERMINATION INITIATED PI7C8152.21 3.9.2 MASTER ABORT RECEIVED PI7C8152.22 3.9.3 TARGET TERMINATION RECEIVED PI7C8152 3.9.4 TARGET TERMINATION INITIATED PI7C8152 ADDRESS DECODING.26 ADDRESS RANGES ADDRESS DECODING.27 4.2.1 BASE LIMIT ADDRESS REGISTER.27 4.2.2 MODE.28 MEMORY ADDRESS DECODING 4.3.1 MEMORY-MAPPED BASE LIMIT ADDRESS REGISTERS 4.3.2 PREFETCHABLE MEMORY BASE LIMIT ADDRESS REGISTERS October 2002 Revision 1.00
PI7C8152 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION SUPPORT 4.4.1 MODE 4.4.2 SNOOP MODE.32 TRANSACTION ORDERING.32 TRANSACTIONS GOVERNED ORDERING RULES GENERAL ORDERING GUIDELINES ORDERING RULES DATA SYNCHRONIZATION
ERROR HANDLING.35 ADDRESS PARITY ERRORS DATA PARITY ERRORS 6.2.1 CONFIGURATION WRITE TRANSACTIONS CONFIGURATION SPACE.37 6.2.2 READ TRANSACTIONS 6.2.3 DELAYED WRITE TRANSACTIONS.38 6.2.4 POSTED WRITE TRANSACTIONS.40 DATA PARITY ERROR REPORTING SUMMARY.42 SYSTEM ERROR (SERR_L) REPORTING.45
EXCLUSIVE ACCESS CONCURRENT LOCKS ACQUIRING EXCLUSIVE ACCESS ACROSS PI7C8152 7.2.1 LOCKED TRANSACTIONS DOWNSTREAM DIRECTION 7.2.2 LOCKED TRANSACTION UPSTREAM DIRECTION ENDING EXCLUSIVE ACCESS.48
ARBITRATION.49 PRIMARY ARBITRATION SECONDARY ARBITRATION 8.2.1 SECONDARY ARBITRATION USING INTERNAL ARBITER.50 8.2.2 PREEMPTION 8.2.3 SECONDARY ARBITRATION USING EXTERNAL ARBITER.52 8.2.4 PARKING.52
CLOCKS PRIMARY CLOCK INPUTS.53 SECONDARY CLOCK OUTPUTS POWER MANAGEMENT RESET PRIMARY INTERFACE RESET SECONDARY INTERFACE RESET.54 CHIP RESET.55 CONFIGURATION REGISTERS.55
11.1 11.2 11.3
12.1 CONFIGURATION REGISTER 12.1.1 VENDOR REGISTER OFFSET 00h.56 12.1.2 DEVICE REGISTER OFFSET 12.1.3 COMMAND REGISTER OFFSET 04h.56 12.1.4 PRIMARY STATUS REGISTER OFFSET 12.1.5 REVISION REGISTER OFFSET 12.1.6 CLASS CODE REGISTER OFFSET 08h.58 October 2002 Revision 1.00
PI7C8152 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION 12.1.7 CACHE LINE SIZE REGISTER OFFSET 12.1.8 PRIMARY LATENCY TIMER REGISTER OFFSET 12.1.9 HEADER TYPE REGISTER OFFSET 0Ch.59 12.1.10 PRIMARY NUMBER REGISTSER OFFSET 18h.59 12.1.11 SECONDARY NUMBER REGISTER OFFSET 12.1.12 SUBORDINATE NUMBER REGISTER OFFSET 18h.59 12.1.13 SECONDARY LATENCY TIMER REGISTER OFFSET 12.1.14 BASE ADDRESS REGISTER OFFSET 1Ch.60 12.1.15 LIMIT ADDRESS REGISTER OFFSET 12.1.16 SECONDARY STATUS REGISTER OFFSET 1Ch.60 12.1.17 MEMORY BASE ADDRESS REGISTER OFFSET 12.1.18 MEMORY LIMIT ADDRESS REGISTER OFFSET 20h.61 12.1.19 PEFETCHABLE MEMORY BASE ADDRESS REGISTER OFFSET 12.1.20 PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER OFFSET 12.1.21 PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER OFFSET 12.1.22 PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER OFFSET 2Ch.62 12.1.23 BASE ADDRESS UPPER 16-BITS REGISTER OFFSET 12.1.24 LIMIT ADDRESS UPPER 16-BITS REGISTER OFFSET 30h.63 12.1.25 POINTER REGISTER OFFSET 34h.63 12.1.26 INTERRUPT REGISTER OFFSET 3Ch.63 12.1.27 BRIDGE CONTROL REGISTER OFFSET 12.1.28 DIAGNOSTIC CHIP CONTROL REGISTER OFFSET 40h.65 12.1.29 ARBITER CONTROL REGISTER OFFSET 12.1.30 EXTENDED CHIP CONTROL REGISTER OFFSET 48h.66 12.1.31 SECONDARY ARBITER PREEMPTION CONTROL REGISTER OFFSET 12.1.32 P_SERR_L EVENT DISABLE REGISTER OFFSET 64h.67 12.1.33 SECONDARY CLOCK CONTROL REGISTER OFFSET 12.1.34 P_SERR_L STATUS REGISTER OFFSET 12.1.35 PORT OPTION REGISTER OFFSET 74h.69 12.1.36 RETRY COUNTER REGISTER OFFSET 12.1.37 PRIMARY MASTER TIMEOUT COUNTER OFFSET 12.1.38 SECONDARY MASTER TIMEOUT COUNTER OFFSET 12.1.39 CAPABILITY REGISTER OFFSET DCh.71 12.1.40 NEXT ITEM POINTER REGISTER OFFSET 12.1.41 POWER MANAGEMENT CAPABILITIES REGISTER OFFSET 12.1.42 POWER MANAGEMENT DATA REGISTER OFFSET E0h.71 12.1.43 SUPPORT EXTENSIONS REGISER OFFSET BRIDGE BEHAVIOR.72 13.1 BRIDGE ACTIONS VARIOUS CYCLE TYPES 13.2 ABNORMAL TERMINATION (INITIATED BRIDGE MASTER).73 13.2.1 MASTER ABORT.73 13.2.2 PARITY ERROR REPORTING 13.2.3 REPORTING PARITY ERRORS 13.2.4 SECONDARY IDSEL MAPPING 14.1 14.2 14.3 14.4 ELECTRICAL TIMING SPECIFICATIONS MAXIMUM RATINGS SPECIFICATIONS SPECIFICATIONS 66MHZ SIGNALING TIMING October 2002 Revision 1.00
PI7C8152 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION 14.5 14.6 14.7 15.1 15.2 33MHZ SIGNALING TIMING RESET TIMING POWER CONSUMPTION PACKAGE INFORMATION.77 160-PIN MQFP PACKAGE DIAGRAM.77 PART NUMBER ORDERING INFORMATION.77
LIST TABLES
Table LIST 160-PIN MQFP. Table TRANSACTIONS Table WRITE TRANSACTION FORWARDING. Table WRITE TRANSACTION DISCONNECT ADDRESS BOUNDARIES.12 Table READ PREFETCH ADDRESS BOUNDARIES Table READ TRANSACTION PREFETCHING Table DEVICE NUMBER IDSEL S_AD MAPPING Table DELAYED WRITE TARGET TERMINATION RESPONSE.23 Table RESPONSE POSTED WRITE TARGET TERMINATION.23 Table RESPONSE DELAYED READ TARGET TERMINATIOIN Table SUMMARY TRANSACTION ORDERING Table SETTING PRIMARY INTERFACE DETECTED PARITY ERROR Table SETTING SECONDARY INTERFACE DETECTED PARITY ERROR BIT.42 Table SETTING PRIMARY MASTER DATA PARITY ERROR DETECTED BIT.43 Table SETTING SECONDARY MASTER DATA PARITY ERROR DETECTED BIT.43 Table ASSERTION P_PERR_L.44 Table ASSERTION S_PERR_L Table ASSERTION P_SERR_L DATA PARITY ERRORS.45 Table 10-1 POWER MANAGEMENT TRANSITIONS
LIST FIGURES
Figure SECONDARY ARBITER EXAMPLE Figure 14-1 SIGNAL TIMING MEASUREMENT CONDITIONS Figure 15-1 160-PIN MQFP PACKAGE OUTLINE.77
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INTRODUCTION
Product Description
PI7C8152 Pericom Semiconductor's PCI-to-PCI Bridge that designed fully compliant with 32-bit, 66MHz implementation Local Specification, Revision 2.2. PI7C8152 supports only synchronous transactions between devices Primary Secondary Buses operating either 33MHz 66MHz. Both buses must operate same frequency. Primary Secondary also operate concurrent mode, resulting added increase system performance. Concurrent operation off-loads isolates unnecessary traffic from Primary Bus, thereby enabling master target device Secondary communicate even while Primary busy.
Product Features
32-bit Primary Secondary Ports 66MHz Compliant with Local Specification, Revision Compliant with PCI-to-PCI Bridge Architecture Specification, Revision 1.1. memory commands Type Type configuration conversion Type Type configuration forwarding Type configuration write special cycle conversion Compliant with Advanced Configuration Power Interface (ACPI) Specification. Compliant with Power Management Specification, Revision 1.1. Concurrent Primary Secondary operation independent intra-Secondary Port channel reduce traffic Primary Port Provides internal arbitration four secondary masters Programmable 2-level priority arbiter Disable control external arbiter Supports posted write buffers directions byte FIFO's delay transactions byte FIFO's posted memory transactions Enhanced address decoding 32-bit address range 32-bit memory-mapped address range 64-bit prefetchable address range addressing palette snooping ISA-aware mode legacy support first 64KB address range Interrupt handling interrupts routed through external interrupt concentrator Supports system transaction ordering rules Extended commercial temperature range 85°C 3.3V core; 3.3V signaling 160-pin MQFP package
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SIGNAL DEFINITIONS
Signal Types
Signal Type Description Input Only Output Only Power Tri-State bi-directional Sustained Tri-State. Active signal must pulled HIGH cycle when deasserting. Open Drain
Signals
Note: Signal names that with "_L" active LOW.
2.2.1
PRIMARY INTERFACE SIGNALS
Name P_AD[31:0] 109, 110, 111, 113, 114, 115, 117, 118, 123, 124, 126, 127, 129, 130, 132, 107, Type Description Primary Address Data: Multiplexed address data bus. Address indicated P_FRAME_L assertion. Write data stable valid when P_IRDY_L asserted read data stable valid when P_TRDY_L asserted. Data transferred rising clock edges when both P_IRDY_L P_TRDY_L asserted. During idle, PI7C8152 drives P_AD valid logic level when P_GNT_L asserted. Primary Command/Byte Enables: Multiplexed command field byte enable field. During address phase, initiator drives transaction type these pins. After that, initiator drives byte enables during data phases. During idle, PI7C8152 drives P_CBE[3:0] valid logic level when P_GNT_L asserted. Primary Parity. Parity even across P_AD[31:0], P_CBE[3:0], P_PAR (i.e. even number 1's). P_PAR input valid stable cycle after address phase (indicated assertion P_FRAME_L) address parity. write data phases, P_PAR input valid clock after P_IRDY_L asserted. read data phase, P_PAR output valid clock after P_TRDY_L asserted. Signal P_PAR tri-stated cycle after P_AD lines tri-stated. During idle, PI7C8152 drives P_PAR valid logic level when P_GNT_L asserted. Primary FRAME (Active LOW). Driven initiator transaction indicate beginning duration access. de-assertion P_FRAME_L indicates final data phase requested initiator. Before being tri-stated, driven de-asserted state cycle.
P_CBE[3:0]
P_PAR
P_FRAME_L
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PI7C8152 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
Name P_IRDY_L Type Description Primary IRDY (Active LOW). Driven initiator transaction indicate ability complete current data phase primary side. Once asserted data phase, de-asserted until data phase. Before tri-stated, driven de-asserted state cycle. Primary TRDY (Active LOW). Driven target transaction indicate ability complete current data phase primary side. Once asserted data phase, de-asserted until data phase. Before tri-stated, driven de-asserted state cycle. Primary Device Select (Active LOW). Asserted target indicating that device accepting transaction. master, PI7C8152 waits assertion this signal within cycles P_FRAME_L assertion; otherwise, terminate with master abort. Before tri-stated, driven de-asserted state cycle. Primary STOP (Active LOW). Asserted target indicating that target requesting initiator stop current transaction. Before tri-stated, driven de-asserted state cycle. Primary LOCK (Active LOW). Asserted initiator, clock cycle after first address phase transaction, attempting perform operation that take more than transaction complete. Primary Select. Used chip select line Type configuration access PI7C8152 configuration space. Primary Parity Error (Active LOW). Asserted when data parity error detected data received primary interface. Before being tri-stated, driven de-asserted state cycle. Primary System Error (Active LOW). driven device indicate system error condition. PI7C8152 drives this Address parity error Posted write data parity error target Secondary S_SERR_L asserted Master abort during posted write transaction Target abort during posted write transaction Posted write transaction discarded Delayed write request discarded Delayed read request discarded Delayed transaction master timeout This signal requires external pull-up resistor proper operation. Primary Request (Active LOW): This asserted PI7C8152 indicate that wants start transaction primary bus. PI7C8152 de-asserts this least clock cycles before asserting again. Primary Grant (Active LOW): When asserted, PI7C8152 access primary bus. During idle P_GNT_L asserted, PI7C8152 will drive P_AD, P_CBE, P_PAR valid logic levels. Primary RESET (Active LOW): When P_RESET_L active, signals should asynchronously tristated.
P_TRDY_L
P_DEVSEL_L
P_STOP_L
P_LOCK_L
P_IDSEL P_PERR_L
P_SERR_L
P_REQ_L
P_GNT_L
P_RESET_L
2.2.2
SECONDARY INTERFACE SIGNALS
Name Type Description
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Name S_AD[31:0] 156, 155, 153, 152, 150, 149, 148, 146, 144, 142, 141, 140, 138, 137, 136, 158, Type Description Secondary Address/Data: Multiplexed address data bus. Address indicated S_FRAME_L assertion. Write data stable valid when S_IRDY_L asserted read data stable valid when S_IRDY_L asserted. Data transferred rising clock edges when both S_IRDY_L S_TRDY_L asserted. During idle, PI7C8152 drives S_AD valid logic level when S_GNT_L asserted respectively. Secondary Command/Byte Enables: Multiplexed command field byte enable field. During address phase, initiator drives transaction type these pins. initiator then drives byte enables during data phases. During idle, PI7C8152 drives S_CBE[3:0] valid logic level when internal grant asserted. Secondary Parity: Parity even across S_AD[31:0], S_CBE[3:0], S_PAR (i.e. even number 1's). S_PAR input valid stable cycle after address phase (indicated assertion S_FRAME_L) address parity. write data phases, S_PAR input valid clock after S_IRDY_L asserted. read data phase, S_PAR output valid clock after S_TRDY_L asserted. Signal S_PAR tri-stated cycle after S_AD lines tri-stated. During idle, PI7C8152 drives S_PAR valid logic level when internal grant asserted. Secondary FRAME (Active LOW): Driven initiator transaction indicate beginning duration access. de-assertion S_FRAME_L indicates final data phase requested initiator. Before being tri-stated, driven de-asserted state cycle. Secondary IRDY (Active LOW): Driven initiator transaction indicate ability complete current data phase secondary side. Once asserted data phase, de-asserted until data phase. Before tri-stated, driven deasserted state cycle. Secondary TRDY (Active LOW): Driven target transaction indicate ability complete current data phase secondary side. Once asserted data phase, de-asserted until data phase. Before tri-stated, driven de-asserted state cycle. Secondary Device Select (Active LOW): Asserted target indicating that device accepting transaction. master, PI7C8152 waits assertion this signal within cycles S_FRAME_L assertion; otherwise, terminate with master abort. Before tri-stated, driven de-asserted state cycle. Secondary STOP (Active LOW): Asserted target indicating that target requesting initiator stop current transaction. Before tri-stated, driven de-asserted state cycle. Secondary LOCK (Active LOW): Asserted initiator, clock cycle after first address phase transaction, when propagating locked transaction downstream. PI7C8152 does propagate locked transactions upstream. Secondary Parity Error (Active LOW): Asserted when data parity error detected data received secondary interface. Before being tri-stated, driven de-asserted state cycle.
S_CBE[3:0]
S_PAR
S_FRAME_L
S_IRDY_L
S_TRDY_L
S_DEVSEL_L
S_STOP_L
S_LOCK_L
S_PERR_L
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Name S_SERR_L S_REQ_L[3:0] Type Description Secondary System Error (Active LOW): driven device indicate system error condition. Secondary Request (Active LOW): This asserted external device indicate that wants start transaction secondary bus. input externally pulled through resistor VDD. Secondary Grant (Active LOW): PI7C8152 asserts these pins allow external masters access secondary bus. PI7C8152 de-asserts these pins least clock cycles before asserting again. During idle S_GNT_L deasserted, PI7C8152 will drive S_AD, S_CBE, S_PAR. Secondary RESET (Active LOW): Asserted when following conditions met: Signal P_RESET_L asserted. Secondary reset bridge control register configuration space set. When asserted, control signals tri-stated zeroes driven S_AD, S_CBE, S_PAR. Secondary Central Function Control Pin: When tied LOW, enables internal arbiter. When tied HIGH, external arbiter must used. S_REQ_L[0] reconfigured secondary grant input, S_GNT_L[0] reconfigured secondary request output.
S_GNT_L[3:0]
S_RESET_L
S_CFN_L
2.2.3
CLOCK SIGNALS
Name P_CLK S_CLKIN Type Description Primary Clock Input: Provides timing transactions primary interface. 0MHz 66MHz frequencies supported PI7C8152. Secondary Clock Input: Provides timing transactions secondary interface. 0MHz 66MHz frequencies supported PI7C8152. However, S_CLKIN must same frequency P_CLK. Secondary Clock Output: Provides secondary clocks phase synchronous with P_CLK. When these clocks used, clock outputs must back S_CLKIN. Unused outputs disabled Writing secondary clock disable bits configuration space Terminating them electrically.
S_CLKOUT[4:0]
2.2.4
MISCELLANEOUS SIGNALS
Name P_VIO Type Description Primary Voltage: This used determine either 3.3V signaling primary bus. P_VIO must tied 3.3V only when devices primary 3.3V signaling. Otherwise, P_VIO tied
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S_VIO Secondary Voltage: This used determine either 3.3V signaling secondary bus. S_VIO must tied 3.3V only when devices secondary 3.3V signaling. Otherwise, S_VIO tied Bus/Power Clock Control Management Pin: When this tied HIGH PI7C8152 placed D3HOT power state, enables PI7C8152 place secondary power state. secondary clocks disabled driven When this tied LOW, there effect secondary clocks when PI7C8152 enters D3HOT power state. Full-Scan Enable Control: When SCAN_EN LOW, full-scan shift operation. When SCAN_EN_H HIGH, full-scan parallel operation. SCAN_TM_L HIGH, SCAN_EN output with logic normal operation, SCAN_TM_L should pulled HIGH SCAN_EN becomes output. Full-Scan Teset Mode Enable: When SCAN_TM_L active (LOW), scan chains will enabled. normal operation, pull SCAN_TM_L HIGH.
BPCCE
SCAN_EN
SCAN_TM_L
2.2.5
POWER GROUND
Name 108, 116, 120, 125, 131, 139, 147, 154, 103, 112, 119, 121, 128, 135, 143, 151, Type Description Power: +3.3V Digital power.
Ground: Digital ground.
LIST 160-PIN MQFP
Table LIST 160-PIN MQFP
Number Name S_PERR_L S_DEVSEL_L S_IRDY_L S_CBE_L[2] S_AD[17] S_AD[22] S_CBE_L[3] S_AD[25] S_AD[27] S_REQ_L[0] S_GNT_L[0] Type Number Name S_PAR S_LOCK_L S_FRAME_L S_AD[16] S_AD[18] S_AD[20] S_AD[24] S_AD[26] S_AD[28] S_AD[30] S_REQ_L[1] S_GNT_L[1] S_GNT_L[3] Type Number Name S_SERR_L S_STOP_L S_TRDY_L S_AD[19] S_AD[21] S_AD[23] S_AD[29] S_AD[31] S_REQ_L[2] S_REQ_L[3] S_GNT_L[2] S_RESET_L Type
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Number Number Number
Name S_CFN_L S_VIO S_CLKOUT[1] S_CLKOUT[4] P_RESET_L P_VIO P_AD[31] P_AD[29] P_AD[27] P_AD[24] P_CBE_L[3] P_AD[22] P_AD[20] P_AD[18] P_IRDY_L P_DEVSEL_L P_PAR P_AD[15] P_AD[10] P_AD[8] P_AD[6] P_AD[4] P_AD[2] P_AD[0] S_AD[1] S_AD[6] S_CBE_L[0] S_AD[9]
Type
Name S_CLKOUT[0] S_CLKOUT[3] SCAN_EN P_GNT_L P_AD[28] P_AD[26] P_IDSEL P_AD[19] P_AD[17] P_CBE_L[2] P_STOP_L P_PERR_L P_CBE_L[1] P_AD[14] P_AD[12] P_CBE_L[0] S_AD[0] S_AD[2] S_AD[4] S_AD[8] S_AD[10] S_AD[12] S_AD[14] S_CBE_L[1]
Type
Name S_CLKIN S_CLKOUT[2] SCAN_TM_L P_CLK P_REQ_L P_AD[30] P_AD[25] P_AD[23] P_AD[21] P_AD[16] P_FRAME_L P_TRDY_L P_LOCK_L P_SERR_L P_AD[13] P_AD[11] P_AD[9] P_AD[7] P_AD[5] P_AD[3] P_AD[1] S_AD[3] S_AD[5] S_AD[7] S_AD[11] S_AD[13] S_AD[15] BPCCE
Type
OPERATION
This Chapter offers information about transactions, transaction forwarding across PI7C8152, transaction termination. PI7C8152 128-byte buffers read data buffering upstream downstream transactions. Also, PI7C8152 128byte buffers write data buffering upstream downstream transactions.
TYPES TRANSACTIONS
This section provides summary transactions performed PI7C8152. Table lists command code name each transaction. Master Target columns indicate support each transaction when PI7C8152 initiates transactions master, primary secondary buses, when PI7C8152 responds transactions target, primary secondary buses.
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PI7C8152 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Table TRANSACTIONS
Types Transactions 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Interrupt Acknowledge Special Cycle Read Write Reserved Reserved Memory Read Memory Write Reserved Reserved Configuration Read Configuration Write Memory Read Multiple Dual Address Cycle Memory Read Line Memory Write Invalidate Initiates Master Primary (Type only) Secondary Responds Target Primary Secondary (Type only)
indicated Table 3-1, following commands supported PI7C8152: PI7C8152 never initiates transaction with reserved command code and, target, PI7C8152 ignores reserved command codes. PI7C8152 does generate interrupt acknowledge transactions. PI7C8152 ignores interrupt acknowledge transactions target. PI7C8152 does respond special cycle transactions. PI7C8152 cannot guarantee delivery special cycle transaction downstream buses because broadcast nature special cycle command inability control transaction target. generate special cycle transactions other buses, either upstream downstream, Type configuration write must used. PI7C8152 neither generates Type configuration transactions primary responds Type configuration transactions secondary bus.
SINGLE ADDRESS PHASE
32-bit address uses single address phase. This address driven P_AD[31:0], command driven P_CBE[3:0]. PI7C8152 supports linear increment address mode only, which indicated when lowest address bits equal zero. either lowest address bits nonzero, PI7C8152 automatically disconnects transaction after first data transfer.
DUAL ADDRESS PHASE
64-bit address uses address phases. first address phase denoted asserting edge FRAME_L. second address phase always follows next clock cycle. 32-bit interface, first address phase contains dual address command code CBE_L[3:0] lines, address bits AD[31:0] lines. second address October 2002 Revision 1.00
PI7C8152 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION phase consists specific memory transaction command code CBE_L[3:0] lines, high address bits AD[31:0] lines. this way, 64-bit addressing supported 32-bit buses. PCI-to-PCI Bridge Architecture Specification supports dual address transactions prefetchable memory range only. Section 4.3.2 discussion prefetchable address space. PI7C8152 supports dual address transactions both upstream downstream direction. PI7C8152 supports programmable 64-bit address range prefetchable memory downstream forwarding dual address transactions. Dual address transactions falling outside prefetchable address range forwarded upstream. Prefetching posting performed manner consistent with guidelines given this specification each type memory transaction prefetchable memory space.
DEVICE SELECT (DEVSEL_L) GENERATION
PI7C8152 always performs positive address decoding (medium decode) when accepting transactions either primary secondary buses. PI7C8152 never does subtractive decode.
DATA PHASE
address phase transaction followed more data phases. data phase completed when IRDY_L either TRDY_L STOP_L asserted. transfer data occurs only when both IRDY_L TRDY_L asserted during same clock cycle. last data phase transaction indicated when FRAME_L de-asserted both TRDY_L IRDY_L asserted, when IRDY_L STOP_L asserted. Section further discussion transaction termination. Depending command type, PI7C8152 support multiple data phase transactions. detailed descriptions PI7C8152 imposes disconnect boundaries, Section 3.6.4 write address boundaries Section 3.7.3 read address boundaries.
WRITE TRANSACTIONS
Write transactions treated either posted write delayed write transactions. Table 3-2shows method forwarding used each type write operation. Table WRITE TRANSACTION FORWARDING
Type Transaction Memory Write Memory Write Invalidate Memory Write memory Write Type Configuration Write Type Forwarding Posted (except memory) Posted Delayed Delayed Delayed
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3.6.1
MEMORY WRITE TRANSACTIONS
Posted write forwarding used "Memory Write" "Memory Write Invalidate" transactions. When PI7C8152 determines that memory write transaction forwarded across bridge, PI7C8152 asserts DEVSEL_L with medium decode timing TRDY_L next cycle, provided that enough buffer space available posted memory write queue address least DWORD data. Under this condition, PI7C8152 accepts write data without obtaining access target bus. PI7C8152 accept DWORD write data every clock cycle. That target wait state inserted. write data stored internal posted write buffers subsequently delivered target. PI7C8152 continues accept write data until following events occurs: initiator terminates transaction de-asserting FRAME_L IRDY_L. internal write address boundary reached, such cache line boundary aligned boundary, depending transaction type. posted write data buffer fills
When last events occurs, PI7C8152 returns target disconnect requesting initiator this data phase terminate transaction. Once posted write data moves head posted data queue, PI7C8152 asserts request target bus. This occur while PI7C8152 still receiving data initiator bus. When grant target received target detected idle condition, PI7C8152 asserts FRAME_L drives stored write address target bus. following cycle, PI7C8152 drives first DWORD write data continues transfer write data until write data corresponding that transaction delivered, until target termination received. long write data exists queue, PI7C8152 drive DWORD write data each clock cycle; that master wait states inserted. write data flowing through PI7C8152 initiator stalls, PI7C8152 will signal last data phase current transaction target queue empties. PI7C8152 will restart follow-on transactions queue data. PI7C8152 ends transaction target when following conditions met: posted write data been delivered target. target returns target disconnect target retry (PI7C8152 starts another transaction deliver rest write data). target returns target abort (PI7C8152 discards remaining write data). master latency timer expires, PI7C8152 longer target grant (PI7C8152 starts another transaction deliver remaining write data).
Section 3.9.3.2 provides detailed information about PI7C8152 responds target termination during posted write transactions.
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PI7C8152 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
3.6.2
MEMORY WRITE INVALIDATE
Posted write forwarding used Memory Write Invalidate transactions. PI7C8152 disconnects Memory Write Invalidate commands aligned cache line boundaries. cache line size value cache line size register gives number DWORD cache line. value cache line size register does meet memory write invalidate conditions, PI7C8152 returns target disconnect initiator cache line boundary.
3.6.3
DELAYED WRITE TRANSACTIONS
Delayed write forwarding used write transactions Type configuration write transactions. delayed write transaction guarantees that actual target response returned back initiator without holding initiating wait states. delayed write transaction limited single DWORD data transfer. When write transaction first detected initiator bus, PI7C8152 forwards delayed transaction, PI7C8152 claims access asserting DEVSEL_L returns target retry initiator. During address phase, PI7C8152 samples command, address, address parity cycle later. After IRDY_L asserted, PI7C8152 also samples first data DWORD, byte enable bits, data parity. This information placed into delayed transaction queue. transaction queued only other existing delayed transactions have same address command, delayed transaction queue full. When delayed write transaction moves head delayed transaction queue ordering constraints with posted data satisfied. PI7C8152 initiates transaction target bus. PI7C8152 transfers write data target. PI7C8152 receives target retry response write transaction target bus, continues repeat write transaction until data transfer completed, until error condition encountered. PI7C8152 unable deliver write data after (default) (maximum) attempts, PI7C8152 will report system error. PI7C8152 also asserts P_SERR_L primary SERR_L enable command register. Section information assertion P_SERR_L. When initiator repeats same write transaction (same command, address, byte enable bits, data), completed delayed transaction head queue, PI7C8152 claims access asserting DEVSEL_L returns TRDY_L initiator, indicate that write data transferred. initiator requests multiple DWORD, PI7C8152 also asserts STOP_L conjunction with TRDY_L signal target disconnect. Note that only those bytes write data with valid byte enable bits compared. byte enable bits turned (driven HIGH), corresponding byte write data compared. initiator repeats write transaction before data been transferred target, PI7C8152 returns target retry initiator. PI7C8152 continues return target retry initiator until write data delivered target, until error condition encountered. When write transaction repeated, PI7C8152 does make entry
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PI7C8152 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION into delayed transaction queue. Section 3.9.3.1 provides detailed information about PI7C8152 responds target termination during delayed write transactions. PI7C8152 implements discard timer that starts counting when delayed write completion head delayed transaction completion queue. initial value this timer retry counter register offset 78h. initiator does repeat delayed write transaction before discard timer expires, PI7C8152 discards delayed write completion from delayed transaction completion queue. PI7C8152 also conditionally asserts P_SERR_L (see Section 6.4).
3.6.4
WRITE TRANSACTION ADDRESS BOUNDARIES
PI7C8152 imposes internal address boundaries when accepting write data. aligned address boundaries used prevent PI7C8152 from continuing transaction over device address boundary provide upper limit maximum latency. PI7C78152 returns target disconnect initiator when reaches aligned address boundaries under conditions shown Table 3-3. Table WRITE TRANSACTION DISCONNECT ADDRESS BOUNDARIES
Type Transaction Delayed Write Posted Memory Write Posted Memory Write Posted Memory Write Invalidate Posted Memory Write Invalidate Condition Memory write disconnect control 0(1) Memory write disconnect control 1(1) Cache line size Cache line size Aligned Address Boundary Disconnects after data transfer aligned address boundary Disconnects cache line boundary aligned address boundary Cache line boundary posted memory write data FIFO does have enough space next cache line 16-DWORD aligned address boundary
Posted Memory Write Cache line size Invalidate Note Memory write disconnect control chip control register offset configuration space.
3.6.5
BUFFERING MULTIPLE WRITE TRANSACTIONS
PI7C8152 continues accept posted memory write transactions long space least DWORD data posted write data buffer remains. posted write data buffer fills before initiator terminates write transaction, PI7C8152 returns target disconnect initiator. Delayed write transactions accepted long least open entry delayed transaction queue exists. Therefore, several posted delayed write transactions exist data buffers same time. Chapter information about multiple posted delayed write transactions ordered.
3.6.6
FAST BACK-TO-BACK WRITE TRANSACTIONS
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PI7C8152 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION PI7C8152 capable decoding forwarding fast back-to-back write transactions. When PI7C8152 cannot accept second transaction because buffer space limitations, returns target retry initiator. fast back-to-back enable must command register upstream write transactions, bridge control register downstream write transactions.
READ TRANSACTIONS
Delayed read forwarding used read transactions crossing PI7C8152. Delayed read transactions treated either prefetchable non-prefetchable. Table shows read behavior, prefetchable non-prefetchable, each type read operation.
3.7.1
PREFETCHABLE READ TRANSACTIONS
prefetchable read transaction read transaction where PI7C8152 performs speculative DWORD reads, transferring data from target before requested from initiator. This behavior allows prefetchable read transaction consist multiple data transfers. However, byte enable bits cannot forwarded data phases done single data phase non-prefetchable read transaction. prefetchable read transactions, PI7C8152 forces byte enable bits data phases. Prefetchable behavior used memory read line memory read multiple transactions, well memory read transactions that fall into prefetchable memory space. amount data that prefetched depends type transaction. amount prefetching also affected amount free buffer space available PI7C8152, read address boundaries encountered. Prefetching should used those read transactions that have side effects target device, that control status registers, FIFO's, target device's base address register registers indicate memory address region prefetchable.
3.7.2
NON-PREFETCHABLE READ TRANSACTIONS
non-prefetchable read transaction read transaction where PI7C8152 requests only DWORD from target disconnects initiator after delivery first DWORD read data. Unlike prefetchable read transactions, PI7C8152 forwards read byte enable information data phase. Non-prefetchable behavior used configuration read transactions, well memory read transactions that fall into non-prefetchable memory space. extra read transactions could have side effects, example, when accessing FIFO, non-prefetchable read transactions those locations. Accordingly, important retain value byte enable bits during data phase, non-prefetchable read transactions. these locations mapped memory space, memory read command target into non-prefetchable (memory-mapped I/O) memory space non-prefetching behavior. October 2002 Revision 1.00
PI7C8152 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
3.7.3
READ PREFETCH ADDRESS BOUNDARIES
PI7C8152 imposes internal read address boundaries read prefetched data. When read transaction reaches these aligned address boundaries, PI7C8152 stops prefetched data, unless target signals target disconnect before read prefetched boundary reached. When PI7C8152 finishes transferring this read data initiator, returns target disconnect with last data transfer, unless initiator completes transaction before pre-fetched read data delivered. leftover prefetched data discarded. Prefetchable read transactions flow-through mode prefetch nearest aligned address boundary, until initiator de-asserts FRAME_L. Section 3.7.6 describes flowthrough mode during read operations. Table 3-4shows read prefetch address boundaries read transactions during nonflow-through mode. Table READ PREFETCH ADDRESS BOUNDARIES
Type Transaction Configuration Read Read Memory Read Memory Read Memory Read Memory Read Line Address Space Non-Prefetchable Prefetchable Prefetchable Cache Line (CLS) Size Prefetch Address Boundary DWORD prefetch) DWORD prefetch) DWORD prefetch) 16-DWORD aligned address boundary Cache line address boundary 16-DWORD aligned address boundary Cache line boundary Queue full Second cache line boundary
Memory Read Line Memory Read Multiple Memory Read Multiple does matter prefetchable non-prefetchable don't care
Table READ TRANSACTION PREFETCHING
Read Behavior Prefetching never allowed Prefetching never allowed Downstream: Prefetching used address prefetchable space Memory Read Upstream: Prefetching used Memory Read Line Prefetching always used Memory Read Multiple Prefetching always used Section detailed information about prefetchable non-prefetchable address spaces. Type Transaction Read Configuration Read
3.7.4
DELAYED READ REQUESTS
PI7C8152 treats read transactions delayed read transactions, which means that read request from initiator posted into delayed transaction queue. Read data from target placed read data queue directed toward initiator interface transferred initiator when initiator repeats read transaction.
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PI7C8152 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION PI7C8152 accepts delayed read request sampling read address, read command, address parity. When IRDY_L asserted, PI7C8152 then samples byte enable bits first data phase. This information entered into delayed transaction queue. PI7C8152 terminates transaction signaling target retry initiator. Upon reception target retry, initiator required continue repeat same read transaction until least data transfer completed, until target response (target abort master abort) other than target retry received.
3.7.5
DELAYED READ COMPLETION TARGET
When delayed read request reaches head delayed transaction queue, PI7C8152 arbitrates target initiates read transaction only previously queued posted write transactions have been delivered. PI7C8152 uses exact read address read command captured from initiator during initial delayed read request initiate read transaction. read transaction non-prefetchable read, PI7C8152 drives captured byte enable bits during next cycle. transaction prefetchable read transaction, drives byte enable bits zero data phases. PI7C8152 receives target retry response read transaction target bus, continues repeat read transaction until least data transfer completed, until error condition encountered. transaction terminated normal master termination target disconnect after least data transfer been completed, PI7C8152 does initiate further attempts read more data. PI7C8152 unable obtain read data from target after (default) (maximum) attempts, PI7C8152 will report system error. number attempts programmable. PI7C8152 also asserts P_SERR_L primary SERR_L enable command register. Section information assertion P_SERR_L. Once PI7C8152 receives DEVSEL_L TRDY_L from target, transfers data read opposite direction read data queue, pointing toward opposite inter-face, before terminating transaction. example, read data response downstream read transaction initiated primary placed upstream read data queue. PI7C8152 accept DWORD read data each clock cycle; that master wait states inserted. number DWORD's transferred during delayed read transaction matches prefetch address boundary given Table (assuming disconnect received from target).
3.7.6
DELAYED READ COMPLETION INITIATOR
When transaction been completed target bus, delayed read data head read data queue, ordering constraints with posted write transactions have been satisfied, PI7C8152 transfers data initiator when initiator repeats transaction. memory read transactions, PI7C8152 aliases memory read line memory read multiple commands memory read when matching command transaction command delayed transaction queue bit[3] offset `1'. PI7C8152 returns target disconnect along with transfer last DWORD read data initiator. PI7C8152 initiator terminates transaction before read data been transferred, remaining read data left data buffers discarded.
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PI7C8152 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION When master repeats transaction starts transferring prefetchable read data from data buffers while read transaction target still progress before read boundary reached target bus, read transaction starts operating flow-through mode. Because data flowing through data buffers from target initiator, long read bursts then sustained. this case, read transaction allowed continue until initiator terminates transaction, until aligned address boundary reached, until buffer fills, whichever comes first. When buffer empties, PI7C8152 reflects stalled condition initiator disconnecting initiator with data. initiator retry transaction later data needed. initiator does need more data, initiator will continue disconnected transaction. this case, PI7C8152 will start master timeout timer. remaining read data will discarded after master timeout timer expires. provide better latency, there other pending data other transactions (Read Data Buffer), remaining read data will discarded even though master timeout timer expired. PI7C8152 implements master timeout timer that starts counting when delayed read completion head delayed transaction queue, read data head read data queue. initial value this timer programmable through configuration transaction. initiator does repeat read transaction before master timeout timer expires (215 default), PI7C8152 discards read transaction read data from queues. PI7C8152 also conditionally asserts P_SERR_L (see Section 6.4). PI7C8152 capability post multiple delayed read requests, maximum four each direction. initiator starts read transaction that matches address read command read transaction that already queued, current read command posted already contained delayed transaction queue. Section discussion delayed read transactions ordered when crossing PI7C8152.
3.7.7
FAST BACK-TO-BACK READ TRANSACTION
PI7C8152 capable decode fast back-to-back read transactions both primary secondary. PI7C8152 cannot generate fast back-to-back read transactions both secondary primary even bit[23] offset bit[9] offset `1'.
CONFIGURATION TRANSACTIONS
Configuration transactions used initialize system. Every device configuration space that accessed configuration commands. registers accessible configuration space only. addition accepting configuration transactions initialization configuration space, PI7C8152 also forwards configuration transactions device initialization hierarchical systems, well special cycle generation. support hierarchical systems, types configuration transactions specified: Type Type
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PI7C8152 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Type configuration transactions issued when intended target resides same initiator. Type configuration transaction identified configuration command lowest bits address 00b. Type configuration transactions issued when intended target resides another bus, when special cycle generated another bus. Type configuration command identified configuration command lowest address bits 01b. register number found both Type Type formats gives DWORD address configuration register accessed. function number also included both Type Type formats indicates which function multifunction device accessed. single-function devices, this value decoded. addresses Type configuration transaction include 5-bit field designating device number that identifies device target that accessed. addition, number Type transactions specifies which transaction targeted.
3.8.1
TYPE ACCESS PI7C8152
configuration space accessed Type configuration transaction primary interface. configuration space cannot accessed from secondary bus. PI7C8152 responds Type configuration transaction asserting P_DEVSEL_L when following conditions during address phase: command configuration read configuration write transaction. Lowest address bits P_AD[1:0] must 00b. Signal P_IDSEL must asserted.
PI7C8152 limits configuration access single DWORD data transfer returns target-disconnect with first data transfer additional data phases requested. Because read transactions configuration space have side effects, bytes requested DWORD returned, regardless value byte enable bits. Type configuration write read transactions data buffers; that these transactions completed immediately, regardless state data buffers. PI7C8152 ignores Type transactions initiated secondary interface.
3.8.2
TYPE TYPE CONVERSION
Type configuration transactions used specifically device configuration hierarchical system. PCI-to-PCI bridge only type device that should respond Type configuration command. Type configuration commands used when configuration access intended device that resides other than where Type transaction generated. PI7C8152 performs Type Type translation when Type transaction generated primary intended device attached directly secondary bus. PI7C8152 must convert configuration command Type format that secondary device respond Type Type translations October 2002 Revision 1.00
PI7C8152 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION performed only downstream direction; that PI7C8152 generates Type transaction only secondary bus, never primary bus. PI7C8152 responds Type configuration transaction translates into Type transaction secondary when following conditions during address phase: lowest address bits P_AD[1:0] 01b. number address field P_AD[23:16] equal value secondary number register configuration space. command P_CBE[3:0] configuration read configuration write transaction.
When PI7C8152 translates Type transaction Type transaction secondary interface, performs following translations address: Sets lowest address bits S_AD[1:0] Decodes device number drives pattern specified Table S_AD[31:16] purpose asserting device's IDSEL signal. Sets S_AD[15:11] Leaves unchanged function number register number fields.
PI7C8152 asserts unique address line based device number. These address lines used secondary IDSEL signals. mapping address lines depends device number Type address bits P_AD[15:11]. Table presents mapping that PI7C8152 uses. Table DEVICE NUMBER IDSEL S_AD MAPPING
Device Number P_AD[15:11] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 11110 11111 Secondary IDSEL S_AD[31:16] 0000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 Generate special cycle (P_AD[7:2] 00h) 0000 0000 0000 0000 (P_AD[7:2] 00h) S_AD
PI7C8152 assert unique address lines used IDSEL signals devices secondary bus, device numbers ranging from through October 2002 Revision 1.00
PI7C8152 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Because electrical loading constraints bus, more than IDSEL signals should necessary. However, device numbers greater than desired, some external method generating IDSEL lines must used, upper address bits then asserted. configuration transaction still translated passed from primary secondary bus. IDSEL asserted secondary device, transaction ends master abort. PI7C8152 forwards Type Type configuration read write transactions delayed transactions. Type Type configuration read write transactions limited single 32-bit data transfer.
3.8.3
TYPE TYPE FORWARDING
Type Type transaction forwarding provides hierarchical configuration mechanism when more levels PCI-to-PCI bridges used. When PI7C8152 detects Type configuration transaction intended downstream from secondary bus, PI7C8152 forwards transaction unchanged secondary bus. Ultimately, this transaction translated Type configuration command special cycle transaction downstream PCI-to-PCI bridge. Downstream Type Type forwarding occurs when following conditions during address phase: lowest address bits equal 01b. number falls range defined lower limit (exclusive) secondary number register upper limit (inclusive) subordinate number register. command configuration read write transaction.
PI7C8152 also supports Type Type forwarding configuration write transactions upstream support upstream special cycle generation. Type configuration command forwarded upstream when following conditions met: lowest address bits equal 01b. number falls outside range defined lower limit (inclusive) secondary number register upper limit (inclusive) subordinate number register. device number address bits AD[15:11] equal 11111b. function number address bits AD[10:8] equal 111b. command configuration write transaction.
PI7C8152 forwards Type Type configuration write transactions delayed transactions. Type Type configuration write transactions limited single data transfer.
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PI7C8152 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
3.8.4
SPECIAL CYCLES
Type configuration mechanism used generate special cycle transactions hierarchical systems. Special cycle transactions ignored acting target forwarded across bridge. Special cycle transactions generated from Type configuration write transactions either upstream down-stream direction. PI7C8152 initiates special cycle target when Type configuration write transaction being detected initiating following conditions during address phase: lowest address bits AD[1:0] equal 01b. device number address bits AD[15:11] equal 11111b. function number address bits AD[10:8] equal 111b. register number address bits AD[7:2] equal 000000b. number equal value secondary number register configuration space downstream forwarding equal value primary number register configuration space upstream forwarding. command CBE_L configuration write command.
When PI7C8152 initiates transaction target interface, command changed from configuration write special cycle. address data for-warded unchanged. Devices that special cycles ignore address decode only command. data phase contains special cycle message. transaction forwarded delayed transaction, this case target response forwarded back (because special cycles result master abort). Once transaction completed target bus, through detection master abort condition, PI7C8152 responds with TRDY_L next attempt con-figuration transaction from initiator. more than data transfer requested, PI7C8152 responds with target disconnect operation during first data phase.
TRANSACTION TERMINATION
This section describes PI7C8152 returns transaction termination conditions back initiator. initiator terminate transactions with following types termination: Normal termination Normal termination occurs when initiator de-asserts FRAME_L beginning last data phase, de-asserts IRDY_L last data phase conjunction with either TRDY_L STOP_L assertion from target. Master abort master abort occurs when target response detected. When initiator does detect DEVSEL_L from target within five clock cycles after asserting FRAME_L, initiator terminates transaction with master abort. FRAME_L still asserted, October 2002 Revision 1.00
PI7C8152 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION initiator de-asserts FRAME_L next cycle, then de-asserts IRDY_L following cycle. IRDY_L must asserted same cycle which FRAME_L deasserts. FRAME_L already de-asserted, IRDY_L de-asserted next clock cycle following detection master abort condition. target terminate transactions with following types termination: Normal termination TRDY_L DEVSEL_L asserted conjunction with FRAME_L de-asserted IRDY_L asserted. Target retry STOP_L DEVSEL_L asserted with TRDY_L de-asserted during first data phase. data transfers occur during transaction. This transaction must repeated. Target disconnect with data transfer STOP_L, DEVSEL_L TRDY_L asserted. signals that this last data transfer transaction. Target disconnect without data transfer STOP_L DEVSEL_L asserted with TRDY_L de-asserted after previous data transfers have been made. Indicates that more data transfers will made during this transaction. Target abort STOP_L asserted with DEVSEL_L TRDY_L de-asserted. Indicates that target will never able complete this transaction. DEVSEL_L must asserted least cycle during transaction before target abort signaled.
3.9.1
MASTER TERMINATION INITIATED PI7C8152
PI7C8152, initiator, uses normal termination DEVSEL_L returned target within five clock cycles PI7C8152's assertion FRAME_L target bus. initiator, PI7C8152 terminates transaction when following conditions met: During delayed write transaction, single DWORD delivered. During non-prefetchable read transaction, single DWORD transferred from target. During prefetchable read transaction, pre-fetch boundary reached. posted write transaction, write data transaction transferred from data buffers target. burst transfer, with exception "Memory Write Invalidate" transactions, master latency timer expires PI7C8152's grant de-asserted. target terminates transaction with retry, disconnect, target abort.
PI7C8152 delivering posted write data when terminates transaction because master latency timer expires, initiates another transaction deliver remaining write
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PI7C8152 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION data. address transaction updated reflect address current DWORD delivered. PI7C8152 pre-fetching read data when terminates transaction because master latency timer expires, does repeat transaction obtain more data.
3.9.2
MASTER ABORT RECEIVED PI7C8152
initiator initiates transaction target does detect DEVSEL_L returned target within five clock cycles assertion FRAME_L, PI7C8152 terminates transaction with master abort. This sets received-master-abort status register corresponding target bus. delayed read write transactions, PI7C8152 able reflect master abort condition back initiator. When PI7C8152 detects master abort response delayed transaction, when initiator repeats transaction, PI7C8152 does respond transaction with DEVSEL_L, which induces master abort condition back initiator. transaction then removed from delayed transaction queue. When master abort received response posted write transaction, PI7C8152 discards posted write data makes more attempt deliver data. PI7C8152 sets received-master-abort status register when master abort received primary bus, sets received master abort secondary status register when master abort received secondary interface. When master abort detected posted write transaction with both master-abort-mode (bit bridge control register) SERR_L enable (bit command register secondary bus) set, PI7C8152 asserts P_SERR_L master-abort-on-posted-write set. masterabort-on-posted-write P_SERR_L event disable register (offset 64h). Note: When PI7C8152 performs Type special cycle conversion, master abort expected termination special cycle target bus. this case, master abort received set, Type configuration transaction disconnected after first data phase.
3.9.3
TARGET TERMINATION RECEIVED PI7C8152
When PI7C8152 initiates transaction target target responds with DEVSEL_L, target transaction with following types termination: Normal termination (upon de-assertion FRAME_L) Target retry Target disconnect Target abort
PI7C8152 handles these terminations different ways, depending type transaction being performed.
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PI7C8152 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION 3.9.3.1 DELAYED WRITE TARGET TERMINATION RESPONSE When PI7C8152 initiates delayed write transaction, type target termination received from target passed back initiator. Table shows response each type target termination that occurs during delayed write transaction. PI7C8152 repeats delayed write transaction until following conditions met: PI7C8152 completes least data transfer. PI7C8152 receives master abort. PI7C8152 receives target abort.
PI7C8152 makes (default) (maximum) write attempts resulting response target retry. Table DELAYED WRITE TARGET TERMINATION RESPONSE
Target Termination Normal Target Retry Target Disconnect Target Abort Response Returning disconnect initiator with first data transfer only multiple data phases requested. Returning target retry initiator. Continue write attempts target Returning disconnect initiator with first data transfer only multiple data phases requested. Returning target abort initiator. received target abort target interface status register. signaled target abort initiator interface status register.
After PI7C8152 makes (default) attempts same delayed write trans-action target bus, PI7C8152 asserts P_SERR_L SERR_L enable (bit command register secondary bus) delayed-write-non-delivery set. delayed-write-non-delivery P_SERR_L event disable register (offset 64h). PI7C8152 will report system error. Section description system error conditions. 3.9.3.2 POSTED WRITE TARGET TERMINATION RESPONSE When PI7C8152 initiates posted write transaction, target termination cannot passed back initiator. Table shows response each type target termination that occurs during posted write transaction. Table RESPONSE POSTED WRITE TARGET TERMINATION
Target Termination Normal Target Retry Target Disconnect Target Abort Repsonse additional action. Repeating write transaction target. Initiate write transaction delivering remaining posted write data. received-target-abort target interface status register. Assert P_SERR# enabled, signaled-system-error primary status register.
Note that when target retry target disconnect returned posted write data associated with that transaction remains write buffers, PI7C8152 initiates another write transaction attempt deliver rest write data. there target retry, exact same address will driven initial write trans-action attempt. target October 2002 Revision 1.00
PI7C8152 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION disconnect received, address that driven subsequent write transaction attempt will updated reflect address current DWORD. initial write transaction Memory-Write-and-Invalidate transaction, partial delivery write data target performed before target disconnect received, PI7C8152 will memory write command deliver rest write data. because incomplete cache line will transferred subsequent write transaction attempt. After PI7C8152 makes (default) write transaction attempts fails deliver posted write data associated with that transaction, PI7C8152 asserts P_SERR_L primary SERR_L enable (bit command register secondary bus) posted-write-non-delivery set. posted-write-non-delivery P_SERR_L event disable register (offset 64h). PI7C8152 will report system error. Section discussion system error conditions. 3.9.3.3 DELAYED READ TARGET TERMINATION RESPONSE When PI7C8152 initiates delayed read transaction, abnormal target responses passed back initiator. Other target responses depend much data initiator requests. Table shows response each type target termination that occurs during delayed read transaction. PI7C8152 repeats delayed read transaction until following conditions met: PI7C8152 completes least data transfer. PI7C8152 receives master abort. PI7C8152 receives target abort.
PI7C8152 makes (default) read attempts resulting response target retry. Table RESPONSE DELAYED READ TARGET TERMINATIOIN
Target Termination Normal Target Retry Target Disconnect Target Abort Response prefetchable, target disconnect only initiator requests more data than read from target. non-prefetchable, target disconnect first data phase. Re-initiate read transaction target initiator requests more data than read from target, return target disconnect initiator. Return target abort initiator. received target abort target interface status register. signaled target abort initiator interface status register.
After PI7C8152 makes 224(default) attempts same delayed read transaction target bus, PI7C8152 asserts P_SERR_L primary SERR_L enable (bit command register secondary bus) delayed-write-non-delivery set. delayed-write-non-delivery P_SERR_L event disable register (offset 64h). PI7C8152 will report system error. Section description system error conditions.
3.9.4
TARGET TERMINATION INITIATED PI7C8152
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PI7C8152 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION PI7C8152 return target retry, target disconnect, target abort initiator reasons other than detection that condition target interface. 3.9.4.1 TARGET RETRY PI7C8152 returns target retry initiator when cannot accept write data return read data result internal conditions. PI7C8152 returns target retry initiator when following conditions met: delayed write transactions: transaction being entered into delayed transaction queue. Transaction already been entered into delayed transaction queue, target response been received. Target response been received progressed head return queue. delayed transaction queue full, transaction cannot queued. transaction with same address command been queued. locked sequence being propagated across PI7C8152, write transaction locked transaction. target locked write transaction locked transaction. more than clocks accept this transaction.
delayed read transactions: transaction being entered into delayed transaction queue. read request already been queued, read data available. Data been read from target, head read data queue posted write transaction precedes delayed transaction queue full, transaction cannot queued. delayed read request with same address command already been queued. locked sequence being propagated across PI7C8152, read transaction locked transaction. PI7C78152 currently discarding previously pre-fetched read data. target locked write transaction locked transaction. more than clocks accept this transaction.
posted write transactions: October 2002 Revision 1.00
PI7C8152 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
posted write data buffer does have enough space address least DWORD write data. locked sequence being propagated across PI7C8152, write transaction locked transaction. When target retry returned initiator delayed transaction, initiator must repeat transaction with same address command well data write transaction, within time frame specified master timeout value. Otherwise, transaction discarded from buffers.
3.9.4.2
TARGET DISCONNECT PI7C8152 returns target disconnect initiator when following conditions met: PI7C8152 hits internal address boundary. PI7C8152 cannot accept more write data. PI7C8152 more read data deliver.
Section 3.6.4 description write address boundaries, Section 3.7.3 description read address boundaries. 3.9.4.3 TARGET ABORT PI7C8152 returns target abort initiator when following conditions met: PI7C8152 returning target abort from intended target. When PI7C8152 returns target abort initiator, sets signaled target abort status register corresponding initiator interface.
ADDRESS DECODING
PI7C8152 uses three address ranges that control memory transaction forwarding. These address ranges defined base limit address registers configuration space. This chapter describes these address ranges, well ISA-mode VGAaddressing support.
ADDRESS RANGES
PI7C8152 uses following address ranges that determine which memory transactions forwarded from primary secondary bus, from secondary primary bus:
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PI7C8152 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION 32-bit address ranges 32-bit memory-mapped (non-prefetchable memory) ranges 32-bit prefetchable memory address ranges
Transactions falling within these ranges forwarded downstream from primary secondary bus. Transactions falling outside these ranges forwarded upstream from secondary primary bus. address translation required PI7C8152. addresses that marked downstream always forwarded upstream.
ADDRESS DECODING
PI7C8152 uses following mechanisms that defined configuration space specify address space downstream upstream forwarding: base limit address registers enable mode snoop
This section provides information address registers mode. Section provides information modes. enable downstream forwarding transactions, enable must command register configuration space. transactions initiated primary will ignored enable set. enable upstream forwarding transactions, master enable must command register. masterenable set, PI7C8152 ignores memory transactions initiated secondary bus. master-enable also allows upstream forwarding memory transactions set. CAUTION configuration state affecting transaction forwarding changed configuration write operation primary same time that transactions ongoing secondary bus, PI7C8152 response secondary transactions predictable. Configure base limit address registers, enable bit, mode bit, snoop before setting enable master enable bits, change them subsequently only when primary secondary buses idle.
4.2.1
BASE LIMIT ADDRESS REGISTER
PI7C8152 implements base limit address registers configuration space that define address range port downstream forwarding. PI7C8152 supports 3227 October 2002 Revision 1.00
PI7C8152 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION addressing, which allows addresses downstream PI7C8152 mapped anywhere address space. transactions with addresses that fall inside range defined base limit registers forwarded downstream from primary secondary bus. transactions with addresses that fall outside this range forwarded upstream from secondary primary bus. range turned setting base address value greater than that limit address. When range turned off, trans-actions forwarded upstream, transactions forwarded downstream. range minimum granularity aligned boundary. maximum range size. base register consists 8-bit field configuration address 1Ch, 16-bit field address 30h. bits 8-bit field define bits [15:12] base address. bottom bits read only indicate that PI7C8152 supports 32-bit addressing. Bits [11:0] base address assumed which naturally aligns base address boundary. bits contained base upper bits register configuration offset define AD[31:16] base address. bits read/write. After primary reset chip reset, value base address initialized 0000 0000h. limit register consists 8-bit field configuration offset 16-bit field offset 32h. bits 8-bit field define bits [15:12] limit address. bottom bits read only indicate that 32-bit addressing supported. Bits [11:0] limit address assumed FFFh, which naturally aligns limit address address block. bits contained limit upper bits register configuration offset define AD[31:16] limit address. bits read/write. After primary reset chip reset, value limit address reset 0000 0FFFh. Note: initial states base limit address registers define range 0000 0000h 0000 0FFFh, which bottom space. Write these registers with their appropriate values before setting either enable master enable command register configuration space.
4.2.2
MODE
PI7C8152 supports mode providing enable bridge control register configuration space. mode modifies response PI7C8152 inside address range order support mapping space presence system. This only affects response PI7C8152 when transaction falls inside address range defined base limit address registers, only when this address also falls inside first 64KB space (address bits [31:16] 0000h). When enable set, PI7C8152 does forward downstream transactions addressing bytes each aligned block. Only those transactions addressing bottom bytes aligned block inside base limit address range forwarded downstream. Transactions above 64KB address boundary forwarded defined address range defined base limit registers. Accordingly, enable set, PI7C8152 forwards upstream those transactions addressing bytes each aligned block within first 64KB October 2002 Revision 1.00
PI7C8152 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION space. master enable command configuration register must also enable upstream forwarding. other transactions initiated secondary forwarded upstream only they fall outside address range. When enable set, devices downstream PI7C8152 have space mapped into first bytes each chunk below 64KB boundary, anywhere space above 64KB boundary.
MEMORY ADDRESS DECODING
PI7C8152 three mechanisms defining memory address ranges forwarding memory transactions: Memory-mapped base limit address registers Prefetchable memory base limit address registers mode
This section describes first mechanisms. Section 4.4.1 describes mode. enable downstream forwarding memory transactions, memory enable must command register configuration space. enable upstream forwarding memory transactions, master-enable must command register. master-enable also allows upstream forwarding transactions set. CAUTION configuration state affecting memory transaction forwarding changed configuration write operation primary same time that memory transactions ongoing secondary bus, response secondary memory transactions predictable. Configure memory-mapped base limit address registers, prefetchable memory base limit address registers, mode before setting memory enable master enable bits, change them subsequently only when primary secondary buses idle.
4.3.1
MEMORY-MAPPED BASE LIMIT ADDRESS REGISTERS
Memory-mapped also referred non-prefetchable memory. Memory addresses that cannot automatically pre-fetched that conditionally pre-fetched based command type should mapped into this space. Read transactions non-prefetchable space exhibit side effects; this space have non-memory-like behavior. PI7C8152 prefetches this space only memory read line memory read multiple commands used; transactions using memory read command limited single data transfer. memory-mapped base address memory-mapped limit address registers define address range that PI7C8152 uses determine when forward memory commands. PI7C8152 forwards memory transaction from primary secondary interface transaction address falls within memory-mapped address range. PI7C8152 ignores memory transactions initiated secondary interface that fall into this address range. transactions that fall outside this address range ignored primary interface forwarded upstream from secondary interface (provided that
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PI7C8152 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION they fall into prefetchable memory range forwarded downstream mechanism). memory-mapped range supports 32-bit addressing only. PCI-to-PCI Bridge Architecture Specification does provide 64-bit addressing memory-mapped space. memory-mapped address range granularity alignment 1MB. maximum memory-mapped address range 4GB. memory-mapped address range defined 16-bit memory-mapped base address register configuration offset 16-bit memory-mapped limit address register offset 22h. bits each these registers correspond bits [31:20] memory address. bits hardwired lowest bits memory-mapped base address assumed 0000h, which results natural alignment boundary. lowest bits memory-mapped limit address assumed FFFFFh, which results alignment block. Note: initial state memory-mapped base address register 0000 0000h. initial state memory-mapped limit address register 000F FFFFh. Note that initial states these registers define memory-mapped range bottom block memory. Write these registers with their appropriate values before setting either memory enable master enable command register configuration space. turn memory-mapped address range, write memory-mapped base address register with value greater than that memory-mapped limit address register.
4.3.2
PREFETCHABLE MEMORY BASE LIMIT ADDRESS REGISTERS
Locations accessed prefetchable memory address range must have true memory-like behavior must exhibit side effects when read. This means that extra reads prefetchable memory location must have side effects. PI7C8152 pre-fetches types memory read commands this address space. prefetchable memory base address prefetchable memory limit address registers define address range that PI7C8152 uses determine when forward memory commands. PI7C8152 forwards memory transaction from primary secondary interface transaction address falls within prefetchable memory address range. PI7C8152 ignores memory transactions initiated secondary interface that fall into this address range. PI7C8152 does respond transactions that fall outside this address range primary interface forwards those transactions upstream from secondary interface (provided that they fall into memory-mapped range forwarded mechanism). prefetchable memory range supports 64-bit addressing provides additional registers define upper bits memory address range, prefetchable memory base address upper bits register, prefetchable memory limit address upper bits register. address comparison, single address cycle (32-bit address) prefetchable memory transaction treated like 64-bit address transaction where upper bits address equal This upper 32-bit value compared prefetchable memory base address upper bits register prefetchable memory limit address
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PI7C8152 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION upper bits register. prefetchable memory base address upper bits register must pass single address cycle transactions downstream. Prefetchable memory address range granularity alignment 1MB. Maximum memory address range when 32-bit addressing being used. Prefetchable memory address range defined 16-bit prefetchable memory base address register configuration offset 16-bit prefetchable memory limit address register offset 26h. bits each these registers correspond bits [31:20] memory address. lowest bits hardwired lowest bits prefetchable memory base address assumed 0000h, which results natural alignment boundary. lowest bits prefetchable memory limit address assumed FFFFFh, which results alignment block. Note: initial state prefetchable memory base address register 0000 0000h. initial state prefetchable memory limit address register 000F FFFFh. Note that initial states these registers define prefetchable memory range bottom block memory. Write these registers with their appropriate values before setting either memory enable master enable command register configuration space. turn prefetchable memory address range, write prefetchable memory base address register with value greater than that prefetchable memory limit address register. entire base value must greater than entire limit value, meaning that upper bits must considered. Therefore, disable address range, upper bits registers both same value, while lower base register greater than lower limit register. Otherwise, upper 32-bit base must greater than upper 32bit limit.
SUPPORT
PI7C8152 provides modes support: mode, supporting VGA-compatible addressing snoop mode, supporting palette forwarding
4.4.1
MODE
When VGA-compatible device exists downstream from PI7C8152, mode bridge control register configuration space enable mode. When PI7C8152 operating mode, forwards downstream those transactions addressing frame buffer memory registers, regardless values base limit address registers. PI7C8152 ignores transactions initiated secondary interface addressing these locations. frame buffer consists following memory address range: 000A 0000h-000B FFFFh
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PI7C8152 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Read transactions frame buffer memory treated non-prefetchable. PI7C8152 requests only single data transfer from target, read byte enable bits forwarded target bus. addresses range 3B0h-3BBh 3C0h-3DFh I/O. These addresses aliases every throughout first 64KB space. This means that address bits [5:10] decoded value, while address bits [31:16] must 0's. BIOS addresses starting C0000h decoded mode.
4.4.2
SNOOP MODE
PI7C8152 provides snoop mode, allowing palette write transactions forwarded downstream. This mode used when graphics device downstream from PI7C8152 needs snoop respond palette write transactions. enable mode, snoop command register configuration space. Note that PI7C8152 claims palette write transactions asserting DEVSEL_L snoop mode. When snoop set, PI7C8152 forwards downstream transactions within 3C6h, 3C8h 3C9h addresses space. Note that these addresses also forwarded part compatibility mode previously described. Again, address bits [15:10] decoded, while address bits [31:16] must equal which means that these addresses aliases every throughout first 64KB space. Note: both mode snoop set, PI7C8152 behaves same only mode were set.
TRANSACTION ORDERING
maintain data coherency consistency, PI7C8152 complies with ordering rules forth Local Specification, Revision 2.2, transactions crossing bridge. This chapter describes ordering rules that control transaction forwarding across PI7C8152.
TRANSACTIONS GOVERNED ORDERING RULES
Ordering relationships established following classes transactions crossing PI7C8152: Posted write transactions, comprised memory write memory write invalidate transactions. Posted write transactions complete source before they complete destination; that data written into intermediate data buffers before reaches target. Delayed write request transactions, comprised write configuration write transactions. Delayed write requests terminated target retry initiator queued delayed transaction queue. delayed write transaction must complete target before completes initiator bus. October 2002 Revision 1.00
PI7C8152 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
Delayed write completion transactions, comprised write configuration write transactions. Delayed write completion transactions complete target bus, target response queued buffers. delayed write completion transaction proceeds direction opposite that original delayed write request; that delayed write completion transaction proceeds from target initiator bus. Delayed read request transactions, comprised memory read, read, configuration read transactions. Delayed read requests terminated target retry initiator queued delayed transaction queue. Delayed read completion transactions, comprised memory read, read, configuration read transactions. Delayed read completion transactions complete target bus, read data queued read data buffers. delayed read completion transaction proceeds direction opposite that original delayed read request; that delayed read completion transaction proceeds from target initiator bus. PI7C8152 does combine merge write transactions: PI7C8152 does combine separate write transactions into single write transaction-this optimization best implemented originating master. PI7C8152 does merge bytes separate masked write transactions same DWORD address-this optimization also best implemented originating master. PI7C8152 does collapse sequential write transactions same address into single write transaction-the Local Specification does permit this combining transactions.
GENERAL ORDERING GUIDELINES
Independent transactions primary secondary buses have relationship only when those transactions cross PI7C8152. following general ordering guidelines govern transactions crossing PI7C8152: ordering relationship transaction with respect other transactions determined when transaction completes, that when transaction ends with termination other than target retry. Requests terminated with target retry accepted completed order with respect other transactions that have been terminated with target retry. order completion delayed requests important, initiator should start second delayed transaction until first been completed. more than delayed transaction initiated, initiator should repeat delayed transaction requests, using some fairness algorithm. Repeating delayed transaction cannot contingent completion another delayed transaction. Otherwise, deadlock occur.
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PI7C8152 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Write transactions flowing direction have ordering requirements with respect write transactions flowing other direction. PI7C8152 accept posted write transactions both interfaces same time, well initiate posted write transactions both interfaces same time. acceptance posted memory write transaction target never contingent completion non-locked, non-posted transaction master. This true PI7C8152 must also true other agents. Otherwise, deadlock occur. PI7C8152 accepts posted write transactions, regardless state completion delayed transactions being forwarded across PI7C8152.
ORDERING RULES
Table shows ordering relationships transactions refers number ordering rules that follow. Table SUMMARY TRANSACTION ORDERING
Pass Posted Write Delayed Read Request Delayed Write Request Delayed Read Completion Delayed Write Completion Posted Write Delayed Read Request Yes5 Delayed Write Request Yes5 Delayed Read Completion Yes5 Delayed Write Completion Yes5
Note: superscript accompanying some table entries refers applicable ordering rule listed this section. Many entries governed these ordering rules; therefore, implementation choose whether transactions pass each other. entries without superscripts reflect PI7C8152's implementation choices. following ordering rules describe transaction relationships. Each ordering rule followed explanation, ordering rules referred number Table 5-1. These ordering rules apply posted write transactions, delayed write read requests, delayed write read completion transactions crossing PI7C8152 same direction. Note that delayed completion transactions cross PI7C8152 direction opposite that corresponding delayed requests. Posted write transactions must complete target order which they were received initiator bus. subsequent posted write transaction setting flag that covers data first posted write transaction; second transaction were complete before first transaction, device checking flag could subsequently consume stale data. delayed read request traveling same direction previously queued posted write transaction must push posted write data ahead posted write transaction must complete target before delayed read request attempted target bus. read transaction same location write data, read transaction were pass write transaction, would return stale data. October 2002 Revision 1.00
PI7C8152 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
delayed read completion must ``pull'' ahead previously queued posted write data traveling same direction. this case, read data traveling same direction write data, initiator read transaction same side PI7C8152 target write transaction. posted write transaction must complete target before read data returned initiator. read transaction reading status register initiator posted write data therefore should complete until write transaction complete. Delayed write requests cannot pass previously queued posted write data. posted memory write transactions, delayed write transaction flag that covers data posted write transaction. delayed write request were complete before earlier posted write transaction, device checking flag could subsequently consume stale data. Posted write transactions must given opportunities pass delayed read write requests completions. Otherwise, deadlocks occur when some bridges which support delayed transactions other bridges which support delayed transactions being used same system. fairness algorithm used arbitrate between posted write queue delayed transaction queue.
DATA SYNCHRONIZATION
Data synchronization refers relationship between interrupt signaling data delivery. Local Specification, Revision 2.2, provides following alternative methods synchronizing data interrupts: device signaling interrupt performs read data just written (software). device driver performs read operation register interrupting device before accessing data written device (software). System hardware guarantees that write buffers flushed before interrupts forwarded.
PI7C8152 does have hardware mechanism guarantee data synchronization posted write transactions. Therefore, posted write transactions must followed read operation, either from device location just written some other location along same path), from device driver device registers.
ERROR HANDLING
PI7C8152 checks, forwards, generates parity both primary secondary interfaces. maintain transparency, PI7C8152 always tries forward existing parity condition other bus, along with address data. PI7C8152 always attempts transparent when reporting errors, this always possible, given presence posted data delayed transactions. support error reporting bus, PI7C8152 implements following: October 2002 Revision 1.00
PI7C8152 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
PERR_L SERR_L signals both primary secondary interfaces Primary status secondary status registers device-specific P_SERR_L event disable register
This chapter provides detailed information about PI7C8152 handles errors. also describes error status reporting error operation disabling.
ADDRESS PARITY ERRORS
PI7C8152 checks address parity transactions both buses, address commands. When PI7C8152 detects address parity error primary interface, following events occur: parity error response command register, PI7C8152 does claim transaction with P_DEVSEL_L; this allow transaction terminate master abort. parity error response set, PI7C8152 proceeds normally accepts transaction directed across PI7C8152. PI7C8152 sets detected parity error status register. PI7C8152 asserts P_SERR_L sets signaled system error status register, both following conditions met: SERR_L enable command register. parity error response command register.
When PI7C8152 detects address parity error secondary interface, following events occur: parity error response bridge control register, PI7C8152 does claim transaction with S_DEVSEL_L; this allow transaction terminate master abort. parity error response set, PI7C8152 proceeds normally accepts transaction directed across PI7C8152. PI7C8152 sets detected parity error secondary status register. PI7C8152 asserts P_SERR_L sets signaled system error status register, both following conditions met: SERR_L enable command register. parity error response bridge control register.
DATA PARITY ERRORS
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PI7C8152 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION When forwarding transactions, PI7C8152 attempts pass data parity condition from interface other unchanged, whenever possible, allow master target devices handle error condition. following sections describe, each type transaction, sequence events that occurs when parity error detected which parity condition forwarded across PI7C8152.
6.2.1
CONFIGURATION WRITE TRANSACTIONS CONFIGURATION SPACE
When PI7C8152 detects data parity error during Type configuration write transaction PI7C8152 configuration space, following events occur: parity error response command register, PI7C8152 asserts P_TRDY_L writes data configuration register. PI7C8152 also asserts P_PERR_L. parity error response set, PI7C8152 does assert P_PERR_L. PI7C8152 sets detected parity error status register, regardless state parity error response bit.
6.2.2
READ TRANSACTIONS
When PI7C8152 detects parity error during read transaction, target drives data data parity, initiator checks parity conditionally asserts PERR_L. downstream transactions, when PI7C8152 detects read data parity error secondary bus, following events occur: PI7C8152 asserts S_PERR_L cycles following data transfer, secondary interface parity error response bridge control register. PI7C8152 sets detected parity error secondary status register. PI7C8152 sets data parity detected secondary status register, secondary interface parity error response bridge control register. PI7C8152 forwards parity with data back initiator primary bus. data with parity pre-fetched read initiator primary bus, data discarded data with parity returned initiator. PI7C8152 completes transaction normally.
upstream transactions, when PI7C8152 detects read data parity error primary bus, following events occur: PI7C8152 asserts P_PERR_L cycles following data transfer, primary interface parity error response command register. PI7C8152 sets detected parity error primary status register. October 2002 Revision 1.00
PI7C8152 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
PI7C8152 sets data parity detected primary status register, primary interface parity-error-response command register. PI7C8152 forwards parity with data back initiator secondary bus. data with parity pre-fetched read initiator secondary bus, data discarded data with parity returned initiator. PI7C8152 completes transaction normally.
PI7C8152 returns initiator data parity that received from target. When initiator detects parity error this read data enabled report initiator asserts PERR_L cycles after data transfer occurs. assumed that initiator takes responsibility handling parity error condition; therefore, when PI7C8152 detects PERR_L asserted while returning read data initiator, PI7C8152 does take further action completes transaction normally.
6.2.3
DELAYED WRITE TRANSACTIONS
When PI7C8152 detects data parity error during delayed write transaction, initiator drives data data parity, target checks parity conditionally asserts PERR_L. delayed write transactions, parity error occur following times: During original delayed write request transaction When initiator repeats delayed write request transaction When PI7C8152 completes delayed write transaction target
When delayed write transaction normally queued, address, command, address parity, data, byte enable bits, data parity captured target retry returned initiator. When PI7C8152 detects parity error write data initial delayed write request transaction, following events occur: parity-error-response corresponding initiator set, PI7C8152 asserts TRDY_L initiator transaction queued. multiple data phases requested, STOP_L also asserted cause target disconnect. cycles after data transfer, PI7C8152 also asserts PERR_L. parity-error-response set, PI7C8152 returns target retry. queues transaction usual. PI7C8152 does assert PERR_L. this case, initiator repeats transaction. PI7C8152 sets detected-parity-error status register corresponding initiator bus, regardless state parity-error-response bit.
Note: parity checking turned data parity errors have occurred queued subsequent delayed write transactions initiator bus, possible that initiator's re-attempts write transaction match original queued delayed write
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PI7C8152 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION information contained delayed transaction queue. this case, master timeout condition occur, possibly resulting system error (P_SERR_L assertion). downstream transactions, when PI7C8152 delivering data target secondary S_PERR_L asserted target, following events occur: PI7C8152 sets secondary interface data parity detected secondary status register, secondary parity error response bridge control register. PI7C8152 captures parity error condition forward back initiator primary bus.
Similarly, upstream transactions, when PI7C8152 delivering data target primary P_PERR_L asserted target, following events occur: PI7C8152 sets primary interface data-parity-detected status register, primary parity-error-response command register. PI7C8152 captures parity error condition forward back initiator secondary bus.
delayed write transaction completed initiator when initiator repeats write transaction with same address, command, data, byte enable bits delayed write command that head posted data queue. Note that parity compared when determining whether transaction matches those delayed transaction queues. cases must considered: When parity error detected initiator subsequent re-attempt transaction detected target When parity error forwarded back from target
downstream delayed write transactions, when parity error detected initiator PI7C8152 write status return, following events occur: PI7C8152 first asserts P_TRDY_L then asserts P_PERR_L cycles later, primary interface parity-error-response command register. PI7C8152 sets primary interface parity-error-detected status register. Because there exact data parity match, write status returned transaction remains queue.
Similarly, upstream delayed write transactions, when parity error detected initiator PI7C8152 write status return, following events occur: PI7C8152 first asserts S_TRDY_L then asserts S_PERR_L cycles later, secondary interface parity-error-response bridge control register (offset 3Ch). PI7C8152 sets secondary interface parity-error-detected secondary status register. October 2002 Revision 1.00
PI7C8152 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
Because there exact data parity match, write status returned transaction remains queue.
downstream transactions, where parity error being passed back from target parity error condition originally detected initiator bus, following events occur: PI7C8152 asserts P_PERR_L cycles after data transfer, following both true: parity-error-response command register primary interface. parity-error-response bridge control register secondary interface.
PI7C8152 completes transaction normally.
upstream transactions, when parity error being passed back from target parity error condition originally detected initiator bus, following events occur: PI7C8152 asserts S_PERR_L cycles after data transfer, following both true: parity error response command register primary interface. parity error response bridge control register secondary interface.
PI7C8152 completes transaction normally.
6.2.4
POSTED WRITE TRANSACTIONS
During downstream posted write transactions, when PI7C8152 responds target, detects data parity error initiator (primary) following events occur: PI7C8152 asserts P_PERR_L cycles after data transfer, parity error response command register primary interface. PI7C8152 sets parity error detected status register primary interface. PI7C8152 captures forwards parity condition secondary bus. PI7C8152 completes transaction normally.
Similarly, during upstream posted write transactions, when PI7C8152 responds target, detects data parity error initiator (secondary) bus, following events occur:
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PI7C8152 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION PI7C8152 asserts S_PERR_L cycles after data transfer, parity error response bridge control register secondary interface. PI7C8152 sets parity error detected status register secondary interface. PI7C8152 captures forwards parity condition primary bus. PI7C8152 completes transaction normally.
During downstream write transactions, when data parity error reported target (secondary) target's assertion S_PERR_L, following events occur: PI7C8152 sets data parity detected status register secondary interface, parity error response bridge control register secondary interface. PI7C8152 asserts P_SERR_L sets signaled system error status register, following conditions met: SERR_L enable command register. posted write parity error P_SERR_L event disable register set. parity error response bridge control register secondary interface. parity error response command register primary interface. PI7C8152 detected parity error primary (initiator) which parity error forwarded from primary secondary bus.
During upstream write transactions, when data parity error reported target (primary) target's assertion P_PERR_L, following events occur: PI7C8152 sets data parity detected status register, parity error response command register primary interface. PI7C8152 asserts P_SERR_L sets signaled system error status register, following conditions met: SERR_L enable command register. parity error response bridge control register secondary interface. parity error response command register primary interface.
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PI7C8152 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION PI7C8152 detected parity error secondary (initiator) bus, which parity error forwarded from secondary primary bus.
Assertion P_SERR_L used signal parity error condition when initiator does know that error occurred. Because data already been delivered with errors, there other signal this information back initiator. parity error forwarded from initiating target bus, P_SERR_L will asserted.
DATA PARITY ERROR REPORTING SUMMARY
previous sections, responses PI7C8152 data parity errors presented according type transaction progress. This section organizes responses PI7C8152 data parity errors according status bits that PI7C8152 sets signals that asserts. Table shows setting detected parity error status register, corresponding primary interface. This when PI7C8152 detects parity error primary interface. Table SETTING PRIMARY INTERFACE DETECTED PARITY ERROR
Primary Detected Parity Error don't care Transaction Type Direction Where Error Detected Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary/ Secondary Parity Error Response Bits
Read Read Read Read Posted Write Posted Write Posted Write Posted Write Delayed Write Delayed Write Delayed Write Delayed Write
Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream
Table shows setting detected parity error secondary status register, corresponding secondary interface. This when PI7C8152 detects parity error secondary interface. Table SETTING SECONDARY INTERFACE DETECTED PARITY ERROR
Secondary Detected Parity Error Transaction Type Direction Where Error Detected Primary Secondary Primary Secondary Primary Secondary Primary/ Secondary Parity Error Response Bits
Read Read Read Read Posted Write Posted Write
Downstream Downstream Upstream Upstream Downstream Downstream
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PI7C8152 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
don't care Posted Write Posted Write Delayed Write Delayed Write Delayed Write Delayed Write Upstream Upstream Downstream Downstream Upstream Upstream Primary Secondary Primary Secondary Primary Secondary
Table shows setting data parity detected primary interface's status register. This under following conditions: PI7C8152 must master primary bus. parity error response command register, corresponding primary interface, must set. P_PERR_L signal detected asserted parity error detected primary bus.
Table SETTING PRIMARY MASTER DATA PARITY ERROR DETECTED
Primary Parity Data Transaction Type Direction Where Error Detected Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Parity Error Response Bits
don't care
Read Read Read Read Posted Write Posted Write Posted Write Posted Write Delayed Write Delayed Write Delayed Write Delayed Write
Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream
Table shows setting data parity detected status register secondary interface. This under following conditions: PI7C8152 must master secondary bus. parity error response must bridge control register secondary interface. S_PERR_L signal detected asserted parity error detected secondary bus.
Table SETTING SECONDARY MASTER DATA PARITY ERROR DETECTED
Secondary Detected Parity Detected Transaction Type Direction Where Error Detected Primary Secondary Primary Primary Secondary Parity Error Response Bits
Read Read Read
Downstream Downstream Upstream
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PI7C8152 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
don't care Read Posted Write Posted Write Posted Write Posted Write Delayed Write Delayed Write Delayed Write Delayed Write Upstream Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary
Table shows assertion P_PERR_L. This signal under following conditions: PI7C8152 either target write transaction initiator read transaction primary bus. parity-error-response must command register primary interface. PI7C8152 detects data parity error primary detects S_PERR_L asserted during completion phase downstream delayed write transaction target (secondary) bus.
Table ASSERTION P_PERR_L
P_PERR# Transaction Type Direction Where Error Detected Primary/ Secondary Parity Error Response Bits
(de-asserted) Read Downstream Primary Read Downstream Secondary (asserted) Read Upstream Primary Read Upstream Secondary Posted Write Downstream Primary Posted Write Downstream Secondary Posted Write Upstream Primary Posted Write Upstream Secondary Delayed Write Downstream Primary Delayed Write Downstream Secondary Delayed Write Upstream Primary Delayed Write Upstream Secondary don't care parity error detected target (secondary) initiator (primary) bus.
Table shows assertion S_PERR_L that under following conditions: PI7C8152 either target write transaction initiator read transaction secondary bus. parity error response must bridge control register secondary interface. PI7C8152 detects data parity error secondary detects P_PERR_L asserted during completion phase upstream delayed write transaction target (primary) bus.
Table ASSERTION S_PERR_L
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PI7C8152 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
S_PERR# Transaction Type Direction Where Error Detected Primary/ Secondary Parity Error Response Bits
(de-asserted) Read Downstream Primary (asserted) Read Downstream Secondary Read Upstream Primary Read Upstream Secondary Posted Write Downstream Primary Posted Write Downstream Secondary Posted Write Upstream Primary Posted Write Upstream Secondary Delayed Write Downstream Primary Delayed Write Downstream Secondary Delayed Write Upstream Primary Delayed Write Upstream Secondary don't care parity error detected target (secondary) initiator (primary) bus.
Table shows assertion P_SERR_L. This signal under following conditions: PI7C8152 detected P_PERR_L asserted upstream posted write transaction S_PERR_L asserted downstream posted write transaction. PI7C8152 detect parity error target posted write transaction. parity error response command register parity error response bridge control register must both set. SERR_L enable must command register.
Table ASSERTION P_SERR_L DATA PARITY ERRORS
P_SERR# Transaction Type Direction Where Error Detected Primary Secondary Parity Error Response Bits
(de-asserted) Read Downstream Primary Read Downstream Secondary Read Upstream Primary Read Upstream Secondary Posted Write Downstream Primary (asserted) Posted Write Downstream Secondary Posted Write Upstream Primary Posted Write Upstream Secondary Delayed Write Downstream Primary Delayed Write Downstream Secondary Delayed Write Upstream Primary Delayed Write Upstream Secondary don't care parity error detected target (secondary) initiator (primary) bus. parity error detected target (primary) initiator (secondary) bus.
SYSTEM ERROR (SERR_L) REPORTING
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PI7C8152 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION PI7C8152 uses P_SERR_L signal report conditionally number system error conditions addition special case parity error conditions described Section 6.2.3. Whenever assertion P_SERR_L discussed this document, assumed that following conditions apply: PI7C8152 assert P_SERR_L reason, SERR_L enable must command register. Whenever PI7C8152 asserts P_SERR_L, PI7C8152 must also signaled system error status register.
compliance with PCI-to-PCI Bridge Architecture Specification, PI7C8152 asserts P_SERR_L when detects secondary SERR_L input, S_SERR_L, asserted SERR_L forward enable bridge control register. addition, PI7C8152 also sets received system error secondary status register. PI7C8152 also conditionally asserts P_SERR_L following reasons: Target abort detected during posted write transaction Master abort detected during posted write transaction Posted write data discarded after (default) attempts deliver (224 target retries received) Parity error reported target during posted write transaction (see previous section) Delayed write data discarded after (default) attempts deliver (224 target retries received) Delayed read data cannot transferred from target after (default) attempts (224 target retries received) Master timeout delayed transaction
device-specific P_SERR_L status register reports reason assertion P_SERR_L. Most these events have additional device-specific disable bits P_SERR_L event disable register that make possible mask P_SERR_L assertion specific events. master timeout condition SERR_L enable that event bridge control register therefore does have device-specific disable bit.
EXCLUSIVE ACCESS
This chapter describes LOCK_L signal implement exclusive access target transactions that cross PI7C8152.
CONCURRENT LOCKS
October 2002 Revision 1.00
PI7C8152 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION primary secondary lock mechanisms operate concurrently except when locked transaction crosses PI7C8152. primary master lock primary target without affecting status lock secondary bus, vice versa. This means that primary master lock primary target same time that secondary master locks secondary target.
ACQUIRING EXCLUSIVE ACCESS ACROSS PI7C8152
bus, before acquiring access LOCK_L signal starting series locked transactions, initiator must first check that both following conditions met: must idle. LOCK_L signal must de-asserted.
initiator leaves LOCK_L signal de-asserted during address phase asserts LOCK_L clock cycle later. Once data transfer completed from target, target lock been achieved.
7.2.1
LOCKED TRANSACTIONS DOWNSTREAM DIRECTION
Locked transactions cross PI7C8152 only downstream direction, from primary secondary bus. When target resides another bus, master must acquire only lock also lock every between target's bus. When PI7C8152 detects primary bus, initial locked transaction intended target secondary bus, PI7C8152 samples address, transaction type, byte enable bits, parity, described Section 3.7.4. also samples lock signal. there lock established between ports target already locked another master, then current lock cycle retried without forward. Because target retry signaled initiator, initiator must relinquish lock primary bus, therefore lock established. first locked transaction must memory read transaction. Subsequent locked transactions memory read memory write transactions. Posted memory write transactions that part locked transaction sequence still posted. Memory read transactions that part locked transaction sequence pre-fetched. When locked delayed memory read request queued, PI7C8152 does queue more transactions until locked sequence finished. PI7C8152 signals target retry transactions initiated subsequent locked read transaction that intended targets other side PI7C8152. PI7C8152 allows transactions queued before locked transaction complete before initiating locked transaction. When locked delayed memory read request transaction moves head delayed transaction queue, PI7C8152 initiates transaction locked read transaction de-asserting LOCK_L target during first address phase, asserting LOCK_L cycle later. LOCK_L already asserted (used another initiator), PI7C8152 waits
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