2-PORT PCI-X BRIDGE REVISION 1.04 3545 NORTH FIRST STREET JOSE, 9
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PI7C21P100
2-PORT PCI-X BRIDGE REVISION 1.04
3545 NORTH FIRST STREET JOSE, 95134 1-877-PERICOM (1-877-737-4266) FAX: 1-408-435-1100 EMAIL: SOLUTIONS@PERICOM.COM INTERNET: HTTP://WWW.PERICOM.COM
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
REVISION HISTORY
Date 12/04/03 12/11/03 01/22/04 Revision Number 1.00 1.01 1.02 Description First Release Data Sheet Minor text corrections made. Addition Features section well couple tables. Text corrections. Corrected Device Register bits 11:0 description. Corrected designation P_RST section 3.2.1
02/02/04 03/15/04
1.03 1.04
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
TABLE CONTENTS
DESCRIPTION FEATURES SIGNAL DEFINITIONS SIGNAL TYPES. SIGNALS 3.2.1 PRIMARY INTERFACE SIGNALS 3.2.2 PRIMARY INTERFACE SIGNALS 64-BIT EXTENSION 3.2.3 SECONDARY INTERFACE SIGNALS 3.2.4 SECONDARY INTERFACE SIGNALS 64-BIT EXTENSION 3.2.5 CLOCK SIGNALS 3.2.6 STRAPPING PINS MISCELLANEOUS SIGNALS. 3.2.7 JTAG BOUNDARY SCAN TEST SIGNALS. 3.2.8 TEST SIGNALS 3.2.9 POWER GROUND SIGNALS LIST. OPERATION TYPES TRANSACTIONS WRITE TRANSACTIONS. 4.2.1 MEMORY WRITE TRANSACTIONS
4.2.1.1 4.2.1.2 4.2.1.3 4.2.1.4 PCI-X PCI-X.24 PCI-X PCI-X PCI.25
4.2.2 DELAYED/SPLIT WRITE TRANSACTIONS 4.2.3 IMMEDIATE WRITE TRANSACTIONS READ TRANSACTIONS 4.3.1 MEMORY READ TRANSACTIONS
4.3.1.1 4.3.1.2 4.3.1.3 4.3.1.4 PCI-X PCI-X.26 PCI-X PCI-X PCI.27
4.3.2 4.3.3 4.3.4 4.3.5
READ CONFIGURATION READ.
TYPE CONFIGURATION READ.27 TYPE CONFIGURATION READ.27
4.3.3.1 4.3.3.2
NON-PREFETCHABLE DWORD READS PREFETCHABLE READS
PCI-X PCI-X PCI-X PCI.28 PCI-X
4.3.5.1 4.3.5.2 4.3.5.3
4.3.6 DYNAMIC PREFETCH (CONVENTIONAL MODE ONLY) CONFIGURATION TRANSACTIONS. 4.4.1 TYPE ACCESS PI7C21P100 4.4.2 TYPE TYPE CONVERSION. 4.4.3 TYPE TYPE FORWARDING 4.4.4 SPECIAL CYCLES. TRANSACTION ORDERING. GENERAL ORDERING GUIDELINES ORDERING RULES
CLOCKS Page March 2004 Revision 1.04
PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION PRIMARY SECONDARY CLOCK INPUTS. CLOCK JITTER MODE CLOCK FREQUENCY DETERMINATION. 6.3.1 PRIMARY BUS. 6.3.2 SECONDARY BUS. 6.3.3 CLOCK STABILITY 6.3.4 DRIVER IMPEDANCE SELECTION RESET. PRIMARY INTERFACE RESET. SECONDARY INTERFACE RESET PARKING WIDTH DETERMINATION. SECONDARY DEVICE MASKING ADDRESS PARITY ERRORS. OPTIONAL BASE ADDRESS REGISTER. OPTIONAL CONFIGURATION ACCESS FROM SECONDARY SHORT TERM CACHING
CONFIGURATION REGISTERS CONFIGURATION REGISTER SPACE
8.1.1.1 SIGNAL TYPE DEFINITION
8.1.2 8.1.3 8.1.4 8.1.5 8.1.6 8.1.7 8.1.8 8.1.9 8.1.10 8.1.11 8.1.12 8.1.13 8.1.14 8.1.15 8.1.16 8.1.17 8.1.18 8.1.19 8.1.20 8.1.21 8.1.22 8.1.23 8.1.24 8.1.25 8.1.26 8.1.27 8.1.28 8.1.29 8.1.30 8.1.31 8.1.32 8.1.33 8.1.34 8.1.35
VENDOR REGISTER OFFSET DEVICE REGISTER OFFSET 00h. COMMAND REGISTER OFFSET PRIMARY STATUS REGISTER OFFSET 04h. REVISION REGISTER OFFSET CLASS CODE REGISTER OFFSET CACHE LINE SIZE REGISTER OFFSET 0Ch. PRIMARY LATENCY TIMER OFFSET 0Ch. HEADER TYPE REGISTER OFFSET BIST REGISTER OFFSET 0Ch. LOWER MEMORY BASE ADDRESS REGISTER OFFSET UPPER MEMORY BASE ADDRESS REGISTER OFFSET PRIMARY NUMBER REGISTER OFFSET SECONDARY NUMBER REGISTER OFFSET SUBORDINATE NUMBER REGISTER OFFSET SECONDARY LATENCY TIMER REGISTER OFFSET BASE ADDRESS REGISTER OFFSET LIMIT REGISTER OFFSET SECONDARY STATUS REGISTER OFFSET MEMORY BASE REGISTER OFFSET 20h. MEMORY LIMIT REGISTER OFFSET PREFETCHABLE MEMORY BASE REGISTER OFFSET PREFETCHABLE MEMORY LIMIT REGISTER OFFSET PREFETCHABLE BASE UPPER 32-BIT REGISTER OFFSET 28h. PREFETCHABLE LIMIT UPPER 32-BIT REGISTER OFFSET BASE UPPER 16-BIT REGISTER OFFSET LIMIT UPPER 16-BIT REGISTER OFFSET 30h. CAPABILITY POINTER OFFSET EXPANSION BASE ADDRESS REGISTER OFFSET INTERRUPT LINE REGISTER OFFSET INTERRUPT REGISTER OFFSET BRIDGE CONTROL REGISTER OFFSET PRIMARY DATA BUFFERING CONTROL REGISTER OFFSET SECONDARY DATA BUFFERING CONTROL REGISTER OFFSET Page March 2004 Revision 1.04
PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION 8.1.36 8.1.37 8.1.38 8.1.39 8.1.40 8.1.41 8.1.42 8.1.43 8.1.44 8.1.45 8.1.46 8.1.47 8.1.48 8.1.49 8.1.50 8.1.51 8.1.52 8.1.53 8.1.54 8.1.55 8.1.56 8.1.57 8.1.58 8.1.59 8.1.60 8.1.61 8.1.62 8.1.63 8.1.64 MISCELLANEOUS CONTROL REGISTER OFFSET EXTENDED CHIP CONTROL REGISTER OFFSET EXTENDED CHIP CONTROL REGISTER OFFSET ARBITER MODE REGISTER OFFSET ARBITER ENABLE REGISTER OFFSET ARBITER PRIORITY REGISTER OFFSET SERR# DISABLE REGISTER OFFSET 5Ch. PRIMARY RETRY COUNTER REGISTER OFFSET SECONDARY RETRY COUNTER REGISTER OFFSET DISCARD TIMER CONTROL REGISTER OFFSET RETRY TIMER STATUS REGISTER OFFSET 6Ch. OPAQUE MEMORY ENABLE REGISTER OFFSET OPAQUE MEMORY BASE REGISTER OFFSET 74h. OPAQUE MEMORY LIMIT REGISTER OFFSET 74h. OPAQUE MEMORY BASE UPPER 32-BIT REGISTER OFFSET 78h. OPAQUE MEMORY LIMIT UPPER 32-BIT REGISTER OFFSET PCI-X CAPABILITY REGISTER OFFSET NEXT CAPABILITY POINTER REGISTER OFFSET 80h. PCI-X SECONDARY STATUS REGISTER OFFSET PCI-X BRIDGE PRIMARY STATUS REGISTER OFFSET 84h. SECONDARY UPSTREAM SPLIT TRANSACTION REGISTER OFFSET 88h. PRIMARY DOWNSTREAM SPLIT TRANSACTION REGISTER OFFSET POWER MANAGEMENT REGISTER OFFSET NEXT CAPABILITIES POINTER REGISTER OFFSET POWER MANAGEMENT CAPABILITIES REGISTER OFFSET POWER MANAGEMENT CONTROL STATUS REGISTER OFFSET 94h. PCI-TO-PCI BRIDGE SUPPORT EXTENSION REGISTER OFFSET SECONDARY PRIVATE DEVICE MASK REGISTER OFFSET MISCELLANEOUS CONTROL REGISTER OFFSET B8h.
IEEE 1149.1 COMPATIBLE JTAG CONTROLLER INSTRUCTION REGISTER. BYPASS REGISTER DEVICE REGISTER. BOUNDARY SCAN REGISTER. JTAG BOUNDARY REGISTER ORDER
ELECTRICAL INFORMATION 10.1 10.2 10.3 10.4 MAXIMUM RATINGS. SPECIFICATIONS SPECIFICATIONS POWER CONSUMPTION.
MECHANICAL INFORMATION ORDERING INFORMATION
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
LIST TABLES
TABLE LIST 304-PIN PBGA TABLE PCI-X TRANSACTIONS. TABLE WRITE TRANSACTION FORWARDING. TABLE READ TRANSACTIN HANDLING TABLE DEVICE NUMBER IDSEL TABLE SUMMARY TRANSACTION ORDERING MODE. TABLE SUMMARY TRANSACTION ORDERING PCI-X MODE. TABLE PROGRAMMABLE PULL-UP CIRCUIT TABLE DRIVER IMPEDANCE SELECTION TABLE DELAY TIMES DE-ASSERTION S_RST#. TABLE DE-ASSERTION S_RST# TABLE CONFIGURATION SPACE TABLE JTAG BOUNDARY SCAN REGISTER TABLE 10-1 TIMING SPECIFICATIONS PCI-X MODE TABLE 10-2 TIMING SPECIFICATIONS CONVENTIONAL MODE
LIST FIGURES
FIGURE 10-1 SIGNAL TIMING MEASUREMENTS. FIGURE 11-1 PACKAGE DIAGRAM 31MM 304-PIN HPBGA
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
DESCRIPTION
PI7C21P100 2-port PCI-X Bridge designed compliant with PCI-X Addendum Local Specification Revision 1.0a. PI7C21P100 able handle 64-bit data maximum frequency 133MHz. PI7C21P100 designed high speed applications such Ethernet, SCSI, Fibre Channel. PI7C21P100 also used expansion, frequency isolations/translations, PCI-X isolations/translations.
FEATURES
INDUSTRY STANDARDS COMPLIANCE PCI-X Addendum Local Specification Revision 1.0a (Mode only) Local Specification Revision PCI-to-PCI Bridge Architecture Specification Revision Power Management Interface Specification Revision Supports power states INTERFACE 3.3V signaling with tolerance 133MHz 64-bit operation both buses Dual address cycle support Concurrent primary secondary operation Primary secondary either mode PCI-X Mode Asynchronous operation support Programmable internal arbiter with support external masters secondary Internal arbiter disabled external arbiter IEEE 1149.1 JTAG support OPERATION Type Type configuration support Configuration register access from both primary secondary buses buffering upstream memory burst read commands buffering downstream memory burst read commands buffering upstream posted memory write commands buffering downstream posted memory write commands Support active transactions each direction ADDITIONAL FEATURES Capabilities pointer Ability define opaque memory address Definable base address register Secondary side PCI-X device privatization PACKAGING 304-pin PBGA,
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
SIGNAL DEFINITIONS
SIGNAL TYPES
Signal Type Description Input Only Output Only Power Tri-State bi-directional Sustained Tri-State. Active signal must pulled HIGH cycle when deasserting. Open Drain Internal pull-up signal Internal pull-down signal
SIGNALS
Signal names that with active LOW.
3.2.1
PRIMARY INTERFACE SIGNALS
Name P_AD[31:0] J23, M21, M22, L21, L22, G23, K20, E23, K21, D23, K22, J21, J22, H21, H22, G21, B20, G22, F20, F22, D18, C19, C17, B17, A20, C16, B16, A19, C15, B14, C13, A15, D14, B18, Type Description Primary Address Data: Multiplexed address data bus. Address indicated P_FRAME# assertion. Write data stable valid when P_IRDY# asserted read data stable valid when P_TRDY# asserted. Data transferred rising clock edges when both P_IRDY# P_TRDY# asserted. During idle, PI7C21P100 drives P_AD[31:0] valid logic level when P_GNT# asserted. Primary Command/Byte Enables: Multiplexed command field byte enable field. During address phase, initiator drives transaction type these pins. After that, initiator drives byte enables during data phases. During idle, PI7C21P100 drives P_CBE[3:0]# valid logic level when P_GNT# asserted. Primary Parity. P_PAR even parity P_AD[31:0] P_CBE[3:0] (i.e. even number 1's). P_PAR valid stable cycle after address phase (indicated assertion P_FRAME#) address parity. write data phases, P_PAR valid clock after P_IRDY# asserted. read data phase, P_PAR valid clock after P_TRDY# asserted. Signal P_PAR tri-stated cycle after P_AD lines tri-stated. During idle, PI7C21P100 drives P_PAR valid logic level when P_GNT# asserted. Primary FRAME (Active LOW). Driven initiator transaction indicate beginning duration access. de-assertion P_FRAME# indicates final data phase requested initiator. Before being tri-stated, driven HIGH cycle. Primary IRDY (Active LOW). Driven initiator transaction indicate ability complete current data phase primary side. Once asserted data phase, de-asserted until data phase. Before tri-stated, driven HIGH cycle.
P_CBE[3:0]#
P_PAR
P_FRAME#
P_IRDY#
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
Name P_TRDY# Type Description Primary TRDY (Active LOW). Driven target transaction indicate ability complete current data phase primary side. Once asserted data phase, de-asserted until data phase. Before tri-stated, driven HIGH cycle. Primary Device Select (Active LOW). Asserted target indicating that device accepting transaction. master, PI7C21P100 waits assertion this signal within cycles P_FRAME# assertion; otherwise, terminate with master abort. Before tri-stated, driven HIGH cycle. Primary STOP (Active LOW). Asserted target indicating that target requesting initiator stop current transaction. Before tri-stated, driven HIGH cycle. Primary LOCK (Active LOW). Asserted initiator, clock cycle after first address phase transaction, attempting perform operation that take more than transaction complete. Primary Select. Used chip select line Type configuration access PI721P100 configuration space. Primary Parity Error (Active LOW). Asserted when data parity error detected data received primary interface. Before being tri-stated, driven HIGH cycle. Primary System Error (Active LOW). driven device indicate system error condition. PI7C21P100 drives this Address parity error Posted write data parity error target Secondary S_SERR# asserted Master abort during posted write transaction Target abort during posted write transaction Posted write transaction discarded Delayed write request discarded Delayed read request discarded Delayed transaction master timeout This signal requires external pull-up resistor proper operation. Primary Request (Active LOW): This asserted PI7C21P100 indicate that wants start transaction primary bus. PI7C21P100 de-asserts this least clock cycles before asserting again. Primary Grant (Active LOW): When asserted, PI7C21P100 access primary bus. During idle P_GNT# asserted, PI7C21P100 will drive P_AD, P_CBE, P_PAR valid logic levels. Primary RESET (Active LOW): When P_RESET# active, signals should asynchronously tristated.
P_DEVSEL#
P_STOP#
P_LOCK#
P_IDSEL
P_PERR#
P_SERR#
P_REQ#
P_GNT#
P_RST#
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
3.2.2
PRIMARY INTERFACE SIGNALS 64-BIT EXTENSION
Name P_AD[63:32] B11, D10, C10, B10, Type Description Primary Upper 32-bit Address Data: Multiplexed address data providing additional bits primary. When dual address command used P_REQ64# asserted, initiator drives upper bits 64-bit address. Otherwise, these bits undefined driven valid logic levels. During data phase transaction, initiator drives upper bits 64-bit write data, target drives upper bits 64-bit read data, when P_REQ64# P_ACK64# both asserted. Otherwise, these bits pulled valid logic level through external resistors. Primary Upper 32-bit Command/Byte Enables: Multiplexed command field byte enable field. During address phase, when dual address command used P_REQ64# asserted, initiator drives transaction type these pins. Otherwise, these bits undefined, initiator drives valid logic level onto pins. read write transactions, initiator drives these bits P_AD[63:32] data bits when P_REQ64# P_ACK64# both asserted. When driven, these bits pulled valid logic level through external resistors. Primary Upper 32-bit Parity: P_PAR64 carries even parity P_AD[63:32] P_CBE[7:4] both address data phases. P_PAR64 driven initiator valid cycle after first address phase when dual address command used P_REQ64# asserted. P_PAR64 valid clock cycle after second address phase dual address transaction when P_REQ64# asserted. P_PAR64 valid cycle after valid data driven when both P_REQ64# P_ACK64# asserted that data phase. P_PAR64 driven device driving read write data cycle after P_AD lines driven. P_PAR64 tri-stated cycle after P_AD lines tri-stated. Devices receive data sample P_PAR64 input check possible parity errors during 64-bit transactions. When driven, P_PAR64 pulled valid logic level through external resistors. Primary 64-bit Transfer Request: P_REQ64# asserted initiator indicate that initiator requesting 64-bit data transfer. P_REQ64# same timing P_FRAME#. When P_REQ64# asserted during reset, 64-bit data path supported. When P_REQ64# HIGH during reset, PI7C21P100 drives P_AD[63:32], P_CBE[7:4], P_PAR64 valid logic levels. When deasserting, P_REQ64# driven HIGH cycle then sustained external pull-up resistor. Primary 64-bit Transfer Acknowledge: P_ACK64# asserted target only when P_REQ64# asserted initiator indicate target's ability transfer data using bits. P_ACK64# same timing P_DEVSEL#. When deasserting, P_ACK64# driven HIGH cycle then sustained external pull-up resistor.
P_CBE[7:4]#
B12, C11,
P_PAR64
P_REQ64#
P_ACK64#
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
3.2.3
SECONDARY INTERFACE SIGNALS
Name S_AD[31:0] N22, N21, P22, P21, M23, P20, N23, R22, T23, R21, W23, T22, U22, U21, V22, V21, W21, V20, AA20, AB18, Y18, AA16, AB15, AC17, AA13, AA12, AC15, AB11, AC11, AC9, AB9, AA15, AB14, AB16, AB12 Type Description Secondary Address/Data: Multiplexed address data bus. Address indicated S_FRAME# assertion. Write data stable valid when S_IRDY# asserted read data stable valid when S_IRDY# asserted. Data transferred rising clock edges when both S_IRDY# S_TRDY# asserted. During idle, PI7C21P100 drives S_AD[31:0] valid logic level when bridge granted bus.
S_CBE[3:0]#
S_PAR
AA17
S_FRAME#
AA14
S_IRDY#
AC19
S_TRDY#
S_DEVSEL#
AC21
S_STOP#
AB20
S_LOCK#
AC20
S_PERR#
AB17
Secondary Command/Byte Enables: Multiplexed command field byte enable field. During address phase, initiator drives transaction type these pins. initiator then drives byte enables during data phases. During idle, PI7C21P100 drives S_CBE[3:0] valid logic level when bridge granted bus. Secondary Parity: S_PAR even parity S_AD[31:0] S_CBE[3:0] (i.e. even number 1's). S_PAR valid stable cycle after address phase (indicated assertion S_FRAME#) address parity. write data phases, S_PAR valid clock after S_IRDY# asserted. read data phase, S_PAR valid clock after S_TRDY# asserted. Signal S_PAR tri-stated cycle after S_AD lines tri-stated. During idle, PI7C21P100 drives S_PAR valid logic level when bridge granted bus. Secondary FRAME (Active LOW): Driven initiator transaction indicate beginning duration access. de-assertion S_FRAME# indicates final data phase requested initiator. Before being tri-stated, driven HIGH cycle. Secondary IRDY (Active LOW): Driven initiator transaction indicate ability complete current data phase secondary side. Once asserted data phase, de-asserted until data phase. Before tri-stated, driven HIGH cycle. Secondary TRDY (Active LOW): Driven target transaction indicate ability complete current data phase secondary side. Once asserted data phase, de-asserted until data phase. Before tri-stated, driven HIGH cycle. Secondary Device Select (Active LOW): Asserted target indicating that device accepting transaction. master, PI7C21P100 waits assertion this signal within cycles S_FRAME# assertion; otherwise, terminate with master abort. Before tri-stated, driven HIGH cycle. Secondary STOP (Active LOW): Asserted target indicating that target requesting initiator stop current transaction. Before tri-stated, driven HIGH cycle. Secondary LOCK (Active LOW): Asserted initiator, clock cycle after first address phase transaction, when propagating locked transaction downstream. PI7C21P100 does propagate locked transactions upstream. Secondary Parity Error (Active LOW): Asserted when data parity error detected data received secondary interface. Before being tri-stated, driven HIGH cycle.
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
Name S_SERR# AB19 Type Description Secondary System Error (Active LOW): driven device indicate system error condition. Secondary Request (Active LOW): This asserted external device indicate that wants start transaction secondary bus. input externally pulled through resistor VDD. Secondary Request (Active LOW): When internal arbiter enabled, this asserted external device indicate that wants start transaction secondary bus. input externally pulled through resistor VDD. When internal arbiter disabled, this used PI7C21P100 input. Secondary Grant (Active LOW): PI7C21P100 asserts these pins allow external masters access secondary bus. PI7C21P100 de-asserts these pins least clock cycles before asserting again. During idle S_GNT# deasserted, PI7C21P100 will drive S_AD, S_CBE, S_PAR. Secondary Grant (Active LOW): When internal arbiter enabled, PI7C21P100 asserts this allow external masters access secondary bus. PI7C21P100 de-asserts this least clock cycles before asserting again. During idle S_GNT# deasserted, PI7C21P100 will drive S_AD, S_CBE, S_PAR. When internal arbiter disabled, this used PI7C21P100 output. Secondary RESET (Active LOW): Asserted when following conditions met: Signal P_RESET# asserted. Secondary reset bridge control register configuration space set. chip reset chip control register configuration space set. When asserted, control signals tri-stated zeroes driven S_AD, S_CBE, S_PAR, S_PAR64.
S_REQ[6:2]#
AC3, AB5, AB3,
S_REQ[1]#
AA23
S_GNT[6:2]#
AC4, AB4, AC5,
S_GNT[1]#
AA19
S_RST#
3.2.4
SECONDARY INTERFACE SIGNALS 64-BIT EXTENSION
Name S_AD[63:32] AB8, AB7, AA7, AB6, AA6, AA5, Y10, AB10, AA11, Type Description Secondary Upper 32-bit Address/Data: Multiplexed address data bus. Address indicated S_FRAME# assertion. Write data stable valid when S_IRDY# asserted read data stable valid when S_IRDY# asserted. Data transferred rising clock edges when both S_IRDY# S_TRDY# asserted. During idle, PI7C21P100 drives S_AD valid logic level when bridge granted bus. Secondary Upper 32-bit Command/Byte Enables: Multiplexed command field byte enable field. During address phase, initiator drives transaction type these pins. initiator then drives byte enables during data phases. During idle, PI7C21P100 drives S_CBE[7:0] valid logic level when bridge granted bus.
S_CBE[7:4]#
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
Name S_PAR64 AA10 Type Description Secondary Upper 32-bit Parity: S_PAR64 carries even parity S_AD[63:32] S_CBE[7:4] both address data phases. S_PAR64 driven initiator valid cycle after first address phase when dual address command used S_REQ64# asserted. S_PAR64 valid clock cycle after second address phase dual address transaction when S_REQ64# asserted. S_PAR64 valid cycle after valid data driven when both S_REQ64# S_ACK64# asserted that data phase. S_PAR64 driven device driving read write data cycle after S_AD lines driven. S_PAR64 tri-stated cycle after S_AD lines tri-stated. Devices receive data sample S_PAR64 input check possible parity errors during 64-bit transactions. When driven, S_PAR64 pulled valid logic level through external resistors. Secondary 64-bit Transfer Request: S_REQ64# asserted initiator indicate that initiator requesting 64-bit data transfer. S_REQ64# same timing S_FRAME#. When S_REQ64# asserted during reset, 64-bit data path supported. When S_REQ64# HIGH during reset, PI7C21P100 drives S_AD[63:32], S_CBE[7:4], S_PAR64 valid logic levels. When deasserting, S_REQ64# driven deasserted state cycle then sustained external pull-up resistor. Secondary 64-bit Transfer Acknowledge: S_ACK64# asserted target only when S_REQ64# asserted initiator indicate target's ability transfer data using bits. S_ACK64# same timing S_DEVSEL#. When deasserting, S_ACK64# driven deasserted state cycle then sustained external pull-up resistor.
S_REQ64#
AB13
S_ACK64#
3.2.5
CLOCK SIGNALS
Name P_CLK Type Description Primary Clock Input: Provides timing transactions primary interface. conventional mode, input clock frequency between 66MHz. PCI-X mode, input clock frequency between 133MHz. Section limitations. Secondary Clock Input: Provides timing transactions secondary interface. conventional mode, input clock frequency between 66MHz. PCI-X mode, input clock frequency between 133MHz. Section limitations. primary running 133MHz, minimum frequency that supplied S_CLK 33MHz.
S_CLK
AB23
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
3.2.6
STRAPPING PINS MISCELLANEOUS SIGNALS
Name S_ARB# Type Description Internal Arbiter Enable: This used PI7C21P100 determine whether secondary uses internal arbiter external arbiter. Enable internal arbiter Disable internal arbiter external arbiter Secondary Maximum Frequency: This used determine maximum frequency secondary when PCI-X mode. mode, function should left floating. secondary interface 133MHz secondary interface 100MHz Secondary PCI-X Capable: This used with S_SEL100 determine frequency mode secondary bus. There three conditions this determining capability secondary bus: Ground: capable PCI-X mode Pull-down: PCI-X 66MHz connected: PCI-X 133MHz S_PCIXCAP Pull-up Driver: This used with S_PCIXAP part programmable pull-up circuit determine state S_PCIXCAP. 1kohm resistor must placed between this S_PCIXCAP. Secondary Driver Mode: This controls output impedance secondary drivers account number loads secondary bus. default impedance select alternate impedance Table impedance values. Primary Driver Mode Control: Controls output impedance primary drivers account number loads primary bus. Default impedance Select alternate impedance S_CLK Input Stable: Determines when S_CLK stable resolve when S_RST# de-asserted. S_CLK stable S_CLK stable Initialization Device Select: S_IDSEL used chip select during configuration reads writes secondary bus. Applications that require access PI7C21P100's configuration registers from secondary side should pull this LOW.
S_SEL100
S_PCIXCAP
S_PCIXCAP_PU
S_DRVR
P_DRVR
S_CLK_STABLE
S_IDSEL
AA22
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
64BIT_DEV# PCI-X Device Width: 64BIT_DEV# sets PCI-X Bridge Status Register support system management software. This signal does change behavior bridge. Sets PCI-X bridge status register Sets PCI-X bridge status register Base Address Register Enable: BAR_EN used enable base address reset power When enabled, 64-bit register offset offset used claim memory region. Disabled register returns memory region claimed Enabled bits 63:20 written software claim memory region IDSEL Reroute Enable: Controls IDSEL reroute function reset power reset value secondary private device mask register changed according value this pin. Reset value secondary private device mask register 00000000h Reset value secondary private device mask register 22F20000h Opaque Region Enable: Used enable opaque memory region reset power Controls bit[0] offset 70h. Disable opaque memory address range Enable opaque memory address range Primary Configuration Busy: Determines value offset sequence initialization primary secondary buses applications that require bridge configuration from secondary bus. Applications that require configuration from secondary should pull this down ground. Type configuration commands accepted normally primary bus. Type configuration commands retried primary accepted secondary bus. Reserved. Must tied ground.
BAR_EN
IDSEL_ROUTE
AC22
OPAQUE_EN
AA18
P_CFG_BUSY
RESERVED
3.2.7
JTAG BOUNDARY SCAN TEST SIGNALS
Name TRST# Type Description Test Clock. Used clock state information data into PI721P100 during boundary scan. Test Mode Select. Used control state Test Access Port controller. Test Data Output. Used serial output test instructions data from test logic. Test Data Input. Serial input JTAG instructions test data. Test Reset. Active signal reset Test Access Port (TAP) controller into initialized state.
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
3.2.8
TEST SIGNALS
Name T_DI1 Type Description Bypass Control PCI-X Mode. strapped value this P_RST# deassertion) controls whether internal PLL's bypassed PCI-X mode. HIGH: PLL's used PCI-X mode LOW: PLL's bypassed PCI-X mode Shorten Initialization Period. Controls period following signals during initialization. LOW: Shorten periods TPIRSTDLY Primary Clocks TXCAP Primary Clocks TSIRSTDLY Secondary Clocks TSRSTDLY Secondary Clocks Primary Clocks HIGH: Normal initialization TPIRSTDLY Table TXCAP Table TSIRSTDLY Table TSRSTDLY Table Test Control. Controls along with internal testing. T_RI T_MODECTL XCLK_OUT P_CLK* S_CLK**
T_DI2
T_MODECTL T_RI XCLK_OUT
T_RI
P_PLL enabled, S_PLL disabled **P_PLL disabled, S_PLL enabled Bypass Control Mode. strapped value this T_RI) controls whether internal PLL's bypassed mode. PLL's bypassed mode T_MODECTL=0: PLL's used mode Scan Chain Enable. Used SCAN_EN with SCAN_being controlled JTAG instruction. S_REQ[6:2] used data inputs scan chains S_GNT[6:2] used data ouputs scan chains
TEST_CE0
3.2.9
POWER GROUND SIGNALS
Name P_VDDA P_VSSA S_VDDA S_VSSA AB21 D11, D13, D15, J20, L20, N20, R20, Y11, Y13, Type Description 2.5V Power: Power supply primary clock domain. 2.5V Power: Ground primary clock domain. 2.5V Power: Power supply secondary clock domain. 2.5V Power: Ground secondary clock domain. Power: Power supply internal logic
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Name VDD2 A12, A22, D17, D19, E20, G20, H23, U20, W20, Y17, Y19, AC2, AC12, AC16 A10, A11, A14, A18, A23, B22, C21, D12, D20, F23, H20, K23, L23, M20, P23, T20, V23, Y12, Y20, AA3, AA21, AB2, AB22, AC1, AC6, AC10, AC13, AC14, AC18, AC23 Type Description Power: Power supply
Ground
LIST
Table LIST 304-PIN PBGA
BALL LOCATION NAME P_AD[56] P_CBE[4]# P_CBE[7]# P_PAR64 P_CBE[0]# P_CBE[3]# P_FRAME# P_AD[4] P_VDDA P_SERR# P_AD[50] P_AD[55] P_AD[59] P_CBE[6]# P_AD[2] P_AD[5] P_CBE[1]# P_AD[15] T_MODECTL VDD2 P_AD[53] P_AD[58] P_CBE[5]# P_AD[1] P_AD[3] P_AD[9] P_AD[10] TRST# TYPE BALL LOCATION NAME P_ACK64# P_AD[60] VDD2 VDD2 P_IRDY# P_AD[7] VDD2 P_AD[43] P_AD[54] P_AD[49] P_AD[52] P_AD[57] P_AD[63] P_AD[0] P_TRDY# P_AD[8] P_IDSEL P_REQ# P_AD[48] P_STOP# P_CFG_BUSY P_PERR# P_AD[61] P_REQ64# P_LOCK# P_AD[6] P_PAR P_GNT# RESERVED TYPE
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BALL LOCATION NAME P_AD[47] P_AD[51] P_AD[62] P_CBE[2]# P_VSSA P_AD[11] P_AD[38] P_AD[45] VDD2 P_RST# P_AD[44] P_AD[13] P_AD[12] P_AD[36] P_AD[41] VDD2 P_AD[14] P_AD[35] P_AD[40] P_AD[17] P_AD[33] P_AD[37] P_AD[19] S_AD[33] P_AD[25] P_AD[21] P_AD[32] S_AD[35] P_AD[27] VDD2 S_AD[38] P_AD[29] S_AD[40] S_AD[31] S_AD[45] S_AD[26] S_AD[29] S_AD[37] S_AD[48] S_AD[24] VDD2 S_AD[50] S_AD[20] S_AD[42] S_AD[52] VDD2 S_AD[19] TYPE BALL LOCATION K223 NAME XCLK_OUT VDD2 VDD2 VDD2 VDD2 P_DEVSEL# P_AD[22] P_DRVER VDD2 P_CLK P_AD[24] P_AD[42] P_AD[46] BAR_EN VDD2 P_AD[16] P_AD[26] P_AD[39] P_AD[18] VDD2 P_AD[34] P_AD[20] P_AD[31] S_AD[34] S_AD[32] P_AD[23] S_AD[36] P_AD[28] S_AD[39] P_AD[30] S_AD[27] S_AD[41] S_AD[30] S_AD[25] S_AD[47] S_AD[43] S_AD[28] S_AD[49] S_AD[22] S_PCIXCAP S_AD[51] S_ARB# S_AD[23] S_AD[53] VDD2 S_AD[18] S_RST# TYPE
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BALL LOCATION AA10 AA12 AA14 AA16 AA18 AA20 AA22 AB11 AB13 AB15 AB17 AB19 AB21 AB23 AC10 AC12 AC14 AC16 AC18 AC20 AC22 NAME S_SEL100 S_AD[14] S_AD[17] S_AD[44] S_CLK_STABLE VDD2 T_RI S_AD[46] S_AD[56] VDD2 VDD2 VDD2 VDD2 T_DI1 TEST_CE0 S_REQ[2]# T_DI2 S_AD[59] S_ACK64# S_PAR64 S_AD[6] S_FRAME# S_AD[10] OPAQUE_EN S_AD[13] S_IDSEL S_GNT[2]# S_REQ[4]# S_REQ[5]# S_AD[62] S_AD[1] S_AD[4] S_REQ64# S_AD[9] S_PERR# S_SERR# S_VDDA S_CLK VDD2 S_GNT[6]# S_CBE[4]# VDD2 VDD2 S_LOCK# IDSEL_ROUTE TYPE BALL LOCATION AA11 AA13 AA15 AA17 AA19 AA21 AA23 AB10 AB12 AB14 AB16 AB18 AB20 AB22 AC11 AC13 AC15 AC17 AC19 AC21 AC23 NAME S_AD[55] S_AD[54] S_AD[16] S_REQ[3]# VDD2 S_AD[15] S_AD[21] S_GNT[3]# S_AD[57] S_CBE[7]# S_TRDY# S_VSSA S_AD[11] 64BIT_DEV# S_PCIXCAP_PU S_AD[58] S_AD[61] S_AD[0] S_CBE[5]# S_AD[7] S_CBE[3]# S_PAR S_GNT[1]# S_REQ[1]# S_GNT[5]# S_AD[60] S_AD[63] S_CBE[6]# S_CBE[0]# S_CBE[2]# S_CBE[1]# S_AD[12] S_STOP# S_REQ[6]# S_GNT[4]# S_DRVR S_AD[2] S_AD[3] S_AD[5] S_AD[8] S_IRDY# S_DEVSEL# TYPE
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
OPERATION
This Chapter offers information about transactions, transaction forwarding across PI7C21P100, transaction termination. PI7C21P100 buffers read data buffering upstream downstream transactions. Also, PI7C21P100 buffers write data buffering upstream downstream transactions.
TYPES TRANSACTIONS
This section provides summary PCI-X transactions performed PI7C21P100. Table lists command code name each PCI-X transaction. Master Target columns indicate support each transaction when PI7C21P100 initiates transactions master, primary secondary buses, when PI7C21P100 responds transactions target, primary secondary buses. Table PCI-X TRANSACTIONS
Types Transactions 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Interrupt Acknowledge Special Cycle Read Write Reserved Reserved Memory Read Memory Write Reserved Reserved Configuration Read Configuration Write Memory Read Multiple Dual Address Cycle Memory Read Line Memory Write Invalidate Initiates Master Primary (Type only) Secondary Responds Target Primary Secondary (Type only)
indicated Table 4-1, following commands supported PI7C21P100: PI7C21P100 never initiates transaction with reserved command code and, target, PI7C21P100 ignores reserved command codes. PI7C21P100 does generate interrupt acknowledge transactions. PI7C21P100 ignores interrupt acknowledge transactions target. PI7C21P100 does respond special cycle transactions. PI7C21P100 cannot guarantee delivery special cycle transaction downstream buses because broadcast nature special cycle command inability control transaction target. generate special cycle transactions other buses, either upstream downstream, Type configuration write must used.
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WRITE TRANSACTIONS
Write transactions treated posted write, delayed/split (PCI-X), immediate write transactions. Table shows method forwarding used each type write operation. Table WRITE TRANSACTION FORWARDING
Type Transaction Memory Write Memory Write Invalidate Memory Write Block (PCI-X) Write Type Configuration Write Type Configuration Write Type Forwarding Posted Posted Posted Delayed Split (PCI-X) Immediate primary bus. Delayed Split (PCI-X) secondary bus. Delayed Split (PCI-X)
4.2.1
MEMORY WRITE TRANSACTIONS
Posted write forwarding used "Memory Write", "Memory Write Invalidate", "Memory Write Block" transactions. When PI7C21P100 determines that memory write transaction forwarded across bridge, PI7C21P100 asserts DEVSEL# with medium decode timing TRDY# next cycle, provided that enough buffer space available posted memory write queue address least DWORD data. Under this condition, PI7C21P100 accepts write data without obtaining access target bus. PI7C21P100 accept DWORD write data every clock cycle. That target wait state inserted. write data stored internal posted write buffers subsequently delivered target. PI7C21P100 continues accept write data until following events occurs: initiator terminates transaction de-asserting FRAME# IRDY#. internal write address boundary reached, such cache line boundary aligned boundary, depending transaction type. posted write data buffer fills When last events occurs, PI7C21P100 returns target disconnect requesting initiator this data phase terminate transaction. Once posted write data moves head posted data queue, PI7C21P100 asserts request target bus. This occur while PI7C21P100 still receiving data initiator bus. When grant target received target detected idle condition, PI7C21P100 asserts FRAME# drives stored write address target bus. following cycle, PI7C21P100 drives first DWORD write data continues transfer write data until write data corresponding that transaction delivered, until target termination received. long write data exists queue, PI7C21P100 drive DWORD write data each clock cycle; that master wait states inserted. write data flowing through PI7C21P100 initiator stalls, PI7C21P100 will signal last data phase current transaction target queue empties. PI7C21P100 will restart follow-on transactions queue data.
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION PI7C21P100 ends transaction target when following conditions met: posted write data been delivered target. target returns target disconnect target retry (PI7C21P100 starts another transaction deliver rest write data). target returns target abort (PI7C21P100 discards remaining write data). master latency timer expires, PI7C21P100 longer target grant (PI7C21P100 starts another transaction deliver remaining write data).
4.2.1.1
PCI-X PCI-X When both buses operating PCI-X mode, PI7C21P100 passes memory write command that receives destination interface along with originating byte count transaction PI7C21P100 attempts transfer memory write command when transaction ends 128-byte boundary crossed. long there least 128-byte data data buffer transfer remains from PCI-X memory write command when 128-byte boundary crossed, transfer will continue. transaction disconnected destination interface middle continuing transfer, byte count address updated transaction presented again destination interface. transaction disconnected middle continuing transfer originating interface, originator must present transaction again with updated byte count address.
4.2.1.2
When both buses operating conventional mode, bridge passes memory write command that receives destination interface, unless PI7C21P100 disconnected middle memory write invalidate cache line boundary. this happens, command will continue memory write when PI7C21P100 attempts reconnect. PI7C21P100 attempts transfer memory write command when transaction ends 128-byte boundary crossed. long 128-byte buffer full transfer remains from memory write command when 128-byte boundary crossed, transfer will continue.
4.2.1.3
PCI-X When originating operating conventional mode destination operating PCI-X mode, PI7C21P100 must buffer memory write transactions from conventional interface count number bytes forwarded PCI-X interface. conventional transaction uses memory write command some byte enables asserted, PI7C21P100 must PCI-X memory write command. conventional command memory write byte enables asserted, PI7C21P100 will PCI-X memory write command. conventional transaction uses memory write invalidate command, PI7C21P100 uses PCI-X memory write block command. PI7C21P100 attempts transfer write data PCI-X interface soon transaction ends 128-byte boundary crossed. Writes greater than bytes possible only more than 128-byte sector fills before write operation issued PCIX interface. Page March 2004 Revision 1.04
PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
4.2.1.4
PCI-X When originating operating PCI-X mode destination operating conventional mode, PI7C21P100 uses conventional memory write command both PCI-X memory write PCI-X memory write block commands. PI7C21P100 attempts transfer write data conventional interface when PCI-X data crosses 128-byte boundary PCI-X transfer occurs. long 128byte buffer full, transfer remains from PCI-X memory write command when 128-byte boundary crossed, transfer will continue conventional interface.
4.2.2
DELAYED/SPLIT WRITE TRANSACTIONS
Delayed/Split write forwarding used write transactions, Type configuration write transactions, Type configuration write transactions. Delayed/Split write forwarding transactions retried originating bus, completed destination necessary), then completed originating bus. DWORD transactions, PI7C21P100 uses delayed transactions conventional mode split requests PCI-X mode. Only request queue entry allowed either delayed split write transactions.
4.2.3
IMMEDIATE WRITE TRANSACTIONS
PI7C21P100 considers Type configuration writes primary meant bridge immediate write transactions bridge. PI7C21P100 will execute transaction indicate completion accepting DWORD data immediately.
READ TRANSACTIONS
Read transactions treated delayed read conventional mode, split read PCI-X mode, immediate read. Table shows read behavior. Table READ TRANSACTIN HANDLING
Type Transaction Memory Read Memory Read Line Memory Read Multiple Memory Read DWORD (PCI-X mode) Memory Read Block (PCI-X mode) Read Type Configuration Read Type Configuration Read Type Handling Delayed Delayed Delayed Split (PCI-X mode) Split (PCI-X mode) Delayed/Split (PCI-X) Immediate primary bus, Delayed/Split (PCI-X mode) secondary Delayed/Split (PCI-X mode)
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4.3.1
MEMORY READ TRANSACTIONS
Memory data transferred from originating side PI7C21P100 destination side using memory read, memory read line, memory read multiple, PCI-X memory read DWORD, PCI-X memory read block transactions. memory read transactions either delayed split originating side PI7C21P100 depending mode originating side.
4.3.1.1
PCI-X PCI-X translation needed these transactions. amount data that fetched controlled downstream upstream split transaction control register. split transaction capacity split transaction commitment limit fields control much data requested time.
4.3.1.2
translation needed these transactions. Memory Read Fetches only requested DWORD command targets nonprefetchable memory space. Bits [25:24] offset bits [9:8] offset control mode prefetching memory read transactions prefetchable range secondary primary respectively. default cache line will prefetched. Memory Read Line Bits [23:22] offset bits [7:6] offset control mode prefetching memory read line transactions prefetchable range secondary primary respectively. default cache line will prefetched. Memory Read Multiple Bits [21:20] offset bits [5:4] offset control mode prefetching memory read multiple transactions prefetchable range secondary primary respectively. default full prefetch, limited value bits [14:12] offset 40h. default value bytes, entire read buffer.
4.3.1.3
PCI-X PI7C21P100 must translate conventional memory read command either memory read DWORD memory read block PCI-X Command. conventional memory read command targets non-prefetchable memory space, command translated into memory read DWORD. other instance, conventional memory read command gets translated into memory read block PCI-X command. Bits [25:24] offset bits [9:8] offset control mode prefetching memory read transactions prefetchable range secondary primary respectively. default cache line will prefetched. default cache line will prefetched. PI7C21P100 translates conventional memory read line command memory read block PCI-X command. Bits [23:22] offset bits [7:6] offset control mode prefetching memory read line transactions prefetchable range secondary primary respectively. default cache line will prefetched.
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION PI7C21P100 must translate conventional memory read multiple command memory read block PCI-X command. Bits [21:20] offset bits [5:4] offset control mode prefetching memory read multiple transactions prefetchable range secondary primary respectively. default full prefetch, limited value bits [14:12] offset 40h. default value bytes, entire read buffer. Using value greater than this possible, constrained setting split transaction commitment limit value upstream downstream split transaction register, since target PCI-X mode. Data fetching operations will disconnected boundaries.
4.3.1.4
PCI-X PI7C21P100 translates PCI-X memory read DWORD commands into conventional memory read commands. PI7C21P100 translates PCI-X memory read block command into three conventional memory read commands based byte count starting address. starting address byte count such that only single DWORD less) being read, conventional transaction uses memory read command. PCI-X transaction reads more than DWORD, does cross cache line boundary (indicated Cache Line Size register conventional Configuration Space header), conventional transaction uses memory read line command. PCI-X transaction crosses cache line boundary, conventional transaction uses memory read multiple command. disconnect occurs before byte count PCI-X memory read block command exhausted, PI7C21P100 continues issue command until bytes count received. PI7C21P100 disconnects once buffer filled prefetches more data 128-byte sectors buffer become free when split completion data returned originator, until byte count exhausted.
4.3.2
READ
Read command translated fetches DWORD data. command will either split PCI-X mode delayed conventional mode.
4.3.3
4.3.3.1
CONFIGURATION READ
TYPE CONFIGURATION READ Type configuration read command only accepted primary interface. command will either split PCI-X mode delayed conventional mode.
4.3.3.2
TYPE CONFIGURATION READ Type configuration read command accepted either primary secondary interface. command returns immediate data primary interface regardless interface mode. secondary interface command treated either split transaction PCI-X mode delayed transaction mode.
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4.3.4
NON-PREFETCHABLE DWORD READS
non-prefetchable read transaction read transaction which PI7C21P100 requests exactly DWORD from target disconnects initiator after delivering that DWORD read data. Unlike prefetchable read transactions, PI7C21P100 forwards read byte enable information data phase. Non-prefetchable behavior used I/O, configuration, memory read transactions that fall into nonprefetchable memory space mode, DWORD read transactions PCI-X mode.
4.3.5
PREFETCHABLE READS
prefetchable read transaction read transaction where PI7C21P100 performs speculative reads, transferring data from target before requested from initiator. This behavior allows prefetchable read transaction consist multiple data transfers. prefetchable read transactions, byte enables asserted data phases. Prefetchable behavior used memory read line memory read multiple transactions, well memory read transactions that fall into prefetchable memory space allowed fetch more than DWORD. amount data that prefetched depends type transaction setting bits primary secondary data buffering control registers configuration space. amount prefetching also affected amount free buffer space available PI7C21P100, read address boundaries encountered.
4.3.5.1
PCI-X PCI-X PCI-X PCI-X transactions, PI7C21P100 continues generate data requests interface keeps prefetch buffer full until entire amount data requested transferred. PCI-X PCI-X transactions, split transaction commitment limit value contained upstream downstream split transaction register determines operation. value greater than equal split transaction capacity (4KB) less than 32KB, maximum request amount bytes. Larger transfers will decomposed into series smaller transfers, until original byte count been satisfied. commitment limit value indicates 32KB more, original request amount used decomposition performed. original request broken into smaller requests bridge waits until previous completion been totally received before request issued. This ensures that data does order that requests with same sequence issued. either case, bridge generates requester each request passed through bridge.
4.3.5.2
method used transfers PCI-to-PCI mode user defined primary secondary data buffering control registers. These registers have bits memory read prefetchable space, memory read line, memory read multiple transactions. memory read, bits select whether read DWORD, read cache line boundary, fill prefetch buffer. memory read line memory read multiple transactions, bits select whether read cache line boundary fill prefetch buffer. cases, bits
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION selected fill prefetch buffer, maximum amount data that requested target interface controllable setting maximum memory read byte count bits Primary Secondary Data Buffering Control registers. When more than bytes requested, bridge fetches data fill buffer then fetches more data keep buffer filled sectors (128 bytes) emptied become free again.
4.3.5.3
PCI-X method used transfers PCI-X mode similar transfers PCI-toPCI mode, except that maximum request amount additionally constrained setting split transaction commitment limit value upstream downstream split transaction register. only other difference that prefetching will stop when originating master disconnects. Prefetching will only stop when requested data received.
4.3.6
DYNAMIC PREFETCH (CONVENTIONAL MODE ONLY)
prefetchable reads described previous section, prefetching length normally predefined cannot changed once set. This cause some inefficiency prefetching length determined could larger smaller than actual data being prefetched. make prefetching more efficient, PI7C21P100 incorporates dynamic prefetching control logic. This logic regulates different memory read commands memory read, memory read line, memory read multiple) improve memory read burst performance. PI7C21P100 tracks every memory read burst transaction tallies status. using status information, PI7C21P100 determine increase, reduce, keep same cache line length prefetched. Over time, PI7C21P100 better match correct cache line setting length data being requested. dynamic prefetching control logic with bits[3:2] offset 48h.
CONFIGURATION TRANSACTIONS
Configuration transactions used initialize system. Every device configuration space that accessed configuration commands. registers accessible configuration space only. addition accepting configuration transactions initialization configuration space, PI7C21P100 also forwards configuration transactions device initialization hierarchical systems, well special cycle generation. support hierarchical systems, types configuration transactions specified: Type Type Type configuration transactions issued when intended target resides same initiator. Type configuration transaction identified configuration command lowest bits address 00b. Type configuration transactions issued when intended target resides another bus, when special cycle generated another bus. Type configuration command identified configuration command lowest address bits 01b.
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register number found both Type Type formats gives DWORD address configuration register accessed. function number also included both Type Type formats indicates which function multifunction device accessed. single-function devices, this value decoded. addresses Type configuration transaction include 5-bit field designating device number that identifies device target that accessed. addition, number Type transactions specifies which transaction targeted.
4.4.1
TYPE ACCESS PI7C21P100
configuration space accessed Type configuration transaction. configuration space accessed from primary secondary interface. S_IDSEL should tied access required from secondary interface. primary interface, PI7C21P100 responds Type configuration transaction accepting transaction when following conditions during address phase: P_CBE[3:0]# indicates configuration write configuration read transaction lowest address bits P_AD[1:0] P_IDSEL asserted Bit[2] offset (Miscellaneous Control Register) secondary interface, PI7C21P100 responds Type configuration transaction accepting transaction when following conditions during address phase: S_CBE[3:0]# indicates configuration write configuration read transaction lowest address bits S_AD[1:0] S_IDSEL asserted function number decoded since bridge single-function device. configuration transactions bridge handled DWORD operations.
4.4.2
TYPE TYPE CONVERSION
Type configuration transactions used specifically device configuration hierarchical PCI/PCI-X system. bridge only type device that should respond Type configuration command. Type configuration commands used when configuration access intended PCI/PCI-X device that resides other than where Type transaction generated. PI7C21P100 performs Type Type translation when Type transaction generated primary interface intended device attached directly secondary interface. PI7C21P100 must convert configuration command Type format that secondary device respond Type Type translations performed only downstream direction. PI7C21P100 responds Type configuration transaction translates into Type transaction secondary interface when following conditions during address phase: lowest address bits P_AD[1:0] 01b. Page March 2004 Revision 1.04
PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION number address field P_AD[23:16] equal value secondary number register configuration space. P_CBE[3:0]# configuration read configuration write transaction. When PI7C21P100 translates Type transaction Type transaction secondary interface, performs following translations address: Sets lowest address bits S_AD[1:0] Decodes device number drives pattern specified Table S_AD[31:16] purpose asserting device's IDSEL signal. Sets S_AD[15:11] secondary operating conventional mode (device number passed through unchanged PCI-X mode) Leaves unchanged function number register number fields. PI7C21P100 asserts unique address line based device number. These address lines used secondary IDSEL signals. mapping address lines depends device number address bits P_AD[15:11] Type transactions. Table presents mapping that PI7C21P100 uses. Table DEVICE NUMBER IDSEL
Device Number P_AD[15:11] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 11110 11111 Secondary IDSEL S_AD[31:16] 0000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 convert special cycle transaction described section 4.4.4
PI7C21P100 forwards Type Type configuration read write transactions delayed transactions mode split transactions PCI-X mode.
4.4.3
TYPE TYPE FORWARDING
Type Type transaction forwarding provides hierarchical configuration mechanism when more levels PCI-to-PCI bridges used. When PI7C21P100 detects Type configuration transaction intended PCI/PCI-X downstream from secondary interface, PI7C21P100 forwards transaction unchanged secondary interface. Ultimately, this transaction translated Type configuration command special cycle transaction downstream bridge. Downstream Type Type forwarding occurs when following conditions during address phase:
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION lowest address bits P_AD[1:0] equal 01b. number falls range defined lower limit (exclusive) secondary number register upper limit (inclusive) subordinate number register. P_AD[1:0] configuration read configuration write transaction. PI7C21P100 also supports Type Type forwarding configuration write transactions upstream support upstream special cycle generation. upstream Type configuration read commands ignored PI7C21P100. PI7C21P100 forwards Type Type configuration read write transactions delayed transactions mode split transactions PCI-X mode.
4.4.4
SPECIAL CYCLES
Type configuration mechanism used generate special cycle transactions hierarchical PCI/PCI-X systems. Special cycle transactions generated from Type configuration write transactions either upstream downstream direction. PI7C21P100 initiates special cycle target when Type configuration write transaction detected initiating following conditions during address phase: lowest address bits AD[1:0] equal 01b. device number address bits AD[15:11] equal 11111b. function number address bits AD[10:8] equal 111b. register number address bits AD[7:2] equal 000000b. number equal value secondary number register downstream transactions equal value primary number register upstream transactions. command configuration write command. When PI7C21P100 initiates transaction target interface, command changed from configuration write special cycle. Devices that special cycles ignore address decode only command. data phase contains special cycle message. transaction forwarded delayed transaction mode split transaction PCI-X mode. Once transaction completed target through detection master abort condition, PI7C21P100 completes transaction initiating accepting retry delayed command mode generating completion message PCI-X mode. Special cycles received PI7C21P100 target ignored.
TRANSACTION ORDERING
maintain data coherency consistency, PI7C21P100 complies with ordering rules forth Local Specification, Revision mode, PCI-X Addendum Local Specification, Revision 1.0a PCI-X mode. This chapter describes ordering rules that control transaction forwarding across PI7C21P100.
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GENERAL ORDERING GUIDELINES
Independent transactions primary secondary buses have relationship only when those transactions cross PI7C21P100. following general ordering guidelines govern transactions crossing PI7C21P100: Requests terminated with target retry accepted completed order with respect other transactions that have been terminated with target retry. order completion delayed split requests important, initiator should start second delayed split transaction until first been completed. more than delayed split transaction initiated, initiator should repeat retried requests, using some fairness algorithm. Repeating delayed split transaction cannot contingent completion another delayed transaction. Otherwise, deadlock occur. Write transactions flowing direction have ordering requirements with respect write transactions flowing other direction. PI7C21P100 accept posted write transactions both interfaces same time, well initiate posted write transactions both interfaces same time. acceptance posted memory memory write transaction target never contingent completion non-locked, non-posted transaction master. This true PI7C21P100 must also true other agents. Otherwise, deadlock occur. PI7C21P100 accepts posted write transactions, regardless state completion delayed transactions being forwarded across PI7C21P100.
ORDERING RULES
Table SUMMARY TRANSACTION ORDERING MODEand Table show ordering relationships transactions refers number ordering rules that follow. Table SUMMARY TRANSACTION ORDERING MODE
Pass Delayed Delayed Delayed Delayed Read Write Read Write Request Request Completion Completion Posted Write Delayed Read Request Delayed Write Request Delayed Read Completion Delayed Write Completion relaxed ordering mode, enable relaxed ordering primary and/or secondary data buffering control registers other mode, read completions pass memory writes. Posted Write
Table SUMMARY TRANSACTION ORDERING PCI-X MODE
Pass Posted Write Delayed Read Request Delayed Write Request Memory Write Split Read Request Split Write Request Split Read Completion Split Write Completion
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Pass Memory Split Read Split Write Split Read Split Write Write Request Request Completion Completion Delayed Read Completion Yes2 Delayed Write Completion relaxed ordering PCI-X PCI-X mode, enable relaxed ordering primary and/or secondary data buffering control registers other mode, read completions pass memory writes. Split Read Completions with same sequence must remain address order.
CLOCKS
This chapter provides information about clocks.
PRIMARY SECONDARY CLOCK INPUTS
primary secondary interface PI7C21P100 each clock input pin. P_CLK clock input primary S_CLK input secondary (S_CLK also controls internal arbiter). clocks independent each other synchronously asynchronously each other value supported PCIX specifications. Each interface utilizes separate internal (phase-locked loop) circuit when running PCI-X mode. mode, PLL's bypassed, allowing clock frequency from 66MHz. primary running 133MHz PCI-X mode, then secondary limited minimum frequency 33MHz conventional mode. secondary slower, primary frequency needs reduced that ratio does exceed 4:1.
CLOCK JITTER
PI7C21P100 tolerates maximum 250ps short term long term jitter clock inputs. Short term jitter defined relationship between clock edge next subsequent clock edge clock cycle, long term jitter same relationship over many clock cycles.
6.3.1
MODE CLOCK FREQUENCY DETERMINATION
PRIMARY
PI7C21P100 does have pins M66EN PCIXCAP signals primary bus. PI7C21P100 adjusts internal configuration based initialization pattern detects P_DEVSEL#, P_STOP#, P_TRDY# rising edge P_RST#. internal being used (the configured PCI-X mode), maximum 100µs from rising edge P_RST# required lock frequency clock supplied P_CLK input.
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6.3.2
SECONDARY
secondary interface capable operating either conventional mode PCI-X mode. PI7C21P100 controls mode frequency secondary utilizing pullup circuit connected S_PCIXCAP. There pull-up resistors circuit recommended PCI-X addendum. first resistor weak pull-up (56K ohms) whose value selected voltage S_PCIXCAP below threshold when PCI-X device attached secondary bus. second resistor strong pull-up, externally wired between S_PCIXCAP S_PCIXCAP_PU. value resistor ohm) selected voltage S_PCIXCAP above high threshold when devices secondary PCI-X capable. detect mode frequency secondary bus, S_PCIXCAP_PU initially disabled PI7C21P100 samples value S_PCIXCAP. PI7C21P100 sees logic S_PCIXCAP, more devices secondary have either pulled signal ground (PCI-X capable) tied ground (only capable conventional mode). differentiate between conditions, PI7C21P100 then enables S_PCIXCAP_PU strong pull-up into circuit. S_PCIXCAP remains logic LOW, must tied ground more devices, initialized conventional mode. S_PCIXCAP_PU pulled more devices capable only PCI-X operation initialized PCI-X mode. PI7C21P100 sees logic HIGH S_PCIXCAP, then devices secondary capable PCI-X operation. PI7C21P100 then samples S_SEL100 distinguish between 66-100 100-133 clock frequency ranges. PI7C21P100 sees logic HIGH S_SEL100, secondary initialized PCI-X mode. value LOW, PCI-X initialized. These ranges allow adjustment clock frequency account loading conditions. There M66EN secondary interface PI7C21P100 because internal bypassed conventional mode. S_CLK used directly, eliminating need distinguish between conventional conventional Table PROGRAMMABLE PULL-UP CIRCUIT
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
6.3.3
CLOCK STABILITY
comply with PCI-X architecture specifications, clock must stable running designated frequency least 100us after deassertion reset. S_CLK_STABLE used determine detect when S_CLK become stable. During reset, PI7C21P100 will wait assertion S_CLK_STABLE before determining mode frequency. PI7C21P100 expecting more than transition S_CLK_STABLE input from "not stable" "stable" state. S_CLK_STABLE input tied HIGH secondary clock input known always stable prior deassertion primary reset signal secondary reset bridge control register. Examples sources S_CLK_STABLE lock indicators circuits that employ PLL's "power good" indicators.
6.3.4
DRIVER IMPEDANCE SELECTION
output drivers PI7C21P100 capable different output impedances, output impedance ohm. output impedance primary secondary interfaces separately controlled. PI7C21P100 selects default impedance value deassertion reset based mode frequency. configured PCI-X mode, assumed that will have fewer devices have higher impedance. this case, drivers utilize output impedance mode. output impedance mode utilized other PCI-X configurations, assuming that more heavily loaded lower impedance. Some applications follow these assumptions control signals provided; P_DRVR primary S_DRVR secondary. When these inputs pulled HIGH, PI7C21P100 will change output impedance drivers their respective interfaces opposite state than assumed default, shown Table 6-2. driver mode changed dynamically, changed during each reset. Table DRIVER IMPEDANCE SELECTION
Primary Mode Conventional PCI-X PCI-X PCI-X Default Driver Mode (P_DRVR=0) Driver Mode (P_DRVR=1) Secondary Mode Conventional PCI-X PCI-X PCI-X Default Driver Mode (S_DRVR=0) Driver Mode (S_DRVR=1)
RESET
primary secondary interface each have their asynchronous reset signal used power-on other times PI7C21P100 into known state. reset signal primary (P_RST#) input pin, while reset signal secondary (S_RST#) output driven PI7C21P100.
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
PRIMARY INTERFACE RESET
When P_RST# asserted, following events occur: PI7C21P100 immediately tri-states primary interface signals. S_AD[31:0] S_CBE[3:0] driven secondary interface other control signals tristated. PI7C21P100 performs chip reset. Registers that have default values reset. PI7C21P100 accessible during P_RST#. After P_RST# deasserted PCI-X mode, PI7C21P100 remains inaccessible 100us enable internal lock target frequency. conventional mode, PI7C21P100 held reset clocks after deassertion P_RST#.
SECONDARY INTERFACE RESET
PI7C21P100 responsible driving secondary reset signals, S_RST#. PI721P100 asserts S_RST# when following conditions met: Signal P_RST# asserted. Signal S_RST# remains asserted long P_RST# asserted does de-assert until P_RST# de-asserted. secondary reset bridge control register set. Signal S_RST# remains asserted until configuration write operation clears secondary reset bit. Several things must occur prior de-assertion S_RST#. Once P_RST# de-asserted secondary reset changed from PI7C21P100 will wait S_CLK_STABLE signal asserted before proceeding. S_CLK must stable frequency within capability limits prior assertion S_CLK_STABLE. Since Local Specification requires that clock stable least 100us prior de-assertion reset, S_CLK_STABLE serves gate timer that ensures that this requirement met. During this time delay period, secondary mode frequency determined through programmable pull-up circuit. This process include 80us capacitive load S_PCIXCAP charged. time 100us timer expires, mode frequency will have been determined. S_RST# signal then de-asserted minimum secondary clock cycles later. When secondary operating PCI-X mode, internal used source clock tree secondary clock domain inside PI7C21P100. appropriate range tuning bits once mode frequency determined, internal reset signal deactivated allow begin locking S_CLK input frequency. requires allowance 100us accomplish this frequency lock. internal reset held logic secondary clock domain until this time period elapsed. While internal reset active, PI7C21P100 will respond secondary transactions. When secondary operating mode, internal secondary interface used. internal reset remains activated, keeping bypass mode, internal logic reset held additional secondary clock cycles.
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION Table DELAY TIMES DE-ASSERTION S_RST#
PCI-X PCI-X PCI-X 6678 primary clock 13350 primary 13350 primary cycles clock cycles clock cycles 100us 133us 133us 200us 100us 133us 6675 primary clock 6675 primary clock 13347 primary 13347 primary TXCAP cycles cycles clock cycles clock cycles 100us 133us 133us 200us 100us 133us secondary secondary secondary secondary TSRSTDLY primary clock primary clock primary clock primary clock cycles cycles cycles cycles 13350 secondary 13350 secondary secondary clock 6687 secondary TSIRSTDLY clock cycles clock cycles cycles clock cycles 100us 133us 133us 200us 100us 133us Note: Primary secondary clock cycles refer clock cycles whose period determined P_CLK S_CLK inputs. TPIRSTDLY Conventional primary clock cycles
Table DE-ASSERTION S_RST#
PARKING WIDTH DETERMINATION
parking refers driving AD[31:0], CBE[3:0], lines known value while idle. general, device implementing arbiter responsible parking assigning another device park bus. device parks when idle, grant asserted, device's request asserted. AD[31:0], CBE[3:0], signals driven after assertion S_RST#. PI7C21P100 will assert S_REQ64# least clock cycles allow devices determine whether they connected 64-bit 32-bit bus.
SECONDARY DEVICE MASKING
Secondary devices masked through configuration power strapping secondary private device mask register. process converting Type configuration transactions Type configuration transactions modified contents secondary private device mask register. configuration transaction that targets device masked this register routed device Secondary architectures which designed support masking Page March 2004 Revision 1.04
PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION devices should implement device number (i.e., S_AD(31)). device mask options (device numbers defined PI7C21P100 allow architectures support private device groupings that single multiple interrupt binding.
ADDRESS PARITY ERRORS
PI7C21P100 checks address parity transactions both buses, address commands. When PI7C21P100 detects address parity error, transaction will claimed will allowed terminate with master abort. result address parity error will controlled parity error response bits both command bridge control registers.
OPTIONAL BASE ADDRESS REGISTER
Base Address register located configuration register offsets optionally used acquire memory region system initialization. PI7C21P100 uses this register claim additional prefetchable memory region secondary bus. When used with secondary device masking, this allows acquisition memory space private devices that otherwise viewable system software. This base address register memory space defined enabled BAR_EN. When BAR_EN pulled LOW, this register location returns zeros reads cannot written. When BAR_EN pulled HIGH, upper memory base address register lower memory base address registers combined specify address bits 63:20 memory region. Memory accesses primary compared against this register, address bits 63:20 equal bits 63:20 address defined combination lower memory base address register upper memory base address register, access claimed PI7C21P100 passed through secondary bus. Memory accesses secondary also compared against this register, address bits 63:20 equal bits 63:20 address defined combination lower memory base address register upper memory base address register, access ignored bridge.
OPTIONAL CONFIGURATION ACCESS FROM SECONDARY
PI7C21P100 accepts Type configuration transactions when following conditions during address phase: S_CBE[3:0]# indicates configuration read configuration write transaction S_AD[1:0] S_IDSEL asserted Applications that require access bridge configuration registers secondary control initialization sequence through P_CFG_BUSY bit[2] offset miscellaneous control register. When P_CFG_BUSY pulled HIGH, bit[2] offset power reset. This causes PI7C21P100 retry Type configuration transactions primary that would otherwise accepted. PI7C21P100 continues retry these transactions until bit[2] offset configuration write initiated secondary bus. This allows device secondary initialize bridge private devices secondary without contention from devices accessing bridge
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION through primary bus. Applications that require access bridge configuration registers secondary should pull both S_IDSEL P_CFG_BUSY pins LOW.
SHORT TERM CACHING
Short Term Caching means provide performance improvements where upstream devices able stream data continuously meet prefetching needs PI7C21P100. When master completes transaction, bridge required discard balance data that prefetched master. prevent performance impacts when dealing with target devices that only stream data bytes before disconnecting, PI7C21P100 utilizes Short Term Caching. This feature applies only when secondary operating conventional mode provides time limited read data cache which bridge will discard prefetched read data after request been completed initiating bus. Short Term Caching optional feature which enabled setting bit[8] bit[15] offset Miscellaneous Control Register When enabled, PI7C21P100 will discard additional prefetched data when read transaction been completed initiating bus. PI7C21P100 will continue prefetch data amount specified bits [30:28] offset Secondary Data Buffering Control Register. Should initiator generate transaction requesting previously prefetched data, PI7C21P100 will return that data. PI7C21P100 will discard data approximately secondary clocks after some data request been returned initiator, initiator requested additional data. This feature applies secondary devices enabled. System designers need ensure that attached devices have memory region(s) that architected accessed only master that additional prefetching will present data initiator same state initial transaction were continued. This feature should only used system designs that able ensure that data provided master been modified since initial transaction.
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
CONFIGURATION REGISTERS
configuration defines DWORD space define various attributes PI7C21P100.
CONFIGURATION REGISTER SPACE
Table CONFIGURATION SPACE
Number Device Primary Status DWORD Address 98h-Ach BCh-FFh
Vendor Primary Command Class Code Revision BIST Header Type Primary Latency Timer Cache Line Size Lower Memory Base Address Upper Memory Base Address Secondary Latency Subordinate Secondary Number Primary Number Timer Number Secondary Status Limit Base Memory Limit Memory Base Prefetchable Memory Limit Prefetchable Memory Base Prefetchable Base Upper 32-bit Prefetchable Limit Upper 32-bit Limit Upper 16-bit Base Upper 16-bit Reserved Capability Pointer Expansion Base Address Bridge Control Interrupt Interrupt Line Secondary Data Buffering Control Primary Data Buffering Control Reserved Miscellaneous Control Reserverd Extended Chip Control Extended Chip Control Reserved Reserved Arbiter Mode Reserved Arbiter Enable Reserved Arbiter Priority Reserved SERR# Disable Primary Retry Counter Secondary Retry Counter Reserved Discard Timer Control Reserved Retry Timer Status Reserved Opaque Memory Enable Opaque Memory Limit Opaque Memory Base Opaque Memory Base Upper 32-bit Opaque Memory Limit Upper 32-bit PCI-X Secondary Status Next Capability Pointer PCI-X Capability PCI-X Bridge Status Secondary Upstream Split Transaction Primary Downstream Split Transaction Power Management Capabilities Next Capabilities Power Management Pointer PCI-to-PCI Bridge Support Extension Power Management Control Status Reserved Secondary Private Device Mask Reserved Reserved Miscellaneous Control Reserved
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION 8.1.1.1 SIGNAL TYPE DEFINITION
SIGNAL TYPE DEFINITION READ ONLY READ WRITE READ WRITE CLEAR
8.1.2
VENDOR REGISTER OFFSET
15:0 FUNCTION Vendor TYPE DESCRIPTION Identifies Pericom vendor this device. Hardwired 12D8h
8.1.3
DEVICE REGISTER OFFSET
31:16 FUNCTION Device TYPE DESCRIPTION Identifies device PI7C21P100. Hardwired 01A7h.
8.1.4
COMMAND REGISTER OFFSET
15:10 FUNCTION Reserved Fast Back-to-Back Enable TYPE DESCRIPTION Reserved. Returns 000000 when read. Fast Back-to-Back Control Prohibits PI7C21P100 initiate fast back-to-back transactions primary This ignored PCI-X mode. Reset System Error Control Disables P_SERR# driver primary Enables P_SERR# driver primary Reset Wait Cycle Control Address/data stepping disabled (primary secondary) This ignored PCI-X mode. Returns when read. Parity Error Response PI7C21P100 ignore detected parity errors continue normal operation PI7C21P100 must take normal action when parity error detected. Reset Palette Snoop Control Ignore palette accesses primary Enables positive decoding response palette writes primary with address bits AD[9:0] equal 3C6h, 3C8h, 3C9h (inclusive aliases; AD[15:10] decoded value. Reset Memory Write Invalidate Control Disables Memory Write Invalidate transactions. PI7C21P100 does generate memory write invalidate transactions. This ignored PCI-X mode. Returns when read. Special Cycle Control PI7C21P100 does respond target Special Cycle transactions. Returns when read.
P_SERR# Enable
Wait Cycle Control
Parity Error Response
Palette Snoop Enable
Memory Write Invalidate Enable
Special Cycle Enable
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
FUNCTION Master Enable TYPE DESCRIPTION Master Control PI7C21P100 does initiate memory transactions primary disables responses memory transactions secondary Enables PI7C21P100 operate master primary memory transactions forwarded from secondary. PCI-X mode, PI7C21P100 allowed initiate split completion transaction regardless status this bit. Reset Memory Space Control Ignore memory transactions primary Enables responses memory transactions primary Reset Space Control Ignores transactions primary Enables responses transaction primary Reset
Memory Space Enable
Space Enable
8.1.5
PRIMARY STATUS REGISTER OFFSET
FUNCTION Detected Parity Error TYPE DESCRIPTION Detected Parity Error Status Address data parity error detected PI7C21P100 Address data parity error detected PI7C21P100 Reset Signaled System Error Status PI7C21P100 assert SERR# PI7C21P100 asserted SERR# Reset Received Master Abort Status Transaction terminated with master abort Transaction terminated with master abort Reset Received Target Abort Status Transaction terminated with target abort Transaction terminated with target abort Reset Signaled Target Abort Status Target device terminate transaction with target abort Target device terminated transaction with target abort DEVESEL# Timing Status Medium decoding. Returns when read. Data Parity Error Status data parity error detected Data parity error detected Reset Fast Back-to-Back Status Target capable decoding fast back-to-back transactions PCI-X mode Target capable decoding fast back-to-back transactions conventional mode Returns PCI-X mode conventional mode Reserved. Returns when read. 66MHz Capable Status Capable 66MHz operation Returns when read. Capability List PI7C21P100 supports capability list offset pointer data structure. Returns when read. Reserved. Returns 0000 when read.
Signaled System Error
Received Master Abort
Received Target Abort
Signaled Target Abort
26:25
DEVSEL# Timing
Data Parity Error
Fast Back-to-Back Capable
Reserved 66MHz Capable
Capability List
19:16
Reserved
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
8.1.6
REVISION REGISTER OFFSET
FUNCTION Revision TYPE DESCRIPTION Specifies revision PI7C21P100. Read
8.1.7
CLASS CODE REGISTER OFFSET
31:24 23:16 15:8 FUNCTION Class Code Class Code Programming Interface TYPE DESCRIPTION Specifies base class code PI7C21P100 identifying Bridge device according specifications. Read Specifies sub-class code identifying PI7C21P100 Bridge device. Read 04h. Subtractive decoding supported. Read
8.1.8
CACHE LINE SIZE REGISTER OFFSET
FUNCTION Cache Line Size TYPE DESCRIPTION Designates cache line size system used when terminating memory write invalidate transactions when prefetching memory read transactions. used PCI-X mode. bit[7:6]: supported should bit[5]: then cache line size DWORDS bit[4]: then cache line size DWORDS bit[3]: then cache line size DWORDS bit[2]: then cache line size DWORDS bit[1:0]: supported should
8.1.9
PRIMARY LATENCY TIMER OFFSET
15:11 10:8 FUNCTION Primary Latency Timer Primary Latency Timer TYPE DESCRIPTION Designates upper bits primary latency timer clock units Designates lower bits primary latency timer clock units. Returns when read force 8-cycle increments latency timer.
8.1.10
HEADER TYPE REGISTER OFFSET
22:16 FUNCTION Single Function Device PCI-to-PCI Configuration TYPE DESCRIPTION Returns when read designate single function device Returns 0000001 when read.
8.1.11
BIST REGISTER OFFSET
31:24 FUNCTION BIST TYPE DESCRIPTION BIST supported. Returns when read.
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
8.1.12
LOWER MEMORY BASE ADDRESS REGISTER OFFSET
31:20 FUNCTION Memory Base Address TYPE DESCRIPTION Address bits[31:20] memory base address BAR_EN BAR_EN then this register reserved returns zeros when read. Reserved. Returns when read Identifies address range defined this register prefetchable. Returns when read Indicates that this lower portion 64-bit register. Returns when read. Indicates that this register memory decoder. Returns when read.
19:4
Reserved Prefetchable Indicator Decoder Width Decoder Type
8.1.13
UPPER MEMORY BASE ADDRESS REGISTER OFFSET
31:0 FUNCTION Upper Memory Base Address TYPE DESCRIPTION Address bits[63:32] memory base address BAR_EN BAR_EN this register reserved returns zeros when read.
8.1.14
PRIMARY NUMBER REGISTER OFFSET
FUNCTION Primary Number TYPE DESCRIPTION Records number segment that PI7C21P100 connected primary side. Reset
8.1.15
SECONDARY NUMBER REGISTER OFFSET
15:8 FUNCTION Secondary Number TYPE DESCRIPTION Records number segment that PI7C21P100 connected secondary side. Reset
8.1.16
SUBORDINATE NUMBER REGISTER OFFSET
23:16 FUNCTION Subordinate Number TYPE DESCRIPTION Records highest number segment that resides behind PI7C21P100. Reset
8.1.17
SECONDARY LATENCY TIMER REGISTER OFFSET
31:24 FUNCTION Secondary Latency Timer TYPE DESCRIPTION Specifies value secondary latency timer clock units. Reset conventional mode Reset PCI-X mode
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
8.1.18
BASE ADDRESS REGISTER OFFSET
FUNCTION Base Address TYPE DESCRIPTION Specifies base address range bits [15:12] used with limit register base upper bits limit upper 16-bit registers Reserved. Returns when read. Returns when read indicate PI7C21P100 supports 32-bit addressing
Reserved 32-bit Addressing
8.1.19
LIMIT REGISTER OFFSET
15:12 11:10 FUNCTION Limit Address Reserved 32-bit Addressing TYPE DESCRIPTION Address bits[15:12] limit address address range operations that passed from primary secondary Reserved. Returns when read. Returns when read indicate PI7C21P100 supports 32-bit addressing
8.1.20
SECONDARY STATUS REGISTER OFFSET
FUNCTION Detected Parity Error TYPE DESCRIPTION Detected Parity Error Status Address data parity error detected PI7C21P100 secondary Address data parity error detected PI7C21P100 secondary Reset Signaled System Error Status PI7C21P100 assert SERR# secondary PI7C21P100 asserted SERR# secondary Reset Received Master Abort Status Transaction terminated with master abort secondary Transaction terminated with master abort secondary Reset Received Target Abort Status Transaction terminated with target abort Transaction terminated with target abort Reset Signaled Target Abort Status Target device terminate transaction with target abort Target device terminated transaction with target abort Reset DEVESEL# Timing Status Medium decoding. Returns when read. Data Parity Error Status data parity error detected secondary Data parity error detected secondary Reset Fast Back-to-Back Status Target capable decoding fast back-to-back transactions PCI-X mode Target capable decoding fast back-to-back transactions conventional mode Returns PCI-X mode conventional mode Reserved. Returns when read.
Signaled System Error
Received Master Abort
Received Target Abort
Signaled Target Abort
26:25
DEVSEL# Timing
Data Parity Error
Fast Back-to-Back Enable
Reserved
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
FUNCTION 66MHz Capable TYPE DESCRIPTION 66MHz Capable Status Capable 66MHz operation Returns when read. Reserved. Returns 00000 when read.
20:16
Reserved
8.1.21
MEMORY BASE REGISTER OFFSET
15:4 FUNCTION Memory Base TYPE DESCRIPTION Specifies base memory mapped address range bit[31:20] used with Memory Limit register specify range 32-bit addresses supported memory mapped transactions. Reset 800h Reserved. Returns when read
Reserved
8.1.22
MEMORY LIMIT REGISTER OFFSET
31:20 FUNCTION Memory Limit TYPE DESCRIPTION Specifies address bits[31:20] limit address address range memory mapped operations. Reset 000h Reserved. Returns when read
19:16
Reserved
8.1.23
PREFETCHABLE MEMORY BASE REGISTER OFFSET
15:4 FUNCTION Prefetchable Memory Base 64-bit Addressing TYPE DESCRIPTION Specifies address bits[31:20] base address address range prefetchable memory operations. Reset 800h Designates 64-bit addressing support. Returns when read.
8.1.24
PREFETCHABLE MEMORY LIMIT REGISTER OFFSET
31:20 FUNCTION Prefetchable Memory Limit 64-bit Addressing TYPE DESCRIPTION Specifies address bits[31:20] limit address address range prefetchable memory operations. Reset 800h Designates 64-bit addressing support. Returns when read.
19:16
8.1.25
PREFETCHABLE BASE UPPER 32-BIT REGISTER OFFSET
31:0 FUNCTION Prefetchable Base Upper 32-bit TYPE DESCRIPTION Specifies address bits[63:32] base address address range prefetchable memory operations. Reset 0000 0000h
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
8.1.26
PREFETCHABLE LIMIT UPPER 32-BIT REGISTER OFFSET
31:0 FUNCTION Prefetchable Limit Upper 32-bit TYPE DESCRIPTION Specifies address bits[63:32] limit address address range prefetchable memory operations. Reset 0000 0000h
8.1.27
BASE UPPER 16-BIT REGISTER OFFSET
15:0 FUNCTION Base Upper 16-bit TYPE DESCRIPTION Specifies address bits[31:16] base address address range operations. Reset 0000h
8.1.28
LIMIT UPPER 16-BIT REGISTER OFFSET
31:16 FUNCTION Limit Upper 16-bit TYPE DESCRIPTION Specifies address bits[31:16] limit address address range operations. Reset 0000h
8.1.29
CAPABILITY POINTER OFFSET
FUNCTION Capability Pointer TYPE DESCRIPTION Pointer capabilities list configuration space. Returns when read.
8.1.30
EXPANSION BASE ADDRESS REGISTER OFFSET
31:0 FUNCTION Expansion Base Address TYPE DESCRIPTION Expansion supported. Returns 00000000h when read
8.1.31
INTERRUPT LINE REGISTER OFFSET
FUNCTION Interrupt Line Register TYPE DESCRIPTION POST program initialize FFh, defining PI7C21P100 does implement interrupt pin.
8.1.32
INTERRUPT REGISTER OFFSET
15:8 FUNCTION Interrupt Register TYPE DESCRIPTION Defines interrupt pin, PI7C21P100 does implement interrupt pins. Read 00h.
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
8.1.33
BRIDGE CONTROL REGISTER OFFSET
31:28 FUNCTION RESERVED Discard Timer P_SERR# Enable TYPE DESCRIPTION Reserved. Returns when read. Discard Timer P_SERR# Enable Does assert P_SERR# primary interface result expiration either primary discard timer secondary discard timer. Asserts P_SERR# primary interface result expiration either primary discard timer secondary discard timer. This ignored PCI-X mode. Reset Master Timeout Status discard timer error Discard timer error (from primary secondary discard timer) This remains when PCI-X mode. Reset Secondary Master Timeout Status secondary discard timer counts clock cycles. secondary discard timer counts clock cycles. secondary interface PCI-X mode, this ignored. Reset Primary Master Timeout Status primary discard timer counts clock cycles. primary discard timer counts clock cycles. primary interface PCI-X mode, this ignored. Reset Fast Back-to-Back Transaction Enable Designates PI7C21P100 does generate fast back-to-back transactions. Returns when read. Secondary Interface Reset Does force assertion S_RST# secondary interface Forces assertion S_RST# secondary interface. Reset Master Abort Mode report master aborts. Returns FFFFFFFFh reads discard data writes. Report master aborts signaling target abort possible asserting SERR# enabled). PCI-X mode, PI7C21P100 will return split completion message, leaving host bridge return FFFFFFFFh nonposted transaction when non-posted transaction ends master abort. Reset Reserved. Returns when read. Enable Does forward compatible memory addresses from primary secondary interface unless they enabled forwarding defined memory address ranges. Forwards compatible memory addresses from primary secondary interface enable Memory enable bits set) independent defined memory address ranges independent enable bit. Enable Forward downstream addresses address defined base limit registers. Forward upstream addresses address range defined base limit registers that first 64KB address space Reset S_SERR# Enable Disable forwarding S_SERR# P_SERR# Enable forwarding S_SERR# P_SERR#. Reset
Master Timeout Status
Secondary Master Timeout Status
Primary Master Timeout Status
Fast Back-to-Back
Secondary Interface Reset
Master Abort Mode
RESERVED Enable
Enable
S_SERR# Enable
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
FUNCTION Parity Error Response Enable TYPE DESCRIPTION Parity Error Response Enable Ignore address data parity errors secondary interface. Enable parity error detection secondary interface.
8.1.34
PRIMARY DATA BUFFERING CONTROL REGISTER OFFSET
14:12 FUNCTION RESERVED Maximum Memory Read Byte Count TYPE DESCRIPTION Reserved. Returns when read. Maximum Memory Read Byte Count 000: bytes (default) 001: bytes 010: bytes 011: bytes 100: 1024 bytes 101: 2048 bytes 110: 4096 bytes 111: bytes Maximum byte count used PI7C21P100 when generating read requests secondary interface response memory read operation initiated primary interface which mode bits[9:8], bits[7:6], bits[5:4] full prefetch. Reset Relaxed Ordering Enable Relaxed ordering disabled conventional mode. primary interface, read completions that occur after first read completion allowed bypass posted writes complete with higher priority conventional mode. PCI-X mode, relaxed ordering attribute field will take precedence. Reset Primary Special Delayed Read Mode Enable Retry primary master which repeats transaction with command code changes. Allows primary master change memory command code (MR, MRL, MRM) after received retry. PI7C21P100 will complete memory read transaction return data back primary master address byte enables same. This ignored PCI-X mode. Reset Primary Read Prefetch Mode cache line prefetch memory read address prefetchable range primary interface Reserved Full prefetch memory read address prefetchable range primary interface. Disconnect first DWORD. These bits ignored PCI-X mode. Reset Primary Read Line Prefetch Mode cache line prefetch memory read line address prefetchable range primary interace Reserved Full prefetch memory read multiple address prefetchable range primary interface Reserved. These bits ignored primary interface PCI-X mode. Primary Read Multiple Prefetch Mode cache line prefetch memory read multiple address prefetchable range primary interface. Reserved. Full prefetch memory read multiple address prefetchable range primary interface. Reserved. These bits ignored primary interface PCI-X mode. Reset Reserved. Returns 0000 when read.
Enable Relaxed Ordering
Primary Special Delayed Read Mode Enable
Primary Read Prefetch Mode
Primary Read Line Prefetch Mode
Primary Read Multiple Prefetch Mode
RESERVED
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
8.1.35
SECONDARY DATA BUFFERING CONTROL REGISTER OFFSET
30.28 FUNCTION RESERVED Maximum Memory Read Byte Count TYPE DESCRIPTION Reserved. Returns when read. Maximum Memory Read Byte Count 000: bytes (default) 001: bytes 010: bytes 011: bytes 100: 1024 bytes 101: 2048 bytes 110: 4096 bytes 111: bytes Maximum byte count used PI7C21P100 when generating read requests primary interface response memory read operation initiated secondary interface which conventional mode bits[9:8], bits[7:6], bits[5:4] full prefetch. Reset Relaxed Ordering Enable Relaxed ordering disabled conventional mode. secondary interface, read completions that occur after first read completion allowed bypass posted writes complete with higher priority conventional mode. PCI-X mode, relaxed ordering attribute field will take precedence. Reset Secondary Special Delayed Read Mode Enable Retry secondary master which repeats transaction with command code changes. Allows secondary master change memory command code (MR, MRL, MRM) after received retry. PI7C21P100 will complete memory read transaction return data back primary master address byte enables same. This ignored PCI-X mode. Reset Secondary Read Prefetch Mode cache line prefetch memory read address prefetchable range secondary interface Reserved Full prefetch memory read address prefetchable range secondary interface. Disconnect first DWORD. These bits ignored PCI-X mode. Reset Secondary Read Line Prefetch Mode cache line prefetch memory read line address prefetchable range secondary interface Reserved Full prefetch memory read multiple address prefetchable range secondary interface Reserved. These bits ignored secondary interface PCI-X mode. Secondary Read Multiple Prefetch Mode cache line prefetch memory read multiple address prefetchable range secondary interface. Reserved. Full prefetch memory read multiple address prefetchable range secondary interface. Reserved. These bits ignored secondary interface PCI-X mode. Reset Reserved. Returns 0000 when read.
Enable Relaxed Ordering
Secondary Special Delayed Read Mode Enable
25:24
Secondary Read Prefetch Mode
23:22
Secondary Read Line Prefetch Mode
21:20
Secondary Read Multiple Prefetch Mode
19:16
RESERVED
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
8.1.36
MISCELLANEOUS CONTROL REGISTER OFFSET
FUNCTION RESERVED Primary Configuration Busy TYPE DESCRIPTION Reserved. Returns 00000 when read. Primary Configuration Busy Type configuration commands accepted normally primary interface. Type configuration commands retried primary interface. This read from both primary secondary buses, written only from secondary bus. Reset value based P_CFG_BUSY. P_CFG_BUSY tied HIGH, reset Data Parity Error Recovery Enable PI7C21P100 pass parity errors through. Cause SERR# asserted whenever either master-data-parityerror bit[8] set. Reset Parity Error Behavior PI7C21P100 will pass corrupted data sequence PERR# will asserted enabled), PI7C21P100 will complete data CBE# performing completion initiating when detecting data parity error non-posted write transaction. Transaction will completed originating bus, PERR# will asserted enabled), appropriate status bits will set, data will discarded request will queued. Reset
Data Parity Error Recovery Enable
Parity Error Behavior
8.1.37
EXTENDED CHIP CONTROL REGISTER OFFSET
FUNCTION RESERVED Bridge Disconnect Discard Timer TYPE DESCRIPTION Reserved. Returns when read. Bridge Disconnect Discard Control PI7C21P100 will discard remaining data after disconnects external master during burst memory reads transaction source bus. PI7C21P100 will keep remaining data after disconnects external master during burst memory reads source bus, until external master returns discard timer expires. Reset Memory Write Transaction Entry Control PI7C21P100 accept memory write transactions PI7C21P100 accept memory write transactions Reset Synchronous Mode Enable Synchronous mode disabled, asynchronous clock input supported. Synchronous mode enabled used decrease frequency frequency latency when PI7C21P100 forwarding transactions through bridge. clock inputs have synchronized primary clock need lead secondary clock with following combinations: Primary Secondary time 33MHz 33MHz 14ns 66MHz 66MHz 66MHz 33MHz 14ns 133MHz 133MHz 133MHz 66MHz Reset Upstream Memory Read Prefetching Dynamic Control Enable upstream memory read prefetching dynamic control Disable upstream memory read prefetching dynamic control Reset (Described section 4.3.6)
Memory Write Transaction Entry Control Synchronous Mode Enable
Upstream Memory Read Prefetching Dynamic Control
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
FUNCTION Downstream Memory Read Prefetching Dynamic Control TYPE DESCRIPTION Downstream Memory Read Prefetching Dynamic Control Enable downstream memory read prefetching dynamic control Disable downstream memory read prefetching dynamic control Reset (Described section 4.3.6) Reserved. Returns when read.
RESERVED
8.1.38
EXTENDED CHIP CONTROL REGISTER OFFSET
11:10 FUNCTION Minimum Free Space Memory Data FIFO Control (Secondary) TYPE DESCRIPTION Minimum Free Space Memory Data FIFO Control (Secondary) Selects minimum free space memory data FIFO accept memory writes secondary PCI-X mode bytes free space accept memory writes bytes free space accept memory writes bytes free space accept memory writes bytes free space accept memory writes Reset Minimum Free Space Memory Data FIFO Control (Primary) Selects minimum free space memory data FIFO accept memory writes primary PCI-X mode bytes free space accept memory writes bytes free space accept memory writes bytes free space accept memory writes bytes free space accept memory writes Reset
Minimum Free Space Memory Data FIFO Control (Primary)
8.1.39
ARBITER MODE REGISTER OFFSET
15:8 FUNCTION Arbiter Fairness Counter TYPE DESCRIPTION Arbiter Fairness Counter These bits initialization value counter used internal arbiter. controls number cycles that arbiter holds device's grant active after detecting request from another device. counter reloaded whenever grant asserted. every grant, counter armed decrement when detects de-assertion FRAME#. arbiter fairness counter 00h, arbiter will remove device's grant until device de-asserted request. Reset GNT# Output Toggling Enable GNT# de-asserted after granted master asserts FRAME# GNT# de-asserts clock after clocks from granted master asserting FRAME#. Reset Broken Master Refresh broken master will ignored forever except when de-asserts REQ# least clock Refresh broken master state after other masters have been served once. Reset Reserved. Returns 0000 when read. Broken Master Timeout Enable Broken master timeout disabled Broken master timeout enabled. This enables internal arbiter count cycles while waiting FRAME# become active when device's GNT# active idle. broken master timeout expires, GNT# device de-asserted. Reset
GNT# Output Toggling Enable
Broken Master Refresh
RESERVED Broken Master Timeout Enable
Page March 2004 Revision 1.04
PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
FUNCTION External Arbiter TYPE DESCRIPTION External Arbiter Enable internal arbiter. Disable internal arbiter. Reset according value S_ARB# during reset. S_ARB# tied LOW, then returns when read. S_ARB# tied HIGH, then returns when read.
8.1.40
ARBITER ENABLE REGISTER OFFSET
FUNCTION RESERVED Enable Arbiter TYPE DESCRIPTION Reserved. Returns when read. Enable Arbiter Disable arbitration master Enable arbitration master Reset Enable Arbiter Disable arbitration master Enable arbitration master Reset Enable Arbiter Disable arbitration master Enable arbitration master Reset Enable Arbiter Disable arbitration master Enable arbitration master Reset Enable Arbiter Disable arbitration master Enable arbitration master Reset Enable Arbiter Disable arbitration master Enable arbitration master Reset Enable Arbiter Disable arbitration internal bridge request Enable arbitration internal bridge request Reset
Enable Arbiter
Enable Arbiter
Enable Arbiter
Enable Arbiter
Enable Arbiter
Enable Arbiter
8.1.41
ARBITER PRIORITY REGISTER OFFSET
FUNCTION RESERVED Arbiter Priority TYPE DESCRIPTION Reserved. Returns when read. Arbiter Priority priority request master High priority request master Reset Arbiter Priority priority request master High priority request master Reset Arbiter Priority priority request master High priority request master Reset Arbiter Priority priority request master High priority request master Reset
Arbiter Priority
Arbiter Priority
Arbiter Priority
Page March 2004 Revision 1.04
PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
FUNCTION Arbiter Priority TYPE DESCRIPTION Arbiter Priority priority request master High priority request master Reset Arbiter Priority priority request master High priority request master Reset Arbiter Priority priority request internal bridge High priority request internal bridge Reset
Arbiter Priority
Arbiter Priority
8.1.42
SERR# DISABLE REGISTER OFFSET
FUNCTION RESERVED PERR# Posted Writes SERR# Disable TYPE DESCRIPTION Reserved. Returns when read. PERR# Posted Writes SERR# Disable Assert SERR# bit[30] offset status register bit[8] offset command register set. Discard delayed transaction. Disable assertion SERR#. Reset Primary Discard Timer SERR# Disable Assert SERR# update bit[30] offset status register primary discard timer expires bit[8] offset command register bit[27] offset control register set. Discard delayed transaction bit[3] offset retry timer status register. Disable assertion SERR# primary discard timer expires. Discard delayed transaction bit[3] offset retry timer status register. Reset Secondary Discard Timer SERR# Disable Assert SERR# update bit[30] offset status register secondary discard timer expires bit[8] offset command register bit[27] offset control register set. Discard delayed transaction bit[3] offset retry timer status register. Disable assertion SERR# primary discard timer expires. Discard delayed transaction bit[3] offset retry timer status register. Reset Primary Retry Count SERR# Disable Assert SERR# update bit[30] offset status register primary retry counter expires bit[8] offset command register set. Discard transaction bit[1] offset retry timer status register. Disable assertion SERR# primary retry counter expires. Discard transaction bit[1] offset retry timer status register. Reset Secondary Retry Count SERR# Disable Assert SERR# update bit[30] offset status register secondary retry counter expires bit[8] offset command register set. Discard transaction bit[0] offset retry timer status register. Disable assertion SERR# primary retry counter expires. Discard transaction bit[0] offset retry timer status register. Reset
Primary Discard Timer SERR# Disable
Secondary Discard Timer SERR# Disable
Primary Retry Count SERR# Disable
Secondary Retry Count SERR# Disable
Page March 2004 Revision 1.04
PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
8.1.43
PRIMARY RETRY COUNTER REGISTER OFFSET
FUNCTION Retry Count Control TYPE DESCRIPTION Retry Count Control Designates retries before expiration Reset Reserved. Returns 000000 when read. Retry Count Control Designates retries before expiration. Reset Reserved. Returns 0000000 when read. Retry Count Control Designates retries before expiration. Reset Reserved. Returns 0000000 when read. Retry Count Control Designates retries before expiration. Reset Reserved. Returns 00000000 when read.
30:25
RESERVED Retry Count Control RESERVED Retry Count Control RESERVED Retry Count Control RESERVED
23:17
15:9
below settings only allowed values. Other settings valid will result smaller retry counts. When counter expires, bridge discards requested transaction primary issues SERR# primary enabled. 0000 0000: 8000 0000: 0100 0000: 0001 0000: 0000 0100: expiration limit Allow retries before expiration Allow retries before expiration Allow retries before expiration Allow retries before expiration
8.1.44
SECONDARY RETRY COUNTER REGISTER OFFSET
FUNCTION Retry Count Control TYPE DESCRIPTION Retry Count Control Designates retries before expiration Reset Reserved. Returns 000000 when read. Retry Count Control Designates retries before expiration. Reset Reserved. Returns 0000000 when read. Retry Count Control Designates retries before expiration. Reset Reserved. Returns 0000000 when read. Retry Count Control Designates retries before expiration. Reset Reserved. Returns 00000000 when read.
30:25
RESERVED Retry Count Control RESERVED Retry Count Control RESERVED Retry Count Control RESERVED
23:17
15:9
below settings only allowed values. Other settings valid will result smaller retry counts. When counter expires, bridge discards requested transaction secondary issues SERR# primary enabled. 0000 0000: 8000 0000: 0100 0000: 0001 0000: 0000 0100: expiration limit Allow retries before expiration Allow retries before expiration Allow retries before expiration Allow retries before expiration
Page March 2004 Revision 1.04
PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
8.1.45
DISCARD TIMER CONTROL REGISTER OFFSET
FUNCTION RESERVED Primary Discard Timer Short Duration TYPE DESCRIPTION Reserved. Returns 0000 when read. Primary Discard Timer Short Duration bit[24] offset bridge control register indicate many clocks should allowed before primary discard timer expires. clocks allowed before discard time expires. Reset Secondary Discard Timer Short Duration bit[25] offset bridge control register indicate many clocks should allowed before secondary discard timer expires. clocks allowed before secondary discard timer expires. Reset Primary Discard Timer Disable Enable primary discard timer conjunction with bit[27] offset bridge control register Disable primary discard timer conjunction with bit[27] offset bridge control register Reset Secondary Discard Timer Disable Enable secondary discard timer conjunction with bit[27] offset bridge control register Disable secondary discard timer conjunction with bit[27] offset bridge control register Reset
Secondary Discard Timer Short Duration
Primary Discard Timer Disable
Secondary Discard Timer Disable
8.1.46
RETRY TIMER STATUS REGISTER OFFSET
FUNCTION RESERVED Primary Discard Timer Status TYPE DESCRIPTION Reserved. Returns 0000 when read. Primary Discard Timer Status primary discard timer expired since last reset. primary discard timer expired since last reset. Reset Secondary Discard Timer Status secondary discard timer expired since last reset. secondary discard timer expired since last reset. Reset Primary Retry Counter Status primary retry counter expired since last request. primary retry counter expired since last request. Reset Secondary Retry Counter Status secondary retry counter expired since last request. secondary retry counter expired since last request. Reset
Secondary Discard Timer Status
Primary Retry Counter Status
Secondary Retry Counter Status
8.1.47
OPAQUE MEMORY ENABLE REGISTER OFFSET
FUNCTION RESERVED Opaque Memory Enable TYPE DESCRIPTION Reserved. Returns 0000000 when read. Opaque Memory Enable Disable opaque memory address range OPAQUE_EN=0. Enable opaque memory address range OPAQUE_EN=1. Reset value OPAQUE_EN during reset.
Page March 2004 Revision 1.04
PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
8.1.48
OPAQUE MEMORY BASE REGISTER OFFSET
15:4 FUNCTION Opaque Memory Base Address TYPE DESCRIPTION Opaque Memory Base Address Address bits[31:20] opaque memory base address conjunction with opaque memory base upper 32-bit register opaque memory limit address. this range, memory transactions accepted PI7C21P100 both primary secondary interfaces. Reset 000h Address Select Returns 0001 when read indicate 64-bit addressing.
Address Select
8.1.49
OPAQUE MEMORY LIMIT REGISTER OFFSET
31:20 FUNCTION Opaque Memory Limit Address TYPE DESCRIPTION Opaque Memory Limit Address Address bits[31:20] opaque memory limit address conjunction with opaque memory limit upper 32-bit register opaque memory base address. this range, memory transactions accepted PI7C21P100 both primary secondary interfaces. Reset FFFh Address Select Returns 0001 when read indicate 64-bit addressing.
19:16
Address Select
8.1.50
OPAQUE MEMORY BASE UPPER 32-BIT REGISTER OFFSET
31:0 FUNCTION Opaque Memory Base Upper 32-bit Regi
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