H8S/2626 H8S/2625 H8S/2624 H8S/2623 H8S/2622 H8S/2621 HD6432626 HD6432
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H8S/2626 Series, H8S/2623 Series H8S/2626F-ZTATTM, H8S/2623F-ZTATH8S/2626 Series
H8S/2626 H8S/2625 H8S/2624 H8S/2623 H8S/2622 H8S/2621 HD6432626 HD6432625 HD6432624 HD6432623 HD6432622 HD6432621
H8S/2623 Series
H8S/2626F-ZTATHD64F2626
H8S/2623F-ZTATHD64F2623 Hardware Manual
ADE-602-164B Rev. 5/25/00 Hitachi, Ltd.
Cautions
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Preface
H8S/2626 Series H8S/2623 Series series high-performance microcontrollers with 32-bit H8S/2600 core, on-chip supporting modules required system configuration. H8S/2600 execute basic instructions state, provided with sixteen 16-bit general registers with 32-bit internal configuration, concise optimized instruction set. handle Mbyte linear address space (architecturally Gbytes). Programs based high-level language also efficiently. address space divided into eight areas. data width access states selected each these areas, various kinds memory connected fast easily. Single-power-supply flash memory (F-ZTATTM*), mask versions available, providing quick flexible response conditions from ramp-up through full-scale volume production, even applications with frequently changing specifications. On-chip supporting functions include 16-bit timer pulse unit (TPU), programmable pulse generator (PPG), watchdog timer (WDT), serial communication interface (SCI), Hitachi controller area network (HCAN), converter, converter (H8S/2626 Series only), ports. addition, data transfer controller (DTC) provided, enabling high-speed data transfer without intervention. H8S/2626 Series H8S/2623 Series enables easy implementation compact, highperformance systems capable processing large volumes data. This manual describes hardware H8S/2626 Series H8S/2623 Series. Refer H8S/2600 Series H8S/2000 Series Programming Manual detailed description instruction set. Note: F-ZTAT (Flexible-ZTAT) trademark Hitachi, Ltd.
Revisions Additions this Edition
Page Table Overview Item Revisions (See Manual Details) Amendments associated with addition H8S/2626 Series Following items amended addition H8S/2626 Series WDT, converter, ports, memory, interrupt controller, power-down mode, product lineup Added Added Added Clock: OSC1, OSC2 (subclock pins) added ports: Note added Port Note added Note added Description amended description amended Note added Exception handling source added Internal interrupt amended
Figure Internal Block Diagram Figure Arrangement Table Functions Each Operating Mode Table Functions
Figure 2-14 Processing States Figure 2-15 State Transitions 2.8.6 Power-Down State 3.2.3 Function Control Register (PFCR) Figure Exception Sources Table Exception Vector Table Figure Interrupt Sources Number Interrupts
Table Correspondence between Interrupt Amended Sources Settings Interrupt Sources Table Interrupt Sources, Vector Addresses, Interrupt Priorities Internal interrupt sources amended Amended
130, 6.3.4 Operation Transitions Power-Down Amended Modes 7.2.6 Function Control Register (PFCR) Overview Table Port Functions description amended Description amended Ports amended Description pins added
230, Port
Page
Item Port 9.10 Port Section Watchdog Timer 15.2.1 Master Control Register (MCR) 15.2.2 General Status Register (GSR) Figure 15-2 Detailed Description Table 15-3 Setting Range TSEG1 TSEG2 15.2.4 Mailbox Configuration Register (MBCR) 15.2.5 Transmit Wait Register (TXPR)
Revisions (See Manual Details) Description pins OSC2 OSC1 added Description BUZZ added WDT1 related description added bits amended bits amended Note added Note added amended amended
15.2.6 Transmit Wait Cancel Register (TXCR) amended 15.2.7 Transmit Acknowledge Register (TXACK) amended
15.2.8 Abort Acknowledge Register (ABACK) amended 15.2.9 Receive Complete Register (RXPR) 15.2.10 Remote Request Register (RFPR) Description amended Description amended amended description amended bits amended descriptions amended Description amended bits amended descriptions amended MCx[1] bits amended Description MCx[1] bits amended descriptions amended IRR0 Clearing Added Variable restriction amended
538, 15.2.11 Interrupt Register (IRR) 15.2.13 Interrupt Mask Register (IMR) 15.2.16 Unread Message Status Register (UMSR)
547, 15.2.17 Local Acceptance Filter Masks (LAFML, LAFMH) 549, 15.2.18 Message Control (MC0 MC15)
553, 15.2.19 Message Data (MD0 MD15) 15.3.2 Initialization after Hardware Reset Rate Settings
Page
Item 15.3.3 Transmit Mode Initialization (After Hardware Reset Only)
Revisions (See Manual Details) IRR0 Clearing Added Message transmission completion interrupt Description amended IRR0 Clearing Added
Message transmission interrupts 15.3.4 Receive Mode Initialization (After Hardware Reset Only)
15.3.5 HCAN Sleep Mode Clearing operation 15.5 Usage Notes Reset Register retention during standby
Description amended
Description amended Added Added
Section Converter [Provided H8S/2626 Series only]
629, 19.5.6 Flash Memory Power Control Register Added (FLPWCR) 19.12 Flash Memory Power-Down States Amendments associated with addition subclock function Section Clock Pulse Generator Section Power-Down Modes [H8S/2623 Series] subclock function) 21A.2.1 Standby Control Register (SBYCR) Amendments associated with addition subclock function Divided series Initial value bits amended
Section Power-Down Modes Divided series [H8S/2626 Series] (subclock function provided) 21B.2.1 Standby Control Register (SBYCR) Table 22-1 Absolute Maximum Ratings Table 22-2 Characteristics Initial value bits amended Amendments associated with addition pins OSC1 OSC2 Amendments associated with addition pins OSC1 OSC2 Amendments associated with addition subclock function Amendments associated with addition converter Amended Amendments associated with addition subclock function Conditions: value amended Conditions: value amended
Figure 22-1 Output Load Circuit Table 22-4 Clock Timing Table 22-5 Control Signal Timing Table 22-6 Timing
Page
Item
Revisions (See Manual Details) Conditions: value amended BUZZ output delay time added Added Conversion time amended Added Added H'FDAC H'FDAD H'FDAE H'FFA2 H'FFA3 H'FFAC DADR2 DADR3 DADR23 TCSR1/TCNT1 TCNT1 FLPWCR
745, Table 22-7 Timing On-Chip Supporting Modules Figure 22-22 WDT1 Output Timing Table 22-8 Conversion Characteristics 22.5 Conversion Characteristics Address
Functions
Registers which amendments have been made this manual H'F800 H'F801 H'F804 MBCR H'F806 TXPR H'F808 TXCR H'F80A TXACK H'F80C ABACK H'F812 H'F816 H'F81C LAFML H'F81E LAFMH H'FDE4 SBYCR H'FDE6 SCKCR H'FDEB PFCR H'FDEC LPWRCR H'FE39 PADDR H'FE40 PAPCR H'FE47 PAODR H'FF09 PADR H'FFB9 PORTA Amended Added Addition H8S/2626 Series
1006 1016 1027
Figure Port Block Diagram (Pins PA5) Figure Port Block Diagram H8S/2626 Series (Pin PF1) Appendix Product Code Lineup
Contents
Section
Overview Overview. Internal Block Diagram Descriptions. 1.3.1 Arrangement 1.3.2 Functions Each Operating Mode. 1.3.3 Functions.
Section
Overview. 2.1.1 Features 2.1.2 Differences between H8S/2600 H8S/2000 2.1.3 Differences from H8/300 CPU. 2.1.4 Differences from H8/300H CPU. Operating Modes Address Space. Register Configuration 2.4.1 Overview 2.4.2 General Registers. 2.4.3 Control Registers. 2.4.4 Initial Register Values Data Formats. 2.5.1 General Register Data Formats 2.5.2 Memory Data Formats. Instruction Set. 2.6.1 Overview 2.6.2 Instructions Addressing Modes 2.6.3 Table Instructions Classified Function. 2.6.4 Basic Instruction Formats. Addressing Modes Effective Address Calculation 2.7.1 Addressing Mode. 2.7.2 Effective Address Calculation. Processing States 2.8.1 Overview 2.8.2 Reset State 2.8.3 Exception-Handling State 2.8.4 Program Execution State 2.8.5 Bus-Released State 2.8.6 Power-Down State.
Basic Timing. 2.9.1 Overview 2.9.2 On-Chip Memory (ROM, RAM) 2.9.3 On-Chip Supporting Module Access Timing. 2.9.4 On-Chip HCAN Module Access Timing 2.9.5 External Address Space Access Timing. 2.10 Usage Note 2.10.1 Instruction
Section
Operating Modes Overview. 3.1.1 Operating Mode Selection. 3.1.2 Register Configuration Register Descriptions. 3.2.1 Mode Control Register (MDCR). 3.2.2 System Control Register (SYSCR) 3.2.3 Function Control Register (PFCR) Operating Mode Descriptions. 3.3.1 Mode 3.3.2 Mode 3.3.3 Mode 3.3.4 Mode Functions Each Operating Mode. Address Each Operating Mode Exception Handling. Overview. 4.1.1 Exception Handling Types Priority 4.1.2 Exception Handling Operation 4.1.3 Exception Vector Table. Reset 4.2.1 Overview 4.2.2 Reset Sequence. 4.2.3 Interrupts after Reset 4.2.4 State On-Chip Supporting Modules after Reset Release Traces Interrupts. Trap Instruction Stack Status after Exception Handling Notes Stack. Interrupt Controller Overview.
Section
Section
5.1.1 Features 5.1.2 Block Diagram 5.1.3 Configuration 5.1.4 Register Configuration Register Descriptions. 5.2.1 System Control Register (SYSCR) 5.2.2 Interrupt Priority Registers (IPRA IPRK, IPRM). 5.2.3 Enable Register (IER) 5.2.4 Sense Control Registers (ISCRH, ISCRL). 5.2.5 Status Register (ISR) Interrupt Sources. 5.3.1 External Interrupts. 5.3.2 Internal Interrupts 5.3.3 Interrupt Exception Handling Vector Table Interrupt Operation 5.4.1 Interrupt Control Modes Interrupt Operation 5.4.2 Interrupt Control Mode 5.4.3 Interrupt Control Mode 5.4.4 Interrupt Exception Handling Sequence 5.4.5 Interrupt Response Times. Usage Notes 5.5.1 Contention between Interrupt Generation Disabling. 5.5.2 Instructions that Disable Interrupts 5.5.3 Times when Interrupts Disabled. 5.5.4 Interrupts during Execution EEPMOV Instruction. Activation Interrupt 5.6.1 Overview 5.6.2 Block Diagram. 5.6.3 Operation
Section
Break Controller (PBC)
Overview. 6.1.1 Features 6.1.2 Block Diagram. 6.1.3 Register Configuration Register Descriptions. 6.2.1 Break Address Register (BARA) 6.2.2 Break Address Register (BARB). 6.2.3 Break Control Register (BCRA) 6.2.4 Break Control Register (BCRB) 6.2.5 Module Stop Control Register (MSTPCRC). Operation 6.3.1 Break Interrupt Instruction Fetch.
6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 6.3.7
Break Interrupt Data Access Notes Break Interrupt Handling Operation Transitions Power-Down Modes Break Operation Continuous Data Transfer When Instruction Execution Delayed State Additional Notes
Section
Controller. Overview. 7.1.1 Features 7.1.2 Block Diagram. 7.1.3 Configuration 7.1.4 Register Configuration Register Descriptions. 7.2.1 Width Control Register (ABWCR) 7.2.2 Access State Control Register (ASTCR). 7.2.3 Wait Control Registers (WCRH, WCRL). 7.2.4 Control Register (BCRH). 7.2.5 Control Register (BCRL). 7.2.6 Function Control Register (PFCR) Overview Control. 7.3.1 Area Partitioning 7.3.2 Specifications 7.3.3 Memory Interfaces. 7.3.4 Interface Specifications Each Area. Basic Interface. 7.4.1 Overview 7.4.2 Data Size Data Alignment 7.4.3 Valid Strobes 7.4.4 Basic Timing 7.4.5 Wait Control Burst Interface 7.5.1 Overview 7.5.2 Basic Timing 7.5.3 Wait Control Idle Cycle. 7.6.1 Operation 7.6.2 States Idle Cycle Write Data Buffer Function Release. 7.8.1 Overview 7.8.2 Operation 7.8.3 States External Released State.
7.8.4 Transition Timing. 7.8.5 Usage Note Arbitration 7.9.1 Overview 7.9.2 Operation 7.9.3 Transfer Timing 7.10 Resets Controller.
Section
Data Transfer Controller (DTC) Overview. 8.1.1 Features 8.1.2 Block Diagram. 8.1.3 Register Configuration Register Descriptions. 8.2.1 Mode Register (MRA). 8.2.2 Mode Register (MRB) 8.2.3 Source Address Register (SAR) 8.2.4 Destination Address Register (DAR). 8.2.5 Transfer Count Register (CRA) 8.2.6 Transfer Count Register (CRB) 8.2.7 Enable Registers (DTCER) 8.2.8 Vector Register (DTVECR) 8.2.9 Module Stop Control Register (MSTPCRA). Operation 8.3.1 Overview 8.3.2 Activation Sources. 8.3.3 Vector Table 8.3.4 Location Register Information Address Space 8.3.5 Normal Mode. 8.3.6 Repeat Mode 8.3.7 Block Transfer Mode. 8.3.8 Chain Transfer. 8.3.9 Operation Timing 8.3.10 Number Execution States. 8.3.11 Procedures Using 8.3.12 Examples DTC. Interrupts. Usage Notes Ports Overview. Port 9.2.1 Overview
Section
9.2.2 Register Configuration 9.2.3 Functions. Port 9.3.1 Overview 9.3.2 Register Configuration 9.3.3 Functions. Port 9.4.1 Overview 9.4.2 Register Configuration 9.4.3 Functions. Port 9.5.1 Overview 9.5.2 Register Configuration 9.5.3 Functions. 9.5.4 Input Pull-Up Function Port 9.6.1 Overview 9.6.2 Register Configuration 9.6.3 Functions. 9.6.4 Input Pull-Up Function Port 9.7.1 Overview 9.7.2 Register Configuration 9.7.3 Functions. 9.7.4 Input Pull-Up Function Port 9.8.1 Overview 9.8.2 Register Configuration 9.8.3 Functions. 9.8.4 Input Pull-Up Function Port 9.9.1 Overview 9.9.2 Register Configuration 9.9.3 Functions. 9.9.4 Input Pull-Up Function 9.10 Port 9.10.1 Overview 9.10.2 Register Configuration 9.10.3 Functions.
Section 16-Bit Timer Pulse Unit (TPU)
10.1 Overview. 10.1.1 Features
10.2
10.3
10.4
10.5
10.6
10.7
10.1.2 Block Diagram. 10.1.3 Configuration 10.1.4 Register Configuration Register Descriptions. 10.2.1 Timer Control Register (TCR) 10.2.2 Timer Mode Register (TMDR) 10.2.3 Timer Control Register (TIOR) 10.2.4 Timer Interrupt Enable Register (TIER) 10.2.5 Timer Status Register (TSR) 10.2.6 Timer Counter (TCNT) 10.2.7 Timer General Register (TGR) 10.2.8 Timer Start Register (TSTR). 10.2.9 Timer Synchro Register (TSYR). 10.2.10 Module Stop Control Register (MSTPCRA). Interface Master. 10.3.1 16-Bit Registers. 10.3.2 8-Bit Registers. Operation 10.4.1 Overview 10.4.2 Basic Functions 10.4.3 Synchronous Operation 10.4.4 Buffer Operation 10.4.5 Cascaded Operation. 10.4.6 Modes 10.4.7 Phase Counting Mode Interrupts. 10.5.1 Interrupt Sources Priorities. 10.5.2 Activation 10.5.3 Converter Activation Operation Timing 10.6.1 Input/Output Timing 10.6.2 Interrupt Signal Timing Usage Notes
Section Programmable Pulse Generator (PPG)
11.1 Overview. 11.1.1 Features 11.1.2 Block Diagram. 11.1.3 Configuration 11.1.4 Registers 11.2 Register Descriptions. 11.2.1 Next Data Enable Registers (NDERH, NDERL). 11.2.2 Output Data Registers (PODRH, PODRL)
11.2.3 Next Data Registers (NDRH, NDRL). 11.2.4 Notes Access. 11.2.5 Output Control Register (PCR). 11.2.6 Output Mode Register (PMR). 11.2.7 Port Data Direction Register (P1DDR) 11.2.8 Module Stop Control Register (MSTPCRA). 11.3 Operation 11.3.1 Overview 11.3.2 Output Timing 11.3.3 Normal Pulse Output 11.3.4 Non-Overlapping Pulse Output 11.3.5 Inverted Pulse Output 11.3.6 Pulse Output Triggered Input Capture 11.4 Usage Notes
Section Watchdog Timer
12.1 Overview. 12.1.1 Features 12.1.2 Block Diagram. 12.1.3 Configuration 12.1.4 Register Configuration 12.2 Register Descriptions. 12.2.1 Timer Counter (TCNT) 12.2.2 Timer Control/Status Register (TCSR) 12.2.3 Reset Control/Status Register (RSTCSR) 12.2.4 Function Control Register (PFCR) 12.2.5 Notes Register Access 12.3 Operation 12.3.1 Watchdog Timer Operation. 12.3.2 Interval Timer Operation. 12.3.3 Timing Setting Overflow Flag (OVF). 12.3.4 Timing Setting Watchdog Timer Overflow Flag (WOVF) 12.4 Interrupts. 12.5 Usage Notes 12.5.1 Contention between Timer Counter (TCNT) Write Increment 12.5.2 Changing Value CKS2 CKS0. 12.5.3 Switching between Watchdog Timer Mode Interval Timer Mode. 12.5.4 System Reset WDTOVF Signal. 12.5.5 Internal Reset Watchdog Timer Mode
Section Serial Communication Interface (SCI)
13.1 Overview. 13.1.1 Features
viii
13.2
13.3
13.4 13.5
13.1.2 Block Diagram. 13.1.3 Configuration 13.1.4 Register Configuration Register Descriptions. 13.2.1 Receive Shift Register (RSR). 13.2.2 Receive Data Register (RDR) 13.2.3 Transmit Shift Register (TSR). 13.2.4 Transmit Data Register (TDR) 13.2.5 Serial Mode Register (SMR). 13.2.6 Serial Control Register (SCR). 13.2.7 Serial Status Register (SSR). 13.2.8 Rate Register (BRR). 13.2.9 Smart Card Mode Register (SCMR) 13.2.10 Module Stop Control Register (MSTPCRB). Operation 13.3.1 Overview 13.3.2 Operation Asynchronous Mode. 13.3.3 Multiprocessor Communication Function. 13.3.4 Operation Clocked Synchronous Mode Interrupts Usage Notes
Section Smart Card Interface
14.1 Overview. 14.1.1 Features 14.1.2 Block Diagram. 14.1.3 Configuration 14.1.4 Register Configuration 14.2 Register Descriptions. 14.2.1 Smart Card Mode Register (SCMR) 14.2.2 Serial Status Register (SSR). 14.2.3 Serial Mode Register (SMR). 14.2.4 Serial Control Register (SCR). 14.3 Operation 14.3.1 Overview 14.3.2 Connections. 14.3.3 Data Format. 14.3.4 Register Settings. 14.3.5 Clock 14.3.6 Data Transfer Operations 14.3.7 Operation Mode. 14.3.8 Operation Block Transfer Mode 14.4 Usage Notes
Section Hitachi Controller Area Network (HCAN)
15.1 Overview. 15.1.1 Features 15.1.2 Block Diagram. 15.1.3 Configuration 15.1.4 Register Configuration 15.2 Register Descriptions. 15.2.1 Master Control Register (MCR). 15.2.2 General Status Register (GSR). 15.2.3 Configuration Register (BCR). 15.2.4 Mailbox Configuration Register (MBCR). 15.2.5 Transmit Wait Register (TXPR) 15.2.6 Transmit Wait Cancel Register (TXCR) 15.2.7 Transmit Acknowledge Register (TXACK) 15.2.8 Abort Acknowledge Register (ABACK). 15.2.9 Receive Complete Register (RXPR) 15.2.10 Remote Request Register (RFPR). 15.2.11 Interrupt Register (IRR) 15.2.12 Mailbox Interrupt Mask Register (MBIMR). 15.2.13 Interrupt Mask Register (IMR) 15.2.14 Receive Error Counter (REC) 15.2.15 Transmit Error Counter (TEC) 15.2.16 Unread Message Status Register (UMSR) 15.2.17 Local Acceptance Filter Masks (LAFML, LAFMH) 15.2.18 Message Control (MC0 MC15). 15.2.19 Message Data (MD0 MD15). 15.2.20 Module Stop Control Register (MSTPCRC). 15.3 Operation 15.3.1 Hardware Software Resets. 15.3.2 Initialization after Hardware Reset 15.3.3 Transmit Mode 15.3.4 Receive Mode. 15.3.5 HCAN Sleep Mode 15.3.6 HCAN Halt Mode 15.3.7 Interrupt Interface. 15.3.8 Interface. 15.4 Interface 15.5 Usage Notes
Section Converter
16.1 Overview. 16.1.1 Features 16.1.2 Block Diagram.
16.2
16.3 16.4
16.5 16.6
16.1.3 Configuration 16.1.4 Register Configuration Register Descriptions. 16.2.1 Data Registers (ADDRA ADDRD). 16.2.2 Control/Status Register (ADCSR). 16.2.3 Control Register (ADCR). 16.2.4 Module Stop Control Register (MSTPCRA). Interface Master. Operation 16.4.1 Single Mode (SCAN 16.4.2 Scan Mode (SCAN 16.4.3 Input Sampling Conversion Time. 16.4.4 External Trigger Input Timing Interrupts. Usage Notes
Section Converter [Provided H8S/2626 Series only]
17.1 Overview. 17.1.1 Features 17.1.2 Block Diagram. 17.1.3 Configuration 17.1.4 Register Configuration 17.2 Register Descriptions. 17.2.1 Data Registers (DADR2, DADR3). 17.2.2 Control Register (DACR23). 17.2.3 Module Stop Control Register (MSTPCRC). 17.3 Operation
Section
18.1 Overview. 18.1.1 Block Diagram. 18.1.2 Register Configuration 18.2 Register Descriptions. 18.2.1 System Control Register (SYSCR) 18.3 Operation 18.4 Usage Notes
Section
19.1 Features. 19.2 Overview. 19.2.1 Block Diagram. 19.2.2 Mode Transitions. 19.2.3 On-Board Programming Modes
19.3 19.4 19.5
19.6
19.7
19.8
19.9 19.10 19.11
19.12 19.13 19.14
19.2.4 Flash Memory Emulation RAM. 19.2.5 Differences between Boot Mode User Program Mode. 19.2.6 Block Configuration Configuration Register Configuration Register Descriptions. 19.5.1 Flash Memory Control Register (FLMCR1). 19.5.2 Flash Memory Control Register (FLMCR2). 19.5.3 Erase Block Register (EBR1). 19.5.4 Erase Block Register (EBR2). 19.5.5 Emulation Register (RAMER) 19.5.6 Flash Memory Power Control Register (FLPWCR) 19.5.7 Serial Control Register (SCRX) On-Board Programming Modes 19.6.1 Boot Mode. 19.6.2 User Program Mode Flash Memory Programming/Erasing. 19.7.1 Program Mode. 19.7.2 Program-Verify Mode 19.7.3 Erase Mode. 19.7.4 Erase-Verify Mode Protection. 19.8.1 Hardware Protection. 19.8.2 Software Protection 19.8.3 Error Protection Flash Memory Emulation RAM. Interrupt Handling when Programming/Erasing Flash Memory Flash Memory Programmer Mode 19.11.1 Socket Adapter Correspondence Diagram 19.11.2 Programmer Mode Operation. 19.11.3 Memory Read Mode. 19.11.4 Auto-Program Mode 19.11.5 Auto-Erase Mode. 19.11.6 Status Read Mode. 19.11.7 Status Polling. 19.11.8 Programmer Mode Transition Time. 19.11.9 Notes Memory Programming. Flash Memory Power-Down States 19.12.1 Note Power-Down States Flash Memory Programming Erasing Precautions Note Switching from F-ZTAT Version Mask Version
Section Clock Pulse Generator
20.1 Overview. 20.1.1 Block Diagram. 20.1.2 Register Configuration 20.2 Register Descriptions. 20.2.1 System Clock Control Register (SCKCR) 20.2.2 Low-Power Control Register (LPWRCR). 20.3 Oscillator. 20.3.1 Connecting Crystal Resonator 20.3.2 External Clock Input 20.4 Circuit. 20.5 Medium-Speed Clock Divider. 20.6 Master Clock Selection Circuit 20.7 Subclock Oscillator. 20.8 Subclock Waveform Shaping Circuit. 20.9 Note Crystal Resonator.
Section Power-Down Modes [H8S/2623 Series]
21A.1 21A.2 Overview 21A.1.1 Register Configuration Register Descriptions. 21A.2.1 Standby Control Register (SBYCR) 21A.2.2 System Clock Control Register (SCKCR) 21A.2.3 Low-Power Control Register (LPWRCR). 21A.2.4 Module Stop Control Register (MSTPCR) Medium-Speed Mode Sleep Mode. 21A.4.1 Sleep Mode. 21A.4.2 Exiting Sleep Mode. Module Stop Mode 21A.5.1 Module Stop Mode 21A.5.2 Usage Notes. Software Standby Mode 21A.6.1 Software Standby Mode 21A.6.2 Clearing Software Standby Mode 21A.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode 21A.6.4 Software Standby Mode Application Example 21A.6.5 Usage Notes. Hardware Standby Mode. 21A.7.1 Hardware Standby Mode. 21A.7.2 Hardware Standby Mode Timing Clock Output Disabling Function.
xiii
21A.3 21A.4
21A.5
21A.6
21A.7
21A.8
Section Power-Down Modes [H8S/2626 Series]
21B.1 Overview 21B.1.1 Register Configuration 21B.2 Register Descriptions. 21B.2.1 Standby Control Register (SBYCR) 21B.2.2 System Clock Control Register (SCKCR) 21B.2.3 Low-Power Control Register (LPWRCR). 21B.2.4 Timer Control/Status Register (TCSR) 21B.2.5 Module Stop Control Register (MSTPCR) 21B.3 Medium-Speed Mode 21B.4 Sleep Mode. 21B.4.1 Sleep Mode. 21B.4.2 Exiting Sleep Mode. 21B.5 Module Stop Mode 21B.5.1 Module Stop Mode 21B.5.2 Usage Notes. 21B.6 Software Standby Mode 21B.6.1 Software Standby Mode 21B.6.2 Clearing Software Standby Mode 21B.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode 21B.6.4 Software Standby Mode Application Example 21B.6.5 Usage Notes. 21B.7 Hardware Standby Mode. 21B.7.1 Hardware Standby Mode. 21B.7.2 Hardware Standby Mode Timing 21B.8 Watch Mode 21B.8.1 Watch Mode 21B.8.2 Exiting Watch Mode 21B.8.3 Notes. 21B.9 Sub-Sleep Mode 21B.9.1 Sub-Sleep Mode 21B.9.2 Exiting Sub-Sleep Mode 21B.10 Sub-Active Mode. 21B.10.1 Sub-Active Mode. 21B.10.2 Exiting Sub-Active Mode. 21B.11 Direct Transitions 21B.11.1 Overview Direct Transitions. 21B.12 Clock Output Disabling Function.
Section Electrical Characteristics
22.1 Absolute Maximum Ratings. 22.2 Characteristics
22.3 Characteristics 22.3.1 Clock Timing. 22.3.2 Control Signal Timing. 22.3.3 Timing 22.3.4 Timing On-Chip Supporting Modules 22.4 Conversion Characteristics 22.5 Conversion Characteristics 22.6 Flash Memory Characteristics 22.7 Usage Note
Appendix Instruction
Instruction List. Instruction Codes Operation Code Map. Number States Required Instruction Execution States During Instruction Execution Condition Code Modification.
Appendix Internal Register
Address Functions.
Appendix Port Block Diagrams
Port Block Diagrams Port Block Diagram. Port Block Diagram. Port Block Diagrams. Port Block Diagram 1003 Port Block Diagrams. 1004 Port Block Diagram 1008 Port Block Diagram. 1009 Port Block Diagrams 1010
Appendix States 1019
Port States Each Mode 1019
Appendix Appendix
Timing Transition Recovery from Hardware Standby Mode 1022 Product Code Lineup 1023
Appendix Package Dimensions 1024
Section Overview
Overview
H8S/2626 Series H8S/2623 Series series microcomputers (MCUs) that integrate peripheral functions required system configuration together with H8S/2600 employing original Hitachi architecture. H8S/2600 internal 32-bit architecture, provided with sixteen 16-bit general registers concise, optimized instruction designed high-speed operation, address 16-Mbyte linear address space. instruction upward-compatible with H8/300 H8/300H instructions object-code level, facilitating migration from H8/300, H8/300L, H8/300H Series. On-chip peripheral functions required system configuration include data transfer controller (DTC) master, memory, a16-bit timer-pulse unit (TPU), programmable pulse generator (PPG), watchdog timer (WDT), serial communication interface (SCI), Hitachi controller area network (HCAN), converter, converter (H8S/2626 Series only), ports. on-chip 256-kbyte flash memory (F-ZTATTM)* 256-, 128-, 64-kbyte mask ROM. connected 16-bit data bus, enabling both byte word data accessed state. Instruction fetching been speeded processing speed increased. Four operating modes, modes provided, there choice single-chip mode external expansion mode. features H8S/2626 Series H8S/2623 Series shown table 1-1. Note: F-ZTAT trademark Hitachi, Ltd.
Table
Item
Overview
Specifications General-register machine Sixteen 16-bit general registers (also usable sixteen 8-bit registers eight 32-bit registers) High-speed operation suitable realtime control Maximum operating frequency: High-speed arithmetic operations 8/16/32-bit register-register add/subtract: 16-bit register-register multiply: 42-bit multiply accumulate: 16-bit register-register divide: 1000 Instruction suitable high-speed operation basic instructions 8/16/32-bit move/arithmetic logic instructions Unsigned/signed multiply divide instructions Multiply-and accumulate instruction Powerful bit-manipulation instructions operating modes Normal mode: 64-kbyte address space (Not available H8S/2626 Series H8S/2623 Series) Advanced mode: 16-Mbyte address space
controller
Address space divided into areas, with specifications settable independently each area Choice 8-bit 16-bit access space each area 2-state 3-state access space designated each area Number program wait states each area Burst directly connectable External release function Supports debugging functions means break interrupts break channels
break controller
Item Data transfer controller (DTC)
Specifications activated internal interrupt software Multiple transfers multiple types transfer possible activation source Transfer possible repeat mode, block transfer mode, etc. Request sent interrupt that activated 6-channel 16-bit timer Pulse input/output processing capability pins Automatic 2-phase encoder count capability Maximum 8-bit pulse output possible with time base Output trigger selectable 4-bit groups Non-overlap margin Direct output inverse output setting Watchdog timer interval timer selectable Subclock operation possible (one channel only) Watchdog timer interval timer selectable
16-bit timer-pulse unit (TPU)
Programmable pulse generator (PPG)
Watchdog timer (WDT), channels (H8S/2626 Series) Watchdog timer (WDT), channel (H8S/2623 Series) Serial communication interface (SCI), channels (SCI0 SCI2) Hitachi controller area network (HCAN), channel converter converter (H8S/2626 Series only)
Asynchronous mode synchronous mode selectable Multiprocessor communication function Smart card interface function CAN: Ver. 2.0B compliant Buffer size: transmit/receive buffers, transmit-only buffer Receive message filtering Resolution: bits Input: channels 13.3 minimum conversion time operation) Single scan mode selectable Sample-and-hold function conversion activated external trigger timer trigger Resolution: bits Output: channels
Item
Specifications input/output pins, input-only pins input/output pins, input-only pins Flash memory masked High-speed static
Product Name H8S/2626, H8S/2623 H8S/2625*, H8S/2622 H8S/2624*, H8S/2621 Note: planning stage kbytes kbytes kbytes kbytes kbytes kbytes
ports (H8S/2626 Series) ports (H8S/2623 Series) Memory
Interrupt controller
Seven external interrupt pins (NMI, IRQ0 IRQ5) Internal interrupt sources H8S/2626: H8S/2623:
Power-down state Operating modes
Eight priority levels settable Medium-speed mode Sleep mode Module stop mode Software standby mode Hardware standby mode Subclock operation (H8S/2626 Series only) Four operating modes
External Data Operating Mode Advanced On-Chip Disabled Disabled Enabled Enabled Initial Width bits bits bits Max. Width bits bits bits
Mode
Description On-chip disabled expansion mode On-chip disabled expansion mode On-chip enabled expansion mode Single-chip mode
Item Clock pulse generator Package Product lineup
Specifications Built-in circuit Input clock frequency: 100-pin plastic (FP-100B) Model Mask Version HD6432626* HD6432623* HD6432625* HD6432622* HD6432624* HD6432621* F-ZTAT Version HD64F2626 HD64F2623 ROM/RAM (Bytes) k/12 Package FP-100B FP-100B FP-100B
Note: planning stage
Internal Block Diagram
Figures show internal block diagrams H8S/2623 Series H8S/2626 Series.
PD7/D15 PD6/D14 PD5/D13 PD4/D12 PD3/D11 PD2/D10 PD1/D9 PD0/D8 Port PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 Port
PF6/AS PF5/RD PF4/HWR PF3/LWR/ADTRG/IRQ3 PF2/WAIT/BREQO PF1/BACK PF0/BREQ/IRQ2
break controller channels) Port
Peripheral data
Peripheral address
EXTAL XTAL PLLVCC PLLCAP PLLVSS STBY WDTOVF FWE*2
PVCC1 PVCC2 PVCC3 PVCC4
Clock pulse generator
H8S/2600
Internal data
Internal address
PA3/A19/SCK2 PA2/A18/RxD2 PA1/A17/TxD2 PA0/A16 PB7/A15/TIOCB5 PB6/A14/TIOCA5 PB5/A13/TIOCB4 PB4/A12/TIOCA4 PB3/A11/TIOCD3 PB2/A10/TIOCC3 PB1/A9/TIOCB3 PB0/A8/TIOCA3 PC7/A7 PC6/A6 PC5/A5/SCK1/IRQ5 PC4/A4/RxD1 PC3/A3/TxD1 PC2/A2/SCK0/IRQ4 PC1/A1/RxD0 PC0/A0/TxD0
controller
Interrupt controller
channel channels
HCAN channel
Port
(Mask ROM, flash memory*1)
Port
Port
converter Port
P97/AN15 P96/AN14 P95/AN13 P94/AN12 P93/AN11 P92/AN10 P91/AN9 P90/AN8
Port
Port
P17/PO15/TIOCB2/TCLKD P16/PO14/TIOCA2/IRQ1 P15/PO13/TIOCB1/TCLKC P14/PO12/TIOCA1/IRQ0 P13/PO11/TIOCD0/TCLKB/A23 P12/PO10/TIOCC0/TCLKA/A22 P11/PO9/TIOCB0/A21 P10/PO8/TIOCA0/A20
HRxD HTxD Vref AVCC AVSS
Notes: Applies H8S/2623 only. used only flash memory version.
Figure Internal Block Diagram
P47/AN7 P46/AN6 P45/AN5 P44/AN4 P43/AN3 P42/AN2 P41/AN1 P40/AN0
PD7/D15 PD6/D14 PD5/D13 PD4/D12 PD3/D11 PD2/D10 PD1/D9 PD0/D8 Port
controller
PF6/AS PF5/RD PF4/HWR PF3/LWR/ADTRG/IRQ3 PF2/WAIT/BREQO PF1/BACK PF0/BREQ/IRQ2
break controller channels) Port
Peripheral address
OSC1 OSC2 EXTAL XTAL PLLVCC PLLCAP PLLVSS STBY WDTOVF FWE*2
PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 Port Port
PVCC1 PVCC2 PVCC3 PVCC4
Clock pulse generator
H8S/2600
Internal address
Internal data
PA3/A19/SCK2 PA2/A18/RxD2 PA1/A17/TxD2 PA0/A16 PB7/A15/TIOCB5 PB6/A14/TIOCA5 PB5/A13/TIOCB4 PB4/A12/TIOCA4 PB3/A11/TIOCD3 PB2/A10/TIOCC3 PB1/A9/TIOCB3 PB0/A8/TIOCA3 PC7/A7 PC6/A6 PC5/A5/SCK1/IRQ5 PC4/A4/RxD1 PC3/A3/TxD1 PC2/A2/SCK0/IRQ4 PC1/A1/RxD0 PC0/A0/TxD0
Interrupt controller
channels channels
HCAN channel converter
Port
(mask flash memory*1)
Peripheral data
Port
converter Port
P97/AN15/DA3 P96/AN14/DA2 P95/AN13 P94/AN12 P93/AN11 P92/AN10 P91/AN9 P90/AN8
Port
Port
P17/PO15/TIOCB2/TCLKD P16/PO14/TIOCA2/IRQ1 P15/PO13/TIOCB1/TCLKC P14/PO12/TIOCA1/IRQ0 P13/PO11/TIOCD0/TCLKB/A23 P12/PO10/TIOCC0/TCLKA/A22 P11/PO9/TIOCB0/A21 P10/PO8/TIOCA0/A20
HRxD HTxD Vref AVCC AVSS
Notes: Applies H8S/2626 only. provided flash memory version only.
Figure Internal Block Diagram
P47/AN7 P46/AN6 P45/AN5 P44/AN4 P43/AN3 P42/AN2 P41/AN1 P40/AN0
1.3.1
Descriptions
Arrangement
Figures show arrangements H8S/2623 Series H8S/2626 Series.
PF0/BREQ/IRQ2 PF1/BACK PF2/WAIT/BREQO PF3/LWR/ADTRG/IRQ3 PF4/HWR PF5/PD PF6/AS EXTAL XTAL STBY PLLVCC PLLCAP PLLVSS PVCC3 AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6 P47/AN7 P90/AN8 P91/AN9 P92/AN10 P93/AN11 P94/AN12 P95/AN13 P96/AN14 P97/AN15 AVSS WDTOVF PVCC4 P10/PO8/TIOCA0/A20 P11/PO9/TIOCB0/A21 P12/PO10/TIOCC0/TCLKA/A22
view (FP-100B)
PA3/A19/SCK2 PA2/A18/RxD2 PA1/A17/TxD2 PA0/A16 PB7/A15/TIOCB5 PB6/A14/TIOCA5 PB5/A13/TIOCB4 PB4/A12/TIOCA4 PB3/A11/TIOCD3 PB2/A10/TIOCC3 PVCC2 PB1/A9/TIOCB3 PB0/A8/TIOCA3 PC7/A7 PC6/A6 PC5/A5/SCK1/IRQ5 PC4/A4/RxD1 PC3/A3/TxD1 PC2/A2/SCK0/IRQ4 PC1/A1/RxD0 PC0/A0/TxD0 PD7/D15 PD6/D14
Figure Arrangement (FP-100B: View)
P13/PO11/TIOCD0/TCLKB/A23 P14/PO12/TIOCA1/IRQ0 P15/PO13/TIOCB1/TCLKC P16/PO14/TIOCA2/IRQ1 P17/PO15/TIOCB2/TCLKD HTxD HRxD PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 PE5/D5 PVCC1 PE6/D6 PE7/D7 PD0/D8 PD1/D9 PD2/D10 PD3/D11 PD4/D12 PD5/D13
AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6 P47/AN7 P90/AN8 P91/AN9 P92/AN10 P93/AN11 P94/AN12 P95/AN13 P96/AN14/DA2 P97/AN15/DA3 AVSS WDTOVF PVCC4 P10/PO8/TIOCA0/A20 P11/PO9/TIOCB0/A21 P12/PO10/TIOCC0/TCLKA/A22
PF0/BREQ/IRQ2 PF1/BACK/BUZZ PF2/WAIT/BREQO PF3/LWR/ADTRG/IRQ3 PF4/HWR PF5/PD PF6/AS EXTAL XTAL STBY PLLVCC PLLCAP PLLVSS PVCC3 OSC2
view (FP-100B)
OSC1 PA3/A19/SCK2 PA2/A18/RxD2 PA1/A17/TxD2 PA0/A16 PB7/A15/TIOCB5 PB6/A14/TIOCA5 PB5/A13/TIOCB4 PB4/A12/TIOCA4 PB3/A11/TIOCD3 PB2/A10/TIOCC3 PVCC2 PB1/A9/TIOCB3 PB0/A8/TIOCA3 PC7/A7 PC6/A6 PC5/A5/SCK1/IRQ5 PC4/A4/RxD1 PC3/A3/TxD1 PC2/A2/SCK0/IRQ4 PC1/A1/RxD0 PC0/A0/TxD0 PD7/D15 PD6/D14
Figure Arrangement (FP-100B: View)
P13/PO11/TIOCD0/TCLKB/A23 P14/PO12/TIOCA1/IRQ0 P15/PO13/TIOCB1/TCLKC P16/PO14/TIOCA2/IRQ1 P17/PO15/TIOCB2/TCLKD HTxD HRxD PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 PE5/D5 PVCC1 PE6/D6 PE7/D7 PD0/D8 PD1/D9 PD2/D10 PD3/D11 PD4/D12 PD5/D13
1.3.2
Functions Each Operating Mode
Tables show functions each operating modes H8S/2623 Series H8S/2626 Series. Table
FP-100B Mode Mode
Functions Each Operating Mode
Name Mode Mode
P13/PO11/TIOCD0/ P13/PO11/TIOCD0/ P13/PO11/TIOCD0/ P13/PO11/TIOCD0/ TCLKB/A23 TCLKB/A23 TCLKB/A23 TCLKB P14/PO12/TIOCA1/ P14/PO12/TIOCA1/ P14/PO12/TIOCA1/ P14/PO12/TIOCA1/ IRQ0 IRQ0 IRQ0 IRQ0 P15/PO13/TIOCB1/ P15/PO13/TIOCB1/ P15/PO13/TIOCB1/ P15/PO13/TIOCB1/ TCLKC TCLKC TCLKC TCLKC P16/PO14/TIOCA2/ P16/PO14/TIOCA2/ P16/PO14/TIOCA2/ P16/PO14/TIOCA2/ IRQ1 IRQ1 IRQ1 IRQ1 P17/PO15/TIOCB2/ P17/PO15/TIOCB2/ P17/PO15/TIOCB2/ P17/PO15/TIOCB2/ TCLKD TCLKD TCLKD TCLKD HTxD HRxD PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 PE5/D5 PVCC1 PE6/D6 PE7/D7 HTxD HRxD PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 PE5/D5 PVCC1 PE6/D6 PE7/D7 HTxD HRxD PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 PE5/D5 PVCC1 PE6/D6 PE7/D7 HTxD HRxD PVCC1
FP-100B Mode PB0/A8/TIOCA3 PB1/A9/TIOCB3 PVCC2 PB2/A10/TIOCC3 PB3/A11/TIOCD3 PB4/A12/TIOCA4 PB5/A13/TIOCB4 PB6/A14/TIOCA5 PB7/A15/TIOCB5 PA0/A16 PA1/A17/TxD2 PA2/A18/RxD2 PA3/A19/SCK2 PVCC3 Mode
Name Mode PC0/A0/TxD0 PC1/A1/RxD0 Mode PC0/TxD0 PC1/RxD0
PC2/A2/SCK0/IRQ4 PC2/SCK0/IRQ4 PC3/A3/TxD1 PC4/A4/RxD1 PC3/TxD1 PC4/RxD1
PC5/A5/SCK1/IRQ5 PC5/SCK1/IRQ5 PC6/A6 PC7/A7 PB0/A8/TIOCA3 PB1/A9/TIOCB3 PVCC2 PB2/A10/TIOCC3 PB3/A11/TIOCD3 PB4/A12/TIOCA4 PB5/A13/TIOCB4 PB6/A14/TIOCA5 PB7/A15/TIOCB5 PA0/A16 PA1/A17/TxD2 PA2/A18/RxD2 PA3/A19/SCK2 PVCC3 PB0/TIOCA3 PB1/TIOCB3 PVCC2 PB2/TIOCC3 PB3/TIOCD3 PB4/TIOCA4 PB5/TIOCB4 PB6/TIOCA5 PB7/TIOCB5 PA1/TxD2 PA2/RxD2 PA3/SCK2 PVCC3
PB0/A8/TIOCA3 PB1/A9/TIOCB3 PVCC2 PB2/A10/TIOCC3 PB3/A11/TIOCD3 PB4/A12/TIOCA4 PB5/A13/TIOCB4 PB6/A14/TIOCA5 PB7/A15/TIOCB5 PA0/A16 PA1/A17/TxD2 PA2/A18/RxD2 PA3/A19/SCK2 PVCC3
FP-100B Mode PLLVSS PLLCAP PLLVCC STBY XTAL EXTAL Mode PLLVSS PLLCAP PLLVCC STBY XTAL EXTAL
Name Mode PLLVSS PLLCAP PLLVCC STBY XTAL EXTAL Mode PLLVSS PLLCAP PLLVCC STBY XTAL EXTAL
PF3/LWR/ADTRG/ PF3/LWR/ADTRG/ PF3/LWR/ADTRG/ PF3/ADTRG/ IRQ3 IRQ3 IRQ3 IRQ3 PF2/WAIT/BREQO PF2/WAIT/BREQO PF2/WAIT/BREQO PF1/BACK PF0/BREQ/IRQ2 AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6 P47/AN7 P90/AN8 P91/AN9 PF1/BACK PF0/BREQ/IIRQ2 AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6 P47/AN7 P90/AN8 P91/AN9 PF1/BACK PF0/BREQ/IIRQ2 AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6 P47/AN7 P90/AN8 P91/AN9 PF0/IRQ2 AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6 P47/AN7 P90/AN8 P91/AN9
FP-100B Mode P92/AN10 P93/AN11 P94/AN12 P95/AN13 P96/AN14 P97/AN15 AVSS WDTOVF PVCC4 P10/PO8/TIOCA0/ P11/PO9/TIOCB0/ Mode P92/AN10 P93/AN11 P94/AN12 P95/AN13 P96/AN14 P97/AN15 AVSS WDTOVF PVCC4
Name Mode P92/AN10 P93/AN11 P94/AN12 P95/AN13 P96/AN14 P97/AN15 AVSS WDTOVF PVCC4 P10/PO8/TIOCA0/ P11/PO9/TIOCB0/ Mode P92/AN10 P93/AN11 P94/AN12 P95/AN13 P96/AN14 P97/AN15 AVSS WDTOVF PVCC4 P10/PO8/TIOCA0 P11/PO9/TIOCB0
P10/PO8/TIOCA0/ P11/PO9/TIOCB0/
P12/PO10/TIOCC0/ P12/PO10/TIOCC0/ P12/PO10/TIOCC0/ P12/PO10/TIOCC0/ TCLKA/A22 TCLKA/A22 TCLKA/A22 TCLKA
Note: pins should connected left open.
Table
FP-100B
Functions Each Operating Mode
Name Mode Mode Mode Mode
P13/PO11/TIOCD0/ P13/PO11/TIOCD0/ P13/PO11/TIOCD0/ P13/PO11/TIOCD0/ TCLKB/A23 TCLKB/A23 TCLKB/A23 TCLKB P14/PO12/TIOCA1/ P14/PO12/TIOCA1/ P14/PO12/TIOCA1/ P14/PO12/TIOCA1/ IRQ0 IRQ0 IRQ0 IRQ0 P15/PO13/TIOCB1/ P15/PO13/TIOCB1/ P15/PO13/TIOCB1/ P15/PO13/TIOCB1/ TCLKC TCLKC TCLKC TCLKC P16/PO14/TIOCA2/ P16/PO14/TIOCA2/ P16/PO14/TIOCA2/ P16/PO14/TIOCA2/ IRQ1 IRQ1 IRQ1 IRQ1 P17/PO15/TIOCB2/ P17/PO15/TIOCB2/ P17/PO15/TIOCB2/ P17/PO15/TIOCB2/ TCLKD TCLKD TCLKD TCLKD HTxD HRxD PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 PE5/D5 PVCC1 PE6/D6 PE7/D7 HTxD HRxD PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 PE5/D5 PVCC1 PE6/D6 PE7/D7 HTxD HRxD PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 PE5/D5 PVCC1 PE6/D6 PE7/D7 HTxD HRxD PVCC1
FP-100B Mode PB0/A8/TIOCA3 PB1/A9/TIOCB3 PVCC2 PB2/A10/TIOCC3 PB3/A11/TIOCD3 PB4/A12/TIOCA4 PB5/A13/TIOCB4 PB6/A14/TIOCA5 PB7/A15/TIOCB5 PA0/A16 PA1/A17/TxD2 PA2/A18/RxD2 PA3/A19/SCK2 OSC1 OSC2 PVCC3 Mode
Name Mode PC0/A0/TxD0 PC1/A1/RxD0 Mode PC0/TxD0 PC1/RxD0
PC2/A2/SCK0/IRQ4 PC2/SCK0/IRQ4 PC3/A3/TxD1 PC4/A4/RxD1 PC3/TxD1 PC4/RxD1
PC5/A5/SCK1/IRQ5 PC5/SCK1/IRQ5 PC6/A6 PC7/A7 PB0/A8/TIOCA3 PB1/A9/TIOCB3 PVCC2 PB2/A10/TIOCC3 PB3/A11/TIOCD3 PB4/A12/TIOCA4 PB5/A13/TIOCB4 PB6/A14/TIOCA5 PB7/A15/TIOCB5 PA0/A16 PA1/A17/TxD2 PA2/A18/RxD2 PA3/A19/SCK2 OSC1 OSC2 PVCC3 PB0/TIOCA3 PB1/TIOCB3 PVCC2 PB2/TIOCC3 PB3/TIOCD3 PB4/TIOCA4 PB5/TIOCB4 PB6/TIOCA5 PB7/TIOCB5 PA1/TxD2 PA2/RxD2 PA3/SCK2 OSC1 OSC2 PVCC3
PB0/A8/TIOCA3 PB1/A9/TIOCB3 PVCC2 PB2/A10/TIOCC3 PB3/A11/TIOCD3 PB4/A12/TIOCA4 PB5/A13/TIOCB4 PB6/A14/TIOCA5 PB7/A15/TIOCB5 PA0/A16 PA1/A17/TxD2 PA2/A18/RxD2 PA3/A19/SCK2 OSC1 OSC2 PVCC3
FP-100B Mode PLLVSS PLLCAP PLLVCC STBY XTAL EXTAL PF3/LWR/ADTRG/ IRQ3 PF2/WAIT/BREQO PF1/BACK/BUZZ PF0/BREQ/IRQ2 AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6 P47/AN7 P90/AN8 P91/AN9 Mode PLLVSS PLLCAP PLLVCC STBY XTAL EXTAL
Name Mode PLLVSS PLLCAP PLLVCC STBY XTAL EXTAL PF3/LWR/ADTRG/ IRQ3 PF2/WAIT/BREQO PF1/BACK/BUZZ PF0/BREQ/IIRQ2 AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6 P47/AN7 P90/AN8 P91/AN9 Mode PLLVSS PLLCAP PLLVCC STBY XTAL EXTAL PF3/ADTRG/ IRQ3 PF1/BUZZ PF0/IRQ2 AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6 P47/AN7 P90/AN8 P91/AN9
PF3/LWR/ADTRG/ IRQ3 PF2/WAIT/BREQO PF1/BACK/BUZZ PF0/BREQ/IIRQ2 AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6 P47/AN7 P90/AN8 P91/AN9
FP-100B Mode P92/AN10 P93/AN11 P94/AN12 P95/AN13 P96/AN14/DA2 P97/AN15/DA3 AVSS WDTOVF PVCC4 P10/PO8/TIOCA0/ P11/PO9/TIOCB0/ Mode P92/AN10 P93/AN11 P94/AN12 P95/AN13 P96/AN14/DA2 P97/AN15/DA3 AVSS WDTOVF PVCC4
Name Mode P92/AN10 P93/AN11 P94/AN12 P95/AN13 P96/AN14/DA2 P97/AN15/DA3 AVSS WDTOVF PVCC4 P10/PO8/TIOCA0/ P11/PO9/TIOCB0/ Mode P92/AN10 P93/AN11 P94/AN12 P95/AN13 P96/AN14/DA2 P97/AN15/DA3 AVSS WDTOVF PVCC4 P10/PO8/TIOCA0 P11/PO9/TIOCB0
P10/PO8/TIOCA0/ P11/PO9/TIOCB0/
P12/PO10/TIOCC0/ P12/PO10/TIOCC0/ P12/PO10/TIOCC0/ P12/PO10/TIOCC0/ TCLKA/A22 TCLKA/A22 TCLKA/A22 TCLKA
Note: pins should connected left open.
1.3.3
Functions
Table summarizes functions. Table
Type Power supply
Functions
Symbol Input Name Power supply Function connection power supply. Connect pins system power supply.
PVCC1 PVCC2 PVCC3 PVCC4
Input Input Input Input Input
Port power supply Port power supply pins. Connect Port power supply these pins same power supply. Port power supply Port power supply Ground connection power supply Connect pins system power supply
Clock
PLLVCC PLLVSS PLLCAP XTAL
Input Input Input Input
power supply On-chip oscillator power supply ground capacitance Crystal On-chip oscillator ground On-chip oscillator external capacitance connection crystal resonator. examples crystal resonator connection external clock input, section Clock Pulse Generator. connection crystal resonator. examples crystal resonator connection external clock input, section Clock Pulse Generator. connection recommended 32.768 resonator. examples crystal resonator connection, section Clock Pulse Generator. connection recommended 32.768 resonator. examples crystal resonator connection, section Clock Pulse Generator. Supplies system clock external devices.
EXTAL
Input
External clock
OSC1*
Input
Subclock
OSC2*
Input
Subclock
Output
System clock
Type Operating mode control
Symbol
Input
Name Mode pins
Function These pins operating mode. relation between settings pins operating mode shown below. Inputs these pins should changed during operation.
Operating Mode Mode Mode Mode Mode
System control
STBY BREQ BREQO
Input Input Input Output
Reset input Standby request request output
When this driven low, chip reset. When this driven low, transition made hardware standby mode. Used external master issue request chip. External request signal used when internal master accesses external space external busreleased state. Indicates that been released external master.
BACK Interrupts
Output Input Input
request acknowledge
Flash write enable flash memory Nonmaskable interrupt Interrupt request Address Requests nonmaskable interrupt. this used, should fixed high. These pins request maskable interrupt. These pins output address signals.
IRQ5 IRQ0 Address
Input Output
Type Data control
Symbol
Input/ output Output Output Output
Name Data Address strobe Read High write
Function Bidirectional data Goes indicate valid address output address bus. Goes indicate reading from external address space. Strobe signal indicating writing external address space; indicates valid data upper data (D15 D8). Strobe signal indicating writing external address space; indicates valid data lower data D0). Requests insertion wait states cycles during access 3-state external address space. These pins input external clock.
Output
write
WAIT
Input
Wait
16-bit timerpulse unit (TPU)
TCLKD TCLKA TIOCA0, TIOCB0, TIOCC0, TIOCD0 TIOCA1, TIOCB1 TIOCA2, TIOCB2 TIOCA3, TIOCB3, TIOCC3, TIOCD3 TIOCA4, TIOCB4 TIOCA5, TIOCB5
Input
Clock input Input capture/ output compare match Input capture/ output compare match Input capture/ output compare match Input capture/ output compare match Input capture/ output compare match Input capture/ output compare match
Input/ output
TGR0A TGR0D input capture input/output compare output/PWM output pins TGR1A TGR1B input capture input/output compare output/PWM output pins TGR2A TGR2B input capture input/output compare output/PWM output pins TGR3A TGR3D input capture input/output compare output/PWM output pins TGR4A TGR4B input capture input/output compare output/PWM output pins TGR5A TGR5B input capture input/output compare output/PWM output pins
Input/ output Input/ output Input/ output
Input/ output Input/ output
Type
Symbol
Output
Name Pulse output
Function Pulse output pins
Programmable PO15 pulse generator (PPG) Watchdog timer (WDT) Serial communication interface (SCI)/ smart card interface WDTOVF TxD2, TxD1, TxD0 RxD2, RxD1, RxD0 SCK2, SCK1, SCK0 Hitachi HTxD controller area network HRxD (HCAN) converter AN15 ADTRG
Output Output
Watchdog timer overflow Transmit data
counter overflow signal output watchdog timer mode Data output pins
Input
Receive data
Data input pins
Input/ output Output Input Input Input
Serial clock
Clock input/output pins
HCAN transmit data HCAN receive data Analog conversion external trigger input Analog output Analog power supply
transmission reception Analog input pins input external trigger start conversion converter analog output pins power supply converters. When converters used, connect this system power supply ground reference voltage converters. Connect this system power supply reference voltage input converters. When converters used, connect this system power supply
converter
DA3,
Output Input
converter, AVCC converter
AVSS
Input
Analog ground
Vref
Input
Analog reference power supply
Type ports
Symbol PA0*
Input/ output Input Input Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output
Name Port
Function Eight input/output pins. Input output selected each port data direction register (P1DDR). Eight input pins Eight input pins input/output pins. Input output selected each port data direction register (PADDR). Eight input/output pins. Input output selected each port data direction register (PBDDR). Eight input/output pins. Input output selected each port data direction register (PCDDR). Eight input/output pins. Input output selected each port data direction register (PDDDR). Eight input/output pins. Input output selected each port data direction register (PEDDR). Eight input/output pins. Input output selected each port data direction register (PFDDR).
Port Port Port
Port
Port
Port
Port
Port
Notes: Applies H8S/2626 Series only. H8S/2626 Series.
Section
Overview
H8S/2600 high-speed central processing unit with internal 32-bit architecture that upward-compatible with H8/300 H8/300H CPUs. H8S/2600 sixteen 16-bit general registers, address 16-Mbyte (architecturally 4-Gbyte) linear address space, ideal realtime control. 2.1.1 Features
H8S/2600 following features. Upward-compatible with H8/300 H8/300H CPUs execute H8/300 H8/300H object programs General-register architecture Sixteen 16-bit general registers (also usable sixteen 8-bit registers eight 32-bit registers) Sixty-nine basic instructions 8/16/32-bit arithmetic logic instructions Multiply divide instructions Powerful bit-manipulation instructions Multiply-and-accumulate instruction Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) @(d:32,ERn)] Register indirect with post-increment pre-decrement [@ERn+ @-ERn] Absolute address [@aa:8, @aa:16, @aa:24, @aa:32] Immediate [#xx:8, #xx:16, #xx:32] Program-counter relative [@(d:8,PC) @(d:16,PC)] Memory indirect [@@aa:8] 16-Mbyte address space Program: Mbytes Data: Mbytes Gbytes architecturally)
High-speed operation frequently-used instructions execute states Maximum clock rate 8/16/32-bit register-register add/subtract 8-bit register-register multiply 8-bit register-register divide 16-bit register-register multiply 16-bit register-register divide 1000 operating modes Normal mode* Advanced mode Note: available H8S/2626 Series H8S/2623 Series. Power-down state Transition power-down state SLEEP instruction clock speed selection 2.1.2 Differences between H8S/2600 H8S/2000
differences between H8S/2600 H8S/2000 shown below. Register configuration register supported only H8S/2600 CPU. Basic instructions four instructions MAC, CLRMAC, LDMAC, STMAC supported only H8S/2600 CPU. Number execution states number execution states MULXU MULXS instructions different each CPU.
Execution States Instruction MULXU Mnemonic MULXU.B MULXU.W MULXS MULXS.B MULXS.W H8S/2600 H8S/2000
addition, there differences address space, register functions, power-down modes, etc., depending model. 2.1.3 Differences from H8/300
comparison H8/300 CPU, H8S/2600 following enhancements. More general registers control registers Eight 16-bit expanded registers, 8-bit 32-bit control registers, have been added. Expanded address space Normal mode* supports same 64-kbyte address space H8/300 CPU. Advanced mode supports maximum 16-Mbyte address space. Note: available H8S/2626 Series H8S/2623 Series. Enhanced addressing addressing modes have been enhanced make effective 16-Mbyte address space. Enhanced instructions Addressing modes bit-manipulation instructions have been enhanced. Signed multiply divide instructions have been added. multiply-and-accumulate instruction been added. Two-bit shift instructions have been added. Instructions saving restoring multiple registers have been added. test instruction been added. Higher speed Basic instructions execute twice fast. 2.1.4 Differences from H8/300H
comparison H8/300H CPU, H8S/2600 following enhancements. Additional control register 8-bit 32-bit control registers have been added. Enhanced instructions Addressing modes bit-manipulation instructions have been enhanced. multiply-and-accumulate instruction been added.
Two-bit shift instructions have been added. Instructions saving restoring multiple registers have been added. test instruction been added. Higher speed Basic instructions execute twice fast.
Operating Modes
H8S/2600 operating modes: normal advanced. Normal mode* supports maximum 64-kbyte address space. Advanced mode supports maximum 16-Mbyte total address space (architecturally maximum 16-Mbyte program area maximum Gbytes program data areas combined). mode selected mode pins microcontroller. Note: available H8S/2626 Series H8S/2623 Series.
Maximum kbytes, program data areas combined
Normal mode*
operating modes
Advanced mode
Maximum 16-Mbytes program data areas combined
Note: available H8S/2626 Series H8S/2623 Series.
Figure Operating Modes Normal Mode (Not Available H8S/2626 Series H8S/2623 Series) exception vector table stack have same structure H8/300 CPU. Address Space: maximum address space kbytes accessed. Extended Registers (En): extended registers used 16-bit registers, upper 16-bit segments 32-bit registers. When used 16-bit register contain value, even when corresponding general register (Rn) used address register. general register referenced register indirect addressing mode with pre-decrement (@-Rn) post-increment (@Rn+) carry borrow occurs, however, value corresponding extended register (En) will affected.
Instruction Set: instructions addressing modes used. Only lower bits effective addresses (EA) valid. Exception Vector Table Memory Indirect Branch Addresses: normal mode area starting H'0000 allocated exception vector table. branch address stored bits (figure 2-2). exception vector table differs depending microcontroller. details exception vector table, section Exception Handling.
H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B
Reset exception vector Manual reset exception vector*
(Reserved system use)
Exception vector table
Exception vector Exception vector
Note: available H8S/2626 Series H8S/2623 Series.
Figure Exception Vector Table (Normal Mode) memory indirect addressing mode (@@aa:8) employed instructions uses 8-bit absolute address included instruction code specify memory operand that contains branch address. normal mode operand 16-bit word operand, providing 16bit branch address. Branch addresses stored area from H'0000 H'00FF. Note that this area also used exception vector table.
Stack Structure: When program counter (PC) pushed onto stack subroutine call, condition-code register (CCR), extended control register (EXR) pushed onto stack exception handling, they stored shown figure 2-3. When invalid, pushed onto stack. details, section Exception Handling.
bits)
EXR*1 Reserved*1,*3 CCR*3 bits)
Subroutine Branch
Exception Handling
Notes: When used stored stack. when used. Ignored when returning.
Figure Stack Structure Normal Mode Advanced Mode Address Space: Linear access provided 16-Mbyte maximum address space (architecturally maximum 16-Mbyte program area maximum 4-Gbyte data area, with maximum Gbytes program data areas combined). Extended Registers (En): extended registers used 16-bit registers, upper 16-bit segments 32-bit registers address registers. Instruction Set: instructions addressing modes used.
Exception Vector Table Memory Indirect Branch Addresses: advanced mode area starting H'00000000 allocated exception vector table units bits. each bits, upper bits ignored branch address stored lower bits (figure 2-4). details exception vector table, section Exception Handling.
H'00000000 Reserved Reset exception vector H'00000003 H'00000004 Reserved Manual reset exception vector* H'00000007 H'00000008 Exception vector table
H'0000000B H'0000000C
(Reserved system use)
H'00000010
Reserved Exception vector
Note: available H8S/2626 Series H8S/2623 Series.
Figure Exception Vector Table (Advanced Mode) memory indirect addressing mode (@@aa:8) employed instructions uses 8-bit absolute address included instruction code specify memory operand that contains branch address. advanced mode operand 32-bit longword operand, providing 32-bit branch address. upper bits these bits reserved area that regarded H'00. Branch addresses stored area from H'00000000 H'000000FF. Note that first part this range also exception vector table.
Stack Structure: advanced mode, when program counter (PC) pushed onto stack subroutine call, condition-code register (CCR), extended control register (EXR) pushed onto stack exception handling, they stored shown figure 2-5. When invalid, pushed onto stack. details, section Exception Handling.
Reserved bits)
EXR*1 Reserved*1,*3 bits)
Subroutine Branch
Exception Handling
Notes: When used stored stack. when used. Ignored when returning.
Figure Stack Structure Advanced Mode
Address Space
Figure shows memory H8S/2600 CPU. H8S/2600 provides linear access maximum 64-kbyte address space normal mode, maximum 16-Mbyte (architecturally 4-Gbyte) address space advanced mode.
H'0000 H'00000000
H'FFFF
Program area
H'00FFFFFF Cannot used H8S/2626 Series H8S/2623 Series H'FFFFFFFF Normal Mode* Advanced Mode
Data area
Note: available H8S/2626 Series H8S/2623 Series.
Figure Memory
2.4.1
Register Configuration
Overview
internal registers shown figure 2-7. There types registers: general registers control registers.
General Registers (Rn) Extended Registers (En) (SP) Control Registers (CR) Legend EXR: CCR: Sign extension MACL MACH
Stack pointer Program counter Extended control register Trace Interrupt mask bits Condition-code register Interrupt mask User interrupt mask bit*
MAC:
Half-carry flag User Negative flag Zero flag Overflow flag Carry flag Multiply-accumulate register
Note: Cannot used interrupt mask H8S/2626 Series H8S/2623 Series.
Figure Registers
2.4.2
General Registers
eight 32-bit general registers. These general registers functionally alike used both address registers data registers. When general register used data register, accessed 32-bit, 16-bit, 8-bit register. When general registers used 32-bit registers address registers, they designated letters (ER0 ER7). registers divide into 16-bit general registers designated letters R7). These registers functionally equivalent, providing maximum sixteen 16-bit registers. registers also referred extended registers. registers divide into 8-bit general registers designated letters (R0H R7H) (R0L R7L). These registers functionally equivalent, providing maximum sixteen 8-bit registers. Figure illustrates usage general registers. usage each register selected independently.
Address registers 32-bit registers
16-bit registers registers (extended registers)
8-bit registers
registers (ER0 ER7) registers
registers (R0H R7H)
registers (R0L R7L)
Figure Usage General Registers
General register function stack pointer (SP) addition general-register function, used implicitly exception handling subroutine calls. Figure shows stack.
Free area
(ER7)
Stack area
Figure Stack 2.4.3 Control Registers
control registers 24-bit program counter (PC), 8-bit extended control register (EXR), 8-bit condition-code register (CCR), 64-bit multiply-accumulate register (MAC). Program Counter (PC): This 24-bit counter indicates address next instruction will execute. length instructions bytes (one word), least significant ignored. (When instruction fetched, least significant regarded Extended Control Register (EXR): This 8-bit register contains trace three interrupt mask bits I0). 7-Trace (T): Selects trace mode. When this cleared instructions executed sequence. When this trace exception generated each time instruction executed. Bits 3-Reserved: They always read
Bits 0-Interrupt Mask Bits I0): These bits designate interrupt mask level details, refer section Interrupt Controller. Operations performed bits LDC, STC, ANDC, ORC, XORC instructions. interrupts, including NMI, disabled three states after these instructions executed, except STC. Condition-Code Register (CCR): This 8-bit register contains internal status information, including interrupt mask half-carry (H), negative (N), zero (Z), overflow (V), carry flags. 7-Interrupt Mask (I): Masks interrupts other than when (NMI accepted regardless setting.) hardware start exceptionhandling sequence. details, refer section Interrupt Controller. 6-User Interrupt Mask (UI): written read software using LDC, STC, ANDC, ORC, XORC instructions. This also used interrupt mask bit. details, refer section Interrupt Controller. 5-Half-Carry Flag (H): When ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, NEG.B instruction executed, this flag there carry borrow cleared otherwise. When ADD.W, SUB.W, CMP.W, NEG.W instruction executed, flag there carry borrow cleared otherwise. When ADD.L, SUB.L, CMP.L, NEG.L instruction executed, flag there carry borrow cleared otherwise. 4-User (U): written read software using LDC, STC, ANDC, ORC, XORC instructions. 3-Negative Flag (N): Stores value most significant (sign bit) data. 2-Zero Flag (Z): indicate zero data, cleared indicate non-zero data. 1-Overflow Flag (V): when arithmetic overflow occurs, cleared other times. 0-Carry Flag (C): when carry occurs, cleared otherwise. Used instructions, indicate carry Subtract instructions, indicate borrow Shift rotate instructions, store value shifted carry flag also used accumulator manipulation instructions.
Some instructions leave some flag bits unchanged. action each instruction flag bits, refer Appendix A.1, List Instructions. Operations performed bits LDC, STC, ANDC, ORC, XORC instructions. flags used branching conditions conditional branch (Bcc) instructions. Multiply-Accumulate Register (MAC): This 64-bit register stores results multiplyand-accumulate operations. consists 32-bit registers denoted MACH MACL. lower bits MACH valid; upper bits sign extension. 2.4.4 Initial Register Values
Reset exception handling loads CPU's program counter (PC) from vector table, clears trace sets interrupt mask bits other bits general registers initialized. particular, stack pointer (ER7) initialized. stack pointer should therefore initialized MOV.L instruction executed immediately after reset.
Data Formats
process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), 32-bit (longword) data. Bit-manipulation instructions operate 1-bit data accessing byte operand data. decimal-adjust instructions treat byte data digits 4-bit data. 2.5.1 General Register Data Formats
Figure 2-10 shows data formats general registers.
Data Type Register Number Data Format
1-bit data
Don't care
1-bit data
Don't care
4-bit data
Upper
Lower
Don't care
4-bit data
Don't care
Upper
Lower
Byte data
Don't care Don't care
Byte data
Figure 2-10 General Register Data Formats
Data Type
Register Number
Data Format
Word data
Word data Longword data
Legend ERn: General register General register General register RnH: General register RnL: General register MSB: Most significant LSB: Least significant
Figure 2-10 General Register Data Formats (cont)
2.5.2
Memory Data Formats
Figure 2-11 shows data formats memory. access word data longword data memory, word longword data must begin even address. attempt made access word longword data address, address error occurs least significant address regarded access starts preceding address. This also applies instruction fetches.
Data Type Address 1-bit data Address Data Format
Byte data
Address
Word data
Address Address
Longword data
Address Address Address Address
Figure 2-11 Memory Data Formats When used address register access stack, operand size should word size longword size.
2.6.1
Instruction
Overview
H8S/2600 types instructions. instructions classified function table 2-1. Table
Function Data transfer
Instruction Classification
Instructions POP* PUSH* LDM, SMOVFPE* MOVTPE*
Size
Types
Arithmetic operations
ADD, SUB, CMP, ADDX, SUBX, DAA, INC, ADDS, SUBS MULXU, DIVXU, MULXS, DIVXS EXTU, EXTS TAS*
MAC, LDMAC, STMAC, CLRMAC Logic operations Shift manipulation Branch System control AND, XOR,
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR Bcc* JMP, BSR, JSR,
TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC,
Block data transfer EEPMOV
Notes: B-byte size; W-word size; L-longword size. POP.W PUSH.W identical MOV.W @SP+, MOV.W @-SP. POP.L PUSH.L identical MOV.L @SP+, MOV.L ERn, @-SP. general name conditional branch instructions. available H8S/2626 Series H8S/2623 Series. Only register ER0, ER1, ER4, should used when using instruction.
2.6.2
Addressing Modes
Table
Function
Instruction
@ERn
@(d:16,ERn)
@(d:32,ERn)
@-ERn/@ERn+
@aa:8
@aa:16
@aa:24
@aa:32
@(d:8,PC)
@(d:16,PC)
@@aa:8
Data transfer
POP, PUSH
LDM, S
MOVEPE*1, MOVTPE*1
Arithmetic operations
ADD,
ADDX, SUBX
ADDS, SUBS
INC,
DAA,
Instructions Addressing Modes
MULXU, DIVXU MULXS, DIVXS
EXTU, EXTS
TAS*2
CLRMAC
Combinations Instructions Addressing Modes
Table indicates combinations instructions addressing modes that H8S/2600 use.
LDMAC, STMAC
@ERn
@(d:16,ERn)
@(d:32,ERn)
@-ERn/@ERn+
@aa:8
@aa:16
@aa:24
@aa:32
@(d:8,PC)
@(d:16,PC)
@@aa:8
Logic operations
AND,
Shift
manipulation
Branch
Bcc,
JMP,
System control
TRAPA
SLEEP
ANDC, ORC, XORC
Block data transfer
Legend Byte Word Longword
Notes: available H8S/2626 Series H8S/2623 Series. Only register ER0, ER1, ER4, should used when using instruction.
Addressing Modes
Function
Instruction
2.6.3
Table Instructions Classified Function
Table summarizes instructions each functional category. notation used table defined below.
Operation Notation (EAd) (EAs) #IMM disp :8/:16/:24/:32 General register (destination)* General register (source)* General register* General register (32-bit register) Multiply-accumulate register (32-bit register) Destination operand Source operand Extended control register Condition-code register (negative) flag (zero) flag (overflow) flag (carry) flag Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical Logical Logical exclusive Move (logical complement) 16-, 24-, 32-bit length
Note: General registers include 8-bit registers (R0H R7H, R7L), 16-bit registers E7), 32-bit registers (ER0 ER7).
Table
Type Data transfer
Instructions Classified Function
Instruction Size* B/W/L Function (EAs) (Ead) Moves data between general registers between general register memory, moves immediate data general register. Cannot used H8S/2626 Series H8S/2623 Series. Cannot used H8S/2626 Series H8S/2623 Series. @SP+ Pops register from stack. POP.W identical MOV.W @SP+, POP.L identical MOV.L @SP+, ERn. @-SP Pushes register onto stack. PUSH.W identical MOV.W @-SP. PUSH.L identical MOV.L ERn, @-SP. @SP+ (register list) Pops more general registers from stack. (register list) @-SP Pushes more general registers onto stack.
MOVFPE MOVTPE
PUSH
S
Type Arithmetic operations
Instruction
Size* B/W/L
Function #IMM Performs addition subtraction data general registers, immediate data data general register. (Immediate byte data cannot subtracted from byte data general register. SUBX instruction.) #IMM Performs addition subtraction with carry borrow byte data general registers, immediate data data general register. Increments decrements general register (Byte operands incremented decremented only.) Adds subtracts value from data 32-bit register. decimal adjust Decimal-adjusts addition subtraction result general register referring produce 4-bit data. Performs unsigned multiplication data general registers: either bits bits bits bits bits bits. Performs signed multiplication data general registers: either bits bits bits bits bits bits. Performs unsigned division data general registers: either bits bits 8-bit quotient 8-bit remainder bits bits 16-bit quotient 16bit remainder.
ADDX SUBX
B/W/L
ADDS SUBS
MULXU
MULXS
DIVXU
Type Arithmetic operations
Instruction DIVXS
Size*
Function Performs signed division data general registers: either bits bits 8-bit quotient 8-bit remainder bits bits 16-bit quotient 16bit remainder. #IMM Compares data general register with data another general register with immediate data, sets bits according result. Takes two's complement (arithmetic complement) data general register. (zero extension) Extends lower bits 16-bit register word size, lower bits 32-bit register longword size, padding with zeros left. (sign extension) Extends lower bits 16-bit register word size, lower bits 32-bit register longword size, extending sign bit. @ERd (<bit @ERd)* Tests memory contents, sets most significant (bit (EAs) (EAd) Performs signed multiplication memory contents adds result multiply-accumulate register. following operations performed: bits bits bits bits, saturating bits bits bits bits, non-saturating Clears multiply-accumulate register zero. MAC, Transfers data between general register multiply-accumulate register.
B/W/L
B/W/L
EXTU
EXTS
CLRMAC LDMAC STMAC
Type Logic operations
Instruction
Size* B/W/L
Function #IMM Performs logical operation general register another general register immediate data. #IMM Performs logical operation general register another general register immediate data. #IMM Performs logical exclusive operation general register another general register immediate data. (Rd) (Rd) Takes one's complement general register contents. (shift) Performs arithmetic shift general register contents. 1-bit 2-bit shift possible. (shift) Performs logical shift general register contents. 1-bit 2-bit shift possible. (rotate) Rotates general register contents. 1-bit 2-bit rotation possible. (rotate) Rotates general register contents through carry flag. 1-bit 2-bit rotation possible.
B/W/L
B/W/L
B/W/L
Shift operations
SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR
B/W/L
B/W/L
B/W/L
B/W/L
Type Bitmanipulation instructions
Instruction BSET
Size*
Function (<bit-No.> <EAd>) Sets specified general register memory operand number specified 3-bit immediate data lower three bits general register. (<bit-No.> <EAd>) Clears specified general register memory operand number specified 3-bit immediate data lower three bits general register. (<bit-No.> <EAd>) (<bit-No.> <EAd>) Inverts specified general register memory operand. number specified 3-bit immediate data lower three bits general register. (<bit-No.> <EAd>) Tests specified general register memory operand sets clears flag accordingly. number specified 3-bit immediate data lower three bits general register. (<bit-No.> <EAd>) ANDs carry flag with specified general register memory operand stores result carry flag. (<bit-No.> <EAd>) ANDs carry flag with inverse specified general register memory operand stores result carry flag. number specified 3-bit immediate data. (<bit-No.> <EAd>) carry flag with specified general register memory operand stores result carry flag. (<bit-No.> <EAd>) carry flag with inverse specified general register memory operand stores result carry flag. number specified 3-bit immediate data.
BCLR
BNOT
BTST
BAND
BIAND
BIOR
Type Bitmanipulation instructions
Instruction BXOR
Size*
Function (<bit-No.> <EAd>) Exclusive-ORs carry flag with specified general register memory operand stores result carry flag. (<bit-No.> <EAd>) Exclusive-ORs carry flag with inverse specified general register memory operand stores result carry flag. number specified 3-bit immediate data. (<bit-No.> <EAd>) Transfers specified general register memory operand carry flag. (<bit-No.> <EAd>) Transfers inverse specified general register memory operand carry flag. number specified 3-bit immediate data. (<bit-No.> <EAd>) Transfers carry flag value specified general register memory operand. (<bit-No.> <EAd>) Transfers inverse carry flag value specified general register memory operand. number specified 3-bit immediate data.
BIXOR
BILD
BIST
Type Branch instructions
Instruction
Size*
Function Branches specified address specified condition true. branching conditions listed below. Mnemonic BRA(BT) BRN(BF) BCC(BHS) BCS(BLO) Description Always (true) Never (false) High same Carry clear (high same) Carry (low) equal Equal Overflow clear Overflow Plus Minus Greater equal Less than Greater than Less equal Condition Always Never CZ=0 CZ=1 NV=0 NV=1
Branches unconditionally specified address. Branches subroutine specified address. Branches subroutine specified address. Returns from subroutine
Type
Instruction
Size*
Function Starts trap-instruction exception handling. Returns from exception-handling routine. Causes transition power-down state. (EAs) CCR, (EAs) Moves source operand contents immediate data EXR. Although 8-bit registers, word-size transfers performed between them memory. upper bits valid. (EAd), (EAd) Transfers contents general register memory. Although 8-bit registers, word-size transfers performed between them memory. upper bits valid. #IMM CCR, #IMM Logically ANDs contents with immediate data. #IMM CCR, #IMM Logically contents with immediate data. #IMM CCR, #IMM Logically exclusive-ORs contents with immediate data. Only increments program counter.
System control TRAPA instructions SLEEP
ANDC
XORC
Type Block data transfer instruction
Instruction EEPMOV.B
Size*
Function then Repeat @ER5+ @ER6+ R4L-1 Until else next; then Repeat @ER5+ @ER6+ R4-1 Until else next; Transfers data block according parameters general registers ER5, ER6. size block (bytes) ER5: starting source address ER6: starting destination address Execution next instruction begins soon transfer completed.
EEPMOV.W
Notes: Size refers operand size. Byte Word Longword Only register ER0, ER1, ER4, should used when using instruction.
2.6.4
Basic Instruction Formats
H8S/2626 Series H8S/2623 Series instructions consist 2-byte (1-word) units. instruction consists operation field field), register field field), effective address extension field), condition field (cc). Operation Field: Indicates function instruction, addressing mode, operation carried operand. operation field always includes first four bits instruction. Some instructions have operation fields. Register Field: Specifies general register. Address registers specified bits, data registers bits bits. Some instructions have register fields. Some have register field. Effective Address Extension: Eight, bits specifying immediate data, absolute address, displacement. Condition Field: Specifies branching condition instructions.
Figure 2-12 shows examples instruction formats.
Operation field only NOP, RTS, etc.
Operation field register fields ADD.B etc.
Operation field, register fields, effective address extension (disp) Operation field, effective address extension, condition field (disp) d:16, MOV.B @(d:16, Rn), etc.
Figure 2-12 Instruction Formats (Examples)
2.7.1
Addressing Modes Effective Address Calculation
Addressing Mode
supports eight addressing modes listed table 2-4. Each instruction uses subset these addressing modes. Arithmetic logic instructions register direct immediate modes. Data transfer instructions addressing modes except program-counter relative memory indirect. manipulation instructions register direct, register indirect, absolute addressing mode specify operand, register direct (BSET, BCLR, BNOT, BTST instructions) immediate (3-bit) addressing mode specify number operand. Table
Addressing Modes
Symbol @ERn @(d:16,ERn)/@(d:32,ERn) @ERn+ @-ERn @aa:8/@aa:16/@aa:24/@aa:32 #xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @@aa:8
Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect
Register Direct-Rn: register field instruction specifies 16-, 32-bit general register containing operand. specified 8-bit registers. specified 16-bit registers. specified 32-bit registers. Register Indirect-@ERn: register field instruction code specifies address register (ERn) which contains address operand memory. address program instruction address, lower bits valid upper bits assumed (H'00). Register Indirect with Displacement-@(d:16, ERn) @(d:32, ERn): 16-bit 32-bit displacement contained instruction added address register (ERn) specified register field instruction, gives address memory operand. 16-bit displacement sign-extended when added.
Register Indirect with Post-Increment Pre-Decrement-@ERn+ @-ERn: Register indirect with post-increment-@ERn+ register field instruction code specifies address register (ERn) which contains address memory operand. After operand accessed, added address register contents stored address register. value added byte access, word transfer instruction, longword transfer instruction. word longword transfer instruction, register value should even. Register indirect with pre-decrement-@-ERn value subtracted from address register (ERn) specified register field instruction code, result becomes address memory operand. result also stored address register. value subtracted byte access, word transfer instruction, longword transfer instruction. word longword transfer instruction, register value should even. Absolute Address-@aa:8, @aa:16, @aa:24, @aa:32: instruction code contains absolute address memory operand. absolute address bits long (@aa:8), bits long (@aa:16), bits long (@aa:24), bits long (@aa:32). access data, absolute address should bits (@aa:8), bits (@aa:16), bits (@aa:32) long. 8-bit absolute address, upper bits assumed (H'FFFF). 16-bit absolute address upper bits sign extension. 32-bit absolute address access entire address space. 24-bit absolute address (@aa:24) indicates address program instruction. upper bits assumed (H'00). Table indicates accessible absolute address ranges. Table Absolute Address Access Ranges
Normal Mode* bits (@aa:8) bits (@aa:16) bits (@aa:32) Program instruction address bits (@aa:24) H'FF00 H'FFFF H'0000 H'FFFF Advanced Mode H'FFFF00 H'FFFFFF H'000000 H'007FFF, H'FF8000 H'FFFFFF H'000000 H'FFFFFF
Absolute Address Data address
Note: available H8S/2626 Series H8S/2623 Series.
Immediate-#xx:8, #xx:16, #xx:32: instruction contains 8-bit (#xx:8), 16-bit (#xx:16), 32-bit (#xx:32) immediate data operand. ADDS, SUBS, INC, instructions contain immediate data implicitly. Some manipulation instructions contain 3-bit immediate data instruction code, specifying number. TRAPA instruction contains 2-bit immediate data instruction code, specifying vector address. Program-Counter Relative-@(d:8, @(d:16, PC): This mode used instructions. 8-bit 16-bit displacement contained instruction sign-extended added 24-bit contents generate branch address. Only lower bits this branch address valid; upper bits assumed (H'00). value which displacement added address first byte next instruction, possible branching range -126 +128 bytes (-63 words) -32766 +32768 bytes (-16383 +16384 words) from branch instruction. resulting value should even number. Memory Indirect-@@aa:8: This mode used instructions. instruction code contains 8-bit absolute address specifying memory operand. This memory operand contains branch address. upper bits absolute address assumed address range (H'0000 H'00FF normal mode, H'000000 H'0000FF advanced mode). normal mode* memory operand word operand branch address bits long. advanced mode memory operand longword operand, first byte which assumed (H'00). Note that first part address range also exception vector area. further details, refer section Exception Handling. Note: available H8S/2626 Series H8S/2623 Series.
Specified @aa:8
Branch address
Specified @aa:8
Reserved Branch address
Normal Mode* Note: available H8S/2626 Series H8S/2623 Series.
Advanced Mode
Figure 2-13 Branch Address Specification Memory Indirect Mode address specified word longword memory access, branch address, least significant regarded causing data accessed instruction code fetched address preceding specified address. (For further information, section 2.5.2, Memory Data Formats.) 2.7.2 Effective Address Calculation
Table indicates effective addresses calculated each addressing mode. normal mode* upper bits effective address ignored order generate 16-bit address. Note: Cannot H8S/2626 Series H8S/2623 Series.
Effective Address Calculation Effective Address (EA) Operand general register contents. Don't care General register contents General register contents disp Sign extension disp Don't care
Addressing Mode Instruction Format
Table
Register direct (Rn)
Register indirect (@ERn)
Register indirect with displacement @(d:16, ERn) @(d:32, ERn)
Effective Address Calculation
General register contents
Register indirect with post-increment pre-decrement Register indirect with post-increment @ERn+
Don't care
General register contents Don't care Operand Size Value added Byte Word Longword
Register indirect with pre-decrement @-ERn
Effective Address Calculation
Addressing Mode Instruction Format
Effective Address (EA)
H'FFFF
Don't care
Absolute address
@aa:8
@aa:16
Don't care
Sign extension
@aa:24
Don't care
@aa:32
Don't care
Immediate #xx:8/#xx:16/#xx:32 Operand immediate data.
Effective Address Calculation contents Effective Address (EA) disp Sign extension disp
Don't care
Addressing Mode Instruction Format
Program-counter relative
@(d:8, PC)/@(d:16,
Memory indirect @@aa:8
Normal mode*
H'000000
Don't care
H'00
Memory contents
Advanced mode
H'000000 Memory contents
Don't care
Note: available H8S/2626 Series H8S/2623 Series.
2.8.1
Processing States
Overview
five main processing states: reset state, exception handling state, program execution state, bus-released state, power-down state. Figure 2-14 shows diagram processing states. Figure 2-15 indicates state transitions.
Reset state on-chip supporting modules have been initialized stopped. Exception-handling state transient state which changes normal processing flow response reset, interrupt, trap instruction. Processing states Program execution state executes program instructions sequence. Bus-released state external been released response request signal from master other than CPU. Sleep mode
Power-down state operation stopped conserve power.*
Software standby mode Hardware standby mode
Note: power-down state also includes medium-speed mode, module stop mode, subactive mode, subsleep mode, watch mode. Subclock functions (subactive mode, subsleep mode, watch mode) available H8S/2623 Series, available H8S/2626 Series.
Figure 2-14 Processing States
request request Program execution state
SLEEP instruction with SSBY
Bus-released state
Sleep mode
Inte
SLEEP instruction with SSBY
Exception handling state
External interrupt request
Software standby mode
RES= High STBY= High, RES= Reset state Reset state Hardware standby mode*2
Power-down state*3
Notes: From state except hardware standby mode, transition reset state occurs whenever goes low. transition also made reset state when watchdog timer overflows. From state, transition hardware standby mode occurs when STBY goes low. Apart from these states, there also watch mode, subactive mode, subsleep mode H8S/2626 Series. section 21B, Power-Down Modes.
Figure 2-15 State Transitions 2.8.2 Reset State
When input goes current processing stops enters reset state. interrupts masked reset state. Reset exception handling starts when signal changes from high. reset state also entered watchdog timer overflow. details, refer section Watchdog Timer.
2.8.3
Exception-Handling State
exception-handling state transient state that occurs when alters normal processing flow reset, interrupt, trap instruction. fetches start address (vector) from exception vector table branches that address. Types Exception Handling Their Priority Exception handling performed traces, resets, interrupts, trap instructions. Table indicates types exception handling their priority. Trap instruction exception handling always accepted, program execution state. Exception handling stack structure depend interrupt control mode SYSCR. Table
Priority High
Exception Handling Types Priority
Type Exception Reset Detection Timing Synchronized with clock Start Exception Handling Exception handling starts immediately after low-to-high transition pin, when watchdog timer overflows. When trace trace starts current instruction current exception-handling sequence When interrupt requested, exception handling starts current instruction current exception-handling sequence Exception handling starts when trap (TRAPA) instruction executed*
Trace
instruction execution exception-handling sequence* instruction execution exception-handling sequence* When TRAPA instruction executed
Interrupt
Trap instruction
Notes: Traces enabled only interrupt control mode Trace exception-handling executed instruction. Interrupts detected ANDC, ORC, XORC, instructions, immediately after reset exception handling. Trap instruction exception handling always accepted, program execution state.
Reset Exception Handling After gone reset state been entered, when goes high again, reset exception handling starts. enters reset state when low. When reset exception handling starts fetches start address (vector) from exception vector table starts program execution from that address. interrupts, including NMI, disabled during reset exception handling after ends. Traces Traces enabled only interrupt control mode Trace mode entered when When trace mode established, trace exception handling starts each instruction. trace exception-handling sequence, cleared trace mode cleared. Interrupt masks affected. saved stack retains value when instruction executed return from trace exception-handling routine, trace mode entered again. Trace exceptionhandling executed instruction. Trace mode entered interrupt control mode regardless state bit. Interrupt Exception Handling Trap Instruction Exception Handling When interrupt trap-instruction exception handling begins, references stack pointer (ER7) pushes program counter other control registers onto stack. Next, alters settings interrupt mask bits control registers. Then fetches start address (vector) from exception vector table program execution starts from that start address. Figure 2-16 shows stack after exception handling ends.
Normal mode*2
CCR*1 bits)
Reserved*1 CCR*1 bits)
Interrupt control mode
Interrupt control mode
Advanced mode
bits)
Reserved*1 bits)
Interrupt control mode
Interrupt control mode
Notes: Ignored when returning. available H8S/2626 Series H8S/2623 Series.
Figure 2-16 Stack Structure after Exception Handling (Examples)
2.8.4
Program Execution State
this state executes program instructions sequence. 2.8.5 Bus-Released State
This state which been released response request from master other than CPU. While released, halts operations. masters other than data transfer controller (DTC). further details, refer section Controller. 2.8.6 Power-Down State
power-down state includes both modes which stops operating modes which does stop. There five modes which stops operating: sleep mode, software standby mode, hardware standby mode, subsleep mode*, watch mode*. There also three other power-down modes: medium-speed mode, module stop mode, subactive mode*. medium-speed mode other masters operate medium-speed clock. Module stop mode permits halting operation individual modules, other than CPU. Subactive mode*, subsleep mode*, watch mode* power-down states using subclock input. details, refer section Power-Down Modes. Note: Supported only H8S/2626 Series; available H8S/2623 Series.
2.9.1
Basic Timing
Overview
H8S/2600 driven system clock, denoted symbol period from rising edge next referred "state." memory cycle cycle consists one, two, three states. Different methods used access on-chip memory, on-chip supporting modules, external address space. 2.9.2 On-Chip Memory (ROM, RAM)
On-chip memory accessed state. data bits wide, permitting both byte word transfer instruction. Figure 2-17 shows on-chip memory access cycle. Figure 2-18 shows states.
cycle Internal address Internal read signal Internal data Internal write signal Write access Internal data Write data Read data Address
Read access
Figure 2-17 On-Chip Memory Access Cycle
cycle
Address HWR, Data
Retained High High High High-impedance state
Figure 2-18 States during On-Chip Memory Access
2.9.3
On-Chip Supporting Module Access Timing
on-chip supporting modules accessed states. data either bits bits wide, depending particular internal register being accessed. Figure 2-19 shows access timing on-chip supporting modules. Figure 2-20 shows states.
cycle
Internal address
Address
Internal read signal Read access Internal data Internal write signal Write access Internal data Write data
Read data
Figure 2-19 On-Chip Supporting Module Access Cycle
cycle
Address
Retained
HWR,
High
High
High
Data
High-impedance state
Figure 2-20 States during On-Chip Supporting Module Access Cycle
2.9.4
On-Chip HCAN Module Access Timing
On-chip HCAN module access performed four states. data width bits. Wait states inserted means wait request from HCAN. On-chip HCAN module access timing shown figures 2-21 2-22, states figure 2-23.
cycle Internal address HCAN read signal Read Internal data HCAN write signal Write Internal data Write data Read data Address
Figure 2-21 On-Chip HCAN Module Access Cycle Wait State)
cycle Internal address HCAN read signal Read Internal data HCAN write signal Write Internal data Write data Read data Address
Figure 2-22 On-Chip HCAN Module Access Cycle (Wait States Inserted)
cycle Address HWR, Data Retained High High High High-impedance state
Figure 2-23 States On-Chip HCAN Module Access 2.9.5 External Address Space Access Timing
external address space accessed with 8-bit 16-bit data width two-state three-state cycle. three-state access, wait states inserted. further details, refer section Controller.
2.10
2.10.1
Usage Note
Instruction
Only register ER0, ER1, ER4, should used when using instruction. instruction generated Hitachi H8/300 series C/C++ compilers. instruction used user-defined intrinsic function, ensure that only register ER0, ER1, ER4, used.
Section Operating Modes
3.1.1
Overview
Operating Mode Selection
H8S/2626 Series H8S/2623 Series have four operating modes (modes These modes enable selection operating mode, enabling/disabling on-chip ROM, initial width setting, setting mode pins (MD2 MD0). Table lists operating modes. Table Operating Mode Selection
External Data On-Chip Initial Width Max. Width
Operating Operating Mode Mode Description
Advanced On-chip disabled, Disabled bits expanded mode bits On-chip enabled, Enabled bits expanded mode Single-chip mode
bits bits bits
Note: available H8S/2626 Series H8S/2623 Series.
CPU's architecture allows Gbytes address space, H8S/2626 Series H8S/2623 Series actually access maximum Mbytes. Modes externally expanded modes that allow access external memory peripheral devices. external expansion modes allow switching between 8-bit 16-bit modes. After program execution starts, 8-bit 16-bit address space each area, depending controller setting. 16-bit access selected area, 16-bit mode set; 8-bit access selected areas, 8-bit mode set. Note that functions each depend operating mode.
H8S/2626 Series H8S/2623 Series used only modes This means that mode pins must select these modes. change inputs mode pins during operation. 3.1.2 Register Configuration
H8S/2626 Series H8S/2623 Series have mode control register (MDCR) that indicates inputs mode pins (MD2 MD0), system control register (SYSCR) that controls operation H8S/2626 Series H8S/2623 Series chip. Table summarizes these registers. Table
Name Mode control register System control register function control register
Registers
Abbreviation MDCR SYSCR PFCR Initial Value Undetermined H'01 H'0D/H'00 Address* H'FDE7 H'FDE5 H'FDEB
Note: Lower bits address.
3.2.1
Register Descriptions
Mode Control Register (MDCR)
MDS2 MDS1 MDS0
Initial value
Note: Determined pins MD0.
MDCR 8-bit register that indicates current operating mode H8S/2626 Series H8S/2623 Series chip. 7-Reserved: Only should written this bit. Bits 3-Reserved: These bits always read cannot modified. Bits 0-Mode Select (MDS2 MDS0): These bits indicate input levels pins (the current operating mode). Bits MDS2 MDS0 correspond MD0. MDS2 MDS0 read-only bits-they cannot written mode (MD2 MD0) input levels latched into these bits when MDCR read. These latches canceled reset.
3.2.2
System Control Register (SYSCR)
MACS INTM1 INTM0 NMIEG RAME
Initial value
SYSCR 8-bit readable/writable register that selects saturating non-saturating calculation instruction, selects interrupt control mode detected edge NMI, enables disables on-chip RAM. SYSCR initialized H'01 reset hardware standby mode. SYSCR initialized software standby mode. 7-MAC Saturation (MACS): Selects either saturating non-saturating calculation instruction.
MACS Description Non-saturating calculation instruction Saturating calculation instruction (Initial value)
6-Reserved: This always read cannot modified. Bits 4-Interrupt Control Mode (INTM1, INTM0): These bits select control mode interrupt controller. details interrupt control modes, section 5.4.1, Interrupt Control Modes Interrupt Operation.
INTM1 INTM0 Interrupt Control Mode
Description Control interrupts Setting prohibited Control interrupts bits Setting prohibited (Initial value)
3-NMI Edge Select (NMIEG): Selects valid edge interrupt input.
NMIEG Description interrupt requested falling edge input interrupt requested rising edge input (Initial value)
2-Reserved: Only should written this bit. 1-Reserved: This always read cannot modified. 0-RAM Enable (RAME): Enables disables on-chip RAM. RAME initialized when reset status released. initialized software standby mode.
RAME Description On-chip disabled On-chip enabled (Initial value)
Note: When used, RAME must
3.2.3
Function Control Register (PFCR)
BUZZE
Initial value
PFCR 8-bit readable/writable register that performs address output control external expanded mode. PFCR initialized H'0D/H'00 reset hardware standby mode. retains previous state software standby mode. Bits 4-Reserved: Only should written these bits. 5-BUZZE Output Enable (BUZZE): This only H8S/2626. Only should writtn this bit. Bits 0-Address Output Enable (AE3-AE0): These bits select enabling disabling address outputs ROMless expanded mode modes with ROM. When enabled address output, address output regardless corresponding setting.
When disabled address output, becomes output port when corresponding
Description A8-A23 address output disabled (Initial value*)
address output enabled; A9-A23 address output disabled address output enabled; A10-A23 address output disabled A8-A10 address output enabled; A11-A23 address output disabled A8-A11 address output enabled; A12-A23 address output disabled A8-A12 address output enabled; A13-A23 address output disabled A8-A13 address output enabled; A14-A23 address output disabled A8-A14 address output enabled; A15-A23 address output disabled A8-A15 address output enabled; A16-A23 address output disabled A8-A16 address output enabled; A17-A23 address output disabled A8-A17 address output enabled; A18-A23 address output disabled A8-A18 address output enabled; A19-A23 address output disabled A8-A19 address output enabled; A20-A23 address output disabled A8-A20 address output enabled; A21-A23 address output disabled (Initial value*) A8-A21 address output enabled; A22, address output disabled A8-A23 address output enabled
Note: expanded mode with ROM, bits initialized B'0000. ROMless expanded mode, bits initialized B'1101. Address pins made address outputs setting corresponding bits
3.3.1
Operating Mode Descriptions
Mode
access 16-Mbyte address space advanced mode. on-chip disabled. Ports function address bus, ports function data bus, part port carries control signals. initial mode after reset bits, with 16-bit access areas. However, note that 8bit access designated controller areas, mode switches bits. 3.3.2 Mode
access 16-Mbyte address space advanced mode. on-chip disabled. Ports function address bus, ports function data bus, part port carries control signals. initial mode after reset bits, with 8-bit access areas. However, note that 16bit access designated controller area, mode switches bits port becomes data bus. 3.3.3 Mode
access 16-Mbyte address space advanced mode. on-chip enabled. Ports function input port pins immediately after reset. Address output performed setting corresponding (data direction register) bits Port function data bus, part port carries data signals. initial mode after reset bits, with 8-bit access areas. However, note that 16bit access designated controller area, mode switches bits port becomes data bus. 3.3.4 Mode
access 16-Mbyte address space advanced mode. on-chip enabled, external addresses cannot accessed. ports available input-output ports.
Functions Each Operating Mode
functions ports vary depending operating mode. Table shows their functions each operating mode. Table
Port Port Port Port Port Port Port Port Legend port Address output Data Control signals, clock After reset
Functions Each Mode
Mode P*/A P/D* P/C* P/C* P*/C Mode P*/A P*/D P/C* P*/C P*/C Mode P*/A P*/A P*/A P*/A P*/A P*/D P/C* P*/C P*/C Mode P*/C
Address Each Operating Mode
address H8S/2623 H8S/2626 shown figure 3-1, address H8S/2622, H8S/2625 figure 3-2, address H8S/2621 H8S/2624 figure 3-3. address space Mbytes modes (advanced modes). address space divided into eight areas modes details, section Controller.
Modes (advanced expanded modes with on-chip disabled) H'000000
Mode (advanced expanded mode with on-chip enabled) H'000000
Mode (advanced single-chip mode)
H'000000
External address space
On-chip
On-chip
H'03FFFF H'040000 H'FFB000 H'FFC000 H'FFEFC0 H'FFF800 Internal registers H'FFFF40 External area H'FFFF40 H'FFB000 H'FFC000 H'FFEFC0 H'FFF800 Internal registers H'FFFF3F External area H'FFFF60 Internal registers H'FFFFC0 On-chip H'FFFFFF H'FFFF60 Internal registers H'FFFFC0 On-chip RAM* H'FFFFFF H'FFFF60 Internal registers H'FFFFC0 On-chip RAM* H'FFFFFF
External address space
Reserved area On-chip RAM* External area
Reserved area On-chip RAM* External area H'FFF800 Internal registers H'FFC000 H'FFEFBF On-chip
Note: External addresses accessed clearing RAME SYSCR
Figure Memory Each Operating Mode H8S/2623 H8S/2626
Modes (advanced expanded modes with on-chip disabled) H'000000
Mode (advanced expanded mode with on-chip enabled) H'000000
Mode (advanced single-chip mode)
H'000000
On-chip
On-chip
External address space
H'01FFFF H'020000
Reserved area
H'040000 H'FFB000 H'FFD000 H'FFEFC0 H'FFF800 Internal registers H'FFFF40 External area H'FFFF40 H'FFB000 H'FFD000 H'FFEFC0 H'FFF800
External address space
Reserved area On-chip RAM* External area
Reserved area On-chip RAM* External area H'FFF800 Internal registers H'FFFF3F External area H'FFFF60 Internal registers H'FFFFC0 On-chip H'FFFFFF Internal registers H'FFD000 H'FFEFBF On-chip
H'FFFF60 Internal registers H'FFFFC0 On-chip RAM* H'FFFFFF
H'FFFF60 Internal registers H'FFFFC0 On-chip RAM* H'FFFFFF
Note: External addresses accessed clearing RAME SYSCR
Figure Memory Each Operating Mode H8S/2622 H8S/2625
Modes (advanced expanded modes with on-chip disabled) H'000000
Mode (advanced expanded mode with on-chip enabled) H'000000
Mode (advanced single-chip mode)
H'000000
On-chip
On-chip
H'00FFFF H'010000
External address space
Reserved area
H'040000 H'FFB000 Reserved area H'FFE000 H'FFEFC0 H'FFF800 Internal registers H'FFFF40 External area H'FFFF40 On-chip RAM* External area H'FFE000 H'FFEFC0 H'FFF800 H'FFB000
External address space
Reserved area On-chip RAM* External area H'FFF800 Internal registers H'FFFF3F External area H'FFFF60 Internal registers H'FFFFC0 On-chip H'FFFFFF Internal registers H'FFE000 H'FFEFBF On-chip
H'FFFF60 Internal registers H'FFFFC0 On-chip RAM* H'FFFFFF
H'FFFF60 Internal registers H'FFFFC0 On-chip RAM* H'FFFFFF
Note: External addresses accessed clearing RAME SYSCR
Figure Memory Each Operating Mode H8S/2621 H8S/2624
Section Exception Handling
4.1.1
Overview
Exception Handling Types Priority
table indicates, exception handling caused reset, trap instruction, interrupt. Exception handling prioritized shown table 4-1. more exceptions occur simultaneously, they accepted processed order priority. Trap instruction exceptions accepted times, program execution state. Exception handling sources, stack structure, operation vary depending interrupt control mode INTM0 INTM1 bits SYSCR. Table
Priority High
Exception Types Priority
Exception Type Reset Start Exception Handling Starts immediately after low-to-high transition pin, when watchdog timer overflows. enters reset state when low. Starts when execution current instruction exception handling ends, trace Starts when direction transition occurs result SLEEP instruction execution. Starts when execution current instruction exception handling ends, interrupt request been issued*
Trace* Direct transition Interrupt
Trap instruction (TRAPA)*3 Started execution trap instruction (TRAPA)
Notes: Traces enabled only interrupt control mode Trace exception handling executed after execution instruction. Interrupt detection performed completion ANDC, ORC, XORC, instruction execution, completion reset exception handling. Trap instruction exception handling requests accepted times program execution state.
4.1.2
Exception Handling Operation
Exceptions originate from various sources. Trap instructions interrupts handled follows: program counter (PC), condition code register (CCR), extended register (EXR) pushed onto stack. interrupt mask bits updated. cleared vector address corresponding exception source generated, program execution starts from that address. reset exception, steps above carried out. 4.1.3 Exception Vector Table
exception sources classified shown figure 4-1. Different vector addresses assigned different exception sources. Table lists exception sources their vector addresses.
Reset
Reset Manual reset*1
Trace Exception sources Interrupts External interrupts: NMI, IRQ5 IRQ0 Internal interrupts: interrupt sources*2 on-chip supporting modules
Trap instruction Notes: available H8S/2626 Series H8S/2623 Series. interrupt sources H8S/2626 Series.
Figure Exception Sources
Table
Exception Vector Table
Vector Address*
Exception Source Reset Manual reset* Reserved
Vector Number
Advanced Mode H'0000 H'0003 H'0004 H'0007 H'0008 H'000B H'000C H'000F H'0010 H'0013 H'0014 H'0017 H'0018 H'001B H'001C H'001F H'0020 H'0023 H'0024 H'0027 H'0028 H'002B H'002C H'002F H'0030 H'0033 H'0034 H'0037 H'0038 H'003B H'003C H'003F H'0040 H'0043 H'0044 H'0047 H'0048 H'004B H'004C H'004F H'0050 H'0053 H'0054 H'0057 H'0058 H'005B H'005C H'005F H'0060 H'0063 H'01FC H'01FF
Trace Direct transitions* (H8S/2626 only) External interrupt
Trap instruction sources)
Reserved
External interrupt
IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5
Reserved
Internal interrupt*
Notes: Lower bits address. details internal interrupt vectors, section 5.3.3, Interrupt Exception Handling Vector Table. available H8S/2626 Series H8S/2623 Series. section 21B.11, Direct Transitions, details.
4.2.1
Reset
Overview
reset highest exception priority. When goes low, processing halts H8S/2626 Series H8S/2623 Series enters reset state. reset initializes internal state registers on-chip supporting modules. Immediately after reset, interrupt control mode set. Reset exception handling begins when changes from high. chip also reset overflow watchdog timer. details section Watchdog Timer. 4.2.2 Reset Sequence
chip enters reset state when goes low. ensure that chip reset, hold least power-up. reset chip during operation, hold least states. When goes high after being held necessary time, chip starts reset exception handling follows: internal state registers on-chip supporting modules initialized, cleared EXR, CCR. reset exception handling vector address read transferred program execution starts from address indicated Figures show examples reset sequence.
Vector fetch
Internal Prefetch first processing program instruction
Address HWR,
High
Reset exception handling vector address (when reset, H'000000, H'000002) Start address (contents reset exception handling vector address) Start address ((5) (4)) First program instruction Note: Three program wait states inserted.
Figure Reset Sequence (Modes
Vector fetch
Prefetch Internal first program processing instruction
Internal address
Internal read signal Internal write signal Internal data High
Reset exception handling vector address (when reset, H'000000, H'000002) Start address (contents reset exception handling vector address) Start address ((5) (4)) First program instruction
Figure Reset Sequence (Modes 4.2.3 Interrupts after Reset
interrupt accepted after reset before stack pointer (SP) initialized, will saved correctly, leading program crash. prevent this, interrupt requests, including NMI, disabled immediately after reset. Since first instruction program always executed immediately after reset state ends, make sure that this instruction initializes stack pointer (example: MOV.L #xx: SP). 4.2.4 State On-Chip Supporting Modules after Reset Release
After reset release, MSTPCRA MSTPCRC initialized H'3F, H'FF, H'FF, respectively, modules except enter module stop mode. Consequently, on-chip supporting module registers cannot read written Register reading writing enabled when module stop mode exited.
Traces
Traces enabled interrupt control mode Trace mode activated interrupt control mode irrespective state bit. details interrupt control modes, section Interrupt Controller. trace mode activated. trace mode, trace exception occurs completion each instruction. Trace mode canceled clearing affected interrupt masking. Table shows state after execution trace exception handling. Interrupts accepted even within trace exception handling routine. saved stack retains value when control returned from trace exception handling routine instruction, trace mode resumes. Trace exception handling carried after execution instruction. Table Status after Trace Exception Handling
Interrupt Control Mode
Trace exception handling cannot used.
Legend Cleared Retains value prior execution.
Interrupts
Interrupt exception handling requested seven external sources (NMI, IRQ5 IRQ0) internal sources (H8S/2626 Series: H8S/2623 Series: on-chip supporting modules. Figure classifies interrupt sources number interrupts each type. on-chip supporting modules that request interrupts include watchdog timer (WDT), 16-bit timer-pulse unit (TPU), serial communication interface (SCI), data transfer controller (DTC), break controller (PBC), Hitachi controller area network (HCAN), converter. Each interrupt source separate vector address. highest-priority interrupt. Interrupts controlled interrupt controller. interrupt controller interrupt control modes assign interrupts other than eight priority/mask levels enable multiplexed interrupt control. details interrupts, section Interrupt Controller.
External interrupts Interrupts
IRQ5 IRQ0
Internal interrupts
WDT* H8S/2626 Series (2), H8S/2623 Series (26) (12) HCAN converter
Notes:
Numbers parentheses numbers interrupt sources. When watchdog timer used interval timer, generates interrupt request each counter overflow.
Figure Interrupt Sources Number Interrupts
Trap Instruction
Trap instruction exception handling starts when TRAPA instruction executed. Trap instruction exception handling execute
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