kSPS, 10-Bit 4-/8-Channel Sampling ADCs AD7811/AD7812 control reg
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FEATURES 10-Bit with Conversion Time AD7811 Four Single-Ended Inputs that Configured Three Pseudo Differential Inputs With Respect Common, Independent Pseudo Differential Channels AD7812 Eight Single-Ended Inputs that Configured Seven Pseudo Differential Inputs with Respect Common, Four Independent Pseudo Differential Channels Onboard Track Hold Onboard Reference 2.5% Operating Supply Range: Specifications V-3.6 DSP/Microcontroller Compatible Serial Interface High Speed Sampling Automatic Power-Down Modes Package Address AD7811 AD7812 Allow Sharing Serial Multipackage Applications Input Signal Range: VREF Reference Input Range: GENERAL DESCRIPTION
kSPS, 10-Bit 4-/8-Channel Sampling ADCs AD7811/AD7812
control registers AD7811 AD7812 allow input channels configured single-ended pseudo differential. control register also features software convert start software power-down. these devices share same serial individually addressed multipackage application hardwiring device address pin. AD7811 available small, 16-lead 0.3" wide, plastic dual-in-line package (mini-DIP), 16-lead 0.15" wide, small outline (SOIC) 16-lead, Thin Shrink Small Outline Package (TSSOP). AD7812 available small, 20-lead 0.3" wide, plastic dual-in-line package (mini-DIP), 20-lead, small outline (SOIC) 20-lead, Thin Shrink Small Outline Package (TSSOP).
PRODUCT HIGHLIGHTS
Power, Single Supply Operation Both AD7811 AD7812 operate from single +2.7 +5.5 supply typically consume only power. power dissipation significantly reduced lower throughput rates using automatic power-down mode e.g., kSPS, V-see Power Throughput. 4-/8-Channel, 10-Bit AD7811 AD7812 have four eight single-ended input channels respectively. These inputs configured pseudo differential inputs using Control Register. On-chip 2.5%) reference circuit that powered down when using external reference. Hardware Software Control AD7811 AD7812 provide both hardware software control Convert Start Power-Down.
AD7811 AD7812 high speed, power, 10-bit converters that operate from single supply. devices contain successive approximation converter, on-chip track/hold amplifier, on-chip reference high speed serial interface that compatible with serial interfaces most DSPs (Digital Signal Processors) microcontrollers. user also option using external reference connecting VREF setting EXTREF control register. VREF tied VDD. slower throughput rates power-down mode used automatically power down between conversions.
FUNCTIONAL BLOCK DIAGRAMS
CREF 1.23V CLOCK CHARGE REDISTRIBUTION VIN1 VIN2 VIN3 VIN4 SERIAL PORT REFIN AGND DGND
CREF 1.23V CLOCK CHARGE REDISTRIBUTION CONTROL LOGIC SERIAL PORT REFIN AGND DGND
AD7811
DOUT SCLK
VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 VIN8
AD7812
DOUT SCLK
CONTROL LOGIC COMP
COMP
CONVST
CONVST
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices. Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Site: http://www.analog.com Fax: 617/326-8703 Analog Devices, Inc., 1997
AD7811/AD7812-SPECIFICATIONS [EXT]. specifications unless otherwise noted.)
Parameter DYNAMIC PERFORMANCE Signal (Noise Distortion) Ratio1 Total Harmonic Distortion (THD)1 Peak Harmonic Spurious Noise1 Intermodulation Distortion1, Second Order Terms Third Order Terms Channel-to-Channel Isolation1, ACCURACY Resolution Minimum Resolution Which Missing Codes Guaranteed Relative Accuracy1 Differential Nonlinearity1 Gain Error1 Gain Error Match1 Offset Error1 Offset Error Match1 ANALOG INPUT Input Voltage Range Input Leakage Current2 Input Capacitance2 REFERENCE INPUTS2 VREF Input Voltage Range Input Leakage Current Input Capacitance ON-CHIP REFERENCE Reference Error Temperature Coefficient LOGIC INPUTS2 VINH, Input High Voltage VINL, Input Voltage VINH, Input High Voltage VINL, Input Voltage Input Current, Input Capacitance, LOGIC OUTPUTS Output High Voltage, Output Voltage, High Impedance Leakage Current High Impedance Capacitance CONVERSION RATE Conversion time Track/Hold Acquisition Time1 Version 0.75 0.75 VREF Units Bits Bits Nominal ppm/°C Typically Test Conditions/Comments Channel, fSAMPLE VREF Internal External kHz,
(VDD +2.7 +3.6
10%, VREF +VDD
Channel
ISOURCE ISINK
REV.
AD7811/AD7812
Parameter POWER SUPPLY Normal Operation Power-Down Full Power-Down Partial Power-Down (Internal Ref) Power Dissipation Normal Operation Auto Full Power-Down Throughput kSPS Throughput kSPS Throughput kSPS Partial Power-Down (Internal Ref) Full Power-Down Version 10.5 31.5 3.15 1.05 Units Power Throughput Section Test Conditions/Comments Specified Performance Digital Inputs
Power-Up Times Section
NOTES Terminology. Sample tested during initial release after redesign process change that affect this parameter. Specifications subject change without notice.
TIMING CHARACTERISTICS1,
Parameter tPOWER-UP t103, Version Units
VREF +VDD [EXT] unless otherwise noted)
Conditions/Comments Power-Up Time AD7811/AD7812 After Rising Edge CONVST Conversion Time CONVST Pulse Width SCLK High Pulse Width SCLK Pulse Width Rising Edge SCLK Rising Edge Setup Time Falling Edge SCLK Falling Edge Setup Time SCLK Rising Edge Data Valid Data Valid SCLK Falling Edge Setup Time Data Valid after SCLK Falling Edge Hold Time SCLK Rising Edge DOUT High Impedance DOUT High Impedance CONVST Falling Edge
(max) (max) (min) (min) (min) (min) (min) (max) (min) (min) (max) (min)
NOTES Sample tested ensure compliance. Figures These numbers measured with load circuit Figure They defined time required cross 10%. Derived from measured time taken data outputs change when loaded with circuit Figure measured number then extrapolated back remove effects charging discharging capacitor. This means that time, quoted Timing Characteristics true relinquish time part such independent external loading capacitances.
OUTPUT
+2.1V 50pF
Figure Load Circuit Digital Output Timing Specifications
REV.
AD7811/AD7812
ABSOLUTE MAXIMUM RATINGS*
DGND -0.3 Digital Input Voltage DGND (CONVST, SCLK, RFS, TFS, DIN, -0.3 Digital Output Voltage DGND (DOUT) -0.3 REFIN AGND -0.3 Analog Inputs VIN1-VIN4 (AD7811) -0.3 VIN1-VIN8 (AD7812) -0.3 Storage Temperature Range -65°C +150°C Junction Temperature +150°C Plastic Package, Power Dissipation Thermal Impedance +105°C/W Lead Temperature, (Soldering secs) +260°C
SOIC Package, Power Dissipation Thermal Impedance 75°C/W Lead Temperature, Soldering Vapor Phase sec) +215°C Infrared sec) +220°C TSSOP Package, Power Dissipation Thermal Impedance 115°C/W Lead Temperature, Soldering Vapor Phase sec) +215°C Infrared sec) +220°C
*Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those listed operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ORDERING GUIDE
Model AD7811YN AD7811YR AD7811YRU AD7812YN AD7812YR AD7812YRU
Linearity Error
Package Description 16-Lead Plastic 16-Lead Small Outline (SOIC) 16-Lead Thin Shrink Small Outline Package (TSSOP) 20-Lead Plastic 20-Lead Small Outline (SOIC) 20-Lead Thin Shrink Small Outline Package (TSSOP)
Package Options N-16 R-16A RU-16 N-20 R-20A RU-20
REV.
AD7811/AD7812
CONFIGURATIONS DIP/SOIC/TSSOP
VREF CREF VIN1 AGND
CONVST SCLK
VREF CREF VIN1 AGND VIN2 VIN3
CONVST SCLK
AD7811
VIEW VIN2 (Not Scale) DOUT VIN3 VIN4 DGND
AD7812
DOUT
VIEW (Not Scale) VIN4 VIN5 VIN6 VIN7 DGND VIN8
FUNCTION DESCRIPTIONS
Pin(s) AD7811
Pin(s) AD7812
Name VREF
Description external reference input applied here. When using external precision reference EXTREF control register must logic one. external reference input range VDD. Reference Capacitor. capacitor connected here improve noise performance on-chip reference. Analog Inputs. analog input range VREF. Analog Ground. Ground reference track/hold, comparator, on-chip reference DAC. Package Address Pin. This Logic Input hardwired high low. When used conjunction with package address control register this input allows devices share same serial bus. example twelve channel solution achieved using AD7811 AD7812 same serial bus. Digital Ground. Ground reference digital circuitry. Transmit Frame Sync. falling edge this Logic Input tells part that control byte should shifted next falling edges SCLK. Receive Frame Sync. rising edge this Logic Input used enable counter serial interface. used provide compatibility with DSPs which continuous serial clock framing signal. also used (Chip Select) multipackage applications. serial interface will ignore SCLK until receives rising edge this input. counter reset serial read operation. Serial Data Output. Serial data shifted this rising edge serial clock. output enters High impedance condition rising edge 11th SCLK pulse. Serial Data Input. control byte read this input. order complete serial write operation SCLK pulses need provided. Only first bits shifted in-see Serial Interface section. Serial Clock Input. external serial clock applied this input obtain serial data from AD7811/AD7812 also latch data into AD7811/AD7812. Data clocked rising edge SCLK latched falling edge SCLK. Convert Start. This edge triggered logic input. Track/Hold goes into Hold Mode falling edge this signal conversion initiated. state this conversion also determines whether part powered down not. operating modes section this data sheet. Positive Supply Voltage +2.7 +5.5
5-11
CREF VIN1-VIN4(8) AGND
DGND
DOUT
SCLK
CONVST
REV.
AD7811/AD7812
TERMINOLOGY Signal (Noise Distortion) Ratio
This measured ratio signal (noise distortion) output converter. signal amplitude fundamental. Noise nonfundamental signals half sampling frequency (fS/2), excluding ratio dependent upon number quantization levels digitization process; more levels, smaller quantization noise. theoretical signal (noise distortion) ratio ideal N-bit converter with sine wave input given Signal (Noise Distortion) (6.02N 1.76) Thus 10-bit converter, this
Total Harmonic Distortion
usually distanced frequency from original sine waves while third order terms usually frequency close input frequencies. result, second third order terms specified separately. calculation intermodulation distortion specification where ratio individual distortion products amplitude fundamental expressed dBs.
Channel-to-Channel Isolation
Channel-to-channel isolation measure level crosstalk between channels. measured applying fullscale sine wave signal nonselected input channels determining much that signal attenuated selected channel. figure given worst case across four eight channels AD7811 AD7812 respectively.
Relative Accuracy
Total harmonic distortion (THD) ratio harmonics fundamental. AD7811 AD7812 defined
(dB)
Relative accuracy, endpoint nonlinearity, maximum deviation from straight line passing through endpoints transfer function.
Differential Nonlinearity
This difference between measured ideal change between adjacent codes ADC.
Offset Error
where amplitude fundamental amplitudes second through sixth harmonics.
Peak Harmonic Spurious Noise
This deviation first code transition (0000 000) (0000 001) from ideal, i.e., AGND LSB.
Offset Error Match
Peak harmonic spurious noise defined ratio value next largest component output spectrum fS/2 excluding value fundamental. Normally, value this specification determined largest harmonic spectrum, parts where harmonics buried noise floor, will noise peak.
Intermodulation Distortion
This difference Offset Error between channels.
Gain Error
This deviation last code transition (1111 110) (1111 111) from ideal, i.e., VREF LSB, after offset error been adjusted out.
Gain Error Match
This difference Gain Error between channels.
Track/Hold Acquisition Time
With inputs consisting sine waves frequencies, active device with nonlinearities will create distortion products difference frequencies where etc. Intermodulation terms those which neither equal zero. example, second order terms include fb), while third order terms include (2fa fb), (2fa fb), 2fb) 2fb). AD7811 AD7812 tested using CCIF standard where input frequencies near input bandwidth used. this case, second third order terms different significance. second order terms
Track/hold acquisition time time required output track/hold amplifier reach final value, within LSB, after conversion (the point which track/hold returns track mode). also applies situations where change selected input channel takes place where there step input change input voltage applied selected input AD7811 AD7812. means that user must wait duration track/hold acquisition time after conversion after channel change/ step input change before starting another conversion, ensure that part operates specification.
REV.
AD7811/AD7812
Control Register (AD7811) Control Register 10-bit-wide, write only register. Control Register written when AD7811 receives falling edge pin. AD7811 will maintain same configuration until control byte written part. control register written same time data being read. This latter feature enhances throughput rates when software control being used when analog input channels being changed frequently. power-up default register contents zeros; therefore, when supplies connected, AD7811 powered down default.
Control Register AD7811
VIN4/AGND DIFF/SGL
CONVST EXTREF
*This don't care bit.
This package address bit. used conjunction with package address allow AD7811s share same serial bus. AD7811 also share same serial with AD7812. When control word written control register AD7811 control word ignored package address control byte does match package address hardwired. Only serial port device that received last valid control byte, i.e., address matched address pin, will attempt drive serial next serial read. When part powers this These bits allow AD7811 fully powered down powered combinations override automatic power-down decision conversion. These bits also decide power-down mode when AD7811 enters power-down conversion. There power-down modes-Full Power-Down Partial Power-Down. Power-Down Options section this data sheet. Description Full Power-Down AD7811 Partial Power-Down Conversion Full Power-Down Conversion Power-Up AD7811
PD1,
VIN4/AGND
DIF/SGL control register must this option otherwise this ignored. Setting VIN4/AGND configures analog inputs AD7811 four single-ended analog inputs referenced analog ground (AGND). setting this input channels VIN1 VIN3 configured three pseudodifferential channels with respect VIN4-see Table This used configure analog inputs single ended pseudo differential pairs. setting this analog inputs configured single ended with respect AGND, pseudo differential with respect VIN4 explained above. Setting this configures analog input channels pseudo differential pairs VIN1/VIN2 VIN3/VIN4-see Table These bits used conjunction with VIN4/AGND DIF/SGL select analog input channel. table shows various channel selections made-see Table Setting this logic initiates conversion. conversion initiated after write control register taken place. This allows signal acquired even channel changed conversion initiated same serial write. reset after conversion. This must logic user wishes external reference reference. When external reference selected chip reference circuitry powers down.
DIF/SGL
CH1, CONVST
EXTREF
REV.
AD7811/AD7812
Control Register (AD7812) Control Register 10-bit-wide, write only register. Control Register written when AD7812 receives falling edge pin. AD7812 will maintain same configuration until control byte written part. control register written same time data being read. This latter feature enhances throughput rates when software control being used when analog input channels being changed frequently. power-up default register contents zeros; therefore, when supplies connected, AD7812 powered down default.
Control Register AD7812
VIN8/AGND DIFF/SGL CONVST EXTREF
This package address bit. used conjunction with package address allow AD7812s share same serial bus. AD7812 also share same serial with AD7811. When control word written control register AD7812 control word ignored package address control byte does match package address hardwired. Only serial port device which received last valid control byte, i.e., address matched address pin, will attempt drive serial next serial read. When part powers this These bits allow AD7812 fully powered down powered combinations override automatic power-down decision conversion. These bits also decide power-down mode when AD7812 enters power-down conversion. There power-down modes-Full Power-Down Partial Power-Down. Power-Down section this data sheet.
PD1,
VIN8/AGND
Description Full Power-Down AD7812 Partial Power-Down Conversion Full Power-Down Conversion Power-Up AD7812
DIF/SGL control register must order this option otherwise this ignored. Setting VIN8/AGND configures analog inputs AD7812 eight single-ended analog inputs referenced analog ground (AGND). setting this input channels VIN1 VIN7 configured seven pseudo differential channels with respect VIN8-see Table This used configure analog inputs single ended pseudo differential pairs. setting this analog inputs configured single ended with respect AGND, pseudo differential with respect VIN8 explained above. Setting this configures analog input channels four pseudo differential pairs VIN1/VIN2, VIN3/VIN4, VIN5/VIN6 VIN7/VIN8-see Table
DIF/SGL
CH2, CH1, These bits used conjunction with VIN8/AGND DIF/SGL select analog input channel. Table shows various channel selections made. CONVST Setting this logic initiates conversion. conversion initiated after write control register taken place. This allows signal acquired even channel changed conversion initiated same write operation. reset after conversion. This must logic user wishes external reference reference. When external reference selected on-chip reference circuitry powers down current consumption reduced about
EXTREF
REV.
AD7811/AD7812
Table AD7811 Channel Configurations
VIN4/AGND
DIF/SGL
Description VIN1 Single Ended with Respect AGND VIN2 Single Ended with Respect AGND VIN3 Single Ended with Respect AGND VIN4 Single Ended with Respect AGND VIN1 Pseudo Differential with Respect VIN4 VIN2 Pseudo Differential with Respect VIN4 VIN3 Pseudo Differential with Respect VIN4 VIN1(+) Pseudo Differential with Respect VIN2(-) VIN3(+) Pseudo Differential with Respect VIN4(-) Internal Test. Input Equal VREF/2 Internal Test. Input Equal VREF
Table AD7812 Channel Configurations
VIN8/AGND
DIF/SGL
Description VIN1 Single Ended with Respect AGND VIN2 Single Ended with Respect AGND VIN3 Single Ended with Respect AGND VIN4 Single Ended with Respect AGND VIN5 Single Ended with Respect AGND VIN6 Single Ended with Respect AGND VIN7 Single Ended with Respect AGND VIN8 Single Ended with Respect AGND VIN1 Pseudo Differential with Respect VIN8 VIN2 Pseudo Differential with Respect VIN8 VIN3 Pseudo Differential with Respect VIN8 VIN4 Pseudo Differential with Respect VIN8 VIN5 Pseudo Differential with Respect VIN8 VIN6 Pseudo Differential with Respect VIN8 VIN7 Pseudo Differential with Respect VIN8 VIN1(+) Pseudo Differential with Respect VIN2(-) VIN3(+) Pseudo Differential with Respect VIN4(-) VIN5(+) Pseudo Differential with Respect VIN6(-) VIN7(+) Pseudo Differential with Respect VIN8(-) Internal Test. Input Equal VREF/2 Internal Test. Input Equal VREF
REV.
AD7811/AD7812
CIRCUIT DESCRIPTION Converter Operation
SUPPLY +2.7V +5.5V 10nF THREE-WIRE SERIAL INTERFACE
AD7811 AD7812 successive approximation analogto-digital converters based around charge redistribution DAC. ADCs convert analog input signals range VDD. Figures show simplified schematics ADC. Figure shows during acquisition phase. closed position comparator held balanced condition sampling capacitor acquires signal VIN.
CHARGE REDISTRIBUTION
VREF CREF SCLK VIN1 VREF INPUT VIN2 DOUT
AD7811/ AD7812
µC/µP
VIN4(8) CONVST AGND
AGND
SAMPLING CAPACITOR
CONTROL LOGIC ACQUISITION PHASE COMPARATOR CLOCK
DGND
Figure Typical Connection Diagram
Analog Input
Figure Acquisition Phase
When starts conversion, Figure will open will move position causing comparator become unbalanced. Control Logic Charge Redistribution used subtract fixed amounts charge from sampling capacitor bring comparator back into balanced condition. When comparator rebalanced, conversion complete. Control Logic generates output code. Figure shows transfer function.
CHARGE REDISTRIBUTION
AGND
SAMPLING CAPACITOR
CONTROL LOGIC CONVERSION PHASE COMPARATOR CLOCK
Figure shows equivalent circuit analog input structure AD7811 AD7812. diodes provide protection analog inputs. Care must taken ensure that analog input signal never exceeds supply rails more than This will cause these diodes become forward biased start conducting current into substrate. maximum current these diodes conduct without causing irreversible damage part. However, worth noting that small amount current being conducted into substrate overvoltage unselected channel cause inaccurate conversions selected channel. capacitor Figure typically about primarily attributed capacitance. resistor lumped component made resistance multiplexer switch. This resistor typically about capacitor sampling capacitor capacitance
Figure Conversion Phase
TYPICAL CONNECTION DIAGRAM
3.5pF
Figure shows typical connection diagram AD7811/ AD7812. AGND DGND connected together device good noise suppression. serial interface implemented using three wires with RFS/TFS connected CONVST Serial Interface section more details. VREF connected well decoupled provide analog input range VDD. AD7811 AD7812 sharing serial with another AD7811 AD7812 then (package address pin) should hardwired low. default power value package address control register applications where power consumption concern, automatic power down conversion should used improve power performance. Power-Down Options section data sheet.
CONVERSION PHASE SWITCH OPEN TRACK PHASE SWITCH CLOSED
Figure Equivalent Analog Input Circuit
analog inputs AD7811 AD7812 configured single ended with respect analog ground (AGND), pseudo differential with respect common, also pseudo differential pairs-see Control Register section.
-10-
REV.
AD7811/AD7812
example pseudo differential scheme using AD7811 shown Figure relevant bits AD7811 Control Register follows DIF/SGL i.e., VIN1 pseudo differential with respect VIN2. signal applied VIN1 pseudo differential scheme sampling capacitor connected VIN2 during conversion AGND described Converter Operation section. This input scheme used remove offsets that exist system. example, system offset offset could applied VIN2 signal applied VIN1. This effect offsetting input span only possible offset input span when reference voltage less than VDD-OFFSET.
CHARGE REDISTRIBUTION VIN1 VIN1 VOFFSET VIN- VOFFSET VIN2 VDD/3 CONVERSION PHASE VIN+ SAMPLING CAPACITOR CONTROL LOGIC COMPARATOR CLOCK
Figure shows equivalent charging circuit sampling capacitor when acquisition phase. represents source impedance buffer amplifier resistive network; internal multiplexer resistance, sampling capacitor. During acquisition phase sampling capacitor must charged within final value. time takes charge sampling capacitor (TCHARGE) given following formula: TCHARGE
VIN+
3.5pF SAMPLING CAPACITOR
Figure Equivalent Sampling Circuit
small values source impedance, settling time associated with sampling circuit (100 effect, acquisition time ADC. example, with source impedance (R2) charge time sampling capacitor approximately charge time becomes significant source impedances greater.
Acquisition Time
Figure Pseudo Differential Input Scheme
When using pseudo differential input scheme signal VIN2 must vary more than during conversion process. signal VIN2 varies during conversion, conversion result will incorrect. single-ended mode sampling capacitor always connected AGND during conversion. Figure shows AD7811/AD7812 pseudo differential input being used make unipolar current measurement. sense resistor used convert current voltage voltage applied differential input shown.
VIN+ RSENSE
applications recommended always buffer analog input signals. source impedance drive circuitry must kept possible minimize acquisition time ADC. Large values source impedance will cause degrade high throughput rates. addition, better performance generally achieved using External capacitor VIN.
ON-CHIP REFERENCE
AD7811/12
VIN-
Figure Current Measurement Scheme
Acquisition Time
AD7811 AD7812 have on-chip reference circuit. schematic Figure shows reference circuit implemented. 1.23 bandgap reference gained provide reference voltage. on-chip reference available externally (SW2 open). external reference (1.2 VDD) applied VREF pin. However order external reference EXTREF control register (Bit must first logic When EXTREF Logic will close, will open amplifier will power down. This will reduce current consumption part about possible different reference voltages selecting on-chip reference external reference.
CREF
EXTERNAL CAPACITOR
starts acquisition phase conversion ends falling edge CONVST signal. conversion settling time associated with sampling circuit. This settling time lasts approximately analog signal VIN+ also being acquired during this settling time. Therefore, minimum acquisition time needed approximately
VREF
1.23V 2.5V
AGND
Figure On-Chip Reference Circuitry
REV.
-11-
AD7811/AD7812
When using automatic power-down between conversions improve power performance part (see Power Throughput) switch will open when part enters power-down mode using internal on-chip reference. This provides high impedance discharge path external capacitor (see Figure typical value external capacitance When part Mode Full Power-Down, because external capacitor holds charge during power-down, internal bandgap reference will power more quickly after relatively short periods full power-down. When operating part Mode Partial Power-Down external capacitor required on-chip reference stays powered while rest circuitry powers down.
TRANSFER FUNCTION
AD7811 AD7812 have power-up time when using external reference when powering from partial power-down. When first connected, AD7811 AD7812 current mode operation. order carry conversion AD7811 AD7812 must first powered writing control register each power-down bits (i.e., full power-up. Quick Evaluation Setup following page.
Mode Full Power-Down (PD1
POWER-UP TIMES
output coding AD7811 AD7812 straight binary. designed code transitions occur successive integer values (i.e., LSB, LSBs, etc.). size VREF/1024. ideal transfer characteristic AD7811 AD7812 shown Figure
111.111 111.110
CODE
111.000 1LSB VREF /1024 011.111
power-up time AD7811 AD7812 after power first connected, after long period Full Power-Down, time takes on-chip 1.23 reference power plus time takes charge external capacitor CREF-see Figure time taken charge CREF 10-bit level given equation (7.6 CREF). CREF power-up time approximately takes power on-chip reference total power-up time either either these conditions However, when powering down fully between conversions achieve better power performance this power-up time reduces after relatively short period power-down CREF holds charge (see On-Chip Reference section). AD7811 AD7812 therefore used Mode with throughput rates kSPS under.
Mode Partial Power-Down (PD1
000.010 000.001 000.000 1LSB +VREF -1LSB ANALOG INPUT
Figure AD7811 AD7812 Transfer Characteristic
POWER-DOWN OPTIONS
power-up time AD7811 AD7812 from Partial Power-Down maximum. When using Partial PowerDown between conversions, there requirement connect external capacitor CREF because reference remains powered This means that AD7811 AD7812 will power after supplies first connected there requirement charge external capacitor.
POWER THROUGHPUT
AD7811 AD7812 provide flexible power management allow user achieve best power performance given throughput rate. power management options selected programming power-down bits (i.e., PD0) control register. Table below summarizes options available. When power-down bits programmed Mode Power Down (full partial), rising edge CONVST will power part. This feature used when powering down between conversions-see Power Throughput. When AD7811 AD7812 placed partial power-down on-chip reference does power down. However, part will power more quickly after long periods power-down when using partial power-down-see Power-Up Times section.
Table III. AD7811/AD7812 Power-Down Options
using Automatic Power-Down (Mode conversion-see Operating Modes section data sheet, superior power performance achieved. Figure shows Automatic Power-Down implemented using CONVST signal achieve optimum power performance AD7811 AD7812. AD7811 AD7812 operated Mode control register Bits respectively Full PowerDown, Partial Power-Down. duration CONVST pulse equal less than power-up time devices-see Operating Modes section. throughput rate reduced, device remains powerdown state longer average power consumption over time drops accordingly.
tPOWER-UP tCONVERT CONVST tCYCLE 100µs 10kSPS POWER-DOWN
CONVST*
Description Full Power-Up Full Power-Down Mode Partial Power-Down (Reference Stays Powered-Up) Power-Down Mode Full Power-Down Power-Down -12-
Figure Automatic Power-Down
*This refers state CONVST signal conversion.
REV.
AD7811/AD7812
example, AD7811 operated continuous sampling mode with throughput rate kSPS, using chip reference power consumption calculated follows. power dissipation during normal operation 10.5 power-up time conversion time AD7811 said dissipate 10.5 (worst case) during each conversion cycle. throughput rate kSPS, cycle time average power dissipated during each cycle 100) (10.5 Figure shows Power Throughput Rate Automatic Full Power-Down.
SUPPLY 10nF
VREF CREF INPUT SCLK VIN1 VIN2 DOUT
AD7812
VIN7 VIN8 AGND DGND
CONVST
Figure Evaluation Quick Setup
POWER
setup uses full duplex, 16-bit, serial interface protocol, e.g., SPI. possible 8-bit transfers carrying consecutive read/write operations. data transferred first. When power first connected device powered down mode operation consuming only AD7812 must first configured carrying serial write operation.
THROUGHPUT kSPS
0.01
Figure AD7811/AD7812 Power Throughput
-100 FREQUENCY AD7811/12 2048 POINT SAMPLING 357.142kHz 30.168kHz
CONVST signal first pulsed enable serial port (rising falling edge respectively-see Serial Interface section). Next, 16-bit serial read/write operation carried out. writing 6040 AD7812 part powered external reference (i.e., VDD) analog input VIN1 selected. data read from part during this read/ write operation invalid. necessary wait approximately before pulsing CONVST again initiating conversion. allow AD7812 power correctly-see Power-Up Times section. Approximately after falling edge CONVST, i.e., after conversion, serial read/write take place. This time 4040 written AD7812 data read from part result conversion. output code straight binary format will left justified 16-bit serial register (MSB clocked first). idling CONVST signal high possible operate AD7812 Mode Mode respectively.
OPERATING MODES
Figure AD7811/AD7812
QUICK EVALUATION SETUP
schematic shown Figure shows suggested configuration AD7812 first look evaluation part. external reference circuit needed VREF connected VDD. CONVST signal connected enable serial port. Also selecting Mode operation (see Operating Modes section) power performance AD7812 evaluated.
mode operation AD7811 AD7812 selected when (logic) state CONVST checked conversion. CONVST signal logic high conversion, part does power down operating Mode however, CONVST signal brought logic before conversion, AD7811 AD7812 will power down conversion. This Mode operation.
REV.
-13-
AD7811/AD7812
POWER-UP
CONVST
CONVERT
CONVERT
6040
4040
4040
DOUT
VALID
VALID DATA
VALID DATA
Figure Read/Write Sequence AD7812
Mode Operation (High Speed Sampling)
When AD7811 AD7812 operated Mode they powered down between conversions. This mode operation allows high throughput rates achieved. timing diagram Figure shows this optimum throughput rate achieved bringing CONVST signal high before conversion. sampling circuitry leaves tracking mode goes into hold falling edge CONVST. conversion also initiated this time. conversion takes complete. this point, result current conversion latched into serial shift register state CONVST signal checked. CONVST signal should logic high conversion prevent part from powering down. serial port AD7811 AD7812 enabled rising edge first SCLK after rising edge signal-see Serial Interface section. explained earlier, this rising edge
CONVST SCLK
should occur before conversion process part powered down. serial read take place stage after rising edge CONVST. serial read initiated before current conversion process (i.e., time "A"), result previous conversion shifted DOUT pin. possible allow serial read extend beyond conversion. this case data will latched into output shift register until read finished. dynamic performance AD7811 AD7812 typically degrades while reading during conversion. user waits until conversion process, i.e., after falling edge CONVST (Point "B") before initiating read, current conversion result shifted out. serial read must finish least prior next falling edge CONVST allow part accurately acquire input signal.
DOUT
CURRENT CONVERSION RESULT
Figure Mode Operation Timing Diagram
Mode Operation (Automatic Power-Down)
When used this mode operation part automatically powers down conversion. This achieved leaving CONVST signal until conversion. Because takes approximately part power-up after been powered down, this mode operation intended used applications where slower throughput rates required, i.e., order kSPS improved power performance required-see Power Throughput section. There power-down modes AD7811/AD7812 enter during automatic power-down. These modes discussed Power-Up Times section this data sheet. timing diagram Figure shows operate part
Mode AD7811/AD7812 powered down, rising edge CONVST pulse causes part power-up. Once part powered after rising edge CONVST) CONVST signal brought conversion initiated this falling edge CONVST signal. conversion takes after this time conversion result latched into serial shift register part powers down. Therefore, when part operated Mode effective conversion time equal power-up time conversion time (2.3 µs).
-14-
REV.
AD7811/AD7812
POWER-UP
CONVST
SCLK
DOUT
CURRENT CONVERSION RESULT
Figure Mode Operation Timing Diagram
NOTE: Although AD7811 AD7812 take power after rising edge CONVST, necessary leave CONVST high after rising edge before bringing initiate conversion. CONVST signal goes before time elapsed, then power-up time timed internally conversion then initiated. Hence AD7811 AD7812 guaranteed have always poweredup before conversion initiated, even CONVST pulsewidth CONVST pulsewidth then conversion initiated falling edge. case Mode operation, rising edge first SCLK after rising edge enables serial port AD7811 AD7812 (see Serial Interface section). serial read initiated soon after this rising edge (Point "A"), i.e., before conversion, result previous conversion shifted DOUT. order read result current conversion, user must wait least after power-up least after falling edge CONVST, (Point "B"), whichever occurs latest before initiating serial read. serial port AD7811 AD7812 still functional even though devices have been powered down. Because possible serial read from part while powered down, AD7811 AD7812 powered only conversion immediately powered down conversion. This significantly improves power consumption part slower throughput rates-see Power Throughput Rate section.
SCLK
SERIAL INTERFACE
serial interface AD7811 AD7812 consists five wires, serial clock input, SCLK, receive data clock synchronization input RFS, transmit data clock synchronization input TFS, serial data output, DOUT, serial data input, DIN, (see Figure 18). serial interface designed allow easy interfacing most microcontrollers DSPs, e.g., PIC16C, PIC17C, QSPI, SPI, DSP56000, TMS320 ADSP21xx, without need gluing logic. When interfacing 8051, SCLK must inverted. Microprocessor/Microcontroller Interface section explains interface some popular DSPs microcontrollers. Figure shows timing diagram serial read write AD7811 AD7812. serial interface works with both continuous noncontinuous serial clock. rising edge falling edge resets counter that counts number serial clocks ensure correct number bits shifted serial shift registers. Once correct number bits have been shifted out, SCLK ignored. order another serial transfer take place counter must reset active edges RFS. first rising SCLK edge after rising edge signal causes DOUT leave high impedance state data clocked onto DOUT line also subsequent SCLK rising edges. DOUT goes back into high impedance state 11th SCLK rising edge-Point Figure minimum SCLKs therefore needed carry
DOUT
Figure Serial Interface Timing Diagram
REV.
-15-
AD7811/AD7812
serial read. Data line latched first SCLK falling edge after falling edge signal subsequent SCLK falling edges. control register updated 13th SCLK rising edge-point Figure minimum SCLK pulses therefore needed complete serial write operation. multipackage applications signals used chip select signals. serial interface will shift data until receives active edge signal.
Simplifying Serial Interface AD7811/AD7812 MC68HC11
Serial Peripheral Interface (SPI) MC68HC11 configured Master Mode (MSTR Clock Polarity (CPOL) Clock Phase (CPHA) configured writing Control Register (SPCR)-see 68HC11 user manual. connection diagram shown Figure
AD7811/AD7812*
SCLK DOUT
MC68HC11*
SCLK/PD4 MISO/PD2 MOSI/PD3
five-wire interface designed support many different serial interface standards. However, possible reduce number lines required just three. simply connecting pins CONVST signal (see Figure CONVST signal used enable serial port reading writing. This only possible where noncontinuous serial clock being used.
MICROPROCESSOR INTERFACING
CONVST
Serial Interface AD7811 AD7812 allows parts directly connected range many different microprocessors. This section explains interface AD7811 AD7812 with some more common microcontroller serial interface protocols.
AD7812/AD7811 PIC16C6x/7x
*ADDITIONAL PINS OMITTED CLARITY
Figure Interfacing MC68HC11
AD7811/AD7812 8051
PIC16C6x Synchronous Serial Port (SSP) configured Master with Clock Polarity This done writing Synchronous Serial Port Control Register (SSPCON). user PIC16/17 Microcontroller User Manual. Figure shows hardware connections needed interface PIC16/17. this example port being used pulse CONVST enable serial port AD7811/ AD7812. This microcontroller transfers only eight bits data during each serial transfer operation; therefore, consecutive read/write operations needed.
AD7811/AD7812 requires clock synchronized serial data. 8051 serial interface must therefore operated Mode this mode serial data enters exits through shift clock output (half duplex). Figure shows 8051 connected AD7811/AD7812. However, because AD7811/AD7812 shifts data rising edge shift clock latches data falling edge, shift clock must inverted.
AD7811/AD7812*
SCLK DOUT
8051*
AD7811/AD7812*
SCLK DOUT
PIC16C6x/7x*
SCK/RC3 SDO/RC5 SDI/
P1.1
CONVST
*ADDITIONAL PINS OMITTED CLARITY
Figure Interfacing 8051 Serial Port
*ADDITIONAL PINS OMITTED CLARITY
Figure Interfacing PIC16/17
possible implement serial interface using data ports 8051. This would also allow full duplex serial transfer implemented. technique involves "bit banging" port (e.g. P1.0) generate serial clock using other ports (e.g. P1.1 P1.2) shift data out- Figure
-16-
REV.
AD7811/AD7812
AD7811/AD7812*
SCLK DOUT P1.0 P1.1 P1.2
8051*
P1.3
TFSW RFSW Normal Framing INVRFS INVTFS Active High Frame Signal DTYPE Right Justify Data SLEN 1001, 10-Bit Data Words ISCLK Internal Serial Clock TFSR RFSR Frame Every Word IRFS External Framing Signal ITFS Internal Framing Signal 10-bit data words will right justified 16-bit serial data registers when using this configuration. Figure shows connection diagram.
*ADDITIONAL PINS OMITTED CLARITY
AD7811/AD7812*
SCLK DOUT
ADSP21xx*
SCLK
Figure Interfacing 8051 Using Ports
AD7811/AD7812 TMS320C5x
Serial interface TMS320C5x uses continuous serial clock frame synchronization signals synchronize data transfer operations with peripheral devices like AD7811. Frame synchronization inputs have been supplied AD7811/AD7812 allow easy interfacing with extra gluing logic. serial port TMS320C5x operate Burst Mode with internal CLKX serial clock) frame sync). Serial Port Control register (SPC) must have following setup: connection diagram shown Figure
*ADDITIONAL PINS OMITTED CLARITY
Figure Interfacing ADSP21xx
AD7811/AD7812 DSP56xxx
AD7811/AD7812*
SCLK
TMS320c5x*
CLKX CLKR
connection diagram Figure shows AD7811 AD7812 connected (Synchronous Serial Interface) DSP56xxx family DSPs from Motorola. operated Synchronous Mode (SYN with internally generated 1-bit clock period frame sync both (FSL1 FSL0 bits respectively).
DOUT
DOUT
AD7811/AD7812*
SCLK
DSP56xxx*
*ADDITIONAL PINS OMITTED CLARITY
Figure Interfacing TMS320c5x
AD7811/AD7812 ADSP21xx
ADSP21xx family DSPs easily interfaced AD7811/AD7812 without need extra gluing logic. SPORT operated normal framing mode. SPORT control register should follows:
*ADDITIONAL PINS OMITTED CLARITY
Figure Interfacing DSP56xxx
REV.
-17-
AD7811/AD7812
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
16-Lead Plastic (N-16)
0.840 (21.33) 0.745 (18.93)
0.280 (7.11) 0.240 (6.10) 0.060 (1.52) 0.015 (0.38) 0.130 (3.30)
0.210 (5.33) 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54)
0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93)
0.070 (1.77) SEATING 0.045 (1.15) PLANE
0.015 (0.381) 0.008 (0.204)
16-Lead Small Outline Package (SOIC) (R-16A)
0.3937 (10.00) 0.3859 (9.80)
0.1574 (4.00) 0.1497 (5.80)
0.2550 (6.20) 0.2284 (5.80)
0.0098 (0.25) 0.0040 (0.10)
0.0688 (1.75) 0.0532 (1.35)
0.0196 (0.50) 0.0099 (0.25)
SEATING PLANE
0.0500 (1.27)
0.0192 (0.49) 0.0138 (0.35)
0.0099 (0.25) 0.0075 (0.19)
0.0500 (1.27) 0.0160 (0.41)
16-Lead Thin Shrink Outline Package (TSSOP) (RU-16)
0.201 (5.10) 0.193 (4.90)
0.177 (4.50) 0.169 (4.30)
0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) 0.0256 (0.65) 0.0118 (0.30) 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090)
0.256 (6.50) 0.246 (6.25)
SEATING PLANE
0.028 (0.70) 0.020 (0.50)
-18-
REV.
AD7811/AD7812
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
20-Lead Plastic (N-20)
1.060 (26.90) 0.925 (23.50)
0.280 (7.11) 0.240 (6.10)
0.210 (5.33) 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54)
0.060 (1.52) 0.015 (0.38) 0.130 (3.30) 0.070 (1.77) SEATING 0.045 (1.15) PLANE
0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93)
0.015 (0.381) 0.008 (0.204)
20-Lead Small Outline Package (SOIC) (R-20A)
0.5118 (13.00) 0.4961 (12.60)
0.1043 (2.65) 0.0926 (2.35)
0.4193 (10.65) 0.3937 (10.00)
0.2992 (7.60) 0.2914 (7.40)
0.0291 (0.74) 0.0098 (0.25)
0.0118 (0.30) 0.0040 (0.10)
0.0500 0.0192 (0.49) (1.27) 0.0138 (0.35) SEATING 0.0125 (0.32) PLANE 0.0091 (0.23)
0.0500 (1.27) 0.0157 (0.40)
20-Lead Thin Shrink Outline Package (TSSOP) (RU-20)
0.260 (6.60) 0.252 (6.40)
0.177 (4.50) 0.169 (4.30)
0.006 (0.15) 0.002 (0.05)
0.0433 (1.10) 0.0256 (0.65) 0.0118 (0.30) 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090)
0.256 (6.50) 0.246 (6.25)
SEATING PLANE
0.028 (0.70) 0.020 (0.50)
REV.
-19-
-20-
C3138-12-7/97
PRINTED U.S.A.
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