Digital Input/Output Card DIO-32d Document Part Document Referenc
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DIO-32d
Digital Input/Output Card
DIO-32d Document Part Document Reference Document Issue Level Manual covers PCBs identified 127-196 127-196.Doc DIO-32d Rev.
rights reserved. part this publication reproduced, stored retrieval system, transmitted, form means, electronic, mechanical, photocopied, recorded otherwise, without prior permission, writing, from publisher. permission contact Blue Chip Technology. Information offered this manual correct time printing. Blue Chip Technology accepts responsibility inaccuracies. This information subject change without notice. trademarks registered names acknowledged.
Blue Chip Technology Ltd. Chowley Oak, Tattenhall Chester, Cheshire 9EX. Telephone 01829 772000 Facsimile 01829 772001.
Amendment History
Issue Level
Issue Date 9/89/95 5/9/95 18/1/96
Author
Amendment Details First approved issue, front sheet. issue 95/120. information added, drawings improved. Minor error corrected. Document Part previously 127-033. window front cover logo. 97/143
25/11/97
Contents
INTRODUCTION. ABOUT MANUAL. CHAPTER Installing DIO-32d Base Address. Interrupt Selection. Further Interrupt Options Driving Timer from External Sources Maximum Input Voltage Range Selecting Output Voltage Source. Other Links CHAPTER Connection Details Digital Inputs Digital Outputs CHAPTER Programming Details µPD71054 Timer. Timer Modes. CHAPTER Technical Specifications. Electromagnetic Compatibility (EMC). Specification CARD LAYOUT
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Contents
APPENDIX NUMBERING SYSTEMS Binary Hexadecimal Numbers Base Address Selection APPENDIX MAPS. PC/XT/AT Address PC/XT Interrupt PC/AT Interrupt Channels.
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Introduction
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INTRODUCTION
DIO-32d compatible short card which provides user with digital inputs digital outputs, which opto-isolated from host computer ground system. card features isolated volt supply, on-board timer user selectable base address, interrupt source interrupt level. timer used interrupt source general purpose timekeeping device.
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About Manual
ABOUT MANUAL
This manual organised into four chapters appendices. Each chapter covers different aspect using DIO-32d. order best results from product, user urged read chapters, paying particular note Chapter which deals with initial installation card. appendices used reference time. Chapter Explaines configure card your computer user selectable links. Details connections from card. Gives details card's address mapping internal register details allowing user write custom software control card. Details card's technical specification. this section determine card's suitability particular application. Gives brief introduction Binary Hexadecimal numbering systems those unfamiliar with concepts. Lists IBM-PC address map, interrupt allocations should used along with Chapter when first installing card.
Chapter Chapter
Chapter
Appendix
Appendix
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Chapter
Installing DIO-32d
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CHAPTER Installing DIO-32d
Before installing card into your computer system, there number user-configurable links that must set. positioning these links will depend upon computer system into which card being fitted. Before fitting links card, please read next section. unfamiliar with binary hexadecimal number systems primer included appendix.
Base Address
correct operation card host computer, range addresses that card will occupy must set. base address represents first address that card will use. DIO-32d requires total contiguous addresses (including base address) correct operation. Blue Chip Technology cards factory default base address hex. Check ensure that base address full range addresses free use. addresses free another range must chosen. guide, please information contained appendix assist choosing suitable base address. sure, refer your computer system handbook information relating other peripheral devices possibly already installed (additional communications cards, parallel ports games ports etc.).
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Installing DIO-32d
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addresses available then proceed follows: Locate header pins (JP3). These pins marked "BASE ADDRESS". Each pair pins represents binary digit starting with pair pins marked with arrow. This pair pins represents lowest value (008 hex), subsequent pins represent increasing values. highest single base address link hex. select address, link position must left open. Placing link pair pins de-selects that particular address. Example: select base address hex, links should follows:
BASE ADDRESS Figure Example Base Address Selection
Interrupt Selection
part link between DIO-32d host computer, interrupt signal occur regular intervals from timer when input changes state. application software then uses interrupt service calling device. interrupts essential greatly enhances functionality card. order interrupts data transfer, user must select Interrupt Request Channel (IRQ) card use. DIO-32d Interrupt Channels IRQ-2
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with selection base addresses, chosen Interrupt Channel must free selected other peripheral system. Appendix used identify Interrupt Channels that normally already most systems which ones will probably free use. Check that selected channel free use. sure, refer your computer system handbook information relating other peripheral devices possibly already installed (additional communications cards, parallel ports games ports etc.). Interrupt Channel chosen available DIO-32d then card follows: Locate header pins labelled JP4. These pins marked "SET INTERRUPT". select interrupt place link pair pins corresponding chosen Interrupt Request Channel. Only channel should selected, other pins must left open. Example: select Interrupt channel links should follows:
INTERRUPT
Figure Example Interrupt Signal Selection
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Installing DIO-32d
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Further Interrupt Options
on-board timer contains three independent counter/timer sections which programmed various count lengths modes operation. source interrupt signal also user option, selectable jumper JP1. interrupt source selected from either Timer Timer
SOURCE
Figure Example Interrupt Source Selection first timers (Timer Timer cascaded. timer period interrupts programmed software. Timers minimum delay microseconds maximum delay 65,535 microseconds. Timer minimum maximum time delays microseconds 71.58 minutes respectively. calculate counter setting divide required delay timer master clock period this case microsecond). example delay microseconds required then: 10,000 counts.
Driving Timer from External Sources
Timers provide interrupt source. Whilst Timer driven on-board oscillator, clock input Timer available connector, user provide external clock input.
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external clock input selectable. share same signal digital input (DIN-1, which differential input), dedicated (singleended) input pin. selection setting jumper JP22. JP22 3pin header. centre connected "A", digital input (DIN1) input. connected, clock input selected source.
JP22 [DIN1] [CLKIN]
Figure Timer Clock Source Selection Jumper external clock must range volts with maximum frequency 10MHz.
Maximum Input Voltage Range
DIO-32d allows maximum input volts. Although range volts, opto-isolators will actually work considerably lower voltages than range. Since opto-isolators strictly digital devices they will allow switching these lower levels. minimum recommended voltage input volts maximum level volts. Voltages greater than volts input will damage card.
Selecting Output Voltage Source
Because digital outputs from DIO-32d open collector types, load must placed between output terminal positive voltage supply. This either external supply, isolated volt supply on-board supply. link JP13 selects which supply used.
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Figure Output Power Supply Selection Jumper internal volt source protected 125mA fuse which will fail excessive load currents drawn. This will occur output shorted ground load resistance's used value. internal supply provide 42mA total (approx. channel channels used). external supply used then maximum current channel increases 500mA. output devices also protected 125mA fuse.
Other Links
Some boards supplied with additional links fitted (JP5 JP12 JP14 JP21). These used should left open.
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JP13
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Connection Details
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CHAPTER Connection Details
following table refers plug rear card. Pin1 connector bottom left when looking `into' pins connector.
SIGNAL +DIN1 (+T2 I/P) -DIN1 (-T2 I/P) +DIN2 -DIN2 +DIN3 -DIN3 +DIN4 -DIN4 +DIN5 -DIN5 +DIN6 -DIN6 +DIN7 -DIN7 +DIN8 -DIN8 +DIN9 SIGNAL -DIN9 +DIN10 -DIN10 +DIN11 -DIN11 +DIN12 -DIN12 +DIN13 -DIN13 +DIN14 -DIN14 +DIN15 INTERNAL +24V +DIN16 TIMER DOUT SIGNAL DOUT2 DOUT3 DOUT4 DOUT5 DOUT6 DOUT7 DOUT8 DOUT9 DOUT10 DOUT11 DOUT12 DOUT13 DOUT14 DOUT15 DOUT16 EXTERNAL +24V COMMON
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Connection Details
Chapter
Digital Inputs
input signals DIO-32d digital with voltage limits zero volts logic volts logic high. Voltages outside these limits cause damage card. Digital inputs channels (DIN1-14) isolated from power supplies also from each other. signals applied between "+DIN" "-DIN" connections. Input channels (DIN15 share common connection, signals must applied between "+DIN" "COMMON GND".
Digital Outputs
digital outputs open collector types must returned positive supply voltage load. positive supply either on-board volts supply externally provided source greater than volts. When output switched "on" then voltage collector output will logic low. output voltage this logic level typically volts.
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Connection Details
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FROM INTERNAL SUPPLY OUTPUT CIRCUITRY
INTERNAL EXTL.24 LOAD FROM EXTERNAL SUPPLY (+24
DOUT
COMMON
FROM EXTERNAL SUPPLY
Figure Showing Dio-32d Output Connections voltage collector output will range from 0.7V logic value equal supplied rail voltage. When output transistor switched maximum permissible current sink 500mA. Note that maximum POWER dissipation each collector output that determines limits operation. Because package limitations, output dissipation total Watts channels Watts channels single output being used then maximum permissible dissipation Watt. absolute maximum permissible collector voltage volts.
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Programming Details
Chapter
CHAPTER Programming Details
address maps DIO-32d shown below. card occupies total contiguous addresses some which both read write.
ADDRESS Base Base Base Base Base Base Base Base FUNCTION Timer input/output Register Timer input/output Register Timer input/output Register Timer Control Register Channels Input Channels Input Channels Output Channels Output READ/ WRITE
µPD71054 Timer
card utilises µPD71054 TIMER chip. This equivalent Intel i8254 device. full details program µPD71054 refer manufacturers' data sheets. µPD71054 contains three independent counters which operated various modes. Presented here brief summary some modes possible programming timers' internal registers. There five basic modes operation each providing different output from device. Timers connected series provide longer delay period. Timer independent. output from Timer Timer selectable jumper allow interrupt generation. clock source Timer link selectable.
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Programming Details
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Clock
Timer
Timer
DIN1+/pins D-type Isoln. Isoln. JP22 Timer Input Timer
Jumper
Figure Timer Circuit Block Diagram
Timer Modes
following modes operation possible programming control register within µPD71054. Mode When programmed, output will LOW. When counter decrements from value loaded into count registers zero, output will HIGH. will remain high until count re-programmed into count registers. Mode Implemented Mode This mode operates frequency divider. When programmed, output high. When count decrements value output will clock cycle only then return HIGH. This cycle repeats continuously without need re-program count value.
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Programming Details
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Mode output toggles each time count register decrements base level from value programmed into count value loaded number then counter will reach zero before output toggles. This mode acts frequency divider with approximate mark-space ratio. Mode This mode similar mode output pulses when count reaches zero instead Mode Implemented.
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Chapter
Technical Specifications
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CHAPTER Technical Specifications
Number Input Channels Number Output Channels Interrupt Signal Options Input Characteristics Inputs Opto-Isolated from Computer Ground Isolation Voltage Voltage Input Range Input Load Current Output Characteristics outputs Opto-Isolated from Computer Ground Isolation Output Type Voltage Limits each output Maximum Current Drive each output Maximum Total Load Power each Block Outputs volts Open Collector Min. volts Max. volts 500mA Watts Volts Min. 3Volts Max. Volts 10ma Input IRQ-2 inclusive
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Technical Specifications
Chapter
Timers Number Timer Channels Timer (On-board Clock Source) Timer Resolution Min. Time Interval Max. Time Interval Timer (External Closk) Minimum Resolution Min. Time Interval Max. Time Interval Limited Addresses Total Addresses Required Board Connections Input/Output Dimensions Board Overall Male Type 8-bit Read, Write) 65.535ms 125ns 125ns None
Length Height Width
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Technical Specifications
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Electromagnetic Compatibility (EMC)
This product meets requirements European Directive (89/336/EEC) eligible bear mark. been assessed operating Blue Chip Technology Icon industrial However, because board installed variety computers, certain conditions have applied ensure that compatibility maintained. meets requirements industrial environment (Class product) subject those conditions. board must installed computer system which provides screening suitable industrial environment. recommendations made computer system manufacturer/supplier must complied with regarding earthing installation boards. board must installed with backplate securely screwed chassis computer ensure good metal-to-metal (i.e. earth) contact. Most problems caused external cabling boards. With analogue boards particular attention must paid this aspect. imperative that external cabling board totally screened, that screen cable connects metal bracket board hence earth. recommended that round screened cables with braided wire screen used preference those with foil screen drain wire. metal connector shells which connect around full circumference screen; they superior those which earth screen simple "pig-tail". Standard ribbon cable will adequate unless contained wholly within cabinetry housing industrial ensure that board meets industrial radiated field immunity V/metre, cable should also fitted with ferrite clamp external cable close possible connector. preferred type Chomerics clip-on style, type H8FE-1004-AS. Ensure that screen external cable bonded good earth remote cable.
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Technical Specifications
Chapter
Cables which connect externally boards levels should exceed meters length. This restriction does apply opto-isolated boards. Failure observe these recommendations invalidate compliance.
Warning This Class product. domestic environment this product cause radio interference which case user required take adequate measures.
Specification
Blue Chip Technology Icon industrial fitted with this card meets following specification: Emissions: 55022:1995 Radiated Conducted Immunity: 50082-2:1991 incorporating Electrostatic Discharge 801-2:1984 Performance Criteria 801-3:1984 Performance Criteria 801-4:1988 Performance Criteria Class Class
Radio Frequency Susceptibility
Fast Burst Transients
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Technical Specifications
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CARD LAYOUT
TIMER MODE
JP22 [DIN1] [CLKIN]
JP22
SOURCE
BASE ADDRESS
INTERRUPT
SOURCE
BASE ADDRESS
INTERRUPT
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JP13
JP13
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Numbering Systems
Appendix
APPENDIX NUMBERING SYSTEMS Binary Hexadecimal Numbers
normal numbering system termed DECIMAL because there possible digits single column numbers. Decimal numbers also referred numbers having Base When counting, numbers increment units column from next increment resets units column carries over into next column. This indicates that there been full (the base number) counts units column. second column therefore termed "tens" column. more convenient when programming number system that provides clearer picture hardware operational register level. most common number systems used BINARY HEXADECIMAL. These systems provide alternative representation decimal numbers. binary number there only possible values result binary numbering often known Base When counting binary numbers number increments units column from next increment units column reset carried over next column. This column indicates that full counts have occurred units column. second column termed "twos" column. Hexadecimal numbers have values followed letters also known system with Base With this counting system units increment from with decimal system, next count units column increments from then After units column resets next column increments from This indicates that sixteen counts have occurred units column. second column termed "sixteen's" column.
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Appendix
Numbering Systems
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following table shows three systems indicate successive numbers:
Decimal Base Binary Base Hexadecimal Base
Notice next higher column does increment until lesser right overflowed. Binary representation ideally suited where visual representation computer register data needed. Each column termed (from Binary digIT). Only five Bits shown above table. With larger numbers, more Bits required. Normally Bits arranged groups eight termed BYTES. definition there BITS BYTE. Each column) value. binary table above rightmost least significant column each digit value Each digit next column value next then
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Numbering Systems
Appendix
following diagram illustrates this.
DECIMAL VALUE
determine decimal value binary pattern, decimal number each column containing binary "1".
DECIMAL VALUE BINARY NUMBER
above example shows binary pattern that equivalent Decimal. binary string defining Byte unwieldy. make less error prone, bits forming byte divided into groups bits, known NIBBLES. With four bits there possible numeric combinations (including zero). convenient method representing each nibble hexadecimal base system. When converting binary hex, byte divided into nibbles each represented single digit. This technique applied selection base address circuit board. following diagram illustrates construction number.
NIBBLE VALUE BINARY NUMBER
HEXADECIMAL: Hexadecimal upper nibble lower nibble resulting value Hex, since Decimal equals Hex.
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Appendix
Numbering Systems
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Base Address Selection
Each column physically represented board pair pins. practice, boards cover range addresses (usually Decimal). Therefore order four bits included, higher order bits added. This gives address range following diagram shows typical pins.
Here link fitted denote binary logic "0", left open indicate binary logic "1". example shows base address setting Hex.
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Maps
Appendix
APPENDIX MAPS PC/XT/AT Address
Address 000-01F 020-03F 040-05F 060-06F 070-07F 080-09F 0A0-0BF 0F8-0FF 1F0-1F8 200-207 278-27F 2F8-2FF 300-31F 360-36F 378-37F 380-38F 3A0-3AF 3B0-3BF 3C0-3CF 3D0-3DF 3F0-3F7 3F8-3FF Allocated Controller (8237A-5) Interrupt Controller (8259A) Timer (8254) Keyboard Controller (8742) Control Port CMOS RAM, Mask (Write) Page Register (Memory Mapper) Interrupt Controller (8259) Clear (80287) Busy Reset (80287) Numeric Processor Extension (80287) Hard Disk Drive Controller Reserved Reserved Parallel Printer Port Reserved Serial Port Reserved Reserved Parallel Printer Port Reserved SDLC Communications, Bisync Reserved Bisync Reserved Reserved Display Controller Diskette Drive Controller Serial Port
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Maps
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PC/XT Interrupt
Number Allocated Parity Timer Keyboard Reserved Asynchronous Communications (Secondary) SDLC Communications Asynchronous Communications (Primary) SDLC Communications Fixed Disk Diskette Parallel Printer
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Maps
Appendix
PC/AT Interrupt
Level CTLR CTLR Allocated Parity Channel Check (Interrupt Controllers) Timer Output Keyboard (Output Buffer Full) Interrupt from CTLR Real-time Clock Interrupt Redirected (IRQ Reserved Reserved Reserved Co-processor Fixed Disk Controller Reserved Serial Port Serial Port Parallel Port Diskette Controller Parallel Port
Channels
Memory Refresh Spare Floppy Disk Drive Spare
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