November 1983 Revised December 1998 CD4066BC Quad Bilateral Switc

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November 1983 Revised December 1998 CD4066BC Quad Bilateral Switc

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CD4066BC Quad Bilateral Switch
November 1983 Revised December 1998
CD4066BC Quad Bilateral Switch
CD4066BC quad bilateral switch intended transmission multiplexing analog digital signals. pin-for-pin compatible with CD4016BC, much lower "ON" resistance, "ON" resistance relatively constant over input-signal range. High degree linearity Extremely "OFF" VDD-VSS 10V, (typ.) switch leakage: VDD-VSS 10V, 25°C 1012(typ.)
Extremely high control input impedance crosstalk (typ.) between switches Frequency response, switch "ON"
Features
Wide supply voltage range High noise immunity analog switching "ON" resistance operation Matched "ON" resistance over signal input "ON" resistance flat over peak-to-peak signal range High "ON"/"OFF" (typ.) kHz, 0.1% distortion (typ.) kHz, 5Vp-p, output voltage ratio High degree linearity High degree linearity RON=5 (typ.) Wide range digital ±7.5 VPEAK 0.45 (typ.)
MHz, (typ.)
Applications
Analog signal switching/multiplexing Signal gating Squelch control Chopper Modulator/Demodulator Commutating switch Digital signal switching/multiplexing CMOS logic implementation conversion Digital control frequency, impedance, phase, analog-signal-gain
Ordering Code:
Order Number CD4066BCM CD4066BCJ CD4066BCN Package Number M14A M14D N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150" Narrow Body 14-Lead Small Outline Package (SOP), EIAJ TYPE 5.3mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available Tape Reel. Specify appending suffix letter ordering code.
Connection Diagram
Assignments SOIC,
Schematic Diagram
1999 Fairchild Semiconductor Corporation
DS005665.prf
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CD4066BC
Absolute Maximum Ratings
(Note (Note Supply Voltage (VDD) Input Voltage (VIN) Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line Small Outline Lead Temperature (TL) (Soldering, seconds) 300°C (Note -0.5V +18V -0.5V VCC+0.5V -65°C +150°C
Recommended Operating Conditions (Note
Supply Voltage (VDD) Input Voltage (VIN) Operating Temperature Range (TA) -40°C +85°C
Note "Absolute Maximum Ratings" those values beyond which safety device cannot guaranteed. They meant imply that devices should operated these limits. tables "Recommended Operating Conditions" "Electrical Characteristics" provide conditions actual device operation. Note unless otherwise specified.
Electrical Characteristics
Symbol Parameter Quiescent Device Current SIGNAL INPUTS OUTPUTS "ON" Resistance
Conditions
-40°C
+25°C 0.01 0.01 0.01
+85°C
Units
(VDD VSS/2) VDD, 1050 1200
"ON" Resistance Between Switches
(VDD VSS/2) ±0.1 ±200
Input Output Leakage Switch "OFF"
CONTROL INPUTS VILC Level Input Voltage 10µA VIHC HIGH Level Input Voltage Input Current (Note VDD-VSS VDDVISV VDDVCV 11.0 11.0 2.25 6.75 2.75 8.25 10-5 11.0
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CD4066BC
Electrical Characteristics
Symbol tPHL, tPLH Parameter Propagation Delay Time Signal Input Signal Output
(Note
Conditions Units
25°C, unless otherwise noted VDD, (Figure 200k tPZH, tPZL Propagation Delay Time Control Input Signal Output High Impedance Logical Level tPHZ, tPLZ Propagation Delay Time Control Input Signal Output Logical Level High Impedance Sine Wave Distortion Frequency Response-Switch "ON" (Frequency (Figure Figure (Figure Figure 5Vp-p, kHz, (Figure -5V, 5Vp-p, Log10 VOS/VOS kHz)-dB, (Figure Feedthrough Switch "OFF" (Frequency Crosstalk Between Switches (Frequency Crosstalk; Control Input Signal Output Maximum Control Input 5.0V, -5.0V, 5.0Vp-p, Log10, VOS/VIS (Figure VC(A) 5.0V; VC(B) 5.0V, VIS(A) Vp-p, Log10, VOS(B)/VIS(A) (Figure 10V, Square Wave, (Figure (Figure VOS(f) VOS(1.0 kHz) 5.0V CIOS Signal Input Capacitance Signal Output Capacitance Feedthrough Capacitance Control Input Capacitance mVp-p 1.25
Note Parameters guaranteed correlated testing. Note These devices should connected circuits with power "ON". Note cases, there approximately probe capacitance output; however, this capacitance included wherever specified. Note voltage in/out voltage out/in pin. voltage control input. Note Conditions VIHC: VDD, standard series standard series IOL.
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CD4066BC
Typical Performance Characteristics
"ON" Resistance Signal Voltage 25°C "ON" Resistance Function Temperature VDD-VSS
"ON" Resistance Function Temperature VDD-VSS
"ON" Resistance Function Temperature VDD-VSS
Special Considerations
applications where separate power sources used drive signal input, current capability should exceed VDD/RL effective external load CD4066BC bilateral switches). This provision avoids permanent current flow clamp action supply when power applied removed from CD4066BC. certain applications, external load-resistor current include both signal-line components. avoid drawing current when switch current flows into terminals voltage drop across bidirectional switch must exceed 0.6V 25°C, 0.4V 25°C (calculated from values shown). current will flow through switch current flows into terminals
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CD4066BC
Test Circuits Switching Time Waveforms
FIGURE tPHL, tPLH Propagation Delay Time Signal Input Signal Output
FIGURE tPZH, tPHZ Propagation Delay Time Control Signal Output
FIGURE tPZL, tPLZ Propagation Delay Time Control Signal Output
distortion frequency response tests feedthrough test
FIGURE Sine Wave Distortion, Frequency Response Feedthrough
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CD4066BC
FIGURE Crosstalk Between Switches
FIGURE Crosstalk: Control Input Signal Output
FIGURE Maximum Control Input Frequency
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CD4066BC
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150" Narrow Body Package Number M14A
14-Lead Small Outline Package (SOP), EIAJ TYPE 5.3mm Wide Package Number M14D
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CD4066BC Quad Bilateral Switch
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL PRESIDENT FAIRCHILD SEMICONDUCTOR CORPORATION. used herein: critical component component life support Life support devices systems devices systems device system whose failure perform reawhich, intended surgical implant into sonably expected cause failure life support body, support sustain life, whose failure device system, affect safety effectiveness. perform when properly used accordance with instructions provided labeling, reasonably expected result significant injury www.fairchildsemi.com user.
Fairchild does assume responsibility circuitry described, circuit patent licenses implied Fairchild reserves right time without notice change said circuitry specifications.

November 1983 Revised December 1998 CD4066BC Quad Bilateral Switc

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