Literature Number: SPRS231D December 2003 Revised March 2005 This
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OMAP5912 Applications Processor
Literature Number: SPRS231D December 2003 Revised March 2005
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Revision History
REVISION HISTORY
This data sheet revision history highlights technical changes made SPRS231B generate SPRS231C. also highlights technical changes made SPRS231C generate SPRS231D; these changes marked "[Revision Revision History table below. Scope: Deleted "Ball Grid Array Mechanical Data" section. Mechanical drawings 289-terminal package 289-terminal package will appended this document automated process. Removed references Compact Camera Port (CCP), Specially Optimized Screen Interface (SoSSI), VLYNQ, Synchronous Serial Interconnect (SSI), Synchronous Serial Transmitter (SST), Synchronous Serial Receiver (SSR), Generic Distribute (GDD), CompactFlash Interface. Made extensive updates Timing Requirements tables Switching Characteristics tables. Changed operating temperature range from Ambient (TA) Case (TC). This document Production Data.
PAGE(S) ADDITIONS/CHANGES/DELETIONS Global: removed references Compact Camera Port (CCP) Specially Optimized Screen Interface (SoSSI) Synchronous Serial Interconnect (SSI) Synchronous Serial Transmitter (SST) Synchronous Serial Receiver (SSR) Generic Distribute (GDD) CompactFlash Interface VLYNQ changed SDRAM.DQMU SDRAM.DQMU changed SDRAM.DQML SDRAM.DQML changed operating temperature range from Ambient (TA) Case (TC) moved Section (Package Thermal Resistance Characteristics) Section removed Table 3-22. Specially Optimized Screen Interface (SoSSI) Registers removed Section 3.5.4, CompactFlash Controller (MPU Only) removed Section 3.6.2, Display Interface SoSSI removed Section 3.6.4, Compact Camera Port (CCP) removed Section 3.8.10, VLYNQ Interface removed Section 5.9, CompactFlash Interface Timings removed Section 5.15, VLYNQ Interface Timings removed Section 5.17, Compact Serial Camera Port (CCP) Timings removed Section 5.19, SoSSI Display Interface Timings Section OMAP5912 Features: removed "Specially Optimized Screen Interface (SoSSI)" feature removed "CompactFlash Controller" feature replaced "Compact Camera Port Interface Parallel CMOS Sensors" feature with "Camera Interface Parallel CMOS Sensors" feature removed "VLYNQ Interface (WLAN 802.11x)" feature "Low-Power, High-Performance CMOS Technology" feature: added "192-MHz Maximum Frequency" sub-feature changed "1.6-V Core Voltage" sub-feature "1.6 Core Voltage" changed "16-Bit EMIFS Access 256M Bytes Flash (for Burst, Programmable Flash)" "16-Bit EMIFS Supports 256M Bytes External Memory (i.e., Async. ROM/RAM, NOR/NAND Flash, Sync. Burst Flash)" changed "16-Bit EMIFF Access 128M Bytes SDRAM, Mobile SDRAM, Mobile DDR" feature "16-Bit EMIFF Access Bytes SDRAM, Mobile SDRAM, Mobile DDR" deleted "Digital Phase-Locked Loop (DPLL) MPU/DSP/TC Clocking Control" feature added "Endian Conversion Unit" feature
CompactFlash trademark CompactFlash Association.
December 2003 Revised March 2005
SPRS231D
Revision History
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ADDITIONS/CHANGES/DELETIONS Table 2-1, Package Terminal Assignments: deleted SoSSI function from signal names with following ball numbers: A13, A14, A15, A16, A17, B14, B15, B16, C12, C13, C15, C16, D12, D13, D14, D15, E11, E12, F10, F11, deleted function from signal names with following ball numbers: P12, deleted function from signal names with following ball numbers: P10, P11, deleted VLYNQ function from signal names with following ball numbers: D17, E16, E17, F13, F15, K13, K14, K16, L16, L17, R11, deleted function from signal names with following ball numbers: H15, J12, L13, L14, M16, M17, N17, deleted CompactFlash function from signal names with following ball numbers: added "Signal must tied low." footnote added footnote reference Ball (CONF) changed SDRAM.DQMU SDRAM.DQMU changed SDRAM.DQML SDRAM.DQML T15: changed signal name from "TDO/VLYNQ.TX0" "Reserved" U14: added "MCSI1.DIN_OUT(3)" signal name Table 2-2, Package Terminal Assignments: deleted SoSSI function from signal names with following ball numbers: A17, A20, B15, B17, B18, B19, B21, C15, C16, C17, C18, C19, C20, D15, D16, D17, D18, G13, G14, G20, deleted function from signal names with following ball numbers: P11, R11, V10, V11, V15, W10, deleted function from signal names with following ball numbers: W13, W14, Y12, deleted VLYNQ function from signal names with following ball numbers: E19, E20, F19, G18, H14, M20, N18, N19, N20, N21, AA15 deleted function from signal names with following ball numbers: J19, L15, M14, P11, P18, P19, P20, R11, R18, deleted CompactFlash function from signal names with following ball numbers: P11, R11, V10, W10, added "Signal must tied low." footnote added footnote reference Ball (CONF) Ball AA15: changed signal name from UART1.RTS(1) UART1.IRSHDN(2) VLYNQ.TX0(3) Z_STATE(6) GPIO39(7)" UART1.RTS(1) UART1.IRSHDN(2) Z_STATE(6) GPIO39(7)" D10: changed SDRAM.DQMU SDRAM.DQMU changed SDRAM.DQML SDRAM.DQML W16: added "MCSI1.DIN_OUT(3)" signal name AA19: changed signal name from "TDO/VLYNQ.TX0" "Reserved" Table 2-3, Package Terminal Characteristics: deleted SoSSI function from signal names with following ball numbers: A13, A14, A15, A16, A17, B14, B15, B16, C12, C13, C15, C16, D12, D13, D14, D15, E11, E12, F10, F11, deleted function from signal names with following ball numbers: P12, deleted function from signal names with following ball numbers: P10, P11, deleted VLYNQ function from signal names with following ball numbers: D17, E16, E17, F13, F15, K13, K14, K16, L16, L17, R11, deleted function from signal names with following ball numbers: H15, J12, L13, L14, M16, M17, N17, deleted CompactFlash function from signal names with following ball numbers: updated BUFFER STRENGTH column signals updated PULLUP/PULLDN column signals with following ball numbers: A13, A15, A16, A17, B14, B16, C12, C13, C15, C16, D12, D13, D14, E11, E12, changed SDRAM.DQMU SDRAM.DQMU changed SDRAM.DQML SDRAM.DQML T15: deleted "TDO VLYNQ.TX0" U14: added "MCSI1.DIN_OUT" signal name updated "PD20 20-µA internal pulldown, footnote
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December 2003 Revised March 2005
Revision History
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ADDITIONS/CHANGES/DELETIONS Table 2-4, Package Terminal Characteristics: deleted SoSSI function from signal names with following ball numbers: A17, A20, B15, B17, B18, B19, B21, C15, C16, C17, C18, C19, C20, D15, D16, D17, D18, G13, G14, G20, deleted function from signal names with following ball numbers: P11, R11, V10, V11, V15, W10, deleted function from signal names with following ball numbers: W13, W14, Y12, deleted VLYNQ function from signal names with following ball numbers: E19, E20, F19, G18, H14, M20, N18, N19, N20, N21, deleted function from signal names with following ball numbers: J19, L15, M14, P11, P18, P19, P20, R11, R18, deleted CompactFlash function from signal names with following ball numbers: P11, R11, V10, W10, updated BUFFER STRENGTH column signals updated PULLUP/PULLDN column signals with following ball numbers: A17, A20, B17, B19, B21, C16, C17, C18, C19, D15, D16, D17, D18, G13, G14, D10: changed SDRAM.DQMU SDRAM.DQMU changed SDRAM.DQML SDRAM.DQML W16: added "MCSI1.DIN_OUT" signal name AA19: deleted "TDO VLYNQ.TX0" updated "PD20 20-µA internal pulldown, footnote Table 2-5, Signal Descriptions: deleted signals SYNCHRONOUS SERIAL INTERCONNECT (SSI) section deleted signals COMPACT CAMERA PORT (CCP) INTERFACE section deleted signals VLYNQ INTERFACE section deleted signals SPECIALLY OPTIMIZED SCREEN INTERFACE (SoSSI) section deleted signals CompactFlash INTERFACE section updated DESCRIPTION column following signals: TRST (added WARNING) GPIO[63:48] GPIO[47:32] GPIO[31:16] GPIO[15:2] SYS_CLK_IN SYS_CLK_OUT OSC1_IN OSC1_OUT LOW_PWR LOW_POWER CONF EXTERNAL MEMORY INTERFACE FAST (EMIFF) SDRAM INTERFACE section: changed SDRAM.DQMU SDRAM.DQMU changed "Active-low" "Active-high" DESCRIPTION changed SDRAM.DQML SDRAM.DQML changed "Active-low" "Active-high" DESCRIPTION MULTIMEDIA CARD/SECURE DIGITAL INPUT/OUTPUT INTERFACES (MMC/SDIOs) section changed MMC.CMD/SPI.DO MMC.CMD; updated signal description changed MMC.DAT0/SPI.DI MMC.DAT0; updated signal description changed MMC2.CMD/SPI.DO MMC2.CMD; updated signal description changed MMC2.DAT0/SPI.DI MMC2.DAT0; updated signal description deleted SPI.CLK, SPI.RDY, SPI.CS1, SPI.CS2, SPI.CS3 MULTICHANNEL SERIAL INTERFACES (MCSIs) section added MCSI1.DIN_OUT JTAG/EMULATION INTERFACE section TDO: deleted ball numbers AA19 INTERRUPTS MISCELLANEOUS CONTROL CONFIGURATION PINS section BFAIL/EXT_FIQ: added reference OMAP5912 Multimedia Processor Power Management Reference Guide (literature number SPRU753) Updated Figure 3-1, OMAP5912 Functional Block Diagram Updated Section 3.1, Functional Block Diagram Features
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Revision History
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ADDITIONS/CHANGES/DELETIONS Updated Section 3.2.1, Global Memory Updated Table 3-1, OMAP5912 Global Memory Added Table 3-2, Chip-Select Mapping Table 3-4, LCDCONV Registers: changed ACCESS WIDTH from registers Updated Table 3-11, System Controller Registers Section 3.2.2.2, Public Peripheral Registers: deleted "Specially Optimized Screen Interface (SoSSI) Registers" from list public peripheral registers Updated Table 3-14, Client Registers Table 3-19, MMC/SDIO1 Registers: FFFB:7830: replaced MPU_MMC_SPI (MMC Configuration Register) with Reserved Updated Table 3-21, Host Registers Table 3-28, SPI1 Registers: added WORD ADDRESS column Table 3-30, General-Purpose Timer1 Registers: deleted GPTMR1_TCAR, GPTimer1 Capture Register Table 3-31, General-Purpose Timer2 Registers: deleted GPTMR2_TCAR, GPTimer2 Capture Register Table 3-32, General-Purpose Timer3 Registers: deleted GPTMR3_TCAR, GPTimer3 Capture Register Table 3-33, General-Purpose Timer4 Registers: deleted GPTMR4_TCAR, GPTimer4 Capture Register Table 3-34, General-Purpose Timer5 Registers: deleted GPTMR5_TCAR, GPTimer5 Capture Register Table 3-36, General-Purpose Timer6 Registers: deleted GPTMR6_TCAR, GPTimer6 Capture Register Table 3-37, General-Purpose Timer7 Registers: deleted GPTMR7_TCAR, GPTimer7 Capture Register Table 3-38, MMC/SDIO2 Registers: FFFB:7C30: replaced MMC2_SPI (MMC2 Configuration Register) with Reserved Table 3-43, General-Purpose Timer8 Registers: deleted GPTMR8_TCAR, GPTimer8 Capture Register Table 3-44, GPIO1 Registers: added WORD ADDRESS column Table 3-45, GPIO2 Registers: added WORD ADDRESS column Table 3-58, TIPB (Private) Bridge Configuration Registers: changed ACCESS WIDTH from registers
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Revision History
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ADDITIONS/CHANGES/DELETIONS Table 3-66, TIPB (Public) Bridge Configuration Registers: changed ACCESS WIDTH from registers Table 3-70, Controller Registers: 0x00 0C0Eh: changed REGISTER NAME DESCRIPTION 0x00 0C0Fh: changed REGISTER NAME DESCRIPTION Updated Table 3-75, Level Interrupt Handler Registers Table 3-76, Interrupt Interface Registers: 0x00 3800h: updated RESET VALUE 0x00 3801h: updated RESET VALUE Updated Table 3-79, EMIF Configuration Registers Updated Table 3-80, I-Cache Registers Updated Figure 3-3, Section 3.5, Private Peripherals: deleted "For instance, timers private peripheral accessible system controller." Updated Section 3.5.1, Timers Updated Section 3.5.4, Controller (MPU Only) Section 3.5.6: changed title from "Random Number Generator (RNG)" "Random Number Generator (RNG) (MPU Only)" updated section Section 3.5.7: changed title from "DES/3DES" "DES/3DES (MPU Only)" updated section Section 3.5.8: changed title from "SHA1/MD5" "SHA1/MD5 (MPU Only)" updated section Updated Section 3.6.2, Camera Interface Section 3.6.7, Keyboard Interface: changed "Keyboard composed specific MPUIOs dedicated keyboard connection:" "Keyboard composed specific MPUIOs dedicated keyboard connection:" Updated Section 3.6.9, Multimedia Card/Secure Digital (MMC/SDIO1) Interface Section 3.8.1: changed title from "Mailboxes" "Mailbox Registers" updated section Section 3.8.3, Serial Port Interface (SPI): updated master mode, provides paragraph Updated Section 3.8.7, Multimedia Card/Secure Digital (MMC/SDIO2) Interface Updated Section 3.11, Traffic Controller (Memory Interfaces) Section 3.12.2, Interface (MPUI): Four access modes: changed "Single-access mode (SAM)" "Shared-access mode (SAM)"
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Revision History
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ADDITIONS/CHANGES/DELETIONS Updated Section 4.1, Device Development-Support Tool Nomenclature Added Figure 4-1, Example Markings OMAP5912 Package Updated Section 5.1, Absolute Maximum Ratings Updated Section 5.2, Recommended Operating Conditions [Revision [Revision Section 5.3, Electrical Characteristics Over Recommended Operating Case Temperature Range (Unless Otherwise Noted): (High-level output voltage), Standard LVCMOS: changed TEST CONDITIONS (Low-level output voltage), Standard LVCMOS: changed TEST CONDITIONS (Low-level output voltage), I2C: changed TEST CONDITIONS from "Fast mode 6-mA load" "Fast mode 2-mA load" changed value from Fast mode 3-mA load: changed value from changed TEST CONDITIONS from "Standard mode 3-mA load" "Standard mode 2-mA load" (Input current), Input pins with 20-µA pulldowns enabled, Low-voltage range: changed value from (Input current), Input pins with 20-µA pulldowns enabled, High-voltage range: changed value from (Input current), Input pins with 100-µA pulldowns enabled, Low-voltage range: changed value from (Input current), Input pins with 100-µA pulldowns enabled, High-voltage range: changed value from (Input current), Input pins with 20-µA pullups enabled, Low-voltage range: changed value from (Input current), Input pins with 20-µA pullups enabled, High-voltage range: changed value from (Input current), Input pins with 100-µA pullups enabled, Low-voltage range: changed value from -170 -185 (Input current), Input pins with 100-µA pullups enabled, High-voltage range: changed value from -110 -185 Updated Figure 5-1, 3.3-V Test Load Circuit "Package Thermal Resistance Characteristics" section (was Section 5.4) been moved Section
Table 5-2, 32-kHz Input Clock Timing Requirements: CK1: changed symbol from "tcyc" "1/tcyc" CK5, Frequency stability: changed value from -250 changed value from added footnote about frequency stability requirement Section 5.5.2, Base Oscillator (12, 19.2 MHz) Input Clock: changed first sentence second paragraph from with maximum effective series resistance maximum." with maximum effective series resistance maximum power dissipation mW." added Table 5-4, 12-MHz 19.2-MHz Input Clock Timing Requirements added Figure 5-6, Input Clock Timings
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Revision History
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ADDITIONS/CHANGES/DELETIONS Section 5.7.1, EMIFS/NOR Flash Interface Timing: combined "EMIFS/Flash Interface Timing" section "EMIFS/Multiplexed Flash Interface Timings" section into this section (EMIFS/NOR Flash Interface Timing) updated Table 5-9, EMIFS/NOR Flash Interface Timing Requirements updated Table 5-10, EMIFS/NOR Flash Interface Switching Characteristics removed "EMIFS/Mux Flash Interface Timing Requirements" table removed "EMIFS/MUX Flash Interface Switching Characteristics" table updated/replaced/added timing diagrams Section 5.7.2, EMIFS/NAND Flash Timing: updated Table 5-11, EMIFS/NAND Flash Timing Requirements updated Table 5-12, EMIFS/NAND Flash Switching Characteristics updated timing diagrams Section 5.8, EMIFF/SDR SDRAM Interface Timing: updated Table 5-13, EMIFF/SDR SDRAM Interface Timing Requirements updated Table 5-14, EMIFF/SDR SDRAM Interface Switching Characteristics updated timing diagrams Section 5.9: changed title from "EMIFF/DDR SDRAM Interface Timing" "EMIFF/Mobile SDRAM Timing" Table 5-15: changed title from "EMIFF/DDR SDRAM Interface Timing Requirements" "EMIFF/Mobile SDRAM Timing Requirements" updated table Table 5-16: changed title from "EMIFF/DDR SDRAM Interface Switching Characteristics" "EMIFF/Mobile SDRAM Switching Characteristics" updated table renamed updated timing diagrams Section 5.10.1, McBSP Transmit Receive Timing: updated Table 5-17, McBSP Timing Requirements updated Table 5-18, McBSP Switching Characteristics updated timing diagrams Section 5.10.2, McBSP Master Slave Timing: updated Table 5-19, McBSP Master Slave Timing Requirements (CLKSTP 10b, CLKXP updated Table 5-20, McBSP Master Slave Switching Characteristics (CLKSTP 10b, CLKXP updated Table 5-21, McBSP Master Slave Timing Requirements (CLKSTP 11b, CLKXP updated Table 5-22, McBSP Master Slave Switching Characteristics (CLKSTP 11b, CLKXP updated Table 5-23, McBSP Master Slave Timing Requirements (CLKSTP 10b, CLKXP updated Table 5-24, McBSP Master Slave Switching Characteristics (CLKSTP 10b, CLKXP updated Table 5-25, McBSP Master Slave Timing Requirements (CLKSTP 11b, CLKXP updated Table 5-26, McBSP Master Slave Switching Characteristics (CLKSTP 11b, CLKXP updated timing diagrams Section 5.11, Multichannel Serial Interface (MCSI) Timing: updated Table 5-27, MCSI Timing Requirements updated Table 5-28, MCSI Switching Characteristics updated timing diagrams Section 5.12, Serial Port Interface (SPI) Timing: updated Table 5-29, Interface Timing Requirements updated Table 5-30, Interface Switching Characteristics updated Figure 5-42, Interface-Transmit Receive Master Slave Timing
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Revision History
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ADDITIONS/CHANGES/DELETIONS Section 5.13, Parallel Camera Interface Timing: updated Table 5-31, Camera Interface Timing Requirements; updated this table, footnote updated Figure 5-43, Camera Interface Timing Section 5.14, Controller LCDCONV Interfaces Timing: updated Table 5-32, Controller LCDCONV Switching Characteristics updated timing diagrams Section 5.15, Multimedia Card/Secure Digital (MMC/SD) Timing: updated Table 5-33, MMC/SD Timing Requirements updated Table 5-34, MMC/SD Switching Characteristics updated timing diagrams Section 5.18, MICROWIRE Interface Timing: updated Table 5-38, MICROWIRE Switching Characteristics Section 5.19, HDQ/1-Wire Interface Timing: updated Table 5-39, HDQ/1-Wire Timing Requirements updated Table 5-40, HDQ/1-Wire Switching Characteristics updated timing diagrams Section 5.20, Embedded Trace Macrocell (ETM) Interface Timing: updated Table 5-41, EInterface Switching Characteristics updated timing diagrams Section Glossary: removed CCP, GDD, MeSSI, SoSSI, SSI, SSR, Section Mechanical Data: deleted "Ball Grid Array Mechanical Data" section Mechanical drawings 289-terminal package 289-terminal package will appended this document automated process. Updated Section 7.1, Package Thermal Resistance Characteristics Table 7-1: changed title from "Thermal Resistance Characteristics" "OMAP5912 Thermal Resistance Characteristics (ZZG)" updated table Added Table 7-2, OMAP5912 Thermal Resistance Characteristics (ZDY) Added Section 7.2, Packaging Information
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Contents
Contents
Section OMAP5912 Features Page
Introduction Description 2.1.1 TMS320C55x Core 2.1.2 ARM926EJ-S RISC Processor Terminal Assignments Terminal Characteristics Multiplexing Signal Description
Functional Overview Functional Block Diagram Features Memory Maps 3.2.1 Global Memory 3.2.2 Subsystem Registers Memory Memory Maps 3.3.1 Global Memory 3.3.2 On-Chip Dual-Access (DARAM) 3.3.3 On-Chip Single-Access (SARAM) 3.3.4 Space Memory External Memory (Managed MMU) Private Peripherals 3.5.1 Timers 3.5.2 Watchdog Timer 3.5.3 Interrupt Handlers 3.5.4 Controller (MPU Only) 3.5.5 LCDCONV (MPU Only) 3.5.6 Random Number Generator (RNG) (MPU Only) 3.5.7 DES/3DES (MPU Only) 3.5.8 SHA1/MD5 (MPU Only) Public Peripherals 3.6.1 Interface 3.6.2 Camera Interface 3.6.3 MICROWIRE Serial Interface 3.6.4 Real-Time Clock (RTC) 3.6.5 Pulse-Width Tone (PWT) 3.6.6 Pulse-Width Light (PWL) 3.6.7 Keyboard Interface 3.6.8 HDQ/1-Wire Interface 3.6.9 Multimedia Card/Secure Digital (MMC/SDIO1) Interface 3.6.10 MPUIO Interface 3.6.11 Pulse Generators (LPG) 3.6.12 Frame Adjustment Counter (FAC) 3.6.13 Operating System (OS) Timer
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Contents
Section Public Peripherals 3.7.1 Multichannel Buffered Serial Ports (McBSP1 3.7.2 Multichannel Serial Interfaces (MCSI1 Shared Peripherals 3.8.1 Mailbox Registers 3.8.2 General-Purpose Timers 3.8.3 Serial Port Interface (SPI) 3.8.4 Universal Asynchronous Receiver/Transmitter (UART) 3.8.5 Master/Slave Interface 3.8.6 Multichannel Buffered Serial Port (McBSP2) 3.8.7 Multimedia Card/Secure Digital (MMC/SDIO2) Interface 3.8.8 General-Purpose (GPIO) 3.8.9 32-kHz Synchro Counter System Controller Controller Traffic Controller (Memory Interfaces) Interprocessor Communication 3.12.1 MPU/DSP Mailbox Registers 3.12.2 Interface (MPUI) 3.12.3 MPU/DSP Shared Memory Hardware Accelerators 3.13.1 DCT/iDCT Accelerator 3.13.2 Motion Estimation Accelerator 3.13.3 Pixel Interpolation Accelerator Power Supply Connection Examples 3.14.1 Core Voltage Supply Connections 3.14.2 Core Voltage Noise Isolation
Page
3.10 3.11 3.12
3.13
3.14
Documentation Support Device Development-Support Tool Nomenclature
Electrical Specifications Absolute Maximum Ratings Recommended Operating Conditions Electrical Characteristics Over Recommended Operating Case Temperature Range Timing Parameter Symbology Clock Specifications 5.5.1 32-kHz Oscillator Input Clock 5.5.2 Base Oscillator (12, 19.2 MHz) Input Clock Reset Timing 5.6.1 OMAP5912 Device Reset 5.6.2 OMAP5912 Core Reset External Memory Interface Timing 5.7.1 EMIFS/NOR Flash Interface Timing 5.7.2 EMIFS/NAND Flash Timing
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Contents
Section 5.10 EMIFF/SDR SDRAM Interface Timing EMIFF/Mobile SDRAM Timing Multichannel Buffered Serial Port (McBSP) Timing 5.10.1 McBSP Transmit Receive Timing 5.10.2 McBSP Master Slave Timing Multichannel Serial Interface (MCSI) Timing Serial Port Interface (SPI) Timing Parallel Camera Interface Timing Controller LCDCONV Interfaces Timing Multimedia Card/Secure Digital (MMC/SD) Timing Inter-Integrated Circuit (I2C) Timing Universal Serial (USB) Timing MICROWIRE Interface Timing HDQ/1-Wire Interface Timing Embedded Trace Macrocell (ETM) Interface Timing
Page
5.11 5.12 5.13 5.14 5.15 5.16 5.17 5.18 5.19 5.20
Glossary
Mechanical Data Package Thermal Resistance Characteristics Packaging Information
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SPRS231D
Figures
List Figures
Figure OMAP5912 289-Ball Plastic Ball Grid Array (Bottom View) OMAP5912 289-Ball Plastic Ball Grid Array (Bottom View) Page
OMAP5912 Functional Block Diagram Supply Connections Typical System External Circuits Noise Isolation
Example Markings OMAP5912 Package
5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23 5-24 5-25 5-26 5-27 5-28
3.3-V Test Load Circuit 32-kHz Oscillator External Crystal 32-kHz Oscillator External Crystal With PI-Network 32-kHz Input Clock Internal System Oscillator External Crystal Input Clock Timings Device Reset Timings Core Reset Timings EMIFS/NOR Flash-Single Word Asynchronous Read EMIFS/NOR Flash-Single Word Asynchronous Read, Full-Handshaking Mode Timing EMIFS/NOR Flash-Asynchronous 32-Bit Read Timing EMIFS/NOR Flash-Asynchronous Read, Page Mode 16-Bit Timing EMIFS/NOR Flash-Single Word Asynchronous Write Timing EMIFS/NOR Flash-Single Word Asynchronous Write, Full-Handshaking Mode EMIFS/NOR Flash-Synchronous Burst Read Timing (Retiming Off, Mode EMIFS/NOR Flash-Synchronous Burst Read Timing (Retiming Mode EMIFS/NOR Flash-Synchronous Burst Read Timing (Retiming Off, Mode EMIFS/Multiplexed Flash-Single Word Asynchronous Read Timing EMIFS/Multiplexed Flash-Single Word Asynchronous Write Timing EMIFS/Multiplexed Flash-Synchronous Burst Read Timing (Retiming Off) EMIFS/NAND Flash-Command Latch Timing EMIFS/NAND Flash-Address Latch Timing EMIFS/NAND Flash-Memory Write Timing EMIFS/NAND Flash-Memory Read Timing EMIFF/SDR SDRAM (Read) Commands (Active Row) EMIFF/SDR SDRAM (Write) Commands (Active Row) EMIFF/SDR SDRAM ACTV (Activate Row) Command EMIFF/SDR SDRAM DCAB (Precharge/Deactivate Row) Command
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Figures
Figure 5-29 5-30 5-31 5-32 5-33 5-34 5-35 5-36 5-37 5-38 5-39 5-40 5-41 5-42 5-43 5-44 5-45 5-46 5-47 5-48 5-49 5-50 5-51 5-52 5-53 5-54 5-55 5-56 5-57 5-58 5-59 5-60 5-61 EMIFF/SDR SDRAM REFR (Refresh) Command EMIFF/SDR SDRAM (Mode Register Set) Command EMIFF/Mobile SDRAM-Command Address Output Timing Definition EMIFF/Mobile SDRAM-Memory Read Timing EMIFF/Mobile SDRAM-Memory Write Timing McBSP Receive Timing McBSP Transmit Timing McBSP Timings Master Slave: CLKSTP 10b, CLKXP McBSP Timings Master Slave: CLKSTP 11b, CLKXP McBSP Timings Master Slave: CLKSTP 10b, CLKXP McBSP Timings Master Slave: CLKSTP 11b, CLKXP MCSI Master Mode Timing MCSI Slave Mode Timing Interface-Transmit Receive Master Slave Timing Camera Interface Timing Mode (LCD.HS/LCD.VS Falling LCD.Px Rising LCD.PCLK-PCD Mode (LCD.HS/LCD.VS Rising LCD.Px Falling LCD.PCLK-PCD MMC/SD Host Command Timing MMC/SD Card Response Timing MMC/SD Host Write Timing MMC/SD Host Read Card Status Timing Timings Integrated Transceiver Interface Timings MICROWIRE Timings Break (Reset) Timing Interface Reading From Slave Device Interface Writing Slave Device Typical Communication Between OMAP5912 Slave HDQ/1-Wire Break (Reset) Timing 1-Wire Interface Reading from 1-Wire Slave Device 1-Wire Interface Writing 1-Wire Slave Device Normal Mode-Half Rate Clock, Rising Falling Clock Edge Demultiplexed Mode Full Rate Clock-Rising Clock Edge
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Tables
List Tables
Table 3-10 3-11 3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-19 3-20 3-21 3-22 3-23 3-24 3-25 3-26 3-27 3-28 3-29 3-30 3-31 3-32 3-33 3-34 Package Terminal Assignments Package Terminal Assignments Package Terminal Characteristics Package Terminal Characteristics Signal Descriptions OMAP5912 Global Memory Chip-Select Mapping Level Interrupt Handler Registers LCDCONV Registers Controller Registers Timer1 Registers Timer2 Registers Timer3 Registers Watchdog Timer Registers Level Interrupt Handler Registers System Controller Registers On-the-Go (OTG) Registers MICROWIRE Registers Client Registers Real-Time Clock (RTC) Registers MPUIO (Keyboard) Registers Pulse Width Light (PWL) Registers Pulse Width Tone (PWT) Registers MMC/SDIO1 Registers Timer 32-kHz Registers Host Registers Frame Adjustment Counter (FAC) Registers HDQ/1-Wire Interface Registers Pulse Generator (LPG1) Registers Pulse Generator (LPG2) Registers UART1 Registers UART2 Registers SPI1 Registers McBSP2 Registers General-Purpose Timer1 Registers General-Purpose Timer2 Registers General-Purpose Timer3 Registers General-Purpose Timer4 Registers General-Purpose Timer5 Registers Page
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Tables
Table 3-35 3-36 3-37 3-38 3-39 3-40 3-41 3-42 3-43 3-44 3-45 3-46 3-47 3-48 3-49 3-50 3-51 3-52 3-53 3-54 3-55 3-56 3-57 3-58 3-59 3-60 3-61 3-62 3-63 3-64 3-65 3-66 3-67 3-68 3-69 3-70 3-71 3-72 3-73 3-74 3-75 3-76 I2C1 Registers General-Purpose Timer6 Registers General-Purpose Timer7 Registers MMC/SDIO2 Registers UART3 Registers GPIO3 Registers GPIO4 Registers 32-kHz Synchro Count Registers General-Purpose Timer8 Registers GPIO1 Registers GPIO2 Registers MPU/DSP Shared Mailbox Registers McBSP1 Registers MCSI1 Registers MCSI2 Registers McBSP3 Registers UART TIPB Switch Registers Ultra Low-Power Device Peripheral Registers OMAP5912 Configuration Registers Device Identification Registers Production Identification Registers Initiator Registers Interface (MPUI) Registers TIPB (Private) Bridge Configuration Registers Traffic Controller EMIFS Registers Traffic Controller OCP-T1/OCP-T2 Registers Traffic Controller OCPI Registers Traffic Controller EMIFF Registers Clock/Reset/Power Mode Control Registers DPLL1 Configuration Register Registers TIPB (Public) Bridge Configuration Registers Global Memory DARAM Blocks SARAM Blocks Controller Registers Timer1 Registers Timer2 Registers Timer3 Registers Watchdog Timer Registers Level Interrupt Handler Registers Interrupt Interface Registers
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Table 3-77 3-78 3-79 3-80 3-81 3-82 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23 5-24 5-25 5-26 5-27 5-28 5-29 5-30 5-31 5-32 5-33 5-34 5-35 Level Interrupt Handler Registers TIPB Bridge Configuration Registers EMIF Configuration Registers I-Cache Registers Clock Mode Registers TIPB Switch Registers 32-kHz Oscillator Switching Characteristics 32-kHz Input Clock Timing Requirements Base Oscillator Switching Characteristics 12-MHz 19.2-MHz Input Clock Timing Requirements OMAP5912 Device Reset Timing Requirements OMAP5912 Device Reset Switching Characteristics MPU_RST Timing Requirements MPU_RST Switching Characteristics EMIFS/NOR Flash Interface Timing Requirements EMIFS/NOR Flash Interface Switching Characteristics EMIFS/NAND Flash Timing Requirements EMIFS/NAND Flash Switching Characteristics EMIFF/SDR SDRAM Interface Timing Requirements EMIFF/SDR SDRAM Interface Switching Characteristics EMIFF/Mobile SDRAM Timing Requirements EMIFF/Mobile SDRAM Switching Characteristics McBSP Timing Requirements McBSP Switching Characteristics McBSP Master Slave Timing Requirements (CLKSTP 10b, CLKXP McBSP Master Slave Switching Characteristics (CLKSTP 10b, CLKXP McBSP Master Slave Timing Requirements (CLKSTP 11b, CLKXP McBSP Master Slave Switching Characteristics (CLKSTP 11b, CLKXP McBSP Master Slave Timing Requirements (CLKSTP 10b, CLKXP McBSP Master Slave Switching Characteristics (CLKSTP 10b, CLKXP McBSP Master Slave Timing Requirements (CLKSTP 11b, CLKXP McBSP Master Slave Switching Characteristics (CLKSTP 11b, CLKXP MCSI Timing Requirements MCSI Switching Characteristics Interface Timing Requirements Interface Switching Characteristics Camera Interface Timing Requirements Controller LCDCONV Switching Characteristics MMC/SD Timing Requirements MMC/SD Switching Characteristics Signals (I2C.SDA I2C.SCL) Switching Characteristics
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Tables
Table 5-36 5-37 5-38 5-39 5-40 5-41 Integrated Transceiver Interface Switching Characteristics MICROWIRE Timing Requirements MICROWIRE Switching Characteristics HDQ/1-Wire Timing Requirements HDQ/1-Wire Switching Characteristics EInterface Switching Characteristics OMAP5912 Thermal Resistance Characteristics (ZZG) OMAP5912 Thermal Resistance Characteristics (ZDY)
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Features
OMAP5912 Features
Low-Power, High-Performance CMOS
Technology 0.13-µm Technology 192-MHz Maximum Frequency Core Voltage ARM926EJ-S (MPU) Core Support 32-Bit 16-Bit (Thumb Mode) Instruction Sets 16K-Byte Instruction Cache 8K-Byte Data Cache Data Program Memory Management Unit (MMU) 17-Word Write Buffer 64-Entry Translation Look-Aside Buffers (TLBs) MMUs TMS320C55x (C55x) Core One/Two Instructions Executed Cycle Dual Multipliers (Two Multiply-Accumulates Cycle) Arithmetic/Logic Units Five Internal Data/Operand Buses Read Buses Write Buses) 16-Bit On-Chip Dual-Access (DARAM) (64K Bytes) 16-Bit On-Chip Single-Access (SARAM) (96K Bytes) Instruction Cache (24K Bytes) Video Hardware Accelerators DCT, iDCT, Pixel Interpolation, Motion Estimation Video Compression 250K Bytes Shared Internal SRAM Memory Traffic Controller (TC) 16-Bit EMIFS Supports 256M Bytes External Memory (i.e., Async. ROM/RAM, NOR/NAND Flash, Sync. Burst Flash) 16-Bit EMIFF Access Bytes SDRAM, Mobile SDRAM, Mobile Memory Management Unit Peripherals Three 32-Bit Timers Watchdog Timer Six-Channel Controller Multichannel Buffered Serial Ports Multichannel Serial Interfaces
Peripherals
Three 32-Bit Timers Watchdog Timer Host Client Controllers On-the-Go (OTG) Controller Ports, With Integrated Transceiver Camera Interface Parallel CMOS Sensors Real-Time Clock (RTC) Pulse-Width Tone (PWT) Interface Pulse-Width Light (PWL) Interface Keyboard Matrix Interface HDQ/1-Wire Interface Multimedia Card (MMC) Secure Digital (SD) Interface General-Purpose I/Os Pulse Generators (LPGs) ETM9 Trace Module ARM926EJ-S Debug 16-/18-Bit Controller With Dedicated System Channel 32-kHz Operating System (OS) Timer
Shared Peripherals
General-Purpose Timers Serial Port Interface (SPI) Three Universal Asynchronous Receiver/Transmitters (UARTs) (Two Supporting mode IrDA) Inter-Integrated Circuit (I2C) Master Slave Interface Multimedia Card (MMC) Secure Digital (SD) Interface Multichannel Buffered Serial Port Shared General-Purpose I/Os 32-kHz Synchro Counter Endian Conversion Unit Hardware Accelerators Cryptographic Functions Random Number Generation 3DES SHA-1 Individual Power-Saving Modes MPU/DSP/TC On-Chip Scan-Based Emulation Logic IEEE 1149.1 (JTAG) Boundary Scan Logic 289-Ball Lead-Free (Ball Grid Array) Packages (ZDY ZZG)
trademarks property their respective owners. IEEE Standard 1149.1-1990 Standard Test-Access Port Boundary Scan Architecture.
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Introduction
Introduction
This section describes main features OMAP5912 device, lists terminal assignments, describes function each terminal. This data manual also provides detailed description section, electrical specifications, parameter measurement information, mechanical data about available packaging.
Description
OMAP5912 highly integrated hardware software platform, designed meet application processing needs next-generation embedded devices. OMAP platform enables OEMs ODMs quickly bring market devices featuring rich user interfaces, high processing performance, long battery life through maximum flexibility fully integrated mixed processor solution. dual-core architecture provides benefits both reduced instruction computer (RISC) technologies, incorporating TMS320C55x core high-performance ARM926EJ-S core. OMAP5912 device designed leading open embedded RISC-based operating systems, well Texas Instruments (TI) DSP/BIOS software kernel foundation, available 289-ball lead-free ball grid array (BGA) packages (ZDY ZZG). OMAP5912 device targeted following applications: Applications Processing Devices Mobile Communications 802.11X Bluetooth GSM, GPRS, EDGE CDMA
Video Image Processing (MPEG4, JPEG, Windows Media Video, etc.) Advanced Speech Applications (text-to-speech, speech recognition) Audio Processing (MPEG-1 Audio Layer3 [MP3], AMR, WMA, AAC, Other Speech Codecs) Graphics Video Acceleration Generalized Access Data Processing
TMS320C55x, C55x, OMAP, DSP/BIOS trademarks Texas Instruments. ARM926EJ-S ETM9 trademarks Limited other countries. Thumb registered trademarks Limited other countries. 1-Wire registered trademark Dallas Semiconductor Corporation. Bluetooth trademark owned Bluetooth SIG, Inc. Windows registered trademark Microsoft Corporation United States and/or other countries.
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Introduction
2.1.1 TMS320C55x Core
core OMAP5912 device based TMS320C55x generation processor core. C55x architecture achieves high performance power through increased parallelism total focus reduction power dissipation. supports internal structure composed program bus, three data read buses, data write buses, additional buses dedicated peripheral activity. These buses provide ability perform three data reads data writes single cycle. parallel, controller perform data transfers cycle independent activity. C55x provides multiply-accumulate (MAC) units, each capable 17-bit 17-bit multiplication single cycle. central 40-bit arithmetic/logic unit (ALU) supported additional 16-bit ALU. ALUs under instruction control, providing ability optimize parallel activity power consumption. These resources managed address unit (AU) data unit (DU) C55x CPU. C55x DSPs support variable byte width instruction improved code density. instruction unit (IU) performs 32-bit program fetches from internal external memory queues instructions program unit (PU). program unit decodes instructions, directs tasks resources, manages fully protected pipeline. Predictive branching capability avoids pipeline flushes execution conditional instructions. OMAP5912 core also includes 24K-byte instruction cache minimize external memory accesses, improving data throughput conserving system power.
2.1.1.1
Tools Support
core supported industry's leading eXpressDSP software environment including Code Composer Studio Integrated Development Environment (IDE), DSP/BIOS software kernel foundation, TMS320 Algorithm Standard, industry's largest third-party network. Code Composer Studio features code generation tools including C-Compiler, Visual Linker, simulator, Real-Time Data Exchange (RTDX), XDS510 emulation device drivers, Chip Support Libraries (CSL). DSP/BIOS scalable real-time software foundation available cost users Texas Instruments' products, providing preemptive task scheduler real-time analysis capabilities with very memory megahertz overhead. TMS320 Algorithm Standard specification coding conventions allowing fast integration algorithms from different teams, sites, third parties into application framework. Texas Instruments' extensive third-party network over providers brings focused competencies complete solutions customers.
2.1.1.2
Software Support
Texas Instruments also developed foundation software available core. C55x Library (DSPLIB) features over C-callable software routines (FIR/IIR filters, Fast Fourier Transforms (FFTs), various computational functions). Image/Video Processing Library (IMGLIB) contains over software routines highly optimized C55x DSPs compiled with latest revision C55x code generation tools. These imaging functions support wide range applications that include compression, video processing, machine vision, medical imaging.
eXpressDSP, Code Composer Studio, TMS320, RTDX, XDS510 trademarks Texas Instruments.
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Introduction
2.1.2 ARM926EJ-S RISC Processor
core ARM926EJ-S reduced instruction computer (RISC) processor. ARM926EJ-S 32-bit processor core that performs 32-bit 16-bit instructions processes 32-bit, 16-bit, 8-bit data. core uses pipelining that parts processor memory system operate continuously. core incorporates: coprocessor (CP15) protection module Data program Memory Management Units (MMUs) with table look-aside buffers. Separate 16K-byte instruction 8K-byte data caches. Both four-way associative with virtual index virtual (VIVT).
OMAP5912 device uses ARM926EJ-S core little-endian mode only. minimize external memory access time, ARM926EJ-S includes instruction cache, data cache, write buffer. general, these transparent program execution.
Terminal Assignments
Figure illustrates ball locations 289-ball package Figure illustrates ball locations 289-ball package. Figure Figure used conjunction with Table Table 2-2, respectively, locate signal names ball grid numbers. ball numbers Table Table read from left-to-right, top-to-bottom.
Bottom View
Figure 2-1. OMAP5912 289-Ball Plastic Ball Grid Array (Bottom View)
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Introduction
Bottom View
Figure 2-2. OMAP5912 289-Ball Plastic Ball Grid Array (Bottom View) Table Table 2-2, signals with multiplexed functions highlighted gray. Signals within multiplexed name separated with forward slashes follows: signal1/signal2/signal3 (e.g., MPUIO1/RTCK/SPIF.SCK)
Signals which associated with specific peripherals denoted using peripheral name, followed period, then signal name; follows: peripheral1.signal1 (i.e., MCSI1.DOUT)
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Introduction
Table 2-1. Package Terminal Assignments
BALL SIGNAL SDRAM.A[1] SDRAM.D[3] CVDDDLL LCD.P[12](0)/ Z_STATE(1)/ GPIO33(7) LCD.P[0](0)/ Z_STATE(1) SDRAM.D[0] SDRAM.D[10] SDRAM.D[9] LCD.P[1](0)/ Z_STATE(1) SDRAM.A[3] SDRAM.DQML CVDD LCD.P[5](0)/ Z_STATE(1) FLASH.A[5](0) DVDD4 SDRAM.A[13] LCD.P[3](0)/ Z_STATE(1) FLASH.A[9](0) SDRAM.A[11] BALL SIGNAL SDRAM.DQSL SDRAM.CLKX SDRAM.A[7] LCD.PCLK(0)/ Z_STATE(1) DVDD5 SDRAM.D[1] SDRAM.D[12] SDRAM.CKE KB.C[2](0)/ GPIO61(7) SDRAM.BA[1] SDRAM.A[5] LCD.P[15](0)/ Z_STATE(1)/ GPIO2(7) LCD.P[2](0)/ Z_STATE(1) FLASH.A[1](0) DVDD4 DVDD4 LCD.HS(0)/ Z_STATE(1) FLASH.A[7](0) SDRAM.WE SDRAM.A[6] BALL SIGNAL SDRAM.D[6] SDRAM.CLK SDRAM.D[11] LCD.P[10](0)/ Z_STATE(1)/ GPIO31(7) SDRAM.A[0] SDRAM.D[5] SDRAM.D[15] LCD.P[11](0)/ Z_STATE(1)/ GPIO32(7) FLASH.A[6](0) SDRAM.BA[0] SDRAM.D[8] LCD.P[8](0)/ Z_STATE(1)/ GPIO29(7) KB.C[1](0)/ MPUIO6(1) SDRAM.RAS DVDD4 LCD.P[14](0)/ Z_STATE(1)/ GPIO35(7) KB.C[4](0)/ GPIO27(7) FLASH.A[4](0) SDRAM.CS LCD.P[13](0)/ Z_STATE(1)/ GPIO34(7) KB.C[3](0)/ GPIO63(6) FLASH.A[10](0) BALL SIGNAL SDRAM.D[2] SDRAM.DQMU SDRAM.DQSH LCD.P[6](0)/ Z_STATE(1) SDRAM.D[4] SDRAM.D[7] SDRAM.D[13] LCD.VS(0)/ Z_STATE(1) FLASH.A[2](0) SDRAM.A[8] SDRAM.D[14] DVDD1
FLASH.A[8](0) SDRAM.CAS SDRAM.A[4] LCD.P[7](0)/ Z_STATE(1) KB.R[3](0)/ MPUIO13(1) FLASH.A[3](0) SDRAM.A[12] LCD.P[4](0)/ Z_STATE(1) KB.R[2[(0)/ MPUIO10(1) FLASH.A[25]
KB.R[1](0)/ MPUIO9(1)
FLASH.A[11](0)
Z_STATE high-impedance "NC" denotes Connect". LOW_STATE Signal must tied low. NOTES: Shading denotes signals with multiplexed functions. number within parenthesis signal name denotes setting (see CTRL SETTING column Table Table 2-4).
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Introduction
Table 2-1. Package Terminal Assignments (Continued)
BALL SIGNAL FLASH.A[20] SDRAM.A[10] BALL SIGNAL FLASH.A[12](0) SDRAM.A[9] KB.R[4](0)/ MPUIO15(1) KB.C[5](0)/ GPIO28(7) FLASH.A[14](0) CVDD2 BALL SIGNAL LCD.AC(0)/ SYS_CLK_OUT(1)/ Z_STATE(2) KB.C[0](0)/ MPUIO0(1) DVDD5 FLASH.A[16](0) CVDD2 MCBSP1.CLKS(0)/ GPIO62(7) BALL SIGNAL SDRAM.A[2] LCD.P[9](0)/ Z_STATE(1)/ GPIO30(7) KB.R[0](0)/ MPUIO8(1) FLASH.A[15](0) FLASH.A[17] CVDD3 MCBSP1.DX(0)/ MCBSP1.FSX(1)/ MCBSP1.DXZ(2)/ GPIO52(7)
MCBSP1.CLKX(0)/ GPIO54(7) FLASH.A[13](0)
DVDD1
MCBSP1.FSX(0)/ MCBSP1.DX(1)/ MCBSP1.DXZ(2) GPIO53(7) FLASH.A[22] FLASH.ADV
CAM.LCLK(0)/ ETM.CLK(1)/ UWIRE.SCLK(2)/ GPIO39(7) FLASH.A[18] CVDD2
MCBSP1.DR(0)/ GPIO51(7) FLASH.A[19] CAM.EXCLK(0)/ ETM.SYNC[0](1)/ UWIRE.SDO(2)/ (6)/ GPIO57(7) CAM.D[7](0)/ ETM.D[7](1)/ UWIRE.CS0(2)/ MMC2.DAT2(3)/ GPIO35(7) FLASH.CS1(0)/ FLASH.CS1L(1)
LDO.FILTER
FLASH.A[21] CAM.D[3](0)/ ETM.D[3](1)/ UART3.RX(2)/ GPIO31(7) CAM.D[5](0)/ ETM.D[5](1)/ UWIRE.SDI(2)/ GPIO33(7)
CVDD3
MPU_BOOT(0)/ USB1.SUSP(2)
CAM.D[6](0)/ ETM.D[6](1)/ UWIRE.CS3(2)/ MMC2.CMD/ GPIO34(7) FLASH.A[23]
FLASH.BE[0](0)/ FLASH.CS2UOE(1)/ GPIO59(7) GPIO62(0)/ FLASH.CS0(1)
FLASH.A[24] FLASH.CS2(0)/ FLASH.BAA(1)/ FLASH.CS2L(2)
FLASH.CS3(0)/ GPIO3(7)
FLASH.D[3]
Z_STATE high-impedance "NC" denotes Connect". LOW_STATE Signal must tied low. NOTES: Shading denotes signals with multiplexed functions. number within parenthesis signal name denotes setting (see CTRL SETTING column Table Table 2-4).
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Table 2-1. Package Terminal Assignments (Continued)
BALL SIGNAL BALL SIGNAL BALL SIGNAL BALL SIGNAL CAM.HS(0)/ ETM.PSTAT[1](1)/ UART2.CTS(2)/ MMC2.DAT0/ GPIO38(7) CAM.D[1](0)/ ETM.D[1](1)/ UART3.RTS(2)/ GPIO29(7) FLASH.CS2U(0)/ GPIO5(1) FLASH.D[12] CVDD3 UART3.RX(0)/ PWL(1)/ UART2.RX(3)/ TIMER.PWM1(4)/ GPIO49(7)
CVDD3
CAM.D[4](0)/ ETM.D[4](1)/ UART3.TX(2)/ GPIO32(7)
CAM.VS(0)/ ETM.PSTAT[2](1)/ MPUIO14(2)/ MMC2.DAT1(3) CAM.D[0](0)/ ETM.D[0](1)/ MPUIO12(2)/ MMC2.DAT3(3) CAM.RSTZ(0)/ ETM.PSTAT[0](1)/ UART2.RTS(2)/ MMC2.CLK(3)/ GPIO37(7)
CAM.D[2](0)/ ETM.D[2](1)/ UART3.CTS(2)/ GPIO30(7) FLASH.CLK(0)/ FLASH.CS2UOE(1) CVDD GPIO11(0)/ HDQ(1)/ ETM.PSTAT[5](5)/ RTDX.D[3](7) UART3.TX(1)/ PWT(2)/ UART2.TX(4) TIMER.PWM0(5)/ GPIO50(7) FLASH.D[5] MCBSP2.DR(0)/ MCBSP2.DX(1)/ MCBSP2.DXZ(2)/ GPIO22(7) MPUIO2(0)/ EXT_DMA_REQ0(1)/ UWIRE.CS1(2)/ SPIF.CS1(6)
DVDD8
FLASH.BE[1](0)/ FLASH.CS2UWE(1)/ GPIO60(7) FLASH.D[6] GPIO14(0)/ KB.R[6](1)/ LCD.RED0(2)/ Z_STATE(3)
GPIO15(0)/ KB.R[7](1)/ TIMER.PWM2(2)
FLASH.D[0]
FLASH.D[2]
DVDD5
FLASH.D[8]
FLASH.RDY(0)/ GPIO10(1) BCLK(0)/ UART3.RTS(1)/ CAM.OUTCLK(6)/ GPIO17(7) GPIO6(0)/ MCBSP3.FSX(2)/ TIMER.EVENT3(3)/ MCSI1.DIN(4)/ TMS(5)
CVDDRTC
GPIO3(0)/ MCBSP3.FSX(2)/ LED1(3)/ ETM.PSTAT[3](5)/ RTDX.D[1](7)
Z_STATE high-impedance "NC" denotes Connect". LOW_STATE Signal must tied low. NOTES: Shading denotes signals with multiplexed functions. number within parenthesis signal name denotes setting (see CTRL SETTING column Table Table 2-4).
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Table 2-1. Package Terminal Assignments (Continued)
BALL SIGNAL GPIO7(0)/ MMC.DAT2(1)/ TCK(3)/ MCSI1.CLK(4)/ ETM.SYNC[1](5)/ RTDX.D[2](7) FLASH.D[4] BALL SIGNAL BALL SIGNAL BALL SIGNAL
GPIO12(0)/ MCBSP3.FSX(1)/ TIMER.EXTCLK(3)
GPIO13(0)/ KB.R[5](1)/ LCD.BLUE0(2)/ Z_STATE(3)
FLASH.D[1]
FLASH.D[11]
FLASH.D[10] MMC.CLK(0)/ GPIO57(7)
FLASH.OE UART1.CTS(0)/ UART1.IRSEL(2)/ GPIO38(7) DVDD9
CVDD I2C.SDA(0)/ GPIO48(7)
MPUIO4(0)/ EXT_DMA_REQ1(1)/ LED2(2)/ UWIRE.CS2(3)/ SPIF.CS2(4)/ MCBSP3.DR(6) FLASH.D[7]
GPIO1(0)/ UART3.RTS(1)
GPIO2(0)/ ETM.PSTAT[4](5)/ RTDX.D[0]
GPIO4(0)/ MCBSP3.FSX(2)/ TIMER.EVENT4(3)/ SPIF.DIN(4)
FLASH.D[9] MCBSP2.FSX(0)/ GPIO21(7) MCSI1.SYNC(0)/ MCBSP3.DR(1)/ USB1.VP(2)/ MCBSP3.FSX(4)
FLASH.RP(0)/ FLASH.CS2UWE(1) MMC.CMD/ GPIO55(7)
FLASH.D[15]
RTC_WAKE_INT(0)/ USB1.SE0(4)/ RST_HOST_OUT(5)/ GPIO55(7)
PWRON_RESET
EMU1
RST_OUT(0)/ GPIO41(7)
MPU_RST(0)/ MPUIO14(6)
MPUIO1(0)/ RTCK(1)/ SPIF.SCK(6)
MPUIO5(0)/ LOW_PWR(1)/ UART3.RTS(3)/ UART1.DTR(4)
GPIO0(0)/ USB.VBUS(2)/ SPIF.DOUT(3)/ MMC2.CLKIN(6) USB.PUEN(0)/ USB.CLKO(1)/ USB.PUDIS(3)/ Z_STATE(4)/ LOW_POWER(6)/ GPIO58(7)
FLASH.D[13]
OSC1_OUT
FLASH.WE
UART2.BCLK(0)/ SYS_CLK_IN(6)
UART2.CTS(0)/ USB2.RCV(1)/ GPIO7(2)/ USB0.RCV(5)
GPIO8(0)/ TRST(3)/ MCSI1.DOUT(4)/ MMC2.CMD
Z_STATE high-impedance "NC" denotes Connect". LOW_STATE Signal must tied low. NOTES: Shading denotes signals with multiplexed functions. number within parenthesis signal name denotes setting (see CTRL SETTING column Table Table 2-4).
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Table 2-1. Package Terminal Assignments (Continued)
BALL SIGNAL BALL SIGNAL BALL SIGNAL BALL SIGNAL MCSI1.DOUT(0)/ USB1.TXD(1)/ TDO(3)/ MCBSP3.DX(4)/ GPIO18(7)/ MCBSP3.DOUT_HIZ UWIRE.SCLK(0)/ KB.C[7](1)/ MPUIO1(2)/ UART3.CTS(4) OSC1_IN
MCSI2.CLK(0)/ USB2.SUSP(1)/ USB0.SUSP(5)/ MMC2.CLK(6)/ GPIO27(7) MCSI1.DIN(0)/ USB1.RCV(1)/ EMU1(3)/ MCBSP3.DR(4)/ GPIO56(7) I2C.SCL
MMC.DAT3(0)/ MPUIO9(1)/ MPUIO6(2)
RTC_ON_NOFF(0)
UWIRE.SDI(0)/ UART3.DSR(1)/ UART1.DSR(2)/ MCBSP3.DR(3)/ SPIF.DIN(6)/ GPIO47(7) FLASH.D[14]
CVDDA UART2.TX(1)/ USB2.TXD(2)/ USB0.TXD(5)/ Z_STATE(6)/ GPIO17(7) MMC.DAT0/ Z_STATE(1)/ GPIO58(7) BCLKREQ(0)/ UART3.CTS(1)/ MMC2.DAT2(6)/ GPIO40(7) Z_STATE(0)/ UWIRE.CS3(1)/ KB.C[6](2)/ SPIF.CS3(3)/ UART3.RX(4)/ Z_STATE(6)/ GPIO44(7)
FLASH.WP
MCBSP2.FSR(0)/ GPIO12(1)
MPUIO3(0)/ MMC2.DAT1(6)
MCSI2.DIN(0)/ USB2.VP(1)/ USB0.VP(5)/ GPIO26(7) UART1.RTS(1)/ UART1.IRSHDN(2)/ Z_STATE(6)/ GPIO39(7) UWIRE.SDO(0)/ UART3.DTR(1)/ UART1.DTR(2)/ MCBSP3.DX(3)/ UART3.RTS(4)/ MCBSP3.DXZ(5)/ SPIF.DOUT(6)/ GPIO46(7)
DVDDRTC
TRST
Z_STATE(0)/ UWIRE.CS0(1)/ MCBSP3.CLKX(2)/ UART3.TX(4)/ SPIF.CS0(6)/ GPIO45(7) UART2.RTS(1)/ USB2.SE0(2)/ MPUIO5(3)/ MPUIO12(4)/ USB0.SE0(5)/
FLASH.CS1U(0)/ GPIO16(7)
USB.DP(0)/ I2C.SDA(4) UART1.RX(5)/ USB.PUEN(7)
CVDD1
MCBSP2.DX(0)/ MCBSP2.DR(1)/ MCBSP2.DXZ(2)/ GPIO19(7)
Z_STATE high-impedance "NC" denotes Connect". LOW_STATE Signal must tied low. NOTES: Shading denotes signals with multiplexed functions. number within parenthesis signal name denotes setting (see CTRL SETTING column Table Table 2-4).
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Table 2-1. Package Terminal Assignments (Continued)
BALL SIGNAL BALL SIGNAL MCLKREQ(0)/ EXT_MASTER_REQ(1)/ UART2.RX(2)/ MMC2.DAT3(6)/ GPIO23(7) CLK32K_IN BALL SIGNAL MCSI2.DOUT(0)/ USB2.TXEN(1)/ USB0.TXEN(5)/ Z_STATE(6)/ GPIO25(7) UART1.TX(1)/ UART1.IRTX(2) BALL SIGNAL
DVDD3
MMC.DAT2(0)/ Z_STATE(1)/ MPUIO11(2)
DVDD6
DVDD7 BFAIL/EXT_FIQ(0)/ UART3.CTS(1)/ UART1.DSR(2)/ MMC.DATDIR1(6) UART2.RX(0)/ USB2.VM(1)/ USB0.VM(5)/ GPIO18(7) MCSI2.SYNC(0)/ GIOP7(1)/ USB2.SPEED(2)/ USB0.SPEED(5)/ MMC2.CMDDIR(6) CLK32K_OUT(0)/ MPUIO0(4)/ USB1.SPEED(5)/ UART1.TX(6)/ GPIO36(7)
RTCK
Reserved
CVDD
USB.DM(0)/ I2C.SCL(4)/ UART1.TX(5)/ Z_STATE(7)
DVDD2
MCLK(0)/ MMC2.DATDIR0(6)/ GPIO24(7) GPIO9(0)/ EMU0(3)/ MCSI1.SYNC(4)/ MMC2.DAT0
MCBSP2.CLKX(0)/ GPIO20(7)
MCBSP2.CLKR(0)/ GPIO11(1)
MMC.DAT1(0)/ MPUIO10(1)/ MPUIO7(2)
OSC32K_OUT
OSC32K_IN
UART1.RX(0)/ UART1.IRRX(2)/ GPIO37(7)
Z_STATE(0)/ MCBSP3.CLKX(1)/ USB1.TXEN(2)/ MCSI1.DIN_OUT(3)/ MCSI1.DIN(4)/ Z_STATE(6)/ GPIO42(7)
MCSI1.CLK(0)/ MCBSP3.DX(1)/ USB1.VM(2)/ TDI(3)/ MCBSP3.CLKX(4)/ GPIO43(7)
EMU0
Z_STATE high-impedance "NC" denotes Connect". LOW_STATE Signal must tied low. NOTES: Shading denotes signals with multiplexed functions. number within parenthesis signal name denotes setting (see CTRL SETTING column Table Table 2-4).
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Introduction
Table 2-2. Package Terminal Assignments
BALL SIGNAL SDRAM.A[3] DVDD4 CVDD SDRAM.CAS SDRAM.A[10] CVDD3 LCD.P[11](0)/ Z_STATE(1)/ GPIO32(7) LCD.P[1](0)/ Z_STATE(1) SDRAM.D[6] SDRAM.DQML SDRAM.D[15] LCD.P[14](0)/ Z_STATE(1)/ GPIO35(7) LCD.HS(0)/ Z_STATE(1) SDRAM.DQSL SDRAM.D[7] SDRAM.D[14] LCD.P[9](0)/ Z_STATE(1)/ GPIO30(7) KB.C[1](0)/ MPUIO6(1) FLASH.A[4](0) KB.R[3](0)/ MPUIO13(1) BALL SIGNAL SDRAM.A[0] CVDD2 LCD.P[13](0)/ Z_STATE(1)/ GPIO34(7) SDRAM.A[5] DVDD4 BALL SIGNAL CVDD2 CVDDDLL DVDD1 SDRAM.A[1] SDRAM.A[2] DVDD4 LCD.AC(0)/ SYS_CLK_OUT(1)/ Z_STATE(2) LCD.P[6](0)/ Z_STATE(1) DVDD5 SDRAM.D[1] SDRAM.D[8] SDRAM.DQSH LCD.P[7](0)/ Z_STATE(1) FLASH.A[5](0) SDRAM.D[0] SDRAM.DQMU SDRAM.D[9] BALL SIGNAL DVDD4 LCD.P[5](0)/ Z_STATE(1) SDRAM.BA[0] SDRAM.A[9]
LCD.VS(0)/ Z_STATE(1) FLASH.A[3](0) SDRAM.D[2] SDRAM.CLK SDRAM.D[11] LCD.P[10](0)/ Z_STATE(1)/ GPIO31(7) KB.C[4](0)/ GPIO27(7) SDRAM.D[4] SDRAM.CLKX SDRAM.D[13] LCD.P[8](0)/ Z_STATE(1)/ GPIO29(7) FLASH.A[25] DVDD1
CVDD3
SDRAM.BA[1] SDRAM.D[5] SDRAM.D[12] LCD.PCLK(0)/ Z_STATE(1) LCD.P[2](0)/ Z_STATE(1) FLASH.A[2](0) SDRAM.D[3] SDRAM.D[10] LCD.P[15](0)/ Z_STATE(1)/ GPIO2(7) KB.C[2](0)/ GPIO61(7) FLASH.A[7](0) KB.R[4](0)/ MPUIO15(1) FLASH.A[9](0)
LCD.P[0](0)/ Z_STATE(1) CVDD2 KB.C[3](0)/ GPIO63(6) FLASH.A[20]
Z_STATE high-impedance "NC" denotes Connect". LOW_STATE Signal must tied low. NOTES: Shading denotes signals with multiplexed functions. number within parenthesis signal name denotes setting (see CTRL SETTING column Table Table 2-4).
SPRS231D
December 2003 Revised March 2005
Introduction
Table 2-2. Package Terminal Assignments (Continued)
BALL SIGNAL BALL SIGNAL KB.C[0](0)/ MPUIO0(1) FLASH.A[12](0) SDRAM.A[8] LCD.P[12](0)/ Z_STATE(1)/ GPIO33(7) MCBSP1.CLKS(0)/ GPIO62(7) FLASH.A[14](0) SDRAM.A[11] KB.R[2[(0)/ MPUIO10(1) BALL SIGNAL KB.R[1](0)/ MPUIO9(1) FLASH.A[11](0) SDRAM.A[4] LCD.P[3](0)/ Z_STATE(1) MCBSP1.CLKX(0)/ GPIO54(7) SDRAM.RAS SDRAM.A[13] MCBSP1.FSX(0)/ MCBSP1.DX(1)/ MCBSP1.DXZ(2) GPIO53(7) BALL SIGNAL
FLASH.A[6](0) SDRAM.CS SDRAM.A[6] KB.C[5](0)/ GPIO28(7) FLASH.A[15](0) SDRAM.A[12] LCD.P[4](0)/ Z_STATE(1)
FLASH.A[10](0) SDRAM.A[7] KB.R[0](0)/ MPUIO8(1)
DVDD5 SDRAM.WE SDRAM.CKE MCBSP1.DX(0)/ MCBSP1.FSX(1)/ MCBSP1.DXZ(2)/ GPIO52(7)
CAM.EXCLK(0)/ ETM.SYNC[0](1)/ UWIRE.SDO(2)/ GPIO57(7) FLASH.A[19] CAM.D[5](0)/ ETM.D[5](1)/ UWIRE.SDI(2)/ GPIO33(7) MPU_BOOT(0)/ USB1.SUSP(2)
MCBSP1.DR(0)/ GPIO51(7)
LDO.FILTER
FLASH.A[17]
FLASH.A[18] CAM.LCLK(0)/ ETM.CLK(1)/ UWIRE.SCLK(2)/ GPIO39(7)
FLASH.A[8](0) CAM.D[7](0)/ ETM.D[7](1)/ UWIRE.CS0(2)/ MMC2.DAT2(3)/ GPIO35(7)
FLASH.A[1](0) CAM.D[6](0)/ ETM.D[6](1)/ UWIRE.CS3(2)/ MMC2.CMD/ GPIO34(7) FLASH.A[23] CAM.D[1](0)/ ETM.D[1](1)/ UART3.RTS(2)/ GPIO29(7)
CVDD3
FLASH.A[22]
FLASH.A[16](0)
FLASH.A[13](0)
CAM.D[2](0)/ ETM.D[2](1)/ UART3.CTS(2)/ GPIO30(7)
CAM.D[4](0)/ ETM.D[4](1)/ UART3.TX(2)/ GPIO32(7) FLASH.BE[0](0)/ FLASH.CS2UOE(1)/ GPIO59(7)
CAM.D[3](0)/ ETM.D[3](1)/ UART3.RX(2)/ GPIO31(7)
FLASH.ADV
FLASH.A[24]
Z_STATE high-impedance "NC" denotes Connect". LOW_STATE Signal must tied low. NOTES: Shading denotes signals with multiplexed functions. number within parenthesis signal name denotes setting (see CTRL SETTING column Table Table 2-4).
December 2003 Revised March 2005
SPRS231D
Introduction
Table 2-2. Package Terminal Assignments (Continued)
BALL SIGNAL BALL SIGNAL UART3.RX(0)/ PWL(1)/ UART2.RX(3)/ TIMER.PWM1(4)/ GPIO49(7) BALL SIGNAL CAM.HS(0)/ ETM.PSTAT[1](1)/ UART2.CTS(2)/ MMC2.DAT0/ GPIO38(7) BALL SIGNAL
FLASH.A[21]
CAM.VS(0)/ ETM.PSTAT[2](1)/ MPUIO14(2)/ MMC2.DAT1(3)
CAM.D[0](0)/ ETM.D[0](1)/ MPUIO12(2)/ MMC2.DAT3(3) FLASH.CS2(0)/ FLASH.BAA(1)/ FLASH.CS2L(2) GPIO7(0)/ MMC.DAT2(1)/ TCK(3)/ MCSI1.CLK(4)/ ETM.SYNC[1](5)/ RTDX.D[2](7)
DVDD8
CVDD
FLASH.CS1(0)/ FLASH.CS1L(1) GPIO2(0)/ ETM.PSTAT[4](5)/ RTDX.D[0]
GPIO62(0)/ FLASH.CS0(1) UART3.TX(1)/ PWT(2)/ UART2.TX(4) TIMER.PWM0(5)/ GPIO50(7) FLASH.D[1]
FLASH.BE[1](0)/ FLASH.CS2UWE(1)/ GPIO60(7) CAM.RSTZ(0)/ ETM.PSTAT[0](1)/ UART2.RTS(2)/ MMC2.CLK(3)/ GPIO37(7) FLASH.CLK(0)/ FLASH.CS2UOE(1) Z_STATE(0)/ UWIRE.CS0(1)/ MCBSP3.CLKX(2)/ UART3.TX(4)/ SPIF.CS0(6)/ GPIO45(7) GPIO11(0)/ HDQ(1)/ ETM.PSTAT[5](5)/ RTDX.D[3](7) FLASH.D[4] MCBSP2.DR(0)/ MCBSP2.DX(1)/ MCBSP2.DXZ(2)/ GPIO22(7)
GPIO15(0)/ KB.R[7](1)/ TIMER.PWM2(2)
FLASH.D[0]
FLASH.D[2]
FLASH.CS3(0)/ GPIO3(7)
MPUIO2(0)/ EXT_DMA_REQ0(1)/ UWIRE.CS1(2)/ SPIF.CS1(6) GPIO14(0)/ KB.R[6](1)/ LCD.RED0(2)/ Z_STATE(3) FLASH.D[5]
GPIO12(0)/ MCBSP3.FSX(1)/ TIMER.EXTCLK(3) FLASH.D[3]
GPIO13(0)/ KB.R[5](1)/ LCD.BLUE0(2)/ Z_STATE(3) FLASH.CS2U(0)/ GPIO5(1) USB.DP(0)/ I2C.SDA(4) UART1.RX(5)/ USB.PUEN(7)
FLASH.D[11]
MMC.CMD/ GPIO55(7)
Z_STATE high-impedance "NC" denotes Connect". LOW_STATE Signal must tied low. NOTES: Shading denotes signals with multiplexed functions. number within parenthesis signal name denotes setting (see CTRL SETTING column Table Table 2-4).
SPRS231D
December 2003 Revised March 2005
Introduction
Table 2-2. Package Terminal Assignments (Continued)
BALL SIGNAL BALL SIGNAL BALL SIGNAL BALL SIGNAL Z_STATE(0)/ UWIRE.CS3(1)/ KB.C[6](2)/ SPIF.CS3(3)/ UART3.RX(4)/ Z_STATE(6)/ GPIO44(7)
CLK32K_IN
MCSI1.CLK(0)/ MCBSP3.DX(1)/ USB1.VM(2)/ TDI(3)/ MCBSP3.CLKX(4)/ GPIO43(7) GPIO4(0)/ MCBSP3.FSX(2)/ TIMER.EVENT4(3)/ SPIF.DIN(4)
GPIO3(0)/ MCBSP3.FSX(2)/ LED1(3)/ ETM.PSTAT[3](5)/ RTDX.D[1](7)
GPIO6(0)/ MCBSP3.FSX(2)/ TIMER.EVENT3(3)/ MCSI1.DIN(4)/ TMS(5)
DVDD5
FLASH.D[6]
FLASH.D[7]
FLASH.D[8]
USB.DM(0)/ I2C.SCL(4)/ UART1.TX(5)/ Z_STATE(7)
UART2.RX(0)/ USB2.VM(1)/ USB0.VM(5)/ GPIO18(7) CLK32K_OUT(0)/ MPUIO0(4)/ USB1.SPEED(5)/ UART1.TX(6)/ GPIO36(7) CVDD3
MCLKREQ(0)/ EXT_MASTER_REQ(1)/ UART2.RX(2)/ MMC2.DAT3(6)/ GPIO23(7) UART1.CTS(0)/ UART1.IRSEL(2)/ GPIO38(7)
MMC.DAT0/ Z_STATE(1)/ GPIO58(7)
PWRON_RESET
GPIO0(0)/ USB.VBUS(2)/ SPIF.DOUT(3)/ MMC2.CLKIN(6) FLASH.D[9] MPUIO4(0)/ EXT_DMA_REQ1(1)/ LED2(2)/ UWIRE.CS2(3)/ SPIF.CS2(4)/ MCBSP3.DR(6) FLASH.D[13]
GPIO1(0)/ UART3.RTS(1)
FLASH.D[10] MPUIO5(0)/ LOW_PWR(1)/ UART3.RTS(3)/ UART1.DTR(4) FLASH.OE
FLASH.D[14]
I2C.SCL
FLASH.D[12] UWIRE.SDI(0)/ UART3.DSR(1)/ UART1.DSR(2)/ MCBSP3.DR(3)/ SPIF.DIN(6)/ GPIO47(7)
MPUIO1(0)/ RTCK(1)/ SPIF.SCK(6)
MPU_RST(0)/ MPUIO14(6)
DVDD9
Z_STATE high-impedance "NC" denotes Connect". LOW_STATE Signal must tied low. NOTES: Shading denotes signals with multiplexed functions. number within parenthesis signal name denotes setting (see CTRL SETTING column Table Table 2-4).
December 2003 Revised March 2005
SPRS231D
Introduction
Table 2-2. Package Terminal Assignments (Continued)
BALL SIGNAL BALL SIGNAL BALL SIGNAL BALL SIGNAL MCLK(0)/ MMC2.DATDIR0(6)/ GPIO24(7) MCSI2.SYNC(0)/ GIOP7(1)/ USB2.SPEED(2)/ USB0.SPEED(5)/ MMC2.CMDDIR(6)
FLASH.RDY(0)/ GPIO10(1) UART2.TX(1)/ USB2.TXD(2)/ USB0.TXD(5)/ Z_STATE(6)/ GPIO17(7) MMC.DAT1(0)/ MPUIO10(1)/ MPUIO7(2) UART1.RX(0)/ UART1.IRRX(2)/ GPIO37(7)
FLASH.D[15]
FLASH.WP
MCBSP2.CLKR(0)/ GPIO11(1)
MPUIO3(0)/ MMC2.DAT1(6)
MMC.CLK(0)/ GPIO57(7) MCSI1.DIN(0)/ USB1.RCV(1)/ EMU1(3)/ MCBSP3.DR(4)/ GPIO56(7) UWIRE.SCLK(0)/ KB.C[7](1)/ MPUIO1(2)/ UART3.CTS(4)
DVDDRTC
OSC32K_IN
EMU0
I2C.SDA(0)/ GPIO48(7)
FLASH.RP(0)/ FLASH.CS2UWE(1) UART2.RTS(1)/ USB2.SE0(2)/ MPUIO5(3)/ MPUIO12(4)/ USB0.SE0(5)/ MCSI2.DOUT(0)/ USB2.TXEN(1)/ USB0.TXEN(5)/ Z_STATE(6)/ GPIO25(7) RTC_WAKE_INT(0)/ USB1.SE0(4)/ RST_HOST_OUT(5)/ GPIO55(7)
FLASH.WE
OSC1_OUT
USB.PUEN(0)/ USB.CLKO(1)/ USB.PUDIS(3)/ Z_STATE(4)/ LOW_POWER(6)/ GPIO58(7) GPIO9(0)/ EMU0(3)/ MCSI1.SYNC(4)/ MMC2.DAT0
MCBSP2.FSR(0)/ GPIO12(1)
MCBSP2.FSX(0)/ GPIO21(7)
MMC.DAT2(0)/ Z_STATE(1)/ MPUIO11(2)
MMC.DAT3(0)/ MPUIO9(1)/ MPUIO6(2)
CVDDRTC
Z_STATE high-impedance "NC" denotes Connect". LOW_STATE Signal must tied low. NOTES: Shading denotes signals with multiplexed functions. number within parenthesis signal name denotes setting (see CTRL SETTING column Table Table 2-4).
SPRS231D
December 2003 Revised March 2005
Introduction
Table 2-2. Package Terminal Assignments (Continued)
BALL SIGNAL BALL SIGNAL BALL SIGNAL Z_STATE(0)/ MCBSP3.CLKX(1)/ USB1.TXEN(2)/ MCSI1.DIN_OUT(3)/ MCSI1.DIN(4)/ Z_STATE(6)/ GPIO42(7) BALL SIGNAL
MCSI1.DOUT(0)/ USB1.TXD(1)/ TDO(3)/ MCBSP3.DX(4)/ GPIO18(7)/ MCBSP3.DOUT_HIZ
BCLKREQ(0)/ UART3.CTS(1)/ MMC2.DAT2(6)/ GPIO40(7)
EMU1
BFAIL/EXT_FIQ(0)/ UART3.CTS(1)/ UART1.DSR(2)/ MMC.DATDIR1(6)
UWIRE.SDO(0)/ UART3.DTR(1)/ UART1.DTR(2)/ MCBSP3.DX(3)/ UART3.RTS(4)/ MCBSP3.DXZ(5)/ SPIF.DOUT(6)/ GPIO46(7) UART2.BCLK(0)/ SYS_CLK_IN(6) GPIO8(0)/ TRST(3)/ MCSI1.DOUT(4)/ MMC2.CMD
FLASH.CS1U(0)/ GPIO16(7) UART2.CTS(0)/ USB2.RCV(1)/ GPIO7(2)/ USB0.RCV(5)
OSC1_IN
MCBSP2.CLKX(0)/ GPIO20(7) MCSI2.CLK(0)/ USB2.SUSP(1)/ USB0.SUSP(5)/ MMC2.CLK(6)/ GPIO27(7) BCLK(0)/ UART3.RTS(1)/ CAM.OUTCLK(6)/ GPIO17(7)
DVDD3
CVDD
RTC_ON_NOFF(0)
UART1.TX(1)/ UART1.IRTX(2) TRST
DVDD7
RTCK
CVDD
CVDDA MCBSP2.DX(0)/ MCBSP2.DR(1)/ MCBSP2.DXZ(2)/ GPIO19(7)
DVDD2
CVDD1
MCSI2.DIN(0)/ USB2.VP(1)/ USB0.VP(5)/ GPIO26(7)
AA11
DVDD6
AA13
OSC32K_OUT
Z_STATE high-impedance "NC" denotes Connect". LOW_STATE Signal must tied low. NOTES: Shading denotes signals with multiplexed functions. number within parenthesis signal name denotes setting (see CTRL SETTING column Table Table 2-4).
December 2003 Revised March 2005
SPRS231D
Introduction
Table 2-2. Package Terminal Assignments (Continued)
BALL SIGNAL UART1.RTS(1)/ UART1.IRSHDN(2)/ Z_STATE(6)/ GPIO39(7) BALL SIGNAL BALL SIGNAL BALL SIGNAL
AA15
AA17
MCSI1.SYNC(0)/ MCBSP3.DR(1)/ USB1.VP(2)/ MCBSP3.FSX(4)
AA19
Reserved
AA20
RST_OUT(0)/ GPIO41(7)
AA21
Z_STATE high-impedance "NC" denotes Connect". LOW_STATE Signal must tied low. NOTES: Shading denotes signals with multiplexed functions. number within parenthesis signal name denotes setting (see CTRL SETTING column Table Table 2-4).
SPRS231D
December 2003 Revised March 2005
Introduction
Terminal Characteristics Multiplexing
Table describes terminal characteristics signals multiplexed each ball package. Table describes terminal characteristics signals multiplexed each ball package. table column headers explained below: BALL NO.: package ball number. SIGNAL NAME: names signals that multiplexed each ball. TYPE: signal direction. CTRL SETTING: Shows control multiplexing modes. PULLUP/PULLDN: Denotes presence internal pullup pulldown. Pullups pulldowns enabled disabled software. BUFFER STRENGTH: Drive strength associated output buffer. OTHER: Contains various terminal information, such buffer type, boundary scan capability, gating/inhibit functionality. RESET STATE: state terminal reset. SUPPLY: voltage supply which powers terminal's buffers. NOTE: Care must taken avoid assigning multiple balls same signal. Violations cause unexpected results. Table 2-3. Package Terminal Characteristics
BALL
SIGNAL NAME SDRAM.CS SDRAM.DQSH SDRAM.DQSL SDRAM.CAS SDRAM.RAS SDRAM.DQML SDRAM.DQMU
TYPE
CTRL SETTING
PULLUP/ PULLDN
BUFFER (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv)
RESET STATE#
SUPPLY DVDD4 DVDD4 DVDD4 DVDD4 DVDD4 DVDD4 DVDD4
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup. Pullup pulldown enabled disabled software. voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
December 2003 Revised March 2005
SPRS231D
Introduction
Table 2-3. Package Terminal Characteristics (Continued)
BALL SDRAM.CLK SDRAM.CLKX SDRAM.CKE LCD.AC SYS_CLK_OUT Z_STATE
SIGNAL NAME SDRAM.WE SDRAM.A[13:0]
TYPE
CTRL SETTING
PULLUP/ PULLDN
BUFFER (Lv) (Hv) (Lv) (Hv)
RESET STATE#
SUPPLY DVDD4 DVDD4
SDRAM.BA[1:0] SDRAM.D[15:0]
(Lv) (Hv) (Lv) (Hv)
DVDD4 DVDD4
RegD[11:9] RegD[11:9] RegD[11:9] RegD[17:15] RegD[17:15]
(Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv)
DVDD4 DVDD4 DVDD4 DVDD1
LCD.PCLK Z_STATE
(Lv) (Hv)
DVDD1
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup. Pullup pulldown enabled disabled software. voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
SPRS231D
December 2003 Revised March 2005
Introduction
Table 2-3. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME LCD.P[15] Z_STATE GPIO2 LCD.P[14] Z_STATE GPIO35 LCD.P[13] Z_STATE GPIO34 LCD.P[12] Z_STATE GPIO33 LCD.P[11] Z_STATE GPIO32 LCD.P[10] Z_STATE GPIO31 LCD.P[9] Z_STATE GPIO30 LCD.VS Z_STATE LCD.P[8] Z_STATE GPIO29
TYPE
CTRL SETTING RegD[20:18] RegD[20:18] RegD[20:18] RegD[23:21] RegD[23:21] RegD[23:21] RegD[26:24] RegD[26:24] RegD[26:24] RegD[29:27] RegD[29:27] RegD[29:27] RegE[2:0] RegE[2:0] RegE[2:0] RegE[5:3] RegE[5:3] RegE[5:3] RegE[8:6] RegE[8:6] RegE[8:6] RegE[11:9] RegE[11:9] RegE[14:12] RegE[14:12] RegE[14:12] RegE[17:15] RegE[17:15] RegE[20:18] RegE[20:18] RegE[23:21] RegE[23:21]
PULLUP/ PULLDN
BUFFER (Lv) (Hv)
RESET STATE#
SUPPLY DVDD1
(Lv) (Hv)
DVDD1
(Lv) (Hv)
DVDD1
(Lv) (Hv)
DVDD1
(Lv) (Hv)
DVDD1
(Lv) (Hv)
DVDD1
(Lv) (Hv)
DVDD1
(Lv) (Hv) (Lv) (Hv)
DVDD1 DVDD1
LCD.P[7] Z_STATE LCD.P[6] Z_STATE LCD.P[5] Z_STATE
(Lv) (Hv) (Lv) (Hv) (Lv) (Hv)
DVDD1 DVDD1 DVDD1
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup. Pullup pulldown enabled disabled software. voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
December 2003 Revised March 2005
SPRS231D
Introduction
Table 2-3. Package Terminal Characteristics (Continued)
BALL
SIGNAL NAME LCD.P[4] Z_STATE LCD.P[3] Z_STATE LCD.P[2] Z_STATE LCD.P[1] Z_STATE LCD.P[0] Z_STATE LCD.HS Z_STATE KB.C[4] GPIO27 KB.C[3] GPIO63 KB.C[2] GPIO61 KB.C[1] MPUIO6 KB.C[0] MPUIO0 KB.R[4] MPUIO15 KB.R[3] MPUIO13 KB.R[2] MPUIO10 KB.R[1] MPUIO9 KB.R[0] MPUIO8
TYPE
CTRL SETTING RegE[26:24] RegE[26:24] RegE[29:27] RegE[29:27] RegF[2:0] RegF[2:0] RegF[5:3] RegF[5:3] RegF[8:6] RegF[8:6] RegD[14:12] RegD[14:12] Reg3[5:3] Reg3[5:3] Reg3[8:6] Reg3[8:6] Reg3[11:9] Reg3[11:9] Reg3[14:12] Reg3[14:12] Reg3[17:15] Reg3[17:15] Reg3[20:18] Reg3[20:18] Reg3[23:21] Reg3[23:21] Reg3[26:24] Reg3[26:24] Reg3[29:27] Reg3[29:27] Reg4[2:0] Reg4[2:0]
PULLUP/ PULLDN
BUFFER (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv)
RESET STATE#
SUPPLY DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 DVDD1
PU20, PD20 PU20, PD20 PU20, PD20 PU20, PD20 PU20, PD20 PU100, PD20 PU100, PD20 PU100, PD20 PU100, PD20 PU100, PD20
(Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv)
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup. Pullup pulldown enabled disabled software. voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
SPRS231D
December 2003 Revised March 2005
Introduction
Table 2-3. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME KB.C[5] GPIO28 MCBSP1.CLKS GPIO62 MCBSP1.CLKX GPIO54 MCBSP1.FSX MCBSP1.DX MCBSP1.DXZ GPIO53 MCBSP1.DX MCBSP1.ESX MCBSP1.DXZ GPIO52 MCBSP1.DR GPIO51 CAM.EXCLK ETM.SYNC[0] UWIRE.SDO LOW_STATE GPIO57 CAM.LCLK ETM.CLK UWIRE.SCLK GPIO39 MPU_BOOT USB1.SUSP CAM.D[7] ETM.D[7] UWIRE.CS0 MMC2.DAT2 GPIO35
TYPE
CTRL SETTING Reg3[2:0] Reg3[2:0] Reg4[8:6] Reg4[8:6] Reg4[11:9] Reg4[11:9] Reg4[14:12] Reg4[14:12] Reg4[14:12] Reg4[14:12] Reg4[17:15] Reg4[17:15] Reg4[17:15] Reg4[17:15] Reg4[20:18] Reg4[20:18] Reg4[23:21] Reg4[23:21] Reg4[23:21] Reg4[23:21] Reg4[23:21] Reg4[26:24] Reg4[26:24] Reg4[26:24] Reg4[26:24] Reg8[29:27] Reg8[29:27] Reg4[29:27] Reg4[29:27] Reg4[29:27] Reg4[29:27] Reg4[29:27]
PULLUP/ PULLDN PU20, PD20 PU20, PD20 PU20, PD20 PU20, PD20
BUFFER (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv)
RESET STATE#
SUPPLY DVDD1 DVDD1 DVDD1 DVDD1
PU20, PD20
(Lv) (Hv)
DVDD1
PU20, PD20 PU20, PD20
(Lv) (Hv) (Lv) (Hv)
DVDD1 DVDD8
PU20, PD20
(Lv) (Hv)
DVDD8
(Lv) (Hv) PU20, PD20 (Lv) (Hv)
DVDD8
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup. Pullup pulldown enabled disabled software. voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
December 2003 Revised March 2005
SPRS231D
Introduction
Table 2-3. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME CAM.D[6] ETM.D[6] UWIRE.CS3 MMC2.CMD GPIO34 CAM.D[5] ETM.D[5] UWIRE.SDI GPIO33 CAM.D[4] ETM.D[4] UART3.TX GPIO32 CAM.D[3] ETM.D[3] UART3.RX GPIO31 CAM.D[2] ETM.D[2] UART3.CTS GPIO30 CAM.D[1] ETM.D[1] UART3.RTS GPIO29 CAM.D[0] ETM.D[0] MPUIO12 MMC2.DAT3
TYPE
CTRL SETTING Reg5[2:0] Reg5[2:0] Reg5[2:0] Reg5[2:0] Reg5[2:0] Reg5[5:3] Reg5[5:3] Reg5[5:3] Reg5[5:3] Reg5[8:6] Reg5[8:6] Reg5[8:6] Reg5[8:6] Reg5[11:9] Reg5[11:9] Reg5[11:9] Reg5[11:9] Reg5[14:12] Reg5[14:12] Reg5[14:12] Reg5[14:12] Reg5[17:15] Reg5[17:15] Reg5[17:15] Reg5[17:15] Reg5[20:18] Reg5[20:18] Reg5[20:18] Reg5[20:18]
PULLUP/ PULLDN PU20, PD20
BUFFER (Lv) (Hv)
RESET STATE#
SUPPLY DVDD8
PU20, PD20
(Lv) (Hv)
DVDD8
PU20, PD20
(Lv) (Hv)
DVDD8
PU20, PD20
(Lv) (Hv)
DVDD8
PU20, PD20
(Lv) (Hv)
DVDD8
PU20, PD20
(Lv) (Hv)
DVDD8
PU20, PD20
(Lv) (Hv)
DVDD8
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup. Pullup pulldown enabled disabled software. voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset Terminal 3-stated BFAIL input input/output buffers Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
SPRS231D
December 2003 Revised March 2005
Introduction
Table 2-3. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME CAM.VS ETM.PSTAT[2] MPUIO14 MMC2.DAT1 CAM.HS ETM.PSTAT[1] UART2.CTS MMC2.DAT0 GPIO38 CAM.RSTZ ETM.PSTAT[0] UART2.RTS MMC2.CLK LOW_STATE GPIO37 LOW_STATE UART3.TX UART2.TX TIMER.PWM0 GPIO50 UART3.RX UART2.RX TIMER.PWM1 GPIO49 GPIO15 KB.R[7] TIMER.PWM2
TYPE
CTRL SETTING Reg5[23:21] Reg5[23:21] Reg5[23:21] Reg5[23:21] Reg5[26:24] Reg5[26:24] Reg5[26:24] Reg5[26:24] Reg5[26:24] Reg5[29:27] Reg5[29:27] Reg5[29:27] Reg5[29:27] Reg5[29:27] Reg5[29:27] Reg6[2:0] Reg6[2:0] Reg6[2:0] Reg6[2:0] Reg6[2:0] Reg6[2:0] Reg6[5:3] Reg6[5:3] Reg6[5:3] Reg6[5:3] Reg6[5:3] Reg6[8:6] Reg6[8:6] Reg6[8:6]
PULLUP/ PULLDN PU20, PD20
BUFFER (Lv) (Hv)
RESET STATE#
SUPPLY DVDD8
PU20, PD20
(Lv) (Hv)
DVDD8
PU20, PD20
(Lv) (Hv)
DVDD8
PU20, PD20
(Lv) (Hv)
DVDD9
PU20, PD20
(Lv) (Hv)
DVDD9
PU100, PD20
(Lv) (Hv)
DVDD9
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup. Pullup pulldown enabled disabled software. voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset Terminal 3-stated BFAIL input input/output buffers Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
December 2003 Revised March 2005
SPRS231D
Introduction
Table 2-3. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME GPIO14 KB.R[6] LCD.RED0 Z_STATE GPIO13 KB.R[5] LCD.BLUE0 Z_STATE GPIO12 MCBSP3.FSX TIMER.EXTCLK GPIO11 ETM.PSTAT[5] GPIO7 MMC.DAT2 MCSI1.CLK ETM.SYNC[1] GPIO6 MCBSP3.ESX TIMER.EVENT3 MCSI1.DIN GPIO4 MCBSP3.FSX TIMER.EVENT4 GPIO3 MCBSP3.FSX LED1 ETM.PSTAT[3]
TYPE
CTRL SETTING Reg6[11:9] Reg6[11:9] Reg6[11:9] Reg6[11:9] Reg6[14:12] Reg6[14:12] Reg6[14:12] Reg6[14:12] Reg6[17:15] Reg6[17:15] Reg6[17:15] Reg6[20:18] Reg6[20:18] Reg6[20:18] Reg6[23:21] Reg6[23:21] Reg6[23:21] Reg6[23:21] Reg6[23:21] Reg6[26:24] Reg6[26:24] Reg6[26:24] Reg6[26:24] Reg6[26:24] Reg6[29:27] Reg6[29:27] Reg6[29:27] Reg7[2:0] Reg7[2:0] Reg7[2:0] Reg7[2:0]
PULLUP/ PULLDN PU100, PD20
BUFFER (Lv) (Hv)
RESET STATE#
SUPPLY DVDD9
PU100, PD20
(Lv) (Hv)
DVDD9
PU20, PD20
(Lv) (Hv)
DVDD9
PU20, PD20
(Lv) (Hv)
DVDD9
PU20, PD20
(Lv) (Hv)
DVDD9
PD100, PU20
(Lv) (Hv)
DVDD9
PD100, PU20
(Lv) (Hv)
DVDD9
PU100, PD20
(Lv) (Hv)
DVDD9
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup. Pullup pulldown enabled disabled software. voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
SPRS231D
December 2003 Revised March 2005
Introduction
Table 2-3. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME GPIO2 ETM.PSTAT[4] GPIO1 UART3.RTS GPIO0 USB.VBUS SPIF.DOUT MMC2.CLKIN MPUIO5 LOW_PWR UART3.RTS UART1.DTR MPUIO4 EXT_DMA_REQ1 LED2 UWIRE.CS2 SPIF.CS2 MCBSP3.DR MPUIO2 EXT_DMA_REQ0 UWIRE.CS1 SPIF.CS1 MPU_RST MPUIO14 MPUIO1 RTCK SPIF.SCK
TYPE I/O/Z I/O/Z
CTRL SETTING Reg7[5:3] Reg7[5:3] Reg7[8:6] Reg7[8:6] Reg7[11:9] Reg7[11:9] Reg7[11:9] Reg7[11:9] Reg7[14:12] Reg7[14:12] Reg7[14:12] Reg7[14:12] Reg7[17:15] Reg7[17:15] Reg7[17:15] Reg7[17:15] Reg7[17:15] Reg7[17:15] Reg7[20:18] Reg7[20:18] Reg7[20:18] Reg7[20:18] Reg9[8:6] Reg9[8:6] Reg7[23:21] Reg7[23:21] Reg7[23:21] Reg7[26:24] Reg7[29:27] Reg7[29:27]
PULLUP/ PULLDN PU100, PD20 PU100, PD20 PU20, PD20
BUFFER (Lv) (Hv) (Lv) (Hv) (Lv) (Hv)
RESET STATE#
SUPPLY DVDD9 DVDD9
DVDD9
PU20, PD20
(Lv) (Hv)
DVDD9
PU20, PD20
(Lv) (Hv)
DVDD9
PU100, PD20
(Lv) (Hv)
DVDD9
(Lv) (Hv) PU100, PD20 (Lv) (Hv)
DVDD9 DVDD9
I2C.SCL I2C.SDA GPIO48
(Lv) (Hv) (Lv) (Hv)
DVDD9 DVDD9
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup. Pullup pulldown enabled disabled software. voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
December 2003 Revised March 2005
SPRS231D
Introduction
Table 2-3. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME UWIRE.SDI UART3.DSR UART1.DSR MCBSP3.DR SPIF.DIN GPIO47 UWIRE.SDO UART3.DTR UART1.DTR MCBSP3.DX UART3.RTS MCBSP3.DXZ SPIF.DOUT GPIO46 UWIRE.SCLK KB.C[7] MPUIO1 UART3.CTS Z_STATE UWIRE.CS0 MCBSP3.CLKX UART3.TX SPIF.CS0 GPIO45 Z_STATE UWIRE.CS3 KB.C[6] SPIF.CS3 UART3.RX Z_STATE GPIO44
TYPE
CTRL SETTING Reg8[2:0] Reg8[2:0] Reg8[2:0] Reg8[2:0] Reg8[2:0] Reg8[2:0] Reg8[5:3] Reg8[5:3] Reg8[5:3] Reg8[5:3] Reg8[5:3] Reg8[5:3] Reg8[5:3] Reg8[5:3] Reg8[8:6] Reg8[8:6] Reg8[8:6] Reg8[8:6] Reg8[11:9] Reg8[11:9] Reg8[11:9] Reg8[11:9] Reg8[11:9] Reg8[11:9] Reg8[14:12] Reg8[14:12] Reg8[14:12] Reg8[14:12] Reg8[14:12] Reg8[14:12] Reg8[14:12]
PULLUP/ PULLDN PU20, PD20
BUFFER (Lv) (Hv)
RESET STATE#
SUPPLY DVDD9
PU20, PD20
(Lv) (Hv)
DVDD9
PU20, PD20
(Lv) (Hv)
DVDD9
PU100, PD20
(Lv) (Hv)
DVDD9
PU20, PD20
(Lv) (Hv)
DVDD9
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup. Pullup pulldown enabled disabled software. voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
SPRS231D
December 2003 Revised March 2005
Introduction
Table 2-3. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME BFAIL/EXT_FIQ UART3.CTS UART1.DSR MMC2.DATDIR1 RST_OUT GPIO41 CONF TRST EMU0 EMU1 RTCK MCSI1.SYNC MCBSP3.DR USB1.VP MCBSP3.FSX MCSI1.CLK MCBSP3.DX USB1.VM MCBSP3.CLKX GPIO43
TYPE
CTRL SETTING Reg8[17:15] Reg8[17:15] Reg8[17:15] Reg8[17:15] Reg9[11:9] Reg9[11:9] RegA[5:3] RegA[5:3] RegA[5:3] RegA[5:3] RegA[8:6] RegA[5:3] RegA[5:3] RegA[5:3] RegA[5:3] RegA[5:3]
PULLUP/ PULLDN PU20, PD20
BUFFER (Lv) (Hv)
RESET STATE#
SUPPLY DVDD9
PU20, PD20 PU20, PD20 PD100, PU20 PD100, PU20 PD100, PU20 PU20, PD20 PU100, PD20 PU100, PD20
(Lv) (Hv)
Input Input
DVDD9 DVDD9 DVDD9 DVDD9 DVDD9 DVDD9 DVDD9 DVDD9 DVDD9 DVDD7
(Lv) (Hv) (Lv) (Hv) (Lv) (Hv)
PU20, PD20
(Lv) (Hv)
PU20, PD20
(Lv) (Hv)
DVDD7
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup. Pullup pulldown enabled disabled software. voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
December 2003 Revised March 2005
SPRS231D
Introduction
Table 2-3. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME Z_STATE MCBSP3.CLKX USB1.TXEN MCSI1.DIN_OUT MCSI1.DIN Z_STATE GPIO42 MCSI1.DIN USB1.RCV EMU1 MCBSP3.DR GPIO56 BCLKREQ UART3.CTS MMC2.DAT2 GPIO40 BCLK UART3.RTS CAM.OUTCLK GPIO17 LOW_STATE UART1.RTS UART1.IRSHDN Z_STATE GPIO39 UART1.CTS UART1.IRSEL GPIO38 UART1.RX UART1.IRRX GPIO37
TYPE
CTRL SETTING Reg9[5:3] Reg9[5:3] Reg9[5:3] Reg9[5:3] Reg9[5:3] Reg9[5:3] Reg9[5:3] RegA[11:9] RegA[11:9] RegA[11:9] RegA[11:9] RegA[11:9] Reg9[29:27] Reg9[29:27] Reg9[29:27] Reg9[29:27] RegA[2:0] RegA[2:0] RegA[2:0] RegA[2:0] Reg9[14:12] Reg9[14:12] Reg9[14:12] Reg9[14:12] Reg9[14:12] Reg9[17:15] Reg9[17:15] Reg9[17:15] Reg9[20:18] Reg9[20:18] Reg9[20:18]
PULLUP/ PULLDN PU20, PD20
BUFFER (Lv) (Hv)
RESET STATE#
SUPPLY DVDD7
PU20, PD20
(Lv) (Hv)
DVDD7
PU20, PD20
(Lv) (Hv)
DVDD7
PU20, PD20
(Lv) (Hv)
DVDD7
PU20, PD20
(Lv) (Hv)
DVDD7
PU20, PD20
(Lv) (Hv)
DVDD7
PU20, PD20
(Lv) (Hv)
DVDD7
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup. Pullup pulldown enabled disabled software. voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
SPRS231D
December 2003 Revised March 2005
Introduction
Table 2-3. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME LOW_STATE UART1.TX UART1.IRTX MCSI1.DOUT USB1.TXD MCBSP3.DX GPIO18 CLK32K_OUT MPUIO0 USB1.SPEED UART1.TX GPIO36 OSC32K_IN OSC32K_OUT RTC_WAKE_INT USB1.SE0 RST_HOST_OUT GPIO55 RTC_ON_NOFF CLK32K_IN PWRON_RESET MMC.DAT3 MPUIO9 MPUIO6 MMC.CLK GPIO57 MMC.DAT0 Z_STATE GPIO58
TYPE
CTRL SETTING Reg9[23:21] Reg9[23:21] Reg9[23:21] Reg9[26:24] Reg9[26:24] Reg9[26:24] Reg9[26:24] Reg9[26:24] RegA[14:12] RegA[14:12] RegA[14:12] RegA[14:12] RegA[14:12] Reg9[2:0] Reg9[2:0] Reg9[2:0] Reg9[2:0] Reg8[20:18] RegA[17:15] Reg10[17:15] Reg10[17:15] Reg10[17:15] RegA[23:21] RegA[23:21] RegB[2:0] RegB[2:0] RegB[2:0]
PULLUP/ PULLDN
BUFFER (Lv) (Hv)
RESET STATE#
SUPPLY DVDD7
(Lv) (Hv)
DVDD7
PU20, PD20
(Lv) (Hv)
DVDDRTC
(Lv) (Hv)
DVDDRTC
(Lv) (Hv)
Input Input
DVDDRTC DVDDRTC DVDDRTC DVDD6
PU20, PD20
(Lv) (Hv)
PD100, PU20 PU20, PD20
(Lv) (Hv) (Lv) (Hv)
DVDD6 DVDD6
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup. Pullup pulldown enabled disabled software. voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
December 2003 Revised March 2005
SPRS231D
Introduction
Table 2-3. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME MMC.DAT2 Z_STATE MPUIO11 MMC.DAT1 MPUIO10 MPUIO7 MMC.CMD GPIO55 MCSI2.CLK USB2.SUSP USB0.SUSP MMC2.CLK GPIO27 MCSI2.DIN USB2.VP USB0.VP GPIO26 MCSI2.DOUT USB2.TXEN USB0.TXEN Z_STATE GPIO25 MCSI2.SYNC GPIO7 USB2.SPEED USB0.SPEED MMC2.CMDDIR MCLKREQ EXT_MASTER_REQ UART2.RX MMC2.DAT3 GPIO23
TYPE
CTRL SETTING RegA[20:18] RegA[20:18] RegA[20:18] RegA[26:24] RegA[26:24] RegA[26:24] RegA[29:27] RegA[29:27] RegB[5:3] RegB[5:3] RegB[5:3] RegB[5:3] RegB[5:3] RegB[8:6] RegB[8:6] RegB[8:6] RegB[8:6] RegB[11:9] RegB[11:9] RegB[11:9] RegB[11:9] RegB[11:9] RegB[14:12] RegB[14:12] RegB[14:12] RegB[14:12] RegB[14:12] RegB[20:18] RegB[20:18] RegB[20:18] RegB[20:18] RegB[20:18]
PULLUP/ PULLDN PD100, PU20
BUFFER (Lv) (Hv)
RESET STATE#
SUPPLY DVDD6
PU20, PD20
(Lv) (Hv)
DVDD6
PD100, PU20 PU20, PD20
(Lv) (Hv) (Lv) (Hv)
DVDD6 DVDD3
PU20, PD20
(Lv) (Hv)
DVDD3
PU20, PD20
(Lv) (Hv)
DVDD3
PU20, PD20
(Lv) (Hv)
DVDD3
PU20, PD20
(Lv) (Hv)
DVDD3
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup. Pullup pulldown enabled disabled software. voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
SPRS231D
December 2003 Revised March 2005
Introduction
Table 2-3. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME GPIO9 EMU0 MCSI1.SYNC MMC2.DAT0 GPIO8 TRST MCSI1.DOUT MMC2.CMD MPUIO3 MMC2.DAT1 MCBSP2.DR MCBSP2.DX MCBSP2.DXZ GPIO22 MCBSP2.FSX GPIO21 MCBSP2.CLKR GPIO11 MCBSP2.CLKX GPIO20 MCBSP2.FSR GPIO12 MCBSP2.DX MCBSP2.DR MCBSP2.DXZ GPIO19 UART2.RX USB2.VM USB0.VM GPIO18
TYPE
CTRL SETTING RegB[23:21] RegB[23:21] RegB[23:21] RegB[23:21] RegB[26:24] RegB[26:24] RegB[26:24] RegB[26:24] RegB[29:27] RegB[29:27] RegC[2:0] RegC[2:0] RegC[2:0] RegC[2:0] RegC[5:3] RegC[5:3] RegC[8:6] RegC[8:6] RegC[11:9] RegC[11:9] RegC[14:12] RegC[14:12] RegC[17:15] RegC[17:15] RegC[17:15] RegC[17:15] RegC[20:18] RegC[20:18] RegC[20:18] RegC[20:18]
PULLUP/ PULLDN PU20, PD20
BUFFER (Lv) (Hv)
RESET STATE#
SUPPLY DVDD3
PU20, PD20
(Lv) (Hv)
DVDD3
PU20, PD20 PU20, PD20
(Lv) (Hv) (Lv) (Hv)
DVDD3 DVDD3
PU20, PD20 PU20, PD20 PU20, PD20 PU20, PD20 PU20, PD20
(Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv)
DVDD3 DVDD3 DVDD3 DVDD3 DVDD3
PU20, PD20
(Lv) (Hv)
DVDD3
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup. Pullup pulldown enabled disabled software. voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
December 2003 Revised March 2005
SPRS231D
Introduction
Table 2-3. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME UART2.CTS USB2.RCV GPIO7 USB0.RCV LOW_STATE UART2.RTS USB2.SE0 MPUIO5 MPUIO12 USB0.SE0 LOW_STATE LOW_STATE UART2.TX USB2.TXD USB0.TXD Z_STATE GPIO17 UART2.BCLK SYS_CLK_IN MCLK MMC2.DATDIR0 GPIO24 USB.PUEN USB.CLKO USB.PUDIS Z_STATE LOW_POWER GPIO58 USB.DP I2C.SDA UART1.RX USB.PUEN
TYPE I/O/Z
CTRL SETTING RegC[23:21] RegC[23:21] RegC[23:21] RegC[23:21] RegC[26:24] RegC[26:24] RegC[26:24] RegC[26:24] RegC[26:24] RegC[26:24] RegC[26:24] RegC[29:27] RegC[29:27] RegC[29:27] RegC[29:27] RegC[29:27] RegC[29:27] RegD[2:0] RegD[2:0] RegB[17:15] RegB[17:15] RegB[17:15] RegD[5:3] RegD[5:3] RegD[5:3] RegD[5:3] RegD[5:3] RegD[5:3] USBTCTL[6:4] USBTCTL[6:4] USBTCTL[6:4] USBTCTL[6:4]
PULLUP/ PULLDN PU20, PD20
BUFFER (Lv) (Hv)
RESET STATE#
SUPPLY DVDD3
(Lv) (Hv)
DVDD3
PU20, PD20
(Lv) (Hv)
DVDD3
(Lv) (Hv) PU20, PD20 (Lv) (Hv)
DVDD3 DVDD3
PU20, PD20
(Lv) (Hv)
DVDD2
18.3 mode)
DVDD2
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup. Pullup pulldown enabled disabled software. voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
SPRS231D
December 2003 Revised March 2005
Introduction
Table 2-3. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME USB.DM I2C.SCL UART1.TX Z_STATE OSC1_IN OSC1_OUT FLASH.CS1U GPIO16 FLASH.WP FLASH.WE FLASH.RP FLASH.CS2UWE
TYPE I/O/Z
CTRL SETTING
PULLUP/ PULLDN
BUFFER 18.3 mode)
RESET STATE#
SUPPLY DVDD2
USBTCTL[6:4] USBTCTL[6:4] USBTCTL[6:4] RegA[2:0] RegA[2:0] RegF[23:21] RegF[23:21]
(Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv)
DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5
FLASH.OE FLASH.A[25:17]
FLASH.A[16] FLASH.A[15] FLASH.A[14] FLASH.A[13] FLASH.A[12] FLASH.A[11]
Reg11[5:3] Reg11[8:6] Reg11[11:9] Reg11[14:12] Reg11[17:15] Reg11[20:18]
PU20, PD20
(Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv)
DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5
PU20, PD20
(Lv) (Hv) (Lv) (Hv)
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup. Pullup pulldown enabled disabled software. voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
December 2003 Revised March 2005
SPRS231D
Introduction
Table 2-3. Package Terminal Characteristics (Continued)
BALL FLASH.CLK FLASH.CS2UOE
SIGNAL NAME FLASH.A[10] FLASH.A[9] FLASH.A[8] FLASH.A[7] FLASH.A[6] FLASH.A[5] FLASH.A[4] FLASH.A[3] FLASH.A[2] FLASH.A[1] FLASH.D[15:0]
TYPE
CTRL SETTING Reg11[23:21] Reg11[26:24] Reg12[5:3] Reg12[8:6] Reg12[11:9] Reg12[14:12] Reg12[17:15] Reg12[20:18] Reg12[23:21] Reg12[26:24]
PULLUP/ PULLDN
BUFFER (Lv) (Hv)
RESET STATE#
SUPPLY DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5
PU20, PD20
(Lv) (Hv) (Lv) (Hv)
PU20, PD20 PU20, PD20 PU20, PD20 PU20, PD20 PU20, PD20 PU20, PD20
(Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv)
Reg10[23:21] Reg10[23:21] RegF[29:27] RegF[29:27] PU100, PD20
(Lv) (Hv) (Lv) (Hv)
DVDD5 DVDD5
FLASH.RDY GPIO10
Input
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup. Pullup pulldown enabled disabled software. voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
SPRS231D
December 2003 Revised March 2005
Introduction
Table 2-3. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME FLASH.ADV FLASH.CS2 FLASH.BAA FLASH.CS2L GPIO62 FLASH.CS0 FLASH.CS1 FLASH.CS1L FLASH.CS2U GPIO5 FLASH.BE[0] FLASH.CS2UOE GPIO59 FLASH.BE[1] FLASH.CS2UWE GPIO60
TYPE
CTRL SETTING RegD[8:6] RegD[8:6] RegD[8:6] Reg10[2:0] Reg10[2:0] Reg10[29:27] Reg10[29:27] Reg10[20:18] Reg10[20:18] Reg10[8:6] Reg10[8:6] Reg10[8:6] Reg10[5:3] Reg10[5:3] Reg10[5:3] Reg10[26:24] Reg10[26:24]
PULLUP/ PULLDN
BUFFER (Lv) (Hv) (Lv) (Hv)
RESET STATE#
SUPPLY DVDD5 DVDD5
(Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv)
Input
DVDD5 DVDD5 DVDD5 DVDD5
(Lv) (Hv)
DVDD5
FLASH.CS3 GPIO3
(Lv) (Hv)
DVDD5
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup. Pullup pulldown enabled disabled software. voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
December 2003 Revised March 2005
SPRS231D
Introduction
Table 2-4. Package Terminal Characteristics
BALL
SIGNAL NAME SDRAM.CS SDRAM.DQSH SDRAM.DQSL SDRAM.CAS SDRAM.RAS SDRAM.DQML SDRAM.DQMU SDRAM.WE SDRAM.A[13:0]
TYPE
CTRL SETTING
PULLUP/ PULLDN
BUFFER (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv)
RESET STATE#
SUPPLY DVDD4 DVDD4 DVDD4 DVDD4 DVDD4 DVDD4 DVDD4 DVDD4 DVDD4
SDRAM.BA[1:0] SDRAM.D[15:0]
(Lv) (Hv) (Lv) (Hv)
DVDD4 DVDD4
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup. Pullup pulldown enabled disabled software. voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
SPRS231D
December 2003 Revised March 2005
Introduction
Table 2-4. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME SDRAM.CLK SDRAM.CLKX SDRAM.CKE LCD.AC SYS_CLK_OUT Z_STATE LCD.PCLK Z_STATE LCD.P[15] Z_STATE GPIO2 LCD.P[14] Z_STATE GPIO35 LCD.P[13] Z_STATE GPIO34 LCD.P[12] Z_STATE GPIO33 LCD.P[11] Z_STATE GPIO32 LCD.P[10] Z_STATE GPIO31 LCD.P[9] Z_STATE GPIO30
TYPE
CTRL SETTING RegD[11:9] RegD[11:9] RegD[11:9] RegD[17:15] RegD[17:15] RegD[20:18] RegD[20:18] RegD[20:18] RegD[23:21] RegD[23:21] RegD[23:21] RegD[26:24] RegD[26:24] RegD[26:24] RegD[29:27] RegD[29:27] RegD[29:27] RegE[2:0] RegE[2:0] RegE[2:0] RegE[5:3] RegE[5:3] RegE[5:3] RegE[8:6] RegE[8:6] RegE[8:6]
PULLUP/ PULLDN
BUFFER (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv)
RESET STATE#
SUPPLY DVDD4 DVDD4 DVDD4 DVDD1
(Lv) (Hv) (Lv) (Hv)
DVDD1 DVDD1
(Lv) (Hv)
DVDD1
(Lv) (Hv)
DVDD1
(Lv) (Hv)
DVDD1
(Lv) (Hv)
DVDD1
(Lv) (Hv)
DVDD1
(Lv) (Hv)
DVDD1
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup. Pullup pulldown enabled disabled software. voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
December 2003 Revised March 2005
SPRS231D
Introduction
Table 2-4. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME LCD.VS Z_STATE LCD.P[8] Z_STATE GPIO29 LCD.P[7] Z_STATE LCD.P[6] Z_STATE LCD.P[5] Z_STATE LCD.P[4] Z_STATE LCD.P[3] Z_STATE LCD.P[2] Z_STATE LCD.P[1] Z_STATE LCD.P[0] Z_STATE LCD.HS Z_STATE KB.C[4] GPIO27 KB.C[3] GPIO63 KB.C[2] GPIO61
TYPE
CTRL SETTING RegE[11:9] RegE[11:9] RegE[14:12] RegE[14:12] RegE[14:12] RegE[17:15] RegE[17:15] RegE[20:18] RegE[20:18] RegE[23:21] RegE[23:21] RegE[26:24] RegE[26:24] RegE[29:27] RegE[29:27] RegF[2:0] RegF[2:0] RegF[5:3] RegF[5:3] RegF[8:6] RegF[8:6] RegD[14:12] RegD[14:12] Reg3[5:3] Reg3[5:3] Reg3[8:6] Reg3[8:6] Reg3[11:9] Reg3[11:9] Reg3[14:12] Reg3[14:12]
PULLUP/ PULLDN
BUFFER (Lv) (Hv) (Lv) (Hv)
RESET STATE#
SUPPLY DVDD1 DVDD1
(Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) PU20, PD20 PU20, PD20 PU20, PD20 PU20, PD20 (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv)
DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 DVDD1
KB.C[1] MPUIO6
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup. Pullup pulldown enabled disabled software. voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
SPRS231D
December 2003 Revised March 2005
Introduction
Table 2-4. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME KB.C[0] MPUIO0 KB.R[4] MPUIO15 KB.R[3] MPUIO13 KB.R[2] MPUIO10 KB.R[1] MPUIO9 KB.R[0] MPUIO8 KB.C[5] GPIO28 MCBSP1.CLKS GPIO62 MCBSP1.CLKX GPIO54 MCBSP1.FSX MCBSP1.DX MCBSP1.DXZ GPIO53 MCBSP1.DX MCBSP1.ESX MCBSP1.DXZ GPIO52
TYPE
CTRL SETTING Reg3[17:15] Reg3[17:15] Reg3[20:18] Reg3[20:18] Reg3[23:21] Reg3[23:21] Reg3[26:24] Reg3[26:24] Reg3[29:27] Reg3[29:27] Reg4[2:0] Reg4[2:0] Reg3[2:0] Reg3[2:0] Reg4[8:6] Reg4[8:6] Reg4[11:9] Reg4[11:9] Reg4[14:12] Reg4[14:12] Reg4[14:12] Reg4[14:12] Reg4[17:15] Reg4[17:15] Reg4[17:15] Reg4[17:15] Reg4[20:18] Reg4[20:18]
PULLUP/ PULLDN PU20, PD20 PU100, PD20 PU100, PD20 PU100, PD20 PU100, PD20 PU100, PD20 PU20, PD20 PU20, PD20 PU20, PD20 PU20, PD20
BUFFER (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv)
RESET STATE#
SUPPLY DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 DVDD1
PU20, PD20
(Lv) (Hv)
DVDD1
MCBSP1.DR GPIO51
PU20, PD20
(Lv) (Hv)
DVDD1
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup. Pullup pulldown enabled disabled software. voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
December 2003 Revised March 2005
SPRS231D
Introduction
Table 2-4. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME CAM.EXCLK ETM.SYNC[0] UWIRE.SDO LOW_STATE GPIO57 CAM.LCLK ETM.CLK UWIRE.SCLK GPIO39 MPU_BOOT USB1.SUSP CAM.D[7] ETM.D[7] UWIRE.CS0 MMC2.DAT2 GPIO35 CAM.D[6] ETM.D[6] UWIRE.CS3 MMC2.CMD GPIO34 CAM.D[5] ETM.D[5] UWIRE.SDI GPIO33 CAM.D[4] ETM.D[4] UART3.TX GPIO32
TYPE
CTRL SETTING Reg4[23:21] Reg4[23:21] Reg4[23:21] Reg4[23:21] Reg4[23:21] Reg4[26:24] Reg4[26:24] Reg4[26:24] Reg4[26:24] Reg8[29:27] Reg8[29:27] Reg4[29:27] Reg4[29:27] Reg4[29:27] Reg4[29:27] Reg4[29:27] Reg5[2:0] Reg5[2:0] Reg5[2:0] Reg5[2:0] Reg5[2:0] Reg5[5:3] Reg5[5:3] Reg5[5:3] Reg5[5:3] Reg5[8:6] Reg5[8:6] Reg5[8:6] Reg5[8:6]
PULLUP/ PULLDN PU20, PD20
BUFFER (Lv) (Hv)
RESET STATE#
SUPPLY DVDD8
PU20, PD20
(Lv) (Hv)
DVDD8
(Lv) (Hv) PU20, PD20 (Lv) (Hv)
DVDD8
PU20, PD20
(Lv) (Hv)
DVDD8
PU20, PD20
(Lv) (Hv)
DVDD8
PU20, PD20
(Lv) (Hv)
DVDD8
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup. Pullup pulldown enabled disabled software. voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset Terminal 3-stated BFAIL input input/output buffers Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
SPRS231D
December 2003 Revised March 2005
Introduction
Table 2-4. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME CAM.D[3] ETM.D[3] UART3.RX GPIO31 CAM.D[2] ETM.D[2] UART3.CTS GPIO30 CAM.D[1] ETM.D[1] UART3.RTS GPIO29 CAM.D[0] ETM.D[0] MPUIO12 MMC2.DAT3 CAM.VS ETM.PSTAT[2] MPUIO14 MMC2.DAT1 CAM.HS ETM.PSTAT[1] UART2.CTS MMC2.DAT0 GPIO38 CAM.RSTZ ETM.PSTAT[0] UART2.RTS MMC2.CLK LOW_STATE GPIO37
TYPE
CTRL SETTING Reg5[11:9] Reg5[11:9] Reg5[11:9] Reg5[11:9] Reg5[14:12] Reg5[14:12] Reg5[14:12] Reg5[14:12] Reg5[17:15] Reg5[17:15] Reg5[17:15] Reg5[17:15] Reg5[20:18] Reg5[20:18] Reg5[20:18] Reg5[20:18] Reg5[23:21] Reg5[23:21] Reg5[23:21] Reg5[23:21] Reg5[26:24] Reg5[26:24] Reg5[26:24] Reg5[26:24] Reg5[26:24] Reg5[29:27] Reg5[29:27] Reg5[29:27] Reg5[29:27] Reg5[29:27] Reg5[29:27]
PULLUP/ PULLDN PU20, PD20
BUFFER (Lv) (Hv)
RESET STATE#
SUPPLY DVDD8
PU20, PD20
(Lv) (Hv)
DVDD8
PU20, PD20
(Lv) (Hv)
DVDD8
PU20, PD20
(Lv) (Hv)
DVDD8
PU20, PD20
(Lv) (Hv)
DVDD8
PU20, PD20
(Lv) (Hv)
DVDD8
PU20, PD20
(Lv) (Hv)
DVDD8
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup. Pullup pulldown enabled disabled software. voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
December 2003 Revised March 2005
SPRS231D
Introduction
Table 2-4. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME LOW_STATE UART3.TX UART2.TX TIMER.PWM0 GPIO50 UART3.RX UART2.RX TIMER.PWM1 GPIO49 GPIO15 KB.R[7] TIMER.PWM2 GPIO14 KB.R[6] LCD.RED0 Z_STATE GPIO13 KB.R[5] LCD.BLUE0 Z_STATE GPIO12 MCBSP3.FSX TIMER.EXTCLK GPIO11 ETM.PSTAT[5]
TYPE
CTRL SETTING Reg6[2:0] Reg6[2:0] Reg6[2:0] Reg6[2:0] Reg6[2:0] Reg6[2:0] Reg6[5:3] Reg6[5:3] Reg6[5:3] Reg6[5:3] Reg6[5:3] Reg6[8:6] Reg6[8:6] Reg6[8:6] Reg6[11:9] Reg6[11:9] Reg6[11:9] Reg6[11:9] Reg6[14:12] Reg6[14:12] Reg6[14:12] Reg6[14:12] Reg6[17:15] Reg6[17:15] Reg6[17:15] Reg6[20:18] Reg6[20:18] Reg6[20:18]
PULLUP/ PULLDN PU20, PD20
BUFFER (Lv) (Hv)
RESET STATE#
SUPPLY DVDD9
PU20, PD20
(Lv) (Hv)
DVDD9
PU100, PD20 PU100, PD20
(Lv) (Hv)
DVDD9
(Lv
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