KS8695X Integrated Multi-Port High-Performance Gateway Solutions

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KS8695X Integrated Multi-Port High-Performance Gateway Solutions

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KS8695X
KS8695X
Integrated Multi-Port High-Performance Gateway Solutions Rev. 1.02
General Description
CENTAUR KS8695X, Multi-Port Gateway-on-a-Chip, delivers level networking integration performance accelerating broadband gateway development. components integrated KS8695X include: Integrated Layer managed switch with five Fast Ethernet transceivers patented mixed-signal lowpower technology, five media access control (MAC) units, high-speed non-blocking switch fabric, dedicated address look-up engine, on-chip frame buffer memory, controls. port partitioned interface with other four ports access. 166MHz ARM(ARM992T) processor with memory management unit (MMU) I-cache Dcache. XceleRoutertechnology interfaces. Shared programmable 8/16/32-bit data 22-bit address with 64MB total memory space SDRAM, ROM, Flash, SRAM, peripheral devices. Other peripheral support logic including GPIO, watchdog timer, interrupt controller, JTAG debugging interface. Complete hardware software reference designs available. KS8695X represents level total solution optimized broadband gateway system development renders speedy routing performance connectivity interfaces value-added networking expansions.
Functional Diagram
KS8695X
Advanced Memory Controller External Controller FLASH/ROM/ SRAM Controller SDRAM Controller JTAG
ARM922T
I-Cache
Advanced High-Performance (AHB)
D-Cache
XceleRouter
Bridge Switch Registers High-Performance Non-Blocking 5-Port Switch
Advanced Peripheral (APB)
Interrupt Controller
GPIOs
UART TX/RX 10/100 TX/RX 10/100 TX/RX 10/100 TX/RX 10/100 TX/RX 10/100
Timer/ Watchdog
XceleRouter trademark Micrel, Inc. registered trademark Advanced Micro Devices, Inc. trademark Advanced RISC Machines Ltd. Intel registered trademark Intel Corporation. WinCE registered trademark Microsoft Corporation.
Micrel, Inc. 2180 Fortune Drive Jose, 95131 (408) 944-0800 (408) 474-1000 http://www.micrel.com
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Engines FIFO engine with burst mode support efficient data transfers FIFOs back-to-back packet transfers Peripheral Support 8/16/32-bit external interface supporting PCMCIA generic CPU/DSP host Eight general-purpose input/output (GPIO) 32-bit timer counters (one watchdog) Interrupt controller ARM922T JTAG debug interface Power Management Reduced system clock speeds System Design 166MHz 125MHz speed Reference HW/SW Evaluation Hardware evaluation board (passes class EMI) Board support package including firmware source codes, linux kernel, software stacks Documentation design programming Commercial Temperature Range: +70°C Available 208-Pin PQFP
Features
CENTAUR KS8695X featuring XceleRouter technology single-chip multi-port gateway-on-a-chip with components integrated high-performance low-cost broadband gateway ARM922T High-Performance Core ARM922T core 166MHz I-cache D-cache Memory management unit (MMU) linux WinCE® 32-bit 16-bit thumb instruction sets smaller memory footprints XceleRouter Technology TCP/UDP/IP packet header checksum generation offload tasks IPv4 packet filtering checksum errors Automatic error packet discard Integrated Switch Engine Transceivers Five 10/100 transceivers five MACs interface, switching) 10BASE-T, 100BASE-TX, 100BASE-FX modes port) On-chip SRAM frame buffer memory Wire-speed switching VLAN 802.1p tag/untag options Extensive counter management support IGMP snooping multicast packet filtering Port-based VLAN QoS/CoS packet prioritization support: port, 802.1p DiffServ-based 802.1D Spanning Tree Protocol support Dedicated entry look-up engine Automatic MDI/MDI-X crossover ports Port mirroring/monitoring/sniffing Broadcast storm protection with control Full- half-duplex flow control Memory External Interfaces 8/16/32-bit wide shared data path SDRAM, ROM/SRAM/Flash external Total memory space 64MB Intel®/AMD®-type Flash support
Applications
Multi-port broadband gateway Multi-port firewall appliances Combination wireless wireline gateway Multi-port VoIP gateway Fiber-to-the-home managed
Ordering Information
Part Number KS8695X Temperature Range +70°C Package 208-Pin PQFP
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Revision History
Revision 1.00 1.01 1.02 Date 05/24/04 06/17/04 10/26/04 Summary Changes Created. Updated System Clock. Updated Timing Diagrams: SRAM Read Write, SDRAM Read Write, External Read/Write Cycles.
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Contents
System Level Applications Description Configuration Functional Description Introduction Features Advanced Memory Controller Features Direct Memory Access (DMA) Engines XceleRouterTechnology Switch Engine Network Interface Peripherals Other Features Signal Description System Level Hardware Interface Configuration Pins Reset System Clock Signal Descriptions Group Address Register Description Memory Memory Example Register Description System Registers Memory Controller Interface Registers Registers Registers UART Registers Interrupt Controller Registers Timer Registers General Purpose Registers Switch Engine Configuration Registers Miscellaneous Registers Absolute Maximum Ratings Operating Ratings Electrical Characteristics Options Timing Diagrams Package Information Dimensions
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System Level Applications
Cable Fiber Satellite 10/100 TX/FX Wireless Auto MDI-X Console Port
SDRAM
Flash
Servers WLAN 10/100 Auto MDI-X Switch Phone
KS8695X
Integrated Multi-Port Broadband Gateway Solution
8/16/32-Bit PCMCIA External
Wireless Coprocessor VoIP
KS8695X
25MHz
Adr[21:0] Data[31:0]
Reset
JTAG
Reset
Auto MDI/MDI-X
10/100 TX/FX
10/100
FIFO
ARM922T Core
D-Cache
AMBA
I-Cache
Switch Controller On-Chip Frame Buffer Memory
Memory Controller SDRAM, Flash, ROM, SRAM
JTAG
FIFO
10/100
10/100
10/100
10/100
LEDs
10/100
10/100
10/100
10/100
XceleRouterWRSTO UART GPIO
Interrupt Control
Auto MDI/MDI-X
Arbiter
Bridge
Timer Watchdog
UART
GPIO
External Interface
8/16/32-Bit PCMCIA, General
Wireless Voice Coding
Coprocessor Host Controller
Print Sharing Parallel Port
Figure KS8695X Applications
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Description
Number
Note: Ground. Power supply. Input. Output. Bidirectional.
Name VDD-IO VSS-IO ADDR10 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 VDD-IO VSS-IO ADDR2 ADDR1 ADDR0 SDCSN1 SDCSN0 SDRASN SDCASN SDWEN VDD-IO VSS-IO SDOCLK SDICLK VDD-CORE VSS-CORE SDQM3 SDQM2 SDQM1 SDQM0 DATA31 DATA30
Type(1)
Function 3.3V Digital Circuitry VDD. Digital VSS. Address Bit. Address Bit. Address Bit. Address Bit. Address Bit. Address Bit. Address Bit. Address Bit. 3.3V Digital Circuitry VDD. Digital VSS. Address Bit. Address Bit. Address Bit. SDRAM Chip Select. Active Chip Select Pins SDRAM. SDRAM Chip Select. Active Chip Select Pins SDRAM. SDRAM Address Strobe. Active Low. SDRAM Column Address Strobe. Active Low. SDRAM Write Enable. Active Low. 3.3V Digital Circuitry VDD. Digital VSS. System/SDRAM Clock Out. SDRAM Clock 1.8V Digital Core VDD. Digital Core VSS. SDRAM Data Input/Output Mask. SDRAM Data Input/Output Mask. SDRAM Data Input/Output Mask. SDRAM Data Input/Output Mask. External Data Bit. External Data Bit.
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Description
Number
Note: Ground. Power supply. Bidirectional.
Name DATA29 VDD-IO VSS-IO DATA28 DATA27 DATA26 DATA25 DATA24 DATA23 DATA22 VDD-CORE VSS-CORE DATA21 DATA20 VDD-IO VSS-IO DATA19 DATA18 DATA17 DATA16 VDD-IO VSS-IO DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 VDD-IO VSS-IO DATA7
Type(1)
Function External Data Bit. 3.3V Digital Circuitry VDD. Digital VSS. External Data Bit. External Data Bit. External Data Bit. External Data Bit. External Data Bit. External Data Bit. External Data Bit. 1.8V Digital Core VDD. Digital Core VSS. External Data Bit. External Data Bit. 3.3V Digital Circuitry VDD. Digital VSS. External Data Bit. External Data Bit. External Data Bit. External Data Bit. 3.3V Digital Circuitry VDD. Digital VSS. External Data Bit. External Data Bit. External Data Bit. External Data Bit. External Data Bit. External Data Bit. External Data Bit. External Data Bit. 3.3V Digital Circuitry VDD. Digital VSS. External Data Bit.
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Number
Note: Ground. Power supply. Input. Output. Bidirectional. Output normal mode; input during reset. connect.
Name DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 VDD-IO VSS-IO ECSN2 ECSN1 ECSN0 EWAITN VDD-IO VSS-IO RCSN1 RCSN0 WRSTO TEST3 EROEN/ WRSTPLS ERWEN3/ TICTESTENN ERWEN2/ TESTREQA ERWEN1/ TESTREQB ERWEN0/ TESTACK VDD-CORE VSS-CORE URXD UDTRN/ DBGENN UTXD Type(1) Function External Data Bit. External Data Bit. External Data Bit. External Data Bit. External Data Bit. External Data Bit. External Data Bit. 3.3V Digital Circuitry VDD. Digital VSS. External Device Chip Select. Active Low. External Device Chip Select. Active Low. External Device Chip Select. Active Low. External Wait. Active Low. 3.3V Digital Circuitry VDD. Digital VSS. ROM/SRAM/FLASH Chip Select. Active Low. ROM/SRAM/FLASH Chip Select. Active Low. Watchdog Timer Reset Output. This must left connect. ROM/SRAM/FLASH External Output Enable. Active Low. /WRSTO Polarity Select. External ROM/SRAM/FLASH Write Byte Enable. Active Low. External ROM/SRAM/FLASH Write Byte Enable. Active Low. External ROM/SRAM/FLASH Write Byte Enable. Active Low. External ROM/SRAM/FLASH Write Byte Enable. Active Low. 1.8V Digital Core VDD. Digital Core VSS. UART Receive Data. UART Data Terminal Ready. Active Low. /Debug Enable (factory test signal). UART Transmit Data.
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Number
Note: Ground. Power supply. Input. Output. Bidirectional. Output normal mode; input during reset.
Name UDSRN URTSN/ CPUCLKSEL UCTSN/ BISTEN UDCDN/ SCANEN URIN/ TSTRST GPIO7 GPIO6 GPIO5/ TOUT1 VDD-IO VSS-IO GPIO4/ TOUT0 GPIO3/ EINT3 GPIO2/ EINT2 GPIO1/ EINT1 GPIO0/ EINT0 TRSTN VDD-CORE VSS-CORE TESTEN WLED1/ B0SIZE1 WLED0/ B0SIZE0 Type(1) Function UART Data Ready. Active Low. UART Request Send/CPU Clock Select. UART Data Ready. Active Low. /BIST Enable (factory test signal). UART Data Carrier Detect. /Scan Enable (factory test signal). UART Ring Indicator/Chip Test Reset (factory test signal). General Purpose Pin. General Purpose Pin. General Purpose Pin/Timer Output Pin. 3.3V Digital Circuitry VDD. Digital VSS. General Purpose Pin/Timer Output Pin. General Purpose Pin/External Interrupt Request Pin. General Purpose Pin/External Interrupt Request Pin. General Purpose Pin/External Interrupt Request Pin. General Purpose Pin/External Interrupt Request Pin. JTAG Test Clock. JTAG Test Mode Select. JTAG Test Data JTAG Test Data Out. JTAG Test Reset. Active Low. 1.8V Digital Core VDD. Digital Core VSS. Chip Test Enable (factory test signal). Programmable Indicator 1/Bank Size Programmable Indicator 0/Bank Size
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Number
Note: Ground. Power supply. Output. connect.
Name L4LED1/ DBGAD7 L4LED0/ DBGAD6 L3LED1/ DBGAD5 L3LED0/ DBGAD4 L2LED1/ DBGAD3 L2LED0/ DBGAD2 L1LED1/ DBGAD1 L1LED0/ DBGAD0 VDD-CORE VSS-CORE TEST4 TEST5 TEST6 TEST7 TEST8 TEST9 TEST10 VDD-IO VSS-IO TEST11 TEST12 TEST13 TEST14 TEST15 TEST16 TEST17 TEST18 Type(1) Function Port Programmable Indicator Port Programmable Indicator Port Programmable Indicator Port Programmable Indicator Port Programmable Indicator Port Programmable Indicator Port Programmable Indicator Port Programmable Indicator 1.8V Digital Core VDD. Digital Core VSS. This must left connect. This must left connect. This must left connect. This must left connect. This must left connect. This must left connect. This must left connect. 3.3V digital Circuitry VDD. Digital VSS. This must left connect. This must left connect. This must left connect. This must left connect. This must left connect. This must left connect. This must left connect. This must left connect.
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Number
Note: Ground. Power supply. Input. Output. Bidirectional. connect.
Name TEST19 RESETN TEST2 XCLK1 XCLK2 VDDA-PLL GNDA VDDAR GNDA GNDA VDDAR WANFXSD/ DOUT WANRXP WANRXM GNDA WANTXM WANTXP GNDA LANRXP1 LANRXM1 GNDA LANTXM1 LANTXP1 VDDAR GNDA ISET VDDAT LANRXP2 LANRXM2 GNDA LANTXM2 LANTXP2 Type(1) Function This must left connect. KS8695X Chip Reset. Active Low. Test (factory test signal). External Clock External Clock (negative polarity). 1.8V Analog PLL. Analog Ground. 1.8V Analog VDD. Analog Ground. Analog Ground. 1.8V Analog VDD. Fiber Signal Detect/DOUT: Factory Analog Test Mode. Receive Signal (differential). Receive Signal (differential). Analog Ground. Transmit Signal (differential). Transmit Signal (differential). Analog Ground. Port Receive Signal (differential). Port Receive Signal (differential). Analog Ground. Port Transmit Signal (differential). Port Transmit Signal (differential). 1.8V Analog VDD. Analog Ground. Transmit Output Current. Connect Ground with 3.01k Resistor. 2.5V/3.3V Analog VDD. Port Receive Signal (differential). Port Receive Signal (differential). Analog Ground. Port Transmit Signal (differential). Port Transmit Signal (differential).
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Number
Note: Ground. Power supply. Input. Output.
Name VDDAT LANRXP3 LANRXM3 GNDA LANTXM3 LANTXP3 GNDA VDDAR LANRXP4 LANRXM4 GNDA LANTXM4 LANTXP4 GNDA VDDAR GNDA VDDAR GNDA TEST1 ADDR19 ADDR18 ADDR17 ADDR16 ADDR15 ADDR14 ADDR13 ADDR21/BA1 ADDR20/BA0 ADDR12 ADDR11 Type(1) Function 2.5V/3.3V Analog VDD. Port Receive Signal (differential). Port Receive Signal (differential). Analog Ground. Port Transmit Signal (differential). Port Transmit Signal (differential). Analog Ground. 1.8V Analog VDD. Port Receive Signal (differential). Port Receive Signal (differential). Analog Ground. Port Transmit Signal (differential). Port Transmit Signal (differential). Analog Ground. 1.8V Analog VDD. Analog Ground. 1.8V Analog VDD. Analog Ground. Test (factory test signal). Address Bit. Address Bit. Address Bit. Address Bit. Address Bit. Address Bit. Address Bit. Address Bit/Bank Address SDRAM Interface. Address Bit/Bank Address SDRAM Interface. Address Bit. Address Bit.
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Configuration
GNDA GNDA VDDAR GNDA VDDA_PLL XCLK2 XCLK1 TEST2 RESETN TEST TEST TEST TEST TEST TEST TEST TEST TEST VSS_IO VDD_IO TEST TEST TEST TEST TEST TEST TEST VSS_CORE VDD_CORE L1LED0/DBGAD0 L1LED1/DBGAD1 L2LED0/DBGAD2 L2LED1/DBGAD3 L3LED0/DBGAD4 L3LED1/DBGAD5 L4LED0/DBGAD6 L4LED1/DBGAD7 WLED0/B0SIZE0 WLED1/B0SIZE1 TESTEN VSS_CORE VDD_CORE TRSTN GPIO0/EINT0 GPIO1/EINT1 GPIO2/EINT2 GPIO3/EINT3 GPIO4/TOUT0
VDDAR WANFXSD/DOUT WANRXP WANRXM GNDA WANTXM WANTXP GNDA LANRXP1 LANRXM1 GNDA LANTXM1 LANTXP1 VDDAR GNDA ISET VDDAT LANRXP2 LANRXM2 GNDA LANTXM2 LANTXP2 VDDAT LANRXP3 LANRXM3 GNDA LANTXM3 LANTXP3 GNDA VDDAR LANRXP4 LANRXM4 GNDA LANTXM4 LANTXP4 GNDA VDDAR GNDA VDDAR GNDA TEST1 ADDR19 ADDR18 ADDR17 ADDR16 ADDR15 ADDR14 ADDR13 ADDR21/BA1 ADDR20/BA0 ADDR12 ADDR11
VSS_IO VDD_IO GPIO5/TOUT1 GPIO6 GPIO7 URIN/TSTRST UDCDN/SCANEN UCTSN/BISTEN URTSN/CPUCLKSEL UDSRN UTXD UDTRN/DBGENN URXD VSS_CORE VDD_CORE ERWEN0/TESTACK ERWEN1/TESTREQB ERWEN2/TESTREQA ERWEN3/TICTESTENN EROEN/WRSTPLS MPMSEL WRSTO RCSN0 RCSN1 VSS_IO VDD_IO EWAITN ECSN0 ECSN1 ECSN2 VSS_IO VDD_IO DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 VSS_IO VDD_IO DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 VSS_IO VDD_IO
October 2004
VDD_IO VSS_IO ADDR10 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 VDD_IO VSS_IO ADDR2 ADDR1 ADDR0 SDCSN1 SDCSN0 SDRASN SDCASN SDWEN VDD_IO VSS_IO SDOCLK SDICLK VDD_CORE VSS_CORE SDQM3 SDQM2 SDQM1 SDQM0 DATA31 DATA30 DATA29 VDD_IO VSS_IO DATA28 DATA27 DATA26 DATA25 DATA24 DATA23 DATA22 VDD_CORE VSS_CORE DATA21 DATA20 VDD_IO VSS_IO DATA19 DATA18 DATA17 DATA16
PQFP (PQ)
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Functional Description
Introduction
CENTAUR KS8695X cost-effective, high-performance router-on-a-chip solution Ethernet-based systems. integrates powerful processor with 5-port switch that consists five units, five physical layer transceivers (PHYs), engines, hardware protocol engines offloading. KS8695X built around 16/32-bit ARM922T RISC processor. ARM922T scalable, high-performance, microprocessor developed highly integrated system-on-a-chip applications. KS8695X offers I-cache D-cache reduce memory access latency high-performance applications. There also SDRAM, SRAM, interfaces with configurable speeds data width. KS8695X provides external interfaces, UART interface, general purpose I/O, JTAG debugging port, internal interrupt controller, internal timers. KS8695X contains independent engines LAN. Each independent engines supports burst mode well little-endian byte ordering memory buffers descriptors. Each engine contains receive FIFO transmit FIFO ensure back-to-back packet reception under-runs packet transmission. integrated switch provides hardware support some most desirable Layer features such port-based VLAN, QoS/CoS packet prioritization, IGMP snooping, Spanning Tree Protocol. switch contains 16Kx32 SRAM on-chip memory frame buffering. embedded frame buffer memory designed with 1.4Gbps on-chip memory bus. This allows KS8695X perform full non-blocking frame switching and/or routing. There five units KS8695X: four WAN. Connected MACs five 10/100 PHYs. These PHYs Micrel's patented low-power analog technology achieve increased performance. units also support auto MDI/MDI-X feature. PHYs support 10BASE-T 100BASE-TX operation IEEE802.3 standard. supports 10BASE-T, 100BASE-TX, 100BASE-FX operation. KS8695X combines proven PHY, MAC, switch technology with protocol engines, powerful ARM922T processor create solution that saves costs, board real-estate, design time while providing outstanding performance variety router applications.
Features
166MHz ARM922T RISC processor core On-chip AMBA interfaces 16-bit thumb programming relax memory requirement I-cache D-cache Little-endian mode supported Configurable memory management unit Supports reduced system clock speed power saving
Advanced Memory Controller Features
Supports glueless connection banks ROM/SRAM/FLASH memory with programmable 8/16/32 data programmable access timing Supports glueless connection SDRAM banks with programmable 8/16/32 data programmable RAS/CAS latency Supports three external banks with programmable 8/16/32 data programmable access timing Programmable system clock speed power management
Direct Memory Access (DMA) Engines
Independent engine with programmable burst mode port Independent engine with programmable burst mode ports Supports little-endian byte ordering memory buffers descriptors Contains large independent receive transmit FIFOs (3KB receive/3KB transmit) back-to-back packet receive, guaranteed under-run packet transmit Data alignment logic scatter gather capability
XceleRouter Technology
Supports IPv4 header/TCP/UDP Packet checksum generation host offloading Supports IPv4 packet filtering based checksum errors
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Switch Engine
5-port 10/100 Integrated switch with four physical layer transceivers 16Kx32 on-chip SRAM frame buffering 1.4Gbps on-chip memory bandwidth wire-speed frame switching 10Mbps, 100Mbps modes operations both full half duplex Supports port-based VLAN Support DiffServ priority, IEEE 802.1p-based priority port-based priority Integrated address look-up engine, supports absolute addresses Automatic address learning, address aging, address migration Broadcast storm protection Full-duplex IEEE 802.3x flow control Half-duplex back pressure flow control Supports IGMP snooping Spanning Tree Protocol support
Network Interface
Features five units five units Supports 10BASE-T 100BASE-TX ports port. Also supports 100BASE-FX port Supports automatic generation checking Supports automatic error packet discard Supports IEEE 802.3 auto-negotiation algorithm full-duplex half-duplex operation 10Mbps 100Mbps Supports full-/half-duplex operation interfaces Fully compliant with IEEE 802.3 Ethernet standards IEEE 802.3 full-duplex flow control half-duplex backpressure collision flow control Supports MDI/MDI-X auto-crossover
Peripherals
Twenty-eight interrupt sources, including four external interrupt sources Normal fast interrupt mode (IRQ, FIQ) supported Prioritized interrupt handling Eight programmable general purpose I/O. Pins individually configurable input, output, mode dedicated signals. programmable 32-bit timers with watchdog timer capability High-speed UART interface 115kbps
Other Features
Integrated generate system clocks JTAG development interface connection 208-pin PQFP
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Signal Description
System Level Hardware Interfaces
KS8695X
Clock Reset
JTAG Ethernet
GPIO
UART
Ethernet
Advanced Memory Interface
Drivers
Factory Test
Power Ground
Figure System Level Interfaces
system level KS8695X features following interfaces: Clock interface crystal external oscillator JTAG development interface Ethernet physical interface Four Ethernet physical interfaces drivers high-speed UART interface Eight GPIO pins Advanced memory interface Programmable synchronous rate Programmable asynchronous interface timing Independently programmable data width static synchronous memory Glueless connection SDRAM Glueless connection flash memory Factory test Power ground
Configuration Pins
Configuration Bank0 Flash Data Width Name B0SIZE[1:0] 118,119 Settings `00'= reserved `01' byte wide `10' half word wide bits) `11' word wide bits) active high active normal mode (PLL) bypass internal
WRSTO Polarity Clock Select
EROEN/WRSTPLS URTSN/CPUCLKSEL
Table Configuration Pins
Reset
KS8695X single reset input that driven system reset circuit simple power reset circuit. KS8695X also features reset output (WRSTO) that used reset other devices system. WRSTO configured either active high reset active reset through strap-in option shown Table KS8695X also built watchdog timer. Once user programs watchdog timer timer setting expires, KS8695X will reset itself also assert WRSTO reset other devices system. Figure shows typical system that uses KS8695X WRSTO system reset.
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Signal Description
System Level Hardware Interfaces
Power Reset Circuit WRSTO
KS8695X
System Reset System
RESETN EROEN/ WRSTPLS
WRSTO Active Memory
Figure Example Reset Circuit
System Clock
clock KS8695X supplied either 25MHz ±50ppm crystal oscillator. oscillator used shall connected input (pin 150) KS8695X. crystal used, shall connected with circuit like shown below. 25MHz input clock used internal generate programmable SDOCLK. SDOCLK system clock, programmed from 25MHz 125MHz using system clock control register offset 0x0004. CPUCLKSEL strap-in option needs pulled normal operation.
KS8695X
URTSN/ CPUCLKSEL
SDOCLK System 25MHz 125MHz
500k 25MHz Xtal
22pF
22pF
Figure Typical Clock Circuit
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Signal Descriptions Group
Clock Reset Pins
Name XCLK1/ CPUCLK Type(1) Description External Clock This signal used source clock transmit clock internal PHY. clock frequency should 25MHz ±50ppm. XCLK1 signal also used reference clock signal internal generate 125MHz internal system clock. CPUCLK: factory clock test input when internal disabled (factory test signal). External Clock Used with XCLK1 when another polarity crystal needed. This unused normal clock input. Normal Mode: UART request send. Active output. During reset: clock select. Select clock source. CPUCLKSEL=0 (normal mode), internal clock output used clock source. CPUCLKSEL=1 (factory test signal): external clock CPUCLK used internal clock source. KS8695X chip reset. Active input asserted least system clock (40ns) cycles reset KS8695X. When reset state, output pins tri-stated open drain signals floating. Watchdog timer reset output. This signal asserted least 200ms RESETN asserted when internal watchdog timer expires. Normal Mode: ROM/SRAM/FLASH External output enable. Active low. When asserted, this signal controls output enable port specified device. During reset: Watchdog timer reset polarity setting. WRSTPLS=0, Active high; WRSTPLS=1, Active low. default.
XCLK2 URTSN/ CPUCLKSEL
RESETN
WRSTO EROEN/ WRSTPLS
JTAG Interface Pins
Name TRSTN Type(1) Description JTAG test clock. JTAG test mode select. JTAG test data JTAG test data out. JTAG test reset. Active low.
Ethernet Physical Interface Pins
Name WANRXP WANRXM WANTXM WANTXP WANFXSD/ DOUT Type(1) Description receive signal (differential). receive signal (differential). transmit signal (differential). transmit signal (differential). fiber signal detect. Signal detect input when port operated 100BASE-FX 100Mb fiber mode. DOUT: factory analog test mode.
Note: Input. Output. Bidirectional. Output normal mode; input during reset.
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Type(1)
Ethernet Physical Interface Pins
Name LANRXP[4:1] Description Port[4:1] receive signal (differential).
LANRXM[4:1]
Port[4:1] receive signal (differential).
LANTXP[4:1]
Port[4:1] transmit signal (differential).
LANTXM[4:1]
Port[4:1] transmit signal (differential).
ISET
transmit output current. Connect ground through 3.01k resistor.
Drivers
Name WLED0/ B0SIZE0 Type(1) Description Normal Mode: indicator Programmable misc. Control register bits [2:0]. `000' Speed; `001' Link; `010' Full/half duplex; `011' Collision; `100' TX/RX activity; `101' Full-duplex collision; `110' Link/Activity. During reset: Bank Data Access Size. Bank used boot program. B0SIZE[1:0] used specify size bank data width follows: `01' byte, `10' half-word, `11' word, `00' reserved. WLED1/ B0SIZE1 Normal Mode: indicator Programmable Misc. Control register bits [6:4]. `000' Speed; `001'= Link; `010' Full/half duplex; `011' Collision; `100' TX/RX activity; `101' Full-duplex collision; `110' Link/Activity. During reset: Bank data access size. Bank used boot program. B0SIZE[1:0] used specify size bank data width follows: `01' byte, `10' half-word, `11' word, `00' reserved.
Note: Input. Output. Output normal mode; input during reset.
L[4:1]LED0
Port[4:1] indicator Programmable switch control register bits [27:25]. `000' Speed; `001' Link; `010' Full/half duplex; `011' Collision; `100' TX/RX activity; `101' Full-duplex collision; `110' Link/Activity. Port[4:1] indicator Programmable switch control register bits [24:22]. `000' Speed; `001' Link; `010' Full/half duplex; `011' Collision; `100' TX/RX activity; `101' Full-duplex collision; `110' Link/Activity.
L[4:1]LED1
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Type(1)
UART Pins
Name URXD UTXD UDTRN/ DBGENN UDSRN URTSN/ CPUCLKSEL Description UART receive data. UART transmit data. UART data terminal ready. Active low. Debug enable (factory test signal). UART data ready. Active low. Normal mode: UART request send. Active output. During reset: clock select. Select clock source. CPUCLKSEL=0 (normal mode), internal clock output used clock source. CPUCLKSEL=1 (factory test signal), external clock CPUCLK used internal clock source. UART clear send. BIST enable (factory test signal). UART data carrier detect. Scan enable (factory test signal). UART ring indicator. Chip test reset (factory test signal).
UCTSN/ BISTEN UDCDN/ SCANEN URIN/ TSTRST
General Purpose Pins
Note: Input. Output. Bidirectional. Output normal mode; input during reset.
Name GPIO0/ EINT0 GPIO1/ EINT1 GPIO2/ EINT2 GPIO3/ EINT3 GPIO4/ TOUT0 GPIO5/ TOUT1 GPIO6 GPIO7
Type(1)
Description General purpose pin/external interrupt request pin. General purpose pin/external interrupt request pin. General purpose pin/external interrupt request pin. General purpose pin/external interrupt request pin. General purpose pin/timer output pin. General purpose pin/timer output pin. General purpose pin. General purpose pin.
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Type(1)
Reserved Pins
Name TEST3 TEST4 TEST5 TEST6 TEST7 TEST8 TEST9 TEST10 TEST11 TEST12 TEST13 TEST14 TEST15 TEST16 TEST17 TEST18 TEST19 Description Reserved Pins serve connect order ensure correct operation device. connect signal these pins. connect. connect. connect. connect. connect. connect. connect. connect. connect. connect. connect. connect. connect. connect. connect. connect.
Advanced Memory Interface (SDRAM/ROM/FLASH/SRAM/EXTERNAL I/O)
Note: Input. Output. connect.
SDICLK SDOCLK ADDR21/BA1 ADDR20/BA0 ADDR[19] ADDR[18] ADDR[17] ADDR[16] ADDR[15] ADDR[14] ADDR[13] ADDR[12] ADDR[11] ADDR[10] ADDR[9] ADDR[8] ADDR[7] ADDR[6] ADDR[5] ADDR[4] ADDR[3] ADDR[2] ADDR[1] ADDR[0]
SDRAM Clock SDRAM clock input SDRAM memory controller interface. System/SDRAM Clock Out: Output internal system clock, also used clock signal SDRAM interface. Address 21/Bank Address Input Address asynchronous accesses. Bank Address Input SDRAM accesses. Address 20/Bank Address Input Address asynchronous accesses. Bank Address Input SDRAM accesses. Address Bus: 22-bit address (including ADDR[21:20] above) covers word memory space shared ROM/SRAM/FLASH, SDRAM, external banks. During SDRAM cycles, internal address used generate addresses SDRAM. number column address bits SDRAM banks programmed from bits SDRAM control registers. ADDR[12:0] SDRAM address, ADDR[21:20] SDRAM bank address. During other cycles, ADDR[21:0] byte address data transfer. Note: address pinout non-sequential design. optimized board level connections SDRAM.
SDRAM ROM/SRAM/Flash, connect ADDR[0] memory, ADDR[1] memory, forth. Address mapping 8-bit, 16-bit, 32-bit access. external devices, system designer must connect address lines conventionally 8-bit, 16-bit, 32-bit access.
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Note: Output. Bidirectional.
Name DATA[31] DATA[30] DATA[29] DATA[28] DATA[27] DATA[26] DATA[25] DATA[24] DATA[23] DATA[22] DATA[21] DATA[20] DATA[19] DATA[18] DATA[17] DATA[16] DATA[15] DATA[14] DATA[13] DATA[12] DATA[11] DATA[10] DATA[9] DATA[8] DATA[7] DATA[6] DATA[5] DATA[4] DATA[3] DATA[2] DATA[1] DATA[0] SDCSN[1] SDCSN[0] SDRASN SDCASN SDWEN SDQM[3] SDQM[2] SDQM[1] SDQM[0] ECSN[2] ECSN[1] ECSN[0] Type Description External DATA Bus. 32-bit bidirectional data data transfer. KS8695X also supports 16-bit data widths.
SDRAM Chip Select: Active chip select pins SDRAM. KS8695X supports SDRAM banks. SDCSN output provided each bank. SDRAM Address Strobe: Active low. address strobe SDRAM. SDRAM Column Address Strobe: Active low. column address strobe SDRAM. SDRAM Write Enable: Active low. write enable signal SDRAM. SDRAM Data Input/Output Mask: Data input/output mask signals SDRAM. SDQM sampled high output mask signal write accesses output enable signal read accesses. Input data masked during write cycle. SDQM0/1/2/3 correspond XDATA[7:0], XDATA[15:8], XDATA[23:16] XDATA[31:24], respectively. External Device Chip Select: Active low. Three external banks provided external memory mapped operations. Each bank stores 16KB. ECSNx signals indicate which three banks selected.
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Name EWAITN Type(1) Description External wait: Active low. This signal asserted when external device ROM/SRAM/FLASH bank needs more access cycles than those defined corresponding control register. ROM/SRAM/FLASH chip select: Active low. KS8695X access external ROM/SRAM/FLASH memory banks. RCSN pins controlled addresses into physical memory banks. Normal mode: External ROM/SRAM/FLASH output enable: Active low. When asserted, this signal controls output enable port specified memory device. During reset: Watchdog timer reset polarity setting. WRSTPLS=0, Active low; WRSTPLS active high. default.
RCSN[1] RCSN[0] EROEN/ WRSTPLS
ERWEN0/ TESTACK ERWEN1/ TESTREQB ERWEN2/ TESTREQA ERWEN3/ TICTESTENN WLED0/ B0SIZE0
External ROM/SRAM/FLASH write byte enable: Active low. When asserted, ERWENx controls byte write enable memory device (except SDRAM). test signal (factory test signal). External ROM/SRAM/FLASH write byte enable: Active low. When asserted, ERWENx controls byte write enable memory device (except SDRAM). test signal (factory test signal). External ROM/SRAM/FLASH write byte enable: Active low. When asserted, ERWENx controls byte write enable memory device except SDRAM). test signal (factory test signal). External ROM/SRAM/FLASH write byte enable. Active low. When asserted, ERWENx controls byte write enable memory device (except SDRAM). test signal (factory test signal). Normal mode: indicator Programmable misc. Control register bits [2:0]. Speed; Link; Full/half duplex; Collision; TX/RX activity; Full-duplex collision; Link/Activity. During reset: Bank data access size. Bank used boot program. B0SiZE[1:0] used specify size bank data width follows: `01' byte, `10' half-word, `11' word, `00' reserved.
WLED1/ B0SIZE1
Normal mode: indicator Programmable Misc. Control register bits [6:4]. Speed; Link; Full/half duplex; Collision; TX/RX activity; Full-duplex collision; Link/Activity. During reset: Bank data access size. Bank used boot program. B0SIZE[1:0] used specify size bank data width follows: `01' byte, `10' half-word, `11' word, `00' reserved.
Factory Test Pins
Note: Input. Output. Output normal mode; input during reset.
Name TESTEN TEST1 TEST2
Type(1)
Description Chip test enable: (factory test signal), pull down used. test pin: (factory test signal). test pin: (factory test signal).
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Type(1)
Power Ground Pins
Note: Power supply. Ground.
Name VDDA-PLL VDDAT VDDAR
Description 1.8V analog PLL. 2.5V/3.3V analog VDD. These pins voltage either 2.5V 3.3V. 1.8V analog VDD.
VDD-CORE
1.8V digital core VDD.
VDD-IO
3.3V digital circuitry VDD.
VSS-CORE
Digital core VSS.
VSS-IO
Digital VSS.
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Note: Ground.
Name GNDA Type(1) Description Analog Ground.
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Address Register Description
Memory
Upon power KS8695X memory configured shown below.
Address Range 0x03FF0000-0x03FFFFFF 0x02000000-0x03FEFFFF 0x00000000-0x01FFFFFF Region 64KB 32MB 32MB Description KS8695X System Configuration Register Space Configured Flash Bank
Memory Example
default base address KS8695X system configuration registers 0x03ff0000. After power user free remap memory their specific application. following example memory space remapped operation.
Address Range 0x03FF0000-0x03FFFFFF 0x02900000-0x03FEFFFF 0x02100000-0x028FFFFF 0x00100000-0x020FFFFF 0x00000000-0x0007FFFF Region 64KB 23MB 32MB 512KB Description KS8695X System Configuration Register Space Spare (External I/O) FLASH SDRAM SRAM
Register Description
KS8695X system configuration registers (SCRs) located block 64KB host memory address space. After power initialization, user remap SCRs desired offset. SCRs bits wide. They wordaligned must accessed using word instructions. description KS8695X system configuration registers follows. definitions, please detailed "Register Description" section.
Address System Registers 0x0000 0x0004 System Configuration Register System Clock Control Register [31:0] [31:0] Description Mode Size
Memory Controller Interface Registers 0x4000 0x4004 0x4008 0x4010 0x4014 0x4020 0x4030 0x4034 0x4038 0x403C 0x4040 External Access Control Register External Access Control Register External Access Control Register ROM/SRAM/FLASH Control Register ROM/SRAM/FLASH Control Register ROM/SRAM/FLASH General Register SDRAM Control Register SDRAM Control Register SDRAM General Control Register SDRAM Buffer Control Register SDRAM Refresh Timer Register [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0]
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Registers Address 0x6000 0x6004 0x6008 0x600C 0x6010 0x6014 0x6018 0x601C 0x6080 0x6084 0x6088 0x608C 0x6090 0x6094 0x6098 0x609C 0x60A0 0x60A4 0x60A8 0x60AC 0x60B0 0x60B4 0x60B8 0x60BC 0x60C0 0x60C4 0x60C8 0x60CC 0x60D0 0x60D4 0x60D8 0x60DC 0x60E0 0x60E4 0x60E8 0x60EC 0x60F0 0x60F4 0x60F8 0x60FC Description Transmit Control Register Receive Control Register Transmit Start Command Register Receive Start Command Register Transmit Descriptor List Base Address Register Receive Descriptor List Base Address Register Station Address Register Station Address High Register Additional Station Address Register Additional Station Address High Register Additional Station Address Register Additional Station Address High Register Additional Station Address Register Additional Station Address High Register Additional Station Address Register Additional Station Address High Register Additional Station Address Register Additional Station Address High Register Additional Station Address Register Additional Station Address High Register Additional Station Address Register Additional Station Address High Register Additional Station Address Register Additional Station Address High Register Additional Station Address Register Additional Station Address High Register Additional Station Address Register Additional Station Address High Register Additional Station Address Register Additional Station Address High Register Additional Station Address Register Additional Station Address High Register Additional Station Address Register Additional Station Address High Register Additional Station Address Register Additional Station Address High Register Additional Station Address Register Additional Station Address High Register Additional Station Address Register Additional Station Address High Register Mode Size [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0]
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Registers Address 0x8000 0x8004 0x8008 0x8010 0x8014 0x8018 0x801C 0x8080 0x8084 0x8088 0x808C 0x8090 0x8094 0x8098 0x809C 0x80A0 0x80A4 0x80A8 0x80AC 0x80B0 0x80B4 0x80B8 0x80BC 0x80C0 0x80C4 0x80C8 0x80CC 0x80D0 0x80D4 0x80D8 0x80DC 0x80E0 0x80E4 0x80E8 0x80EC 0x80F0 0x80F4 0x80F8 0x80FC Description Transmit Control Register Receive Control Register Transmit Start Command Register Transmit Descriptor List Base Address Receive Descriptor List Base Address Station Address Register Station Address High Register Additional Station Address Register Additional Station Address Register High Additional Station Address Register Additional Station Address Register High Additional Station Address Register Additional Station Address Register High Additional Station Address Register Additional Station Address Register High Additional Station Address Register Additional Station Address Register High Additional Station Address Register Additional Station Address Register High Additional Station Address Register Additional Station Address Register High Additional Station Address Register Additional Station Address Register High Additional Station Address Register Additional Station Address Register High Additional Station Address Register Additional Station Address Register High Additional Station Address Register Additional Station Address Register High Additional Station Address Register Additional Station Address Register High Additional Station Address Register Additional Station Address Register High Additional Station Address Register Additional Station Address Register High Additional Station Address Register Additional Station Address Register High Additional Station Address Register Additional Station Address Register High Mode Size [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0]
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UART Registers Address 0xE000 0xE004 0xE008 0xE00C 0xE010 0xE014 0xE018 0xE01C 0xE020 Interrupt Controller Registers Address 0xE200 0xE204 0xE208 0xE210 0xE20C 0xE214 0xE218 0xE21C 0xE220 0xE224 0xE228 0xE22C 0xE230 0xE234 Timer Registers Address 0xE400 0xE404 0xE408 0xE40C 0xE410 General Purpose Registers Address 0xE600 0xE604 0xE608 Description Port Mode Register Port Control Register Port Data Register Mode Size [31:0] [31:0] [31:0] Description Timer Control Register Timer Timeout Count Register Timer Timeout Count Register Timer Pulse Count Register Timer Pulse Count Register Mode Size [31:0] [31:0] [31:0] [31:0] [31:0] Description Interrupt Mode Control Register Interrupt Enable Register Interrupt Status Register Used Interrupt Priority Register Interrupt Priority Register Interrupt Priority Register Timer Interrupt Priority Register UART Interrupt Priority Register External Interrupt Interrupt Priority Register Communications Channel Interrupt Error Response Register Interrupt Mask Status Register Interrupt Pending Highest Priority Register Interrupt Pending Highest Priority Register Mode Size [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] Description UART Receive Buffer Register UART Transmit Holding Register UART FIFO Control Register UART Line Control Register UART Modem Control Register UART Line Status Register UART Modem Status Register UART Baud Rate Divisor Register UART Status Register Mode Size [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0]
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Switch Engine Configuration Registers Address 0xE800 0xE804 0xE808 0xE80C 0xE810 0xE814 0xE818 0xE81C 0xE820 0xE824 0xE828 0xE82C 0xE830 0xE834 0xE838 0xE83C 0xE840 0xE844 0xE848 0xE84C 0xE850 Miscellaneous Registers Address 0xEA00 0xEA04 0xEA08 0xEA0C 0xEA10 Description Device Register Revision Register Used Miscellaneous Control Register Power Management Register Mode Size [31:0] [31:0] [31:0] [31:0] [31:0] Description Switch Engine Control Register Switch Engine Control Register Port Configuration Register Port Configuration Register Port Configuration Register Port Configuration Register Port Configuration Register Ports Auto Negotiation (AN) Register Ports Auto Negotiation (AN) Register Look-up Engine (LUE) Control Register Look-up Engine (LUE) Indirect Register High Look-up Engine (LUE) Indirect Register Advance Feature Control Register DSCP Register High DSCP Register Switch Engine Address Register High Switch Engine Address Register Management Counter Indirect Access Register Management Counter Data Register Ports Power Management Ports Power Management Mode Size [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0]
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Absolute Maximum Ratings(1)
Supply Voltage (VDDAR, VDDA_PLL, VDD_CORE) -0.5V +2.4V (VDDAT, VDD_IO) -0.5V +4.0V Input Voltage (all inputs) -0.5V +4.0V Output Voltage (all outputs) -0.5V +4.0V Lead Temperature (soldering, 10sec.) 270°C Storage Temperature (TS) -55°C +150°C
Operating Ratings(2)
Supply Voltage (VDDAR, VDDA_PLL, VDD_CORE) +1.7V +1.9V (VDDAT)(3) +2.4V +2.6V (VDDAT)(3) +3.135V +3.456V (VDD_IO) +3.0V +3.6V Ambient Temperature (TA) -0°C +70°C Junction Temperature (TJ) 150°C Package Thermal Resistance(4) PQFP (JA) Flow 39.1°C/W
Electrical Characteristics(5)
Symbol Parameter Condition Units Total Supply Current (including output driver current) 100BASE-TX Operation: ports 100% Utilization, SDOCLK 125MHz IRX, IDDC IDDIO IRX, IDDC IDDIO IRX, IDDC IDDIO Inputs Outputs
Notes: Exceeding absolute maximum rating damage device. device guaranteed function outside operating rating. Unused inputs must always tied appropriate logic voltage level (Ground VDD). VDDAT operate from either 2.5V 3.3V supply. heat spreader package. Specification packaged product only.
100BASE-TX (Analog I/O) 100BASE-TX (Analog Digital Core) 100BASE-TX (Digital I/O)
VDDAT +2.5V +3.3V VDDA_PLL, VDDAR, VDD_CORE +1.8V VDD_IO +3.3V VDDAT +2.5V +3.3V VDDA_PLL, VDDAR, VDD_CORE +1.8V VDD_IO +3.3V VDDAT +2.5V +3.3V VDDA_PLL, VDDA, VDD_CORE +1.8V VDD_IO +3.3V
0.220 0.223 0.164
10BASE-TX Operation: ports 100% Utilization, SDOCLK 125MHz 10BASE-TX (Analog I/O) 10BASE-TX (Analog Digital Core) 10BASE-TX (Digital I/O) 0.165 0.333 0.133
Auto-Negotiation Mode: SDOCLK 125MHz 10BASE-TX (Analog I/O) 10BASE-TX (Analog Digital Core) 10BASE-TX (Digital I/O) 0.033 0.216 0.118
Input High Voltage Input Voltage Input Current (Excluding pull-up/pull-down) VDD_IO -8mA
Output High Voltage Output Voltage Output Tri-state Leakage
+0.4V
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Symbol Parameter Condition
Units
100BASE-TX Transmit (measured differentially after transformer) VIMB Peak Differential Output Voltage Output Voltage Imbalance Rise/Fall Time Rise/Fall Time Imbalance termination differential output termination differential output 0.95 1.05
100BASE-TX Transmit (measured differentially after transformer) Duty Cycle Distortion Overshoot VSET Reference Voltage ISET Output Jitters 10BASE-TX Receive Squelch Threshold 5MHz square wave Peak-to-peak ±0.5
10BASE-TX Transmit (measured differentially after transformer) VDDAT 2.5V Peak Differential Output Voltage Jitters Added Rise/Fall Time termination differential output termination differential output ±3.5
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Options
standalone SOHO system using KS8695X, Micrel recommends following low-cost bundle: MIC5209BM +1.8V digital supply (VDD_CORE) MIC5209-3.3BS +3.3V digital supply (VDD_IO) analog transmit supply (VDDAT) Since each system have different power requirement, sure contact your Micrel sales representative Field Application Engineer help find cost-effective solution your project.
VDDAT
V1.8PLL
Ferrite Bead
Ferrite Bead 100µF 10nF 0.1µF 22µF 0.1µF 10nF
VDD_IO
V5.0 MIC5209-3.3BS
Ferrite Bead
V1.8A
100µF
0.1µF
100µF
10nF
0.1µF
Ferrite Bead 100µF 0.1µF 0.1µF
V5.0
MIC5209BM
V1.8 (VDD_CORE)
Ferrite Bead
1.5K 100µF 0.1µF 100µF 0.1µF 0.1µF
Figure Low-Cost Option
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Timing Diagrams
Supply Voltages RESETN Strap-In Strap-In Output
Figure Reset Timing
Symbol
Parameter Stable supply voltages reset high Configuration set-up time Configuration hold time Reset strap-in output
Units
Table Reset Timing Parameters
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Figure Static/Flash Memory Read Cycle
Figure Static/Flash Memory Write Cycle
Symbol Tcta Tcos Taac Tdsu Tcws Tcah Tocs Toew Twcs
Parameter Valid address setup time valid setup time Address access time Valid read data setup time valid setup time Address hold time Rising edge hold time pulsewidth Rising edge hold time
RBiTACC
RBiTACC
Units
+1.0
RBiTACC RBiTACC RBiTACC
Table Static/Flash Memory Timing Parameters
Symbol
RBiTACC
Note:
Parameter(1) Programmable bank access time
Registers 0x4010, 0x4014
Table Programmable Static Memory Timing Parameters
Refers chip select parameters
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Figure External Read Write Cycles
Symbol Tcta Tcos Tdsu Tcws Tcah Toew Tocs, Tcsw
Parameter Valid address setup valid setup time Valid read data setup time valid setup time write data hold time ADDR hold time OE/WE pulsewidth Rising edge OE/WE hold time
Min(1) +0.8 +0.6
Typ(1) +1.1 +0.6
Max(1) +1.3 +1.0
Units
EBiTACS EBiTACS EBiTACS EBiTCOS EBiTCOS EBiTCOS
EBiTCOS EBiTCOS EBiTCOS
+0.6
+0.6
+1.0
EBiTCOH EBiTCOH EBiTCOH
+1.0
EBiTACT
+1.0
+1.4
EBiTACT
Table External Memory Timing Parameters
Note: Measurements minimum were taken 0oC, typical 25oC, maximum 100oC.
Symbol
EBiTACS EBiTACT EBiTCOS EBiTCOH
Parameter(1) Programmable bank address setup time before chip select Programmable bank write enable/output enable access time Programmable bank chip select setup time before Programmable bank chip select hold time
Registers 0x4000, 0x4004, 0x4008 0x4000, 0x4004, 0x4008 0x4000, 0x4004, 0x4008 0x4000, 0x4004, 0x4008
Table Programmable External Timing Parameters
Note: Refers chip select parameters
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Figure SDRAM Read Timing
Figure SDRAM Write Timing
Symbol
SDTRC
Parameter Programmable SDRAM CASE Latency Programmable SDRAM Latency
Registers 0x4038 0x4038
SDCAS
Table SDRAM Timing Parameters October 2004 M9999-102604
KS8695X
Symbol SDRAM Parameter Signals Rise Time Clock rise time Address rise time Bank select rise time Data rise time Chip select rise time rise time rise time rise time rise time
Units
SDRAM Signal Fall Time Clock fall time Address fall time Bank select fall time Data fall time Chip select fall time fall time fall time fall time fall time
SDRAM Timing Specifications Clock-to-chip select output delay Clock-to-chip select hold time Clock-to-address high-to-low Clock-to-address low-to-high Clock-to-bank select high-to-low Clock-to-bank select low-to-high Clock-to-RAS output delay Clock-to-RAS hold time Clock-to-CAS output delay Clock-to-CAS hold time Clock-to-WE output delay Clock-to-WE hold time Clock-to-DQM output delay Clock-to-DQM hold time Clock-to-data output delay Clock-to-data hold time
Table SDRAM Interface Timing
Symbol RBiTPACC RBiTPA Parameter Programmable bank access time Programmable bank page address access time Registers 0x4010, 0x4014 0x4010, 0x4014
Table Static Memory Timing Parameters M9999-102604 October 2004
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Package Information
208-Pin PQFP (PQ)
MICREL, INC.
2180 FORTUNE DRIVE JOSE, 95131
(408) 944-0800
(408) 474-1000
http://www.micrel.com
information furnished Micrel this data sheet believed accurate reliable. However, responsibility assumed Micrel use. Micrel reserves right change circuitry specifications time without notification customer. Micrel Products designed authorized components life support appliances, devices systems where malfunction product reasonably expected result personal injury. Life support devices systems devices systems that intended surgical implant into body support sustain life, whose failure perform reasonably expected result significant injury user. Purchaser's sale Micrel Products life support appliances, devices systems Purchaser's risk Purchaser agrees fully indemnify Micrel damages resulting from such sale. 2004 Micrel, Incorporated.
October 2004
M9999-102604

KS8695X Integrated Multi-Port High-Performance Gateway Solutions

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