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STD110 0.25µm 2.5V CMOS Standard Cell Library Pure Logic Products Data


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STD110 0.25µm 2.5V CMOS Standard Cell Library Pure Logic Products
STD110 0.25µm 2.5V CMOS Standard Cell Library Pure Logic Products Data Book 1999-2000 Samsung Electronics Co., Ltd. rights reserved. part this document reproduced, form means, without prior written consent publisher. Samsung assumes responsibility errors resulting from information contained herein, does convey license under patent rights Samsung others. Samsung reserves right make changes products product specification improve function design time, without notice. STD110 trademarks Samsung Electronics Co., Ltd. Verilog registered trademark Cadence Design Systems, Inc. Viewlogic registered trademark Viewlogic Systems, Inc. Mentor registered trademark Mentor Graphics Synopsys registered trademark Synopsys, Inc.
Head Office Samsung Electronics Co., System Business, ASIC Division, Design Technology #24, Nongseo-Ri, Kiheung-Eup, Yongin-City, Kyunggi-Do, Korea 82-2-760-6500, 6501 (Hot Line) 82-331-209-4920 http://www.intl.samsungsemi.com Printed Republic Korea
Marketing Team Samsung Electronics Co., System Business, ASIC Division, ASIC Marketing Team #24, Nongseo-Ri, Kiheung-Eup, Yongin-City, Kyunggi-Do, Korea 82-2-331-209-1930 82-2-331-209-1919
Introduction
This databook contains information about STD110 0.25µm 2.5V standard cell library pure Logic products developed (Samsung Electronics Corporation). "library" basically contains various kinds internal cells soft-macros which used developing ASIC (Application Specific Integrated Circuit). also includes design helping designers work workstation platform, sorts design environments needed automatic chip design. There seven chapters this databook: Chapter Chapter Chapter Chapter Chapter Chapter Introduction Electrical Characteristics Internal Macrocells Input/Output Cells Compiled Macrocells
this databook each cell followed electrical characteristics, these characteristic values almost equal when corresponding cell operated real chip. purpose this databook prevent misuse misapplication STD110 cell library providing precise information about cell list, electrical data, directions use, matters demanding special attention. want more information about Digital cores Analog cores that included this databook, access Samsung ASIC contact Head Office.
ASIC
STD110
Contents
Introduction
Library Description .1-1 Features .1-2 Support .1-4 Product Family .1-4 1.4.1 Analog Core Cell.1-4 1.4.2 Internal Macrocells.1-12 1.4.3 Compiled Macrocells.1-12 1.4.4 Input/Output Cells .1-13 Timings.1-16 Delay Model .1-22 Testability Design Methodology.1-24 Maximum Fanouts .1-27 Packages Capability Lead Count .1-34 1.10 Power Dissipation.1-36 1.11 VDD/VSS Rules Guidelines.1-39 1.12 Crystal Oscillator Considerations .1-45
Electrical Characteristics
Electrical Characteristics.2-1
Internal Macrocells
Overview .3-1 Summary Tables .3-2 Logic Cells AD2DH/AD2/AD2D2/AD2D4 .3-17 AD3DH/AD3/AD3D2/AD3D4 .3-19 AD4DH/AD4/AD4D2/AD4D4 .3-21 AD5/AD5D2/AD5D4 .3-24 ND2DH/ND2/ND2D2/ND2D4 .3-27 ND3DH/ND3/ND3D2/ND3D4 .3-29 ND4DH/ND4/ND4D2/ND4D2B/ND4D4 .3-32 ND5/ND5D2/ND5D4.3-35 ND6/ND6D2/ND6D4.3-38
ASIC
STD110
Contents ND8/ND8D2/ND8D4 .3-42 .3-46 .3-49 NR4DH/NR4/NR4D2/NR4D2B/NR4D4 .3-53 NR5/NR5D2/NR5D4 .3-56 NR6/NR6D2/NR6D4 .3-60 NR8/NR8D2/NR8D4 .3-64 OR2DH/OR2/OR2D2/OR2D4 .3-68 OR3DH/OR3/OR3D3/OR3D4 .3-70 OR4DH/OR4/OR4D2/OR4D4 .3-73 OR5/OR5D2/OR5D4 .3-76 XN2/XN2D2/XN2D4 .3-80 XN3/XN3D2/XN3D4 .3-82 XO2/XO2D2/XO2D4 .3-84 XO3/XO3D2/XO3D4 .3-86 .3-88 .3-91 AO2111/AO2111D2 .3-94 .3-97 AO22DHA/AO22A/AO22D2A/AO22D4A .3-100 AO221/AO221D2/AO221D4.3-103 AO222A/AO222D2A/AO222D4A.3-112 AO2222/AO2222D2/AO2222D4.3-114 AO31DH/AO31/AO31D2/AO31D4.3-118 AO311/AO311D2/AO311D4.3-121 AO3111/AO3111D2 .3-125 AO32/AO32D2/AO32D4.3-128 AO321/AO321D2/AO321D4.3-132 AO322/AO322D2/AO322D4.3-136 AO33/AO33D2/AO33D4.3-140 AO331/AO331D2/AO331D4.3-144 AO332/AO332D2/AO332D4.3-148 AO4111/AO4111D2 .3-152 .3-155 .3-158 OA2111/OA2111D2 .3-161 .3-164 OA22DHA/OA22AOA22D2A/OA22D4A .3-167 OA221/OA221D2/OA221D4.3-170 OA2222/OA2222D2/OA2222D4.3-179 OA31/OA31D2/OA31D4.3-183
STD110
ASIC
Contents OA311/OA311D2/OA311D4.3-186 OA3111/OA3111D2 .3-190 OA32/OA32D2/OA32D4.3-193 OA321/OA321D2/OA321D.3-197 OA322/OA322D2/OA322D4.3-201 OA33/OA33D2/OA33D4.3-205 OA331/OA331D2/OA331D4.3-209 OA332/OA332D2/OA332D4.3-213 OA4111/OA4111D2 .3-217 SCG1/SCG1D2 .3-220 SCG2//SCG2D2 .3-223 SCG3/SCG3D2 .3-225 SCG4/SCG4D2 .3-228 SCG5/SCG5D2 .3-231 SCG6/SCG6D2 .3-234 SCG7/SCG7D2 .3-236 SCG8/SCG8D2 .3-239 SCG9/SCG9D2 .3-241 SCG10/SCG10D2 .3-243 SCG11/SCG11D2 .3-246 SCG12/SCG12D2 .3-248 SCG13/SCG13D2 .3-250 SCG14/SCG14D2 .3-252 SCG15/SCG15D2 .3-254 SCG16/SCG16D2 .3-256 SCG17/SCG17D2 .3-258 SCG18/SCG18D2 .3-260 SCG19/SCG19D2 .3-263 SCG20/SCG20D2 .3-265 SCG21/SCG21D2 .3-267 SCG22/SCG22D2 .3-269 DL1D2/DL1D4 .3-271 DL2D2/DL2D4 .3-272 DL3D2/DL3D4 .3-273 DL4D2/DL4D4 .3-274 DL5D2/DL5D4 .3-275 DL10D2/DL10D4 .3-276 .3-277 IVT/IVTD2/IVTD4/IVTD8/IVTD16 .3-282 .3-284 .3-286 OAK_NID10P/OAK_NID20P .3-289
ASIC
STD110
Contents NIT/NITD2/NITD4/NITD8/NITD16 .3-290 .3-293 OAK_DUCLK10/OAK_DUCLK16.3-296 Flip-Flops FD1/FD1D2 .3-303 FD1CS/FD1CSD2 .3-305 FD1S/FD1SD2 .3-307 FD1SQ/FD1SQD2.3-309 FD1Q/FD1QD2 .3-311 FD2/FD2D2 .3-313 FD2CS/FD2CSD2 .3-315 FD2S/FD2SD2 .3-319 FD2SQ/FD2SQD2.3-321 FD2Q/FD2QD2 .3-323 FD3/FD3D2 .3-325 FD3CS/FD3CSD2 .3-327 FD3S/FD3SD2 .3-331 FD3SQ/FD3SQD2.3-333 FD3Q/FD3QD2 .3-335 FD4/FD4D2 .3-337 FD4CS/FD4CSD2 .3-340 FD4S/FD4SD2 .3-344 FD4SQ/FD4SQD2.3-348 FD4Q/FD4QD2 .3-351 FD5/FD5D2 .3-353 FD5S/FD5SD2 .3-355 FD6/FD6D2 .3-357 FD6S/FD6SD2 .3-359 FD7/FD7D2 .3-361 FD7S/FD7SD2 .3-363 FD8/FD8D2 .3-365 FD8S/FD8SD2 .3-368 FDS2/FDS2D2 .3-372 FDS2CS/FDS2CSD2 .3-374 FDS2S/FDS2SD2 .3-376 FDS3/FDS3D2 .3-378 FDS3CS/FDS3CSD2 .3-380 FDS3S/FDS3SD2 .3-382 FJ1/FJ1D2.3-384 FJ1S/FJ1SD2 .3-386 FJ2/FJ2D2.3-388
STD110
viii
ASIC
Contents FJ2S/FJ2SD2 .3-390 FJ4/FJ4D2.3-392 FJ4S/FJ4SD2 .3-395 FT2/FT2D2 .3-398 Latches LD1/LD1D2 .3-402 LD1A/LD1D2A.3-404 LD1Q/LD1QD2 .3-406 LD2/LD2D2 .3-408 LD2Q/LD2QD2 .3-411 LD3/LD3D2 .3-413 LD4/LD4D2 .3-416 LD5/LD5D2 .3-419 LD5Q/LD5QD2 .3-421 LD6/LD6D2 .3-423 LD6Q/LD6QD2 .3-426 LD7/LD7D2 .3-428 LD8/LD8D2 .3-431 OAK_LDI2/OAK_LDI2D2 .3-434 OAK_LDI3/OAK_LDI3D2 .3-437 LS0/LS0D2 .3-442 LS1/LS1D2 .3-444 Holder BUSHOLDER .3-448 Internal Clock Drivers CK(2/4/6/8) .3-449 Decoders .3-452 DC4I .3-454 DC8I .3-456 Adders FADH/FA/FAD2.3-461 HADH/HA/HAD2.3-464 SCG23/SCG23D2 .3-467 Multiplexers MX2DH/MX2/MX2D2/MX2D4 .3-471 MX2X4 .3-474 MX2IDH/MX2I/MX2ID2/MX2ID4 .3-477
ASIC
STD110
Contents MX2IX4 .3-483 MX3I/MX3ID2/MX3ID4 .3-486 MX4/MX4D2/MX4D4 .3-490 MX8/MX8D2/MX8D4 .3-494
Input/Output Cells
Overview .4-1 Summary Tables .4-2 Input Buffers PvIC/PvICD/PvICU.4-9 PvIS/PvISD/PvISU .4-13 PvIT/PvITD/PvITU .4-17 Output Buffers PvOByz .4-21 PvODyz .4-30 PvOTyz .4-40 Bi-Directional Buffers PvBaDyz/PvBaUDyz .4-60 PvBaTyz/PvBaDTyz/PvBaUTyz .4-60 Input Clock Drivers PSCKDCaby.4-62 PSCKDSaby.4-66 Oscillators PHSOSC(K1/K2/M1/M2/M3) .4-71 PHSOSC(K17/K27/M16/M26/M36) .4-77 PSOSC(K1/K2/M1/M2) .4-83 Buffers PTIPCI.4-90 PTOPCI .4-91 PTBPCI .4-92 Buffers PBUSB/PBUSB1 .4-95 PBUSB_LS.4-96 PBUSB_FS.4-97
STD110
ASIC
Contents Power Pads .4-104 .4-104 Analog Interface PIC_ABB .4-106 PICC_ABB .4-107 PICEN_ABB .4-108 POT_ABB.4-109 Slot Cells EV2I_ABB/EV2OP_ABB/EV2T_ABB .4-112 Common Slot Cells .4-113
Compiled Macrocells
Overview Compiled Memory .5-1 Compiled Memory Naming Convention.5-1 Characteristics Timing Power.5-2 Built-In Self Test Compiled Memory .5-3 Selection Guide Compiled Memory.5-4 High-Density Compiled Memory SPSRAM_HD .5-7 SPSRAMBW_HD .5-17 DPSRAM_HD .5-27 SPARAM_HD .5-37 DROM_HD .5-48 MROM_HD.5-56 ARFRAM_HD .5-64 FIFO_HD .5-83 Low-Power Compiled Memory SPSRAM_LP .5-95 DPSRAM_LP .5-105 SPARAM_LP .5-115 DROM_LP .5-125 MROM_LP.5-133
ASIC
STD110
Contents Overview Compiled Datapath Overview Compiled Datapath .5-141 Compiled Macrocell Selection Guide .5-142 ADDER.5-143 .5-148 .5-153
PLL2013X .6-1
STD110
ASIC
NOTE
Introduction
Table Contents
Library Description Features Support Product Family. 1.4.1 Analog Core Cells. 1.4.2 Internal Macrocells 1-12 1.4.3 Compiled Macrocells 1-12 1.4.4 Input/Output Cells 1-14 Timings. 1-16 Delay Model 1-22 Testability Design Methodology. 1-24 Maximum Fanouts. 1-27 Packages Capability Lead Count 1-34 1.10 1.11 Power Dissipation 1-36 VDD/VSS Rules Guidelines 1-39
1.12 Crystal Oscillator Considerations. 1-45
Introduction
Library Description
Library Description
ASIC offers STD110 0.25um CMOS standard cell library. SEC's 0.25um cell-based logic process providing layers interconnect metal with various pad-pitch options such 70um pitch 80um pitch pad. STD110 which reduced power dissipation system cost merging logic whole connecting internally from logic memory data ideal high-performance products such graphics controller, projector, portable STD110 support eight million gate counts logic providing usable gate. STD110 faster than 0.35um library MDL90. Logic density times greater than that MDL90. power consumption compiled memory smaller than MDL90. STD110 also supports fully user-configurable compiled memory datapath elements. Each element provided compiler. different types compiled memories STD110 available support memories suitable high-density low-power applications. support mixed voltage environments, 2.5V, 3.3V drive 5V-tolerant cells available. LVTTL, LVCMOS, PCI, OSC, AGP, PECL, HSTL, LVDS buffers supported. better support system-on-chip design style, various core cells available including processor cores like ARM7TDMI/ARM9TDMI/ ARM920T/ARM940T from ARM, Teaklite from DSPG. STD110 supports data transmission communication core such USB, IEEE1284 UART. list analog core cells includes ADC, DAC, CODEC, LVDS, RAMDAC with various bits frequency ranges. design methodology offers comprehensive timing driven design flow including automated time budgeting, tight floorplan synthesis intergration, powerful timing analysis timing driven layout. advanced characterization flow provides accurate timing data robust delay models 0.25um very deep-submicron technology. Advanced verification methods like static timing analysis formal verification provide effective verification methodology with variety simulators cycle based simulation. methodology supports scan design, BIST JTAG boundary scan. provides full test-ready with efficient core test integration methodology.
ASIC
STD110
Features
Introduction
Features
2.5V standard cell library including processor analog cores 0.25um five layer metal(from four layer metal option) CMOS technology Logic, processor analog High basic cell usages million gates Maximum usage: five layer metal High speed Typical 2-input NAND gate delay (ND2D4): 70ps (F/O=2 (0.02pF)) Operation temperature (TA) Commercial range: +70°C Industrial range: -40°C +85°C Digital cores usages Hard-macro: ARM7TDMI, ARM9TDMI, ARM920T, ARM940T, Oak, Teaklite Soft-macro: AMBA, Controller, SDRAM Controller, Interrupt Controller, IIC, WDT, RTC, USB, IrDA, UART(16C450, 16C550), Fast Ethernet MAC, P1394a LINK, Decoder, Viterbi Decoder Analog cores usages Ultra voltage analog core (2.5V 1.8V) available Analog core supply voltage: 2.5V analog core: 2.5V 1.8V analog core: 1.8V ADC: 8bit (30M, 2.5V), 10bit ((30M, 100M, 2.5V), (250K, 20M, 1.8V)), 12bit (200K, 20M, 2.5V) DAC: 8bit (2M, 2.5V), 10bit ((300M, 2.5V), (2M, 1.8V)), 12bit ((2M, 2.5V), (80M, 1.8V)) CODEC: 8bit (8K~11K), 16bit (44.1K) PLL: 300M (FSPLL, 2.5V), (PLL, 1.8V), 170M(FSPLL, 1.8V) Others: 300M (RAMDAC+PLL) Fully user-configurable Static RAMs ROMs High-density low-power memory available Duty-free cycle synchronous memory available 2-bank architecture available Flexible aspect ratio available 256K-bit single-port SRAM available. 128K-bit dual-port SRAM available. 512K-bit diffusion metal-2 available. 16K-bit multi-port register file available. 32K-bit FIFO available. Fully configurable datapath macrocells adder available barrel shifter available multiplier with 1-stage pipeline available Various output driver strength available tightly integrate apollo, Avant!, design environment cells 2.5V/3.3V tolerant 3-level (high, medium, slew rate control 1/2/4/6/8/10/12mA available 3.3V 2.5V output buffers 1/2/3mA available 5V-tolerant output buffers
STD110
ASIC
Introduction
Features
available ((33MHz, 66MHz, 3.3V), (33MHz, 3.3/5V tolerant)) (full speed/low speed) SSTL2 (DDR SDRAM interface, 200MHz) (AGP2.0 Compliant, 66MHz@1X,133MHz@2X, 266MHz@4X) PECL (2.5V interface, 400MHz) HSTL (class1, class2, 30MHz) LVDS (3.3V(2.5V optional) interface, 300MHz) Various package options QFP, thin QFP, power QFP, plastic BGA, super BGA, plastic leaded chip carrier, etc. Fully integrated software support Logic synthesis: Synopsys Design Compiler Logic simulation: Cadence Verilog-XL, Cadence NC-Verilog, Viewlogic ViewSim, Mentor ModelSim-VHDL, Mentor ModelSim-Verilog, Synopsys VSS, Synopsys Scan insertion ATPG: Synopsys TestGen, Synopsys Test Compiler, Mentor Fastscan Static timing analysis: Synopsys PrimeTime, Synopsys MOTIVE analysis: Avant! Star-RC Power analysis: Synopsys DesignPower, CubicPower (ln-House Tool) Formal verification: Synopsys Formality, Chrysalis Design VERIFYer, Verplex Tuxedo-LEC Fault simulation: Cadence Verifault, SuperTest (In-House Tool) Delay calculator: CubicDelay (In-House Tool)
STD110 contains user selectable clock tree cells(CTC). pre-layout design stage, these will used cells which represent actual clock tree informatin P&R. features ASIC flow follows: user selectable clock tree cells(CTC) STD110 Good pre-layout post-layout correlation customer netlist modification Accurate post-layout back-annotation mechanism Insertion delay, skew, transition time management Clock tree information file generation Cover 30,000 fanouts gate count spanning block (GCCSB) Tightly coupled with in-house delay calculator, CubicDelay Gated support Hierarchical/Flatten verilog, edif interface more detail information flow, refer "CTC flow guideline CubicDelay" included ASIC design kit.
ASIC
STD110
Support
Introduction
Support
ASIC provides efficient solution multi-million gate ASICs very deep submicron (VDSM) technology. large system-on-chip (SOC) type designs, static verification methodology (static timing analysis formal verification) will shorten your design cycle time, which turn will lessen today's ever-increasing time-to-market pressure. Design-for-Test (DFT) methodology service take through phases test insertion, test pattern generation fault grading high test coverage. STD110 supports rich collection industry-standard tools from Cadence, Synopsys, Mentor graphics, Avant! multiple design platforms such Solaris Customers allowed choose among industry-leading tools from design capture, synthesis, simulation, layout. Several powerful proprietary software tools seamlessly integrated design kits improve your product quality. high simulation accuracy, STD110 uses proprietary delay calculator. Cell delay calculated based matrix delay parameters each macrocell, signal interconnect delay calculated based tree analysis.
Product Family
STD110 library include following design elements: Analog core cells Digital core cells Internal macrocells Compiled macrocells Input/Output cells. 1.4.1 ANALOG CORE CELLS Introduction Analog Cores ASIC leading suppliers cell based mixed analog digital designs. leading supplier mixed analog digital designs, ASIC more analog design experience than other vendors. Analog been will continue part strategic focus ASIC. Analog design part total ASIC integrated design system. Workstation symbols supplied analog cells entered part design customer design center. ASIC uses basically same automatic layout verification tools analog cells digital cells. Analog designs processed same production line digital designs. SEC's analog core family comprises ADC,DAC,PLL sigma-delta ADC/DAC, their brief functional descriptions introduced below. [data sheets analog cores available] Analog-to-Digital Converters Analog-to-digital converters provide link between analog world digital systems. their extensive analog mixed analog-digital operations, converters often appear bottleneck data processing applications, limiting overall speed precision. converter produces digital output, function analog input, f(A) While input assume infinite number values, output selected from only finite codes given converter's output word length(i.e, resolution). Thus, must approximate each input level with these codes, this process called 'quantization'.
STD110
ASIC
Introduction
Product Family
digital system amplitude quantized into discrete steps, same time signal sampled discrete time intervals. This time interval called sampling time sampling frequency. After sampling quantization process, analog signal(A) becomes digital output (D). Digital-to-Analog Converters converters digital-to-analog conversion circuits, which also called DACs. They considered decoding devices that accept digitally coded signals provide analog output form currents voltages. this manner, they provide interface between digital signal computer systems continuous signals analog world. They employed variety applications, from display systems voice sythesizers automatic test systems, digital controlled attenuators, process control actuators. addition, they components inside most converters. Figure shows functional block diagram basic converter system. input converter digital word, made stream binary bits comprised 0's. output analog quantity which voltage current, related input KVREF where scale factor, VREF reference voltage, total number bits, b1,b2,.,bn coefficients, which quntized function input binary word which determines coefficients, output exhibits discrete voltage level ranging from zero maximum value
Vo(max)= VREF
with minimum step change given
Figure 1-1.
Functional Block Diagram Basic Converter
Digital Data Input
Converter
Analog Output
ASIC
STD110
Product Family
Introduction
Sigma-Delta ADC/DAC VLSI offers high speed high density, reduced accuracy analog components reduced signal range (reduced dynamic range). Hence, exchange digital complexity resolution time resolution signal amplitude needed. good solution over-sampling data converter. Oversampling sigma-delta converter used slow speed (audio band) application because process limit. It's noise shaping (sigma-delta) feature make high resolution about max. SND=90~100dB path, analog single input converted differential signal with anti-aliasing filtering through anti-aliasing filter block. sigma-delta modulator converts signal into oversampled noise-shaping 1bit (Pulse Density Modulation). Following digital decimation filter reject band noise outputs 16bits high resolution digital data with down sampled rate. path, digital input data oversampled interpolation filter converted noise-shaped 1bit through digital sigma-delta modulator. Analog SC-post-filter rejects band noise. anti-image filter rejects sampling images outputs single analog signal with high resolution. Phase Locked Loop Samsung's cores implemented analog function provide frequency multiplication capabilities enable system designers synchronize ASIC chip-level clock networks with common reference signal. past, designers wishing incorporate into digital design environment only options: special mixed-signal process incorporate analog functions onto chip digital that incorporated into standard digital process. However, mixed-signal process expensive feasible solution. other hand digital PLLs typically require huge silicon area exhibits poor locking time despite their high accuracy. Differing from previous solutions, Samsung's cores implemented standard digital CMOS process while functioning analog PLL. Samsung's cores: Require only off-chip passive components whole function Remove need expensive mixed-signal process Provide faster locking time than digital PLLs Present jitter characteristics Glossary Core Families Digital-to-Analog Converter
Resolution n-bit binary converter should able provide distinct different analog output values corresponding n-bit binary words. converter that satisfies this criterion said have resolution bits. smallest output change that resolved linear full-scale span. Accuracy Error converter difference between actual analog output output that expected when given digital code applied converter. Source error include gain error, offset error, linearity errors noise. Error usually commensurate with resolution, less than 2-(n+1), full scale.
STD110
ASIC
Introduction
Product Family
Figure 1-2.
Analog Output
Error Converter
Analog Output Actual Ideal Ideal Actual
Gain Error
Offset Error Digital Input Digital Input
(Least-Significant Bit) system which numerical magnitude represented series binary digits, that that carries smallest value weight. represents smallest analog change that resolved n-bit converter.
(Analog Value) FSR/2n Full-Scale Range, number bits
(Most-Significant Bit) binary digit with largest numerical weighting. Normally, digital word weighting full range. Compliance-Voltage Range current output DAC, maximum range of(output) terminal voltage which device will provide specified currentoutput characteristics. Glitch glitch switching transient appearing output during code transition. value expressed product voltage (V*ns) current (mA*ns) time duration charge transferred. Harmonic Distortion (and Total Harmonic Distortion) driven digitized representation sine wave. ratio harmonics output fundamental value THD. Usually only lower order harmonics included, such second through fifth.
20log
amplitude fundamental
Signal-to-Noise Ratio (SNR) This signal noise ratio depends resolution converter automatically includes specifications linearity, distortion, sampling time uncertainty, glitches, noise, settling time. Over half sampling frequency, this signal noise ratio must specified should ideally follows theoretical formula;
S/Nmax 6.02N 1.76dB
Slew Rate Slew rate device circuit limitation rate change output voltage, usually imposed some basic circuit consideration such limited current charge capacitor. Amplifiers with slew rate V/µs common moderate cost. Slew rates greater than about V/µs usually seen only more sophisticated (and expensive) devices output slewing speed voltage-output converter usually limited slew rate amplifier used output used).
ASIC
STD110
Product Family
Introduction
Settling Time time required, following prescribed data change from point login input change, output reach remain within given fraction (usually ±1/2lsb) final value. Typical prescribed changes full scale, 1MSB 1LSB major carry. Settling time current-output DACs quite fast. major share settling time voltageoutput usually contributed settling time output op-amp circuit.
Figure 1-3. Setting Time
Slew Rate Final Setting
Slewing Setting Time
Power-Supply Sensitivity -The sensitivity converter changes power-supply voltages normally expressed terms percent-of-full-scale change analog output value fractions 1LSB) change power supply. Power supply sensitivity also expressed relation specified shift supply voltage. converter considered "good" change reading full scale does exceed 1/2LSB change power supply. Even better specs necessary converters designed battery operation. (integral Linearity Error) Linearity error converter, expressed full-scale range multiples 1LSB, deviation analog values plot measured conversion relationship from straight line. straight line either "best straight line" determined empirically manipulation gain and/or offset equalize maximum positive negative deviation actual transfer characteristics from this straight line; straight line passing through endpoints transfer characteristic endpoints transfer characteristic after they have been calibrated (sometimes referred "endpoint" linearity). Endpoint linearity error similar relative accuracy error. multiplying converters, analog linearity error, specified digital code, defined same multipliers, deviation from "best straight line" through plot analog output-input response. (Differential Linearity Error) adjacent digital codes should result measured output values that exactly 1LSB apart (2-n full scale n-bit converter). deviation measured "step" from ideal difference called differential linearity error expressed multiplies 1LSB. important specification because differential linearity error greater than 1LSB lead non-monotonic response converter missed codes converter. Monotonic said monotonic output either increases remains constant digital input increases with result that output will always single-valued function input. specification "monotonic"
STD110
ASIC
Introduction
Product Family
(over given temperature range) sometimes substituted differential nonlinearity specification since differential nonlinearity less than 1LSB sufficient condition monotonic behaviour. Analog-to-Digital Converter
(Integral Linearity Error: INL) Integral nonlinearity refers deviation each individual code from line drawn from "zero" through "full scale". point used "zero" occurs 1/2LSB before first code transition. "Full scale" defined level 1/2LSB beyond last code transition. deviation measured from center each particular code true straight line. (Differential Linearity Error: DNL) ideal exhibits code transitions that exactly 1LSB apart. deviation from this ideal value. often specified terms resolution which missing codes guaranteed. Offset Error first transition should occur level 1/2LSB above "zero". Offset defined deviation actual first code transition from that point. Gain Error first code transition should occur analog value 1/2LSB above nominal negative full scale. last transition should occur analog value 1/2LSB below nominal positive full scale. Gain error deviation actual difference between first last code transitions ideal difference between first last code transitions. Pipeline Delay (Latency) number clock cycles between conversion initiation associated output data being made available. output data provided every clock cycle. Effective Number Bits (ENOB) This measure device's dynamic performance obtained from SNDR from sine wave curve test according following expression:
ENOB SNDR 1.76/6.02 ENOB N-log2[RMS error (actual) error (ideal)]
Analog Bandwidth analog input frequency which spectral power fundamental frequency, determined analysis reduced 3dB. Aperture Delay delay between sampling clock instant analog input signal sampled. Aperture Jitter sample sample variation aperture delay. Error Rate (BER) number spurious code errors produced given input sine wave frequency given clock frequency. this case number codes occurring outside histogram cusp sine wave. Signal Noise Ratio This signal noise ratio depends resolution converter automatically includes specifications linearity, distortion, sampling time uncertainty, glitches, noise, settling time. Over half sampling frequency, this signal noise ratio must specified should ideally follow theoretical formula;
S/Nmax 6.02N 1.76dB
ASIC
STD110
Product Family
Introduction
Phase Locked Loop
Lock Time time takes lock onto system clock. Fast slow lock time controlled loop filter characteristics. loop filter characteristics controlled varying components. (Remember that define damping-factor well) Phase Error phase difference between feedback clock signal system signal clock. Clock Jitter deviations clock's output transitions from their ideal positions define clock jitter. Jitter sometimes specified absolute value nanoseconds. jitter measurement made specified voltage.
Cycle-to-Cycle Jitter: change clock's output transition from corresponding position previous cycle. This kind jitter most difficult measure usually requires time-interval analyzer Figure 1-4. Cycle-to-Cycle Jitter
Clock
Noise: jitter t2-t1 jitter t3-t2
maximum such values over multiple cycles (J1,J2.) max. cycle-tocycle jitter. Period Jitter: Period jitter measures maximum change clock's output transition from ideal position. period-jitter measurements calculate timing margins systems. Figure 1-5. Period Jitter
ideal cycle:
Clock Jitter
Long-term Jitter: Long-term jitter measures maximum change clock's output transition from ideal position over many cycles. many cycles depends application frequency. classic example system affected long-term jitter graphics card driving Power Down Mode: state which quiescent current lowered very level conserve power. Synthesize clock: system clock relatively rate compared system components. CPU, example, require internal clock that several times faster than system clock. Designers
STD110
1-10
ASIC
Introduction
Product Family
technology synthesize higher frequency on-chip clock using system clock reference. Deskew clock: Multiple chips printed circuit board cores different sizes within single system chip experience clock skew. using technology shift phase reference clock within each chip core, designers minimize skew tune system perform potential. Duty Ratio: percentage period that output high state. Output frequency range: maximum output frequency range minus minimum output frequency that produced with input signal which cell specifications still apply.
Customer Service provides full custom support customers need analog cores. SEC's worldwide sales offices representatives give customers firsthand support analog cores. needed, engineers prepared provide fully customized total solution satisfy customers. Technical Support customers want develop mixed-signal products, provides technical support meet customers needs. Mixed-signal design quite different from pure logic design terms circuit design, techniques, layout test methodology. Thus provides successful technical guide firmly support development steps. Definition Analog Core Data Sheet Types Each product developed will supported technical literature where data sheets progress through following levels refinement Core Preview Describes main features specifications core that under development. Some specifications such exact pin-outs finalized time publication.The purpose this document provide customers with advance product planning information. Preliminary Datasheet This first document completely describing core. contains features, application, timing diagram, theory operation, core information, test guide, layout guide AC/DC electrical information. This data sheet based prototype silicon performance worst case simulation models.The purpose this data sheet provide ASIC customer with technical information sufficiently detailed guarantee that they safely begin active development. 3.Final Data sheet This updated version preliminary data sheet reflecting actual performance final silicon. Updates include tighter specifications, more min. max. values. purpose this data sheet communicate confirmed performance cores which have passed qualification, been fully characterized.
ASIC
1-11
STD110
Product Family
Introduction
1.4.2 INTERNAL MACROCELLS Internal Macrocells lowest level logic functions such NAND, flip-flop used logic designs. There about different types internal macrocells. They usually come four levels drive strength (0.5X, 4X). These macrocells have many levels representations-logic symbol, logic model, timing model, transistor schematic, HSPICE netlist, physical layout, placement routing model. 1.4.3 COMPILED MACROCELLS Compiled macrocells STD110 consist compiled memory compiled datapath macrocells. 1.4.3.1 Compiled Memory Macrocells Memories STD110 fully user-configurable provided compiler. different types memories available STD110. suitable highdensity application with high-performance, called STD110-HD compiled memory. other suitable low-power application, called STD110-LP compiled memory. STD110-HD compiled memory, eight types memories available such single-port synchronous/asynchronous static RAM, dual-port synchronous static RAM, synchronous diffusion/metal-programmable ROM, multi-port asynchronous register file synchronous first-in first-out memory. Synchronous memories have fully synchronous operation rising-edge clock duty-free cycle available. Also, bit-write capability available. Asynchronous memories have synchronous operation write enable signal during write mode have asynchronous operation address signal during read mode. Multi-port asynchronous register file supports four kinds configurations such port(1-read/1-write), port(1-read/2-write 2-read/1write) port (2-read/2-write). first-in first-out memory which widely used communication buffering types applications also fully synchronous operation rising- edge clock. other hand, STD110-LP compiled memory, five types memories available such single-port synchronous/asynchronous static RAM, dual-port synchronous static synchronous diffusion/metal-programmable ROM. Synchronous memories almost same that STD110-HD except that duty-free cycle available. Asynchronous memory same that STD110-HD. dramatically reduce power consumption STD110-LP, some lowpower techniques such partial activation architecture cell array divided word-line structure adopted, rather than STD110-HD. Basically STD110-HD STD110-LP, power-down mode which significantly reduces power dissipated during read write mode provided. Also compiled memories have standby mode except multi-port asynchronous register file first-in first-out memory. While standby mode, data stored memory retained, data outputs remain stable power greatly reduced because memory operation internally blocked while memory contents data outputs unaffected.
STD110
1-12
ASIC
Introduction
Product Family
improve memory performance reduce power consumption, 2bank architecture provided except some memories such dual-port synchronous static RAM, multi- port asynchronous register file first-in first-out memory. 2-bank architecture, only bank activated other bank standby mode. support various memory shapes which determined floorplan chip design, flexible memory aspect ratios provided. certain specific memory configuration, types timing, power area values provided automatic datasheet generator. easily interface layout, physical abstract data Silicon Ensemble Apollo, called phantom cell black box, provided. BIST(Built-In Self-Test) circuitry currently available most STD110 compiled memories. BIST circuits designed detect fault types that impact functionality memory generated softmacro-based BIST generator. softmacro-based BIST generator generates both individual BIST netlist each memory shared BIST netlist memories used design. However, when several memories same different type area used design, generate individual BIST netlist each memory, there some redundant blocks because individual BIST netlist same function. this case, would better shared BIST netlist eliminate such redundancy reduce area. 1.4.3.2 Compiled Datapath Macrocells Compiled datapath macro cells include Adder, Barrel Shifter Multiplier. Adder performs adding adding/subtracting operation control mode selection signal. Barrel Shifter makes input data shift rotate left/right direction. shift operation, vacant padded with zero, value, external data. Multiplier performs compliment multiplication. pipeline stage insertion available high operating frequency. They have output drive strengths, which equal 2X-Drive primitive cell library. hard macro cells built through Apollo, placement routing tool from Avant!. leaf cells have same physical configuration compatible with primitive cell library. allows that primitive cell used slice cell datapath module design. provide kinds engineering design services. support additional compiled datapath macrocells such ALUs, Comparators, Priority encoders, Incrementers Decrementers, Another make hardwired datapath module design which provides regular structured layout.
ASIC
1-13
STD110
Product Family
Introduction
1.4.4 INPUT/OUTPUT CELLS There about seven hundreds different buffers. Each cell implemented solely basic cell architecture which forms periphery chip. test logic provided enable efficient parametric (threshold voltage) testing input buffers including LVCMOS level converters, Schmitt trigger input buffers, clock drivers oscillator buffers. Pull-up pull-down resistors optional features. Three basic types output buffers (non-inverting, tri-state open drain) available range driving capabilities from 12mA 2.5V, 3.3V drive from 5.0V tolerant drive. levels slew rate controls provided each buffer type (except 1mA, buffers) reduce output power/ground noise signal ringing, especially simultaneous switching outputs. Bi-directional buffers combinations input buffers output buffers (tristate open drain) single unit. structure been fully characterized protection latch-up resistance. user's convenience, STD110 library provides 100K pull-down pull-up resistance respectively. 1.4.4.1 Applications
support mixed voltage environments, LVTTL, LVCMOS Schmitt trigger cells available 2.5V, 3.3V interface tolerant interface. application diagram follows. Figure 1-6. Applications
2.5V 3.3V 3.3/ tolerant Internal Circuit operating voltage: 2.5V 2.5V 3.3V
Input Buffer
Output Buffer
1.4.4.2
Cell Drives Options
provide designers with greater flexibility, each buffer selected among various current levels (e.g., 1mA, 2mA,., 12mA). choice currentlevel buffers affects their propagation delay current noise. slew rate control helps decrease system noise output signal overshoot/undershoot caused switching output buffers. output edge rate slowed down selecting high slew rate control cells.
STD110
1-14
ASIC
Introduction
Product Family
STD110 provides three different sets output slew rate controls. Only slot required slew rate control options. 1.4.4.3 Tolerant Buffers
STD110 library based process which most optimum performance 2.5V. this process, voltage more than 3.6V allowed gate oxide because reliability problem. special circuit adopted order make voltage tolerable 5.25V offer interface driving 3mA. Obviously, this circuit constructed permit more than 3.6V gate oxide. external circuit diagram follows. maximum external tolerance this buffer 5.25V. used 3.3V normal buffer. Figure 1-7. Tolerant Buffers
3.3V Output voltage 3.3V Open drain output tolerant input Tri-state output Bi-directional 0.25µm 2.5V process Input Input Normal process 3.3V 5.0V
1.4.4.4 Buffers buffers designed local application which industrystandard, high-performance 32bit 64bit architecture. ASIC offers input, output, bi-directional buffers 33MHz 66MHz operation. These buffers compliant with local specification 2.1. 1.4.4.5 (Universal Serial Bus) Buffers Various kinds peripheral equipment such mouse, stick, keyboard, modem, scanner printer improve power computer. However, easy connect them properly computer. specification established late 1995 good solution this problem, providing facile method expansion. ASIC offers full speed speed buffers that complies with Universal Serial specification 1.0, 1.1. 1.4.4.6 Other Buffers ASIC support various kinds buffers such HSTL, SSTL, AGP, PECL, LVDS, more information please contact
ASIC
1-15
STD110
Timings
Introduction
Timings
1.5.1 WIRE LENGTH LOAD Table 1-1. shows equivalent standard load matrix 4-layer 5-layer metal interconnect. equivalent standard load values function gate count fanout. These values based capacitive loading used wire length estimates which affect propagation delay. Equivalent Standard loads 4-layer 5-layer Metal Interconnect
Fanouts 1.159 1.530 4.192 4.596 12.843 13.520 14.871 16.225 18.099 19.375 22.324 25.078 32.631 39.706 46.327 52.517 60.251 67.558 75.754 1.101 1.454 3.982 4.366 12.201 12.843 14.128 15.414 17.195 18.406 21.208 23.825 31.000 37.721 44.011 49.891 57.239 64.180 71.965 78.436 87.950 2.242 2.932 8.247 9.327 17.125 18.026 19.830 21.631 24.132 25.836 29.767 33.439 43.509 52.941 61.770 70.023 80.335 90.078 101.005 2.131 2.786 7.834 8.861 16.268 17.125 18.839 20.549 22.925 24.543 28.278 31.767 41.333 50.295 58.682 66.523 76.318 85.575 95.955 104.582 117.266 3.822 5.561 12.439 13.925 21.406 22.533 24.786 26.852 30.166 32.476 37.739 42.657 56.047 68.596 80.342 91.321 104.770 117.479 131.728 3.631 5.283 11.818 13.229 20.336 21.406 23.546 25.509 28.658 30.852 35.852 40.524 53.245 65.166 76.324 86.755 99.532 111.606 125.141 136.393 152.935 5.113 7.701 16.494 18.523 22.684 23.885 26.588 28.693 32.177 34.593 40.113 45.272 59.341 72.524 84.864 96.399 110.594 124.008 139.052 4.856 7.317 15.670 17.597 21.549 22.691 25.259 27.257 30.567 32.862 38.107 43.008 56.374 68.898 80.621 91.579 105.065 117.807 132.099 143.976 161.439 5.965 8.964 16.801 18.889 23.600 24.849 27.596 29.845 33.435 35.915 41.593 46.898 61.381 74.956 87.657 99.532 114.189 128.041 143.573 5.667 8.515 15.961 17.944 22.420 23.606 26.216 28.353 31.763 34.119 39.514 44.554 58.312 71.208 83.274 94.555 108.479 121.639 136.394 148.655 166.687 7.020 10.500 17.980 20.241 24.296 25.582 28.363 30.718 34.390 36.919 42.719 48.140 62.946 76.821 89.807 101.946 116.958 131.146 147.053 6.669 9.976 17.081 19.229 23.081 24.304 26.944 29.181 32.670 35.073 40.584 45.733 59.798 72.980 85.317 96.849 111.110 124.588 139.700 152.259 170.727 7.859 12.110 21.026 23.582 26.001 27.372 30.317 32.868 36.777 39.467 45.642 51.408 67.174 81.946 95.771 108.693 124.701 139.827 156.788 7.466 11.505 19.976 22.403 24.701 26.004 28.801 31.225 34.938 37.494 43.360 48.837 63.815 77.849 90.983 103.257 118.466 132.836 148.949 162.339 182.031 10.94 15.211 22.806 27.031 29.730 31.299 34.634 37.479 42.032 45.186 52.399 59.135 77.514 94.736 110.853 125.919 144.463 161.985 181.634 10.397 14.451 21.666 25.679 28.244 29.734 32.903 35.606 39.931 42.926 49.779 56.178 73.637 90.000 105.311 119.622 137.239 153.885 172.552 188.067 210.877 28.672 29.903 35.536 41.002 39.828 41.865 46.268 50.016 53.235 54.763 59.180 63.283 75.639 87.196 97.994 108.065 123.979 139.017 155.879 27.238 28.408 33.760 38.952 37.837 39.771 43.955 47.515 50.573 52.025 56.220 60.119 71.856 82.837 93.093 102.661 117.779 132.067 148.084 161.397 180.976 45.642 47.725 48.347 54.253 63.672 66.931 73.871 79.707 84.861 87.312 94.390 100.964 120.743 139.244 156.527 172.646 198.073 222.099 249.038 43.360 45.339 45.929 51.540 60.488 63.584 70.178 75.722 80.618 82.947 89.670 95.916 114.706 132.281 148.700 164.014 188.169 210.995 236.587 257.858 289.134 79.821 83.520 84.605 94.944 127.344 133.812 147.587 159.207 169.459 174.320 188.385 201.447 240.788 277.587 311.959 344.022 394.685 442.560 496.241 75.830 79.344 80.374 90.198 120.977 127.122 140.207 151.247 160.986 165.605 178.967 191.374 228.749 263.707 296.362 326.821 374.950 420.432 471.429 513.812 576.135
Table 1-1.
Gates Count 5000 10000 50000 100000 150000 200000 300000 400000 500000 600000 800000 1000000 1500000 2000000 2500000 3000000 4000000 5000000 6000000 5000 10000 50000 100000 150000 200000 300000 400000 500000 600000 800000 1000000 1500000 2000000 2500000 3000000 4000000 5000000 6000000 7000000 8000000
STD110
1-16
ASIC
Introduction
Timings
1.5.2 TIMING PARAMETERS This section discusses issues involving timing parameters. 1.5.2.1 Transition Time Figure 1-8. shows definition rise transition time (tR) fall transition time (tF). Transition time defined delay between time when input (output) signal voltage level supply voltage (VDD) time input (output) signal voltage level VDD. Figure 1-8. Rise Fall Transition Times
1.5.2.2
Propagation Delays
Figure 1-9. shows definition propagation delays. Propagation delay defined delay between time when input signal voltage level supply voltage (VDD) time when output signal voltage level VDD. Figure 1-9. Propagation Delay
tPLH
tPHL
tPLH
tPHL
ASIC
1-17
STD110
Timings
Introduction
1.5.2.3
Setup Hold Time
Figure 1-10. shows definition setup time hold time. setup timing check defined minimum interval which data signal must remain stable before active transition clock. change data signal within this interval results timing violation. hold timing check defined minimum interval which data signal must remain stable after active transition clock. change data signal within this interval results timing violation. Figure 1-10. Setup Hold Times
1.5.2.4 Recovery Times Figure 1-11. shows definition recovery time. recovery timing check measures time between release asynchronous control signal from active state next active clock edge. example, time between cell. active edge occurs soon after release state becomes uncertain. state value value clocked into from data input. Figure 1-11. Recovery Time
STD110
1-18
ASIC
Introduction
Timings
1.5.2.5
Removal Times
Figure 1-12. shows definition removal time. removal timing check measures time between active clock edge release asynchronous control signal from active state. example, time between cell. release occurs soon after active edge clock, state becomes uncertain. uncertainty caused value value clocked into from data input. Figure 1-12. Removal Time
1.5.2.6 Minimum Pulse Widths Figure 1-13. shows definition minimum pulse width. minimum pulse width timing check minimum allowable time positive (high) negative (low) phase each cycle. Figure 1-13. Minimum Pulse Width
tPWH tPWL
1.5.2.7 Minimum Period Figure 1-14. shows definition minimum period. minimum period timing check minimum allowable time complete cycle signal. Figure 1-14. Minimum Period
tPRD
ASIC
1-19
STD110
Timings
Introduction
1.5.3
TEMPERATURE SUPPLY VOLTAGE
next figure describes propagation delay derating factors (KT, function on-chip junction temperature (TJ) supply voltage (VDD). result power dissipation, junction temperature generally higher than ambient temperature. temperature inside package (junction temperature, calculated using chip power dissipation thermal resistance ambient temperature (JA) package. Information package thermal performance obtained from application engineers. Figure 1-15. Effect Temperature Supply Voltage Propagation Delay
Temperature (TJ)
1.143 1.086 1.065
1.000 0.964 0.906
(°C)
Supply Voltage (VDD)
1.075
1.000
0.940
(Volt)
STD110
1-20
ASIC
Introduction
Timings
1.5.4 BEST WORST CASE CONDITIONS circuit should designed operate properly within given specification level, either commercial industrial. recommended that circuits simulated best case, normal case, worst case conditions each specification level. following expressions also allow effect process variation circuit performance. Best case(Worst case): (TWC) TNOM where Best case propagation delay Worst case propagation delay TNOM Normal propagation delay 2.5V typical process) Refer toTable 1-2., Table 1-3., Table 1-4. 1.5.5 DERATING FACTORS STD110 multipliers applied nominal delay data order estimate effects supply voltage, temperature process. Nominal data provided conditions 2.5V, 25°C typical process. derating factors STD110 follows. Table 1-2. STD110 cell process derating factor (KP) Slow 1.212 Fast 0.841
Process Factor (KP) Table 1-3. Temp. Table 1-4. Voltage (oC)
STD110 cell temperature derating factor (KT) 1.143 1.086 1.065 1.000 0.964 0.906
STD110 cell voltage derating factor (KV) 1.075 1.000 0.940
ASIC
1-21
STD110
Delay Model
Introduction
Delay Model
ASIC timing characteristics consist following components: Cell propagation delay from input output transitions based input waveform slope, fanout loads distributed interconnection wire resistance capacitance. Interconnection wire delay across metal lines. Timing requirement parameters such setup time, hold time, recovery time, skew time, minimum pulse width, etc. Derating factors junction temperature, power supply voltage, process variations.
Timing model STD110 focuses characterize cell propagation delay time accurately. accomplish this goal, 2-dimensional table look-up delay model been adopted. index variables this table input waveform slope output load capacitance. figure below. ASIC design automation system supports n-dimensional table model even though adopted 2-dimensional model 0.25µm cell-based products. Figure 1-16. 2-Dimensional Table Delay Model
Propagation Delay [ns] Input Waveform Slope [ns] Load [pF]
STD110
1-22
ASIC
Introduction
Delay Model
Table 1-5. shows example this model 2-input NAND cell. data this table high-to-low transition delay times from input pins output pin. number points values index variables differ each cell. Table 1-5.
SLOP
Table Delay Model Example 0.0050 0.03644 0.05508 0.07719 0.06421 0.0220 0.07275 0.09725 0.16698 0.17730 0.3030 0.66481 0.68658 0.92337 1.10970 0.5840 1.25660 1.27820 1.49790 1.74950
0.0200 0.1700 1.5850 3.0000
Notice that 4-by-4 table used. Delay values between grid points beyond this table determined linear interpolation extrapolation methods. This general table delay model provides great flexibility well high accuracy since extensive software revisions required when cell library updated. other timing components such interconnection wire delay, timing requirement parameters derating factors characterized commonly-accepted industry. figure below summarizes features ASIC's delay model. 2-dimensional table delay model output loading input waveform slope effects used.The slopes (tR, delay times (tPLH, tPHL) cell instances calculated recursively. input waveform slope each primary input loading capacitance each primary output assigned individually default. delays cells interconnection wires supported. effect distributed interconnection wire resistance capacitance cell delay analysed using effective capacitance concept.
Figure 1-17. Features Delay Model
ASIC
1-23
STD110
Testability Design Methodology
Introduction
Testability Design Methodology
1.7.1 SCAN DESIGN Multiplexed scan flip-flop that minimizes area delay overhead needed implement scan design. Automated design rules checking, scan insertion, test pattern generation High fault coverage synchronous designs
1.7.2 BOUNDARY-SCAN IEEE 1149.1 JTAG boundary-scan registers with primitive cells Boundary-Scan Description Language (BSDL) description board testing Combination with internal scan design core testing
Boundary Scan Architecture boundary scan architecture contains (Test Access Port), controller, instruction register group test data registers. instruction test data registers separate shift-register-based paths connected parallel with common serial data input common serial data output which connected TAP, signals. controller selects alternative instruction test data register paths between TDO. schematic view level design test logic architecture shown Figure 118. Figure 1-18. JTAG Test Access Port (TAP) Block Diagram
Scannable Register Device Identity Register Instruction Register Controller Bypass Register TEST ACCESS PORT (TAP)
SYSTEM LOGIC
Multiplexer
Boundary Scan Path
STD110
1-24
ASIC
Introduction
Testability Design Methodology
Boundary Scan Functional Block Descriptions (Test Access Port) general-purpose port that provide with access many test support functions built into component, including test logic. includes three inputs (TCK; Test Clock Signal, TMS; Test Mode Signal TDI; Test Data Input) output (TDO; Test Data Output) required test logic. optional fourth input (TRSTN; Test Reset) provided asynchronous initialization test logic. values applied pins sampled rising edge TCK, value placed changes falling edge TCK. Controller controller receives TCK, interprets signals TMS, generates clock control signals both instruction test data registers other parts test circuitries required. Instruction Register/Instruction Decoder Test instructions shifted into held instruction register. Test instructions include selection tests performed test data register accessed. basic 3-bit instruction register instruction decoder provided macrofunctions library. Test Data Registers Data registers include bypass register, boundary scan register, device identification register other design specific registers. Only bypass- boundary scan registers mandatory; rest optional. Bypass register: bypass register provides single-bit serial connection through circuit when none other test data registers selected. used allow test data flow through given device other components product without affecting normal operation. Boundary scan register: boundary scan register detects typical production defects board interconnects, such opens, shorts, etc. also allows access component inputs outputs when test their logic sample flow-through signals. Special boundary scan register macrocells provided this purpose. These special registers discussed next section next pages. Design-specific test data register: These optional registers provided allow access design-specific test support features integrated circuit, such self-test, scan test. Device identification register: This optional test data register that allows manufacturer part number variant components identified. 32-bit identification register partitioned into four fields: Device version identifier1st field Device part number Manufacturer's JEDEC number first four bits beginning from field bits field bits field -tied High
ASIC
1-25
STD110
Testability Design Methodology
Introduction
ASIC designer free fill version part number manner long total twenty bits used. SEC's JEDEC code: decimal 1001110 Continuation field bits) 0000 Contents device identification register: XXXX XXXXXXXXXXXXXXXX 0000 1001110 Users define these fields.
Boundary Scan Register (connection boundary scan cells)
Boundary Scan Path
Instruction Register
Test Access Port (TAP)
Test Data Register
Controller
Circuit Prior Boundary Scan (Core Logic)
Bypass Register
1.7.3 BIST (BUILT-IN SELF-TEST) Efficient test solution compiled memory macrocells speed parallel testing multiple memories Less routing overhead test requirements
STD110
1-26
ASIC
Introduction
Maximum Fanouts
Maximum Fanouts
1.8.1 INTERNAL MACROCELLS maximum fanouts STD110 primitive cells follows. Note that these fanout limitation values calculated when rise fall times input signal 0.213ns. Depending rise fall times, maximum fanout limitations varied case case. following table maximum fanout values pins STD110 internal macrocells listed. Table 1-6. Maximum Fanouts Internal Macrocells (When input tR/tF 0.213ns, fanout (SL) 0.006710pF) Cell Output Maximum Name Fanouts
ad2d2 ad2d4 ad2dh ad3d2 ad3d4 ad3dh ad4d2 ad4d4 ad4dh ad5d2 ad5d4 ao21 ao211 ao2111 ao2111d2 ao211d2 ao211d2b ao211d4 ao211dh ao21d2 ao21d2b ao21d4 ao21dh ao22 ao221 ao221d2 ao221d4 ao222 ao2222 ao2222d2 ao2222d4 ao222a ao222d2 ao222d2a ao222d2b ao222d4 ao222d4a ao22a
Cell Name
ao22d2 ao22d2a ao22d2b ao22d4 ao22d4a ao22dh ao22dha ao31 ao311 ao3111 ao3111d2 ao311d2 ao311d4 ao31d2 ao31d4 ao31dh ao32 ao321 ao321d2 ao321d4 ao322 ao322d2 ao322d4 ao32d2 ao32d4 ao33 ao331 ao331d2 ao331d4 ao332 ao332d2 ao332d4 ao33d2 ao33d4 ao4111 ao4111d2 busholder
Output
Maximum Fanouts
10000
dc4i
dc8i
dl1d2 dl1d4 dl2d2 dl2d4 dl3d2 dl3d4 dl4d2 dl4d4 dl5d2 dl5d4 dl10d2 dl10d4
ASIC
1-27
STD110
Maximum Fanouts
Introduction
Cell Name
oak_duclk oak_duclk fad2 fadh fd1d2 fd1cs fd1csd2 fd1q fd1qd2 fd1s fd1sd2 fd1sq fd1sqd2 fd2d2 fd2cs fd2csd2 fd2q fd2qd2 fd2s fd2sd2 fd2sq fd2sqd2 fd3d2 fd3cs fd3csd2 fd3q fd3qd2 fd3s fd3sd2 fd3sq fd3sqd2 fd4d2 fd4cs
Output
Maximum Fanouts
Cell Name
fd4csd2 fd4q fd4qd2 fd4s fd4sd2 fd4sq fd4sqd2 fd5d2 fd5s fd5sd2 fd6d2 fd6s fd6sd2 fd7d2 fd7s fd7sd2 fd8d2 fd8s fd8sd2 fds2 fds2d2 fds2cs fds2csd2 fds2s fds2sd2 fds3 fds3d2 fds3cs fds3csd2 fds3s
Output
Maximum Fanouts
STD110
1-28
ASIC
Introduction
Maximum Fanouts
Cell Name
fds3sd2 fj1d2 fj1s fj1sd2 fj2d2 fj2s fj2sd2 fj4d2 fj4s fj4sd2 ft2d2 had2 hadh ivcd11 ivcd13 ivcd22 ivcd26 ivcd44 ivd2 ivd3 ivd4 ivd6 ivd8 ivd16 ivdh ivtd2 ivtd4 ivtd8 ivtd16 ivtn ivtnd2 ivtnd4 ivtnd8 ivtnd16
Output
Maximum Fanouts
Cell Name
ld1d2 ld1a ld1d2a ld1q ld1qd2 ld2d2 ld2q ld2qd2 ld3d2 ld4d2 ld5d2 ld5q ld5qd2 ld6d2 ld6q ld6qd2 ld7d2 ld8d2 oak_ldi2 oak_ldi2d2 oak_ldi3 oak_ldi3d2 ls0d2 ls1d2 mx2d2 mx2d4 mx2dh mx2i mx2ia mx2id2
Output
Maximum Fanouts
ASIC
1-29
STD110
Maximum Fanouts
Introduction
Cell Name
mx2id2a mx2id4 mx2id4a mx2idh mx2idha mx2ix4
Output
Maximum Fanouts
2384 4731
Cell Name
nr2a nr2d2 nr2d2b nr2d4 nr2dh nr3a nr3d2 nr3d2b nr3d4 nr3dh nr4d2 nr4d4 nr4dh nr5d2 nr5d4 nr6d2 nr6d4 nr8d2 nr8d4 oa21 oa211 oa2111 oa2111d2 oa211d2 oa211d2b oa211d4 oa211dh oa21d2 oa21d2b oa21d4 oa21dh oa22 oa221 oa221d2 oa221d4 oa222 oa2222 oa2222d2 oa2222d4 oa222d2 oa222d2b oa222d4 oa22a oa22d2 oa22d2a oa22d2b oa22d4 oa22d4a oa22dh oa22dha oa31 oa311 oa3111 oa3111d2 oa311d2 oa311d4 oa31d2 oa31d4 oa31dh oa32
Output
Maximum Fanouts
mx2x4
mx3i mx3id2 mx3id4 mx4d2 mx4d4 mx8d2 mx8d4 nd2d2 nd2d4 nd2dh nd3d2 nd3d4 nd3dh nd4d2 nd4d2b nd4d4 nd4dh nd5d2 nd5d4 nd6d2 nd6d4 nd8d2 nd8d4 oak_nid10p nid16 nid2 oak_nid20p nid3 nid4 nid6 nid8 nidh nitd16 nitd2 nitd4 nitd8 nitn nitnd16 nitnd2 nitnd4 nitnd8
STD110
1-30
ASIC
Introduction
Maximum Fanouts
Cell Name
oa321 oa321d2 oa321d4 oa322 oa322d2 oa322d4 oa32d2 oa32d4 oa33 oa331 oa331d2 oa331d4 oa332 oa332d2 oa332d4 oa33d2 oa33d4 oa4111 oa4111d2 or2d2 or2d4 or2dh or3d2 or3d4 or3dh or4d2 or4d4 or4dh or5d2 or5d4 scg1 scg1d2 scg2 scg2d2 scg3 scg3d2 scg4 scg4d2 scg5 scg5d2 scg6 scg6d2 scg7 scg7d2 scg8 scg8d2 scg9 scg9d2 scg10 scg10d2 scg11 scg11d2 scg12 scg12d2 scg13 scg13d2 scg14 scg14d2 scg15 scg15d2 scg16
Output
Maximum Fanouts
Cell Name
scg16d2 scg17 scg17d2 scg18 scg18d2 scg19 scg19d2 scg20 scg20d2 scg21 scg21d2 scg22 scg22d2 scg23 scg23d2 xn2d2 xn2d4 xn3d2 xn3d4 xo2d2 xo2d4 xo3d2 xo3d4
Output
Maximum Fanouts
ASIC
1-31
STD110
Maximum Fanouts
Introduction
1.8.2 CELLS maximum fanouts cells follows. Table 1-7. Maximum Fanouts Cells (tR/tF 0.213ns, fanout (SL) 0.006710pF) Cell Output Maximum Name Fanouts
phic phicd phicu phis phisd phisu phit phitd phitu phsosck1 phsosck17 phsosck2 phsosck27 phsoscm1 phsoscm16 phsoscm2 phsoscm26 phsoscm3 phsoscm36 pic_abb picc_abb picd picen_abb picu pipci pisd pisu psosck1 psosck2 psoscm1 psoscm2 ptic pticd pticu ptipci ptis ptisd ptisu ptit ptitd ptitu
STD110
1-32
ASIC
Introduction
Maximum Fanouts
1.8.3 CELL FANOUT STD110 maximum fanout cells <Condition> 2.5V Fanout 0.00357pF input FD1) Standard Load (SL) 0.006710pF Input slope 0.213ns output transition time (mott) =1.5ns Maximum frequency 200MHz length (µm/fanout): branch length each fanout except trunk Table 1-8. Maximum Fanout Cells
5000 10000 5000 10000 case that interconnection considered 1172 1561
Trunk width (µm) length (µm/fanout) Trunk length (µm)
Table 1-9.
Maximum Fanout Cells
0.44 5000 10000 5000 10000 case that interconnection considered 2384 4731
Trunk width (µm) length (µm/fanout) Trunk length (µm) nid2 nid3 nid4 nid6 nid8 nid16 oak_nid10p oak_nid20p
high fanout nets including clock net, strongly recommends using clock tree synthesis.
ASIC
1-33
STD110
Package Capability Lead Count
Introduction
Package Capability Lead Count
Lead Count
Package Lead Inductance SOP/SSOP (Small Outline Package) 8.7mm 5.1mm 10.2 15.6 14.1 18.4 12.6 29.0mm 20nH 12.7 29.0 16nH TSOP/TSSOP (Thin SOP) 3.0mm 9.7mm 14.0 10.2 18.9 10.2 21.4 10.2 22.6 12.0 20.0mm 12.4 16.4 PSOP/PSSOP (Power SOP) 7.64 12.8 11.0 15.9
STD110
1-34
ASIC
Introduction
Package Capability Lead Count
Package Lead Inductance (Quad Flat Package) 12nH 11nH 17nH 15nH TQFP (Thin Quad Flat Package) 10nH 11nH 13nH PLCC (Plastic Leaded Chip Carrier) 16.6 16.5mm <5nH 29.3 29.3 13nH Package Lead Inductance SBGA (Super BGA) Lp/g Lsig 42.5 42.5 PBGA (Plastic BGA) Lp/g Lsig <9nH 13nH 18nH 21nH 13nH 14nH PBGA (Plastic BGA) Lp/g Lsig <10nH 13nH 18nH 21nH 13nH 14nH
Lead Count
Lead Count
ASIC
1-35
STD110
1.10
Power Dissipation
Introduction
1.10 Power Dissipation
1.10.1 ESTIMATION POWER DISSIPATION CMOS CIRCUIT CMOS circuits have been traditionally considered consume power since they draw very small amount current steady state. However, recent revolution CMOS technology that allows very high gate density changed power dissipation should understood. power dissipation CMOS circuit affected various factors such number gates, switching frequency, loading output gate, Power dissipation important when designers decide amount necessary power supply current device operate safety. Propagation delays reliability device also depend power dissipation that determines temperature which operates. obtain high speed reliability, designers must estimate power dissipation device accurately determine appropriate environments including package system cooling methods. This section describes concepts types power dissipation (static dynamic) CMOS circuit, method calculating those STD110 library. 1.10.2 STATIC (DC) POWER DISSIPATION There types static current contributing total static power dissipation CMOS circuits. leakage current gates resulted reverse bias between well substrate region. There current path from power ground CMOS because transistor pair always off, therefore, static current except leakage current flows through internal gates device. amount this leakage current however, range tens nano amperes, which negligible. other current that flows through input output buffers when circuit interfaced with other devices, especially TTL. current pull-up/ pull-down transistor input buffers about 33µA 3.3V) 25uA 2.5V) typically, which also negligible. Therefore, only current that output buffers source sink counted estimate total static power dissipation. power dissipation output bi-directional buffers determined following formula:
PDC_OUTPUT [mW] VOL(k) IOL(k) tL(k) VOH(k) IOH(k) tH(k) PDC_BI [mW] VOL(k) IOL(k) IOH(k) tH(k) Sout
where, Number output bidirectional buffers Total operation time output mode logic high state time logic state time (Supposed that output bidirectional buffers have just logic high state) Sout output mode ratio bidirectional buffers (typically 0.5)
STD110
1-36
ASIC
Introduction
1.10
Power Dissipation
1.10.3 DYNAMIC (AC) POWER DISSIPATION When CMOS gate changes state, draws switching current result charging discharging load capacitance, energy associated with switching current node capacitance,
where power supply voltage. addition power dissipated load capacitance, CMOS circuits consume power shortcircuit current flowing through temporary VDD-to-ground path during switching. dynamic power dissipation entire chip much more complicated estimate since depends degree switching activity circuit. found that degree switching activity average recommends this number used estimating total dynamic power dissipation. 1.10.4 POWER DISSIPATION STD110 This section describes equations estimate power dissipation STD110. explained previous section, total power dissipation (PTOTAL) consists static power dissipation (PDC) dynamic power dissipation (PAC). PTOTAL negligible case CMOS logic. dynamic power dissipation caused three components: input buffers (PAC_INPUT), output buffers (PAC_OUTPUT), bidirectional buffers (PAC_BI), internal cells (PAC_INTERNAL). PAC_ INPUT PAC_OUTPUT PAC_BI PAC_INTERNAL Each term mentioned above characterized following equations:
N_2.5V_input
PAC_INPUT [mW] PAC_OUTPUT [mW] 6.25
N_3.3V_input N_total_input Ik_eq_p 6.25 (0.001 Ci_inload) j_eq_p
N_2.5V_output
N_2.5V_output
i_eq_p
N_3.3V_output
j_eq_p
N_3.3V_output
0.001 Ci_outload 10.89
0.001 Cj_outload
PAC_BI [mW] PAC_BI_INPUT Sout PAC_BI_OUTPUT Sout
N_2.5V_bi
PAC_BI_INPUT [mW] PAC_BI_OUTPUT [mW] 6.25
N_3.3V_bi N_total_bi Ik_eq_p 6.25 0.001 Ci_inload j_eq_p
N_2.5V_bi
N_2.5V_bi
i_eq_p
N_3.3V_bi
j_eq_p
N_3.3V_bi
0.001 Ci_outload 10.89
N_macro
0.001 Ci_outload
PAC_INTERNAL [mW] 0.001 0.2317 0.0167
0.001
ASIC
1-37
STD110
1.10
Power Dissipation
Introduction
where N_2.5V_input number 2.5V interface input buffers used N_3.3V input number 3.3V interface input buffers used, N_total_input N_2.5V_input N_3.3V input N_2.5V_output number 2.5V interface output buffers used, N_3.3V_output number 3.3V interface output buffers used, N_2.5V_bi number 2.5V interface bidirectional buffers used, N_3.3V_bi number 3.3V interface bidirectional buffer used, N_macro number macro cells used, size design gate count, operating frequency MHz, estimated degree switching activity (typically internal I/O), Sout output mode ratio bidirectional buffers (typically 0.5), load capacitance characterized power i-th hard macro block (µW/MHz) 1.10.5 TEMPERATURE POWER DISSIPATION total power dissipation, PTOTAL used find device temperature following equation:
PTOTAL
where
thermal impedance,
junction temperature device, ambient temperature.
Thermal impedances packages given following table. junction temperature, obtained multiplying PTOTAL appropriate adding determines derating factor propagation delays also indicates reliability measures. Hence, designers achieve desired derating factor reliability targets choosing appropriate packages system cooling methods. Table 1-10. Number Thermal Impedances Plastic Packages SOP/TSOP 41-44 46-56 44-71 39-59 34-56 27-33 34-46
JA[°C/W] JA[°C/W] JA[°C/W] JA[°C/W] JA[°C/W]
Number
51-62
43-56
43-74
27-61
33-47
43-51
29-51
22-43
28-47
29-42
TQFP/LQFP Number 68-70 37-70 35-62 PBGA Number 19-22 16-19 SBGA Number 14.1 13.1 11.7 10.2 (TEPBGA) (TEPBGA) 31-34 37-56 30-42
STD110
1-38
ASIC
Introduction
1.11
VDD/VSS Rules Guidelines
1.11 VDD/VSS Rules Guidelines
There three kinds STD110, providing power internal area. Core logic VDD2I, VSS2I Pre-driver (I/O area) VDD2P, VDD3P, VSS2P, VSS3P Output-drive (I/O area) VDD2O, VDD3O, VSS2O, VSS3O
number pads required specific design depends following factors: Number input output buffers Number simultaneous switching outputs Number used gates simultaneous switching gates Operating frequency
1.11.1 BASIC PLACEMENT GUIDELINES purpose these guidelines minimize drop noise reliable device operations. Core logic pre-driver VDD/VSS pads should evenly distributed sides chip. have core block demanding high power (compiled memory, analog), extra power pads should placed that side. Power pads group should evenly distributed group. place quiet signal (analog, reference) analog power (VDDA/ VSSA) bi-directional buffer next group. opposite types power pads (VDD/VSS) should placed close possible. possible, place power pads (VDD/VSS) corner chip.
1.11.2 VDD2I/VSS2I ALLOCATION GUIDELINES purpose these guidelines ensure that minimum number core logic power pairs meeting electromigration current limit used. number VDD2I/VSS2I pads required specific design determined function operating frequency chip. VDD2I width number pads equal those VSS2I VDD2I/VSS2I buses pads should distributed evenly core each side chip. total number core logic VDD2I pads equal that VSS2I pads.
ASIC
1-39
STD110
1.11
VDD/VSS Rules Guidelines
Introduction
number VDD2I/VSS2I pairs required design calculated from following expression: number VDD2I/VSS2I pairs 0.001 0.0927 0.0067
N_macro
round
where, core (excluding hard macro blocks) size gate counts switching ratio (typically 0.1) Operating frequency (MHz) Characterized current i-th hard macro block (mA/MHz) Operating frequency i-th hard macro block (MHz) Current limit VDD/VSS pairs based ElectroMigration rule (80mA) reliable device operation minimize voltage drop, minimum number VDD2I/VSS2I power pairs Extra power needed demanding high power macro blocks (SRAM, analog block.). 1.11.3 VDD2P/VSS2P (VDD3P/VSS3P) ALLOCATION GUIDELINES. These guidelines ensure that adequate input threshold voltage margin maintained during switching. number VDD2P/VSS2P (VDD3P/VSS3P) pads required design calculated from following expression: leq_p Number_ of_VDD2P/VSS2P(VDD3P/VSS3P) pairs round above expression, Ieq_p (Average current input/output buffers bi-direction pre-drivers maximum operational frequency) [mA] (Refer Table 1-11)
N_input
Ieq_p
N_bi N_output Ij_eq_p_out Ik_eq_p_in Sout) Ik_eq_p_out Sout eq_p_in
where N_input number input buffers used, N_output number output buffers used, N_bi number bi-directional buffers used, operating frequency MHz, Sout output mode ratio bi-directional buffers (typically 0.5), Current limit VDD/VSS pairs based electromigration rule. (80mA)
Table 1-11. 2.5V Interface Input Buffer Type Ieq_p (mA) Output Pre-Driver Type Ieq_p (mA) Normal Slew rate B1-4 0.14 0.14
CMOS 0.35 Driver B6-8 0.27 0.25
B10-12 0.41 0.35
T1-4 0.24 0.25
CMOS Schmitt 0.36 Tristate T6-8 0.36 0.35
T10-12 0.53 0.45
STD110
1-40
ASIC
Introduction
1.11
VDD/VSS Rules Guidelines
Table 1-12. 3.3V Interface Input Buffer Type Ieq_p Normal (mA) Tolerant Output Pre-driver Type Ieq_p (mA) Normal Tolerant Normal Slew rate
CMOS 0.52 0.60 CMOS Driver B1-4 B6-8 0.25 0.46 0.28 0.37
0.54 0.60 B10-12 0.55 0.46 T1-4 0.34 0.36 (T1,2,3) 0.50
Schmitt Trigger 0.54 0.51 Tristate T6-8 T10-12 0.51 0.60 0.45 0.55
reliable device operation minimum voltage drop, least pairs VDD2P/VSS2P (VDD3P/VSS3P) power pads needed. 1.11.4 VDD2O/VSS2O (VDD3O/VSS3O) ALLOCATION GUIDE (Simultaneous Switching Output) current induced power ground inductance cause system failure because voltage fluctuations. calculation output drive power numbers, consider noise well current limit based electromigration. define outputs switching simultaneously windows, such type buffers.
NOTE: case heavy load, high frequency package inductance, number power pads block could determined electromigration rule rather than limit noise. number power pads block should determined worse power number under limit noise that under limit electromigration rule.
Number power pads block Number power pads block under limit noise Calculating number power each group from following expressions: number_of_SSO NVDDOeach_SSO -NBvdd DSSO_mode number_of_SSO NVSSOeach_SSO -NBvss DSSO_mode above formula, NVDDOeach_sso Number VDD2O (VDD3O) required each group NVSSOeach_sso Number VSS2O (VSS3O) required each group NBvdd =Number buffers VDD2O (VDD3O) power with lead inductance NBvss Number buffers VSS2O (VSS3O) ground with lead inductance Package lead frame inductance (refer package capability lead count) Dsso_mode DL_mode DP_mode DV_mode DT_mode DC_mode (Refer Table 1-13. Table 1-14.) DL_mode Lead inductance derating factor DP_mode Process derating factor DV_mode Voltage derating factor DT_mode Temperature derating factor DC_mode Cload derating factor (*mode either vss.)
ASIC
1-41
STD110
1.11
VDD/VSS Rules Guidelines
Introduction
Table 1-13. Item
Package Lead
Derating Equation (external 2.5V interface) Mode Equation
DL_vdd DL_vss 0.0417 0.9375 0.0417 0.9375 0.0417 0.9375 0.0417 0.9375 1.0000 1.2549 1.7255 1.0000 1.2549 1.7451 0.8824 voltage 3.3235 0.5882 voltage 2.5882 0.8824 voltage 3.3235 0.5882 voltage 2.5882 0.0024 temperature 1.0000 0.0032 temperature 0.9786 0.0031 temperature 1.0000 0.0029 temperature 1.0071 0.0347 Cload 0.6525 0.0286 Cload 0.8369 0.0354 Cload 0.6456 0.0285 Cload 0.8544
Range
10nH 10nH 15nH 10nH 10nH 15nH best typical worst best typical worst voltage voltage voltage voltage temperature temperature temperature temperature 10pF Cload 30pF 30pF Cload 50pF 10pF Cload 30pF 30pF Cload 50pF
Process DP_vdd
DP_vss Voltage DV_vdd DV_vss Temperature DT_vdd DT_vss Cload DC_vdd DC_vss
Table 1-14. Item
Package Lead
Derating Equation (external 3.3V interface) Mode Equation
DL_vdd DL_vss 0.0462 1.1538 0.0231 1.3846 0.0469 0.7813 0.0313 0.9375 1.0000 1.2537 2.2985 1.0000 1.1563 1.4063 1.2936 voltage 5.4328 0.4478 voltage 2.6119 0.4166 voltage 2.5000 0.4166 voltage 2.5000 0.0036 temperature 1.0000 0.0041 temperature 0.9878 0.0038 temperature 1.0000 0.0028 temperature 1.0227 0.0338 Cload 0.6618 0.0554 Cload 0.0146 0.0444 Cload 0.5556 0.0370 Cload 0.7778
Range
10nH 10nH 15nH 10nH 10nH 15nH best typical worst best typical worst voltage voltage voltage voltage temperature temperature temperature temperature 10pF Cload 30pF 30pF Cload 50pF 10pF Cload 30pF 30pF Cload 50pF
Process DP_vdd
DP_vss Voltage DV_vdd DV_vss Temperature DT_vdd DT_vss Cload DC_vdd DC_vss
STD110
1-42
ASIC
Introduction
1.11
VDD/VSS Rules Guidelines
Table 1-15. Buffer Type
NBvdd/NBvss Parameter (Process best, Volt =2.7V/3.6V Temp. 0°C, Llead 1nH) Normal Slew-Rate Medium (sm) Slew-Rate High (sh) Voltage Type NBvdd NBvss NBvdd NBvss NBvdd NBvss
pob1 (pot1) pob2 (pot2) pob4 (pot4) pob6 (pot6) pob8 (pot8) pob12 (pot12) phob1 (phot1) phob2 (phot2) phob4 (phot4) phob6 (phot6) phob8 (phot8) phob12 (phot12) ptot1 ptot2 ptot3
2.5V Interface
3.3V Interface
Tolerant
NOTE: pob1 means output driver cell, pob12 means 12mA output driver cell.
Calculating number required power total from following expression: NVDDO1sso NVDDOeach_sso NVSSO1sso NVSSOeach_sso above formula, NVDDOsso Number VDD2O (VDD3O) total buffers NVSSOsso Number VSS2O (VSS3O) total buffers
ASIC
1-43
STD110
1.11
VDD/VSS Rules Guidelines
Introduction
Number power pads block under limit electromigration rule Calculating following expression: NVDDO2SSO NVSSO2SSO -Iem
N_SSO_output N_SSO_bi
Ieq_o
Ieq_o
0.001 Ci_outload
0.001 j_outload j_out
where N_SSO_output number simultaneous switching output buffers used, N_SSO_bi number simultaneous switching bi-directional buffers used, Coutload Output load capacitance [pF] Operating voltage Maximum operating frequency [MHz] Switching ratio (typically 0.5) Sout Output mode ratio bidirectional buffers (typically 0.5) Current limit VDD/VSS paris based electromigration rule. (80mA) Number power pads non-SSO block Calculating following expression: NVDDOnon_SSO NVSSOnon_SSO -Iem Ieq_o
N_non_SSO_output
Ieq_o
N_non_SSO_bi
0.001 Ci_outload
0.001 j_outload j_out
where N_non_SSO_output number non-simultaneous switching output buffers used, N_non_SSO_bi number non-simultaneous switching bi-directional buffers used, Coutload Output load capacitance [pF] Operating voltage Maximum operating frequency [MHz] Switching ratio (typically 0.5) Sout Output mode ratio bidirectional buffers (typically 0.5) Current limit VDD/VSS paris based electromigration rule. (80mA)
Total number power pads VDD2O/VSS2O (VDD3O/VSS3O) Calculating following expressions:
Number VDD2O (VDD3O) NVDDO1SSO, NVDDO2SSO NVDDOnon_SSO round-up Number VSS2O (VSS3O) NVSSO1SSO, NVSSO2SSO NVSSOnon_SSO round-up
When open drain type buffers used, consider using VSS2O (VSS3O) pads since they have current sink only.
STD110
1-44
ASIC
Introduction
1.12
Crystal Oscillator Consideration
1.12 Crystal Oscillator Consideration
1.12.1 OVERVIEW STD110 contains circuit commonly referred "on-chip oscillator." on-chip circuit itself oscillator amplifier which suitable being used amplifier part feedback oscillator. With proper selection offchip components, this oscillator circuit performs better than other types clock oscillators. very important select suitable off-chip components work with onchip oscillator circuitry. should noted, however, that cannot assume responsibility writing specifications off-chip components complete oscillator circuit, guaranteeing performance finished design production, more than transistor manufacturer, whose data sheets show number suggested amplifier circuits, assume responsibility operation, production, them. often asked don't publish list required crystal ceramic resonator specifications, recommend values other off-chip components. This been done past, sometimes with consequences that were intended. Suppose suggest maximum crystal resistance 30ohms some given frequency. Then your crystal supplier tells 30ohm crystals going cost twice much 50ohm crystals. Fearing that will "guarantee operation" with 50ohm crystals, order expensive ones. fact, guarantees only what embodied within product. Besides, there reason 50ohm crystals couldn't used, other off-chip components suitably adjusted. Should recommend values other off-chip components? Should 50ohm crystals 30ohm crystals? With respect what should optimize their selection? Should minimize start-up time maximize frequency stability? many applications, neither start-up time frequency stability particularly critical, "recommendations" only restricting your system unnecessary tolerances. depends application. 1.12.2 OSCILLATOR DESIGN CONSIDERATIONS ASIC designers have number options clocking system. main decision whether "on-chip" oscillator external oscillator. choice on-chip oscillator, what kinds external components external oscillator, what type oscillator would decisions have based both economic technical requirements. this section will discuss some factors that should considered.
ASIC
1-45
STD110
1.12
Crystal Oscillator Consideration
Introduction
1.12.2.1 On-Chip Oscillator most cases, on-chip amplifier with appropriate external components provides most economical solution clocking problem. Exceptions arise server environments when frequency tolerances tighter than about 0.01%. external components that commonly used CMOS gate oscillator positive reactance (normal crystal oscillator), capacitors, resistor shown figure below. Figure 1-19. CMOS Oscillator Inside Chip PADA
PADY
Feedback Amplifier
1.12.2.2 Crystal Specifications Specifications appropriate crystal very critical, unless frequency fundamental-mode crystal medium better quality used. often asked what maximum crystal resistance should specified. best answer that question lower better, what available. crystal resistance will have some effect start-up time steady-state amplitude, much that can't compensated appropriate selection capacitance, Similar questions asked about specifications load capacitance shunt capacitance. best advice give understand what these parameters mean they affect operation circuit (that being purpose this application note), then decide yourself such specifications meaningful your frequency tolerances tighter than about 0.1%. Part problem that crystal manufacturers accustomed talking "ppm" tolerances with radio engineers simply won't take your order until you've filled their list frequency tolerance requirements, both yourself crystal manufacturer. Don't 0.003% crystals your actual frequency tolerance
STD110
1-46
ASIC
Introduction
1.12
Crystal Oscillator Consideration
1.12.2.3 Oscillation Frequency oscillation frequency determined 99.5% crystal about 0.5% circuit external crystal. on-chip amplifier little effect frequency, which should since amplifier parameterizes temperature process dependent. influence on-chip amplifier frequency means input output (pin-to-ground) capacitances, which parallel PADA-to-PADY (pin-to-pin) capacitance, which parallels crystal. input pin-to-pin capacitances about each. Internal phase deviations capacitance 30pF. These deviations from ideal have less effect positive reactance oscillator (with inverting amplifier) than comparable series resonant oscillator (with non-inverting amplifier) reasons: first, effect output capacitor; second, positive reactance oscillator less sensitive, frequency-wise, such phase errors. 1.12.2.4 Selection Optimal values capacitors depend whether quartz crystal ceramic resonator being used, also application-specific requirements start-up time frequency tolerance. Start-up time sometimes more critical microcontroller systems than frequency stability, because various reset initialization requirements. Less commonly, accuracy oscillator frequency also critical, example, when oscillator being used time base. general rule, fast start-up stable frequency tend pull oscillator design opposite directions. Considerations both start-up time frequency stability over temperature suggest that should about equal least 15pF. (But they don't have either.) Increasing value these capacitances above some 50pF improves frequency stability. also tends increase start-up time. These maximum value (several hundred depending value quartz ceramic resonator) above which oscillator won't start all. on-chip amplifier simple inverter, user select values between some 50pF, depending whether start-up time frequency stability more critical parameter specific application. 1.12.2.5 Selection CMOS inverter might work better this application since large (1megaohm) used hold inverter linear region. Logic gates tend have fairly output resistance, which testabilizes oscillator. that reason resistor (several k-ohm) often added feedback network, shown Figure 1-19. higher frequencies 30pF capacitor sometimes used position, compensate some internal propagation delay.
ASIC
1-47
STD110
1.12
Crystal Oscillator Consideration
Introduction
1.12.2.6 Capacitance Selection Internal pin-to-ground pin-to-pin capacitances, PADA PADY have some effect oscillator. These capacitances normally taken range 10pF, they extremely difficult evaluate. measurement such capacitance necessarily include effects from others. advantage positive reactance oscillator that pin-to ground cap. paralleled external bulk capacitance, precise determination their value unnecessary. would suggest that there little justification more precision than assign them value (PADA-to-ground PADA-to-PADY). This value probably error more than 4pF. PADY-to-ground cap. entirely "pin capacitance", more like "equivalent output capacitance" some 30pF, having include effect internal phase delays. This value varies some extent with temperature, process, frequency. 1.12.2.7 Placement Components Noise glitches arising PADA PADY pins wrong time cause miscount internal clock-generating circuitry. These kinds glitches produced through capacitive coupling between oscillator components traces carrying digital signals with fast rise fall times. this reason, oscillator components should mounted close chip have short, direct traces PADA, PADY, pins. possible, dedicated only crystal feedback amplifier. 1.12.3 TROUBLESHOOTING OSCILLATOR PROBLEMS first thing consider case difficulty that there significant differences stray caps between test actual application, particularly actual application multi-layer board. Noise glitches, that present test application board, another possibility. Capacitive coupling between oscillator circuitry other signal already been mentioned source miscounts internal clocking circuitry. Inductive coupling also doubtful, there strong current nearby. These problems function layout. Surrounding oscillator components with "quit" traces (for example, ground) will alleviate capacitive coupling signals having fast transition time. minimize inductive coupling, layout should minimize areas loops formed oscillator components. loops demanding checked follows: PADA through resonator PADY; PADA through pin; PADY through pin. unusual find that ground ends eventually connect only after looping around farthest ends board. good. Finally, should overlooked that software problems sometimes imitate symptoms slow-starting oscillator incorrect frequency. Never underestimate perversity software problem.
STD110
1-48
ASIC
Electrical Characteristics
Contents
Electrical Characteristics
ELECTRICAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
0.3V, 85°C, VEXT 0.25V case tolerant)
Symbol Parameter High level input voltage LVCMOS interface LVTTL interface level input voltage LVCMOS interface LVTTL interface Switching threshold Schmitt trigger, positive-going threshold Schmitt trigger, negative-going threshold High level input current Input buffer Input buffer with pull-down level input current Input buffer Input buffer with pull-up High level output voltage Type B12Note1 Type Type Type Type Type Type Type Type level output voltage Type B12Note1 Type Type Type Type Type Type Type Type Tri-state output leakage current Output short circuit current Quiescent supply current Input capacitanceNote3 Output capacitanceNote3 Condition 0.7VDD 0.3VDD LVCMOS LVTTL LVCMOS/LVTTL LVCMOS/LVTTL Schmitt-trigger 0.05 0.575 0.65 0.5VDD Type Unit
-1µA -1mA -2mA -3mA -4mA -6mA -8mA -10mA -12mA 10mA 12mA VOUT =VSS VEXT 3.6V, 3.6V, Input Bidirectional Buffers Output Buffer
0.05
COUT
100Note2
ASIC
STD110
ELECTRICAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
0.2V, 85°C case general I/O)
Symbol VTVH Parameter High level input voltage LVCMOS interface level input voltage LVCMOS interface Switching threshold Schmitt trigger, positive-going threshold Schmitt trigger, negative-going threshold High level input current Input buffer Input buffer with pull-down level input current Input buffer Input buffer with pull-up High level output voltage Type B12Note1 Type Type Type Type Type Type Type level output voltage Type B12Note1 Type Type Type Type Type Type Type Tri-state output leakage current Output short circuit current Quiescent supply current Input capacitanceNote3 Output capacitanceNote3 Condition LVCMOS LVCMOS LVCMOS Schmitt-trigger 0.05 0.65 0.5VDD Type Unit
-1µA -1mA -2mA -4mA -6mA -8mA -10mA -12mA 10mA 12mA VOUT =VSS VEXT 3.6V, 3.6V, Input Bidirectional Buffers Output Buffer
0.05
COUT
100Note2
NOTES: Type means output driver cells, type B6/B12 means 6mA/12mA output driver cells. This value depends customer design. This value exclude package parasitics.
STD110
ASIC
ELECTRICAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Symbol Parameter supply voltage input voltage 2.5V Input buffer 3.3V Input buffer tolerant input buffer VOUT Ilatch TSTG output voltage Latch-up current Storage temperature 2.5V buffer 3.3V buffer ±200 Rating Unit
Recommended Operating Conditions
Symbol supply voltage Parameter 2.5V 3.3V tolerant Analog core supply voltage Commercial temperature range Industrial temperature range 2.5V Core 1.8V Core Rating Unit
ASIC
STD110
Internal Macrocells
Contents
Overview Summary Tables. Logic Cells. Flip-Flops. 3-300 Latches. 3-400 Holder. 3-448 Internal Clock Drivers 3-449 Decoders 3-451 Adders 3-460 Multiplexers 3-470
INTERNAL MACROCELLS
OVERVIEW
OVERVIEW
third chapter contains data sheets logic cells, flip-flops, latches, holder, internal clock drivers, decoders, adders multiplexers. electrical characteristics each cell follow basic cell data. Summary tables following pages list whole STD110 internal macrocells type show their reference page numbers your convenience. Moreover, find more detailed description tables leading pages each category.
ASIC
STD110
SUMMARY TABLES
INTERNAL MACROCELLS
SUMMARY TABLES
Logic Cells
Cell Type Cells Cell Name AD2DH/AD2/AD2D2/AD2D4 AD3DH/AD3/AD3D2/AD3D4 AD4DH/AD4/AD4D2/AD4D4 AD5/AD5D2/AD5D4 NAND Cells ND2DH/ND2/ND2D2/ND2D4 ND3DH/ND3/ND3D2/ND3D4 ND4DH/ND4/ND4D2/ND4D2B/ND4D4 ND5/ND5D2/ND5D4 ND6/ND6D2/ND6D4 ND8/ND8D2/ND8D4 Cells NR4DH/NR4/NR4D2/NR4D4 NR5/NR5D2/NR5D4 NR6/NR6D2/NR6D4 NR8/NR8D2/NR8D4 Cells OR2DH/OR2/OR2D2/OR2D4 OR3DH/OR3/OR3D3/OR3D4 OR4DH/OR4/OR4D2/OR4D4 OR5/OR5D2/OR5D4 Exclusive-NOR Cells Exclusive-OR Cells Combinational Cells XN2/XN2D2/XN2D4 XN3/XN3D2/XN3D4 XO2/XO2D2/XO2D4 XO3/XO3D2/XO3D4 AO2111/AO2111D2 AO22DHA/AO22A/AO22D2A/AO22D4A AO221/AO221D2/AO221D4 AO222/AO222D2/AO222D2B/AO222D4 AO222A/AO222D2A/AO222D4A AO2222/AO2222D2/AO2222D4 AO31DH/AO31/AO31D2/AO31D4 AO311/AO311D2/AO311D4 AO3111/AO3111D2 AO32/AO32D2/AO32D4 Page 3-17 3-19 3-21 3-24 3-27 3-29 3-32 3-35 3-38 3-42 3-46 3-49 3-53 3-56 3-60 3-64 3-68 3-70 3-73 3-76 3-80 3-82 3-84 3-86 3-88 3-91 3-94 3-97 3-100 3-103 3-107 3-112 3-114 3-118 3-121 3-125 3-128
STD110
ASIC
INTERNAL MACROCELLS
SUMMARY TABLES
Cell Type
Cell Name AO321/AO321D2/AO321D4 AO322/AO322D2/AO322D4 AO33/AO33D2/AO33D4 AO331/AO331D2/AO331D4 AO332/AO332D2/AO332D4 AO4111/AO4111D2
Page 3-132 3-136 3-140 3-144 3-148 3-152 3-155 3-158 3-161 3-164 3-167 3-170 3-174 3-179 3-183 3-186 3-190 3-193 3-197 3-201 3-205 3-209 3-213 3-217 3-220 3-223 3-225 3-228 3-231 3-234 3-236 3-239 3-241 3-243 3-246 3-248 3-250 3-252 3-254 3-256 3-258
Combinational Cells NAND
OA2111/OA2111D2 OA22DHA/OA22A/OA22D2A/OA22D4A OA221/OA221D2/OA221D4 OA222/OA222D2/OA222D2B/OA222D4 OA2222/OA2222D2/OA2222D4 OA31DH/OA31/OA31D2/OA31D4 OA311/OA311D2/OA311D4 OA3111/OA3111D2 OA32/OA32D2/OA32D4 OA321/OA321D2/OA321D4 OA322/OA322D2/OA322D4 OA33/OA33D2/OA33D4 OA331/OA331D2/OA331D4 OA332/OA332D2/OA332D4 OA4111/OA4111D2
Complex Cells
SCG1/SCG1D2 SCG2/SCG2D2 SCG3/SCGD2 SCG4/SCG4D2 SCG5/SCG5D2 SCG6/SCG6D2 SCG7/SCG7D2 SCG8/SCG8D2 SCG9/SCG9D2 SCG10/SCG10D2 SCG11/SCG11D2 SCG12/SCG12D2 SCG13/SCG13D2 SCG14/SCG14D2 SCG15/SCG15D2 SCG16/SCG16D2 SCG17/SCG17D2
ASIC
STD110
SUMMARY TABLES
INTERNAL MACROCELLS
Cell Type Complex Cells SCG18/SCG18D2 SCG19/SCG19D2 SCG20/SCG20D2 SCG21/SCG21D2 SCG22/SCG22D2 Delay Cells DL1D2/DL1D4 DL2D2/DL2D4 DL3D2/DL3D4 DL4D2/DL4D4 DL5D2/DL5D4 DL10D2/DL10D4 Inverters Inverting Tri-State Buffers Non-Inverting Buffers Clock Buffers core only Non-Inverting Tri-State Buffers Phase Clock Generator Buffers core only Clock Tree Synthesis Buffers
Cell Name
Page 3-260 3-263 3-265 3-267 3-269 3-271 3-272 3-273 3-274 3-275 3-276 3-277 3-280 3-282 3-284 3-286 3-289 3-290 3-293 3-296 3-298
IVCD(11/13)/IVCD(22/26)/IVCD44 IVT/IVTD2/IVTD4/IVTD8/IVTD16 OAK_NID10P/OAK_NID NIT/NITD2/NITD4/NITD8/NITD16 OAK_DUCLK10/OAK_DUCLK16 CTSB/2/3/4/6/8/16
Flip-Flops
Cell Type Flip-Flop FD1/FD1D2 FD1CS/FD1CSD2 FD1S/FD1SD2 FD1SQ/FD1SQD2 FD1Q/FD1QD2 Flip-Flop with Reset FD2/FD2D2 FD2CS/FD2CSD2 FD2S/FD2SD2 FD2SQ/FD2SQD2 FD2Q/FD2QD2 Flip-Flop with FD3/FD3D2 FD3CS/FD3CSD2 FD3S/FD3SD2 FD3SQ/FD3SQD2 FD3Q/FD3QD2 Cell Name Page 3-303 3-305 3-307 3-309 3-311 3-313 3-315 3-319 3-321 3-323 3-325 3-327 3-331 3-333 3-335
STD110
ASIC
INTERNAL MACROCELLS
SUMMARY TABLES
Cell Type Flip-Flop with Reset, FD4/FD4D2 FD4CS/FD4CSD2 FD4S/FD4SD2 FD4SQ/FD4SQD2 FD4Q/FD4QD2 Flip-Flop with Negative Edge Trigger FD5/FD5D2 FD5S/FD5SD2 FD6/FD6D2 FD6S/FD6SD2 FD7/FD7D2 FD7S/FD7SD2 FD8/FD8D2 FD8S/FD8SD2 Flip-Flop with Synchronous Clear FDS2/FDS2D2
Cell Name
Page 3-337 3-340 3-344 3-348 3-351 3-353 3-355 3-357 3-359 3-361 3-363 3-365 3-368 3-372 3-374 3-376 3-378 3-380 3-382 3-384 3-386 3-388 3-390 3-392 3-395 3-398
FDS2CS/FDS2CSD2 FDS2S/FDS2SD2 FDS3/FDS3D2 FDS3CS/FDS3CSD2 FDS3S/FDS3SD2 Flip-Flop FJ1/FJ1D2 FJ1S/FJ1SD2 FJ2/FJ2D2 FJ2S/FJ2SD2 FJ4/FJ4D2 FJ4S/FJ4SD2 Toggle Flip-Flop FT2/FT2D2
Latches
Cell Type Latch with Active High LD1/LD1D2 LD1A/LD1D2A LD1Q/LD1QD2 LD2/LD2D2 LD2Q/LD2QD2 LD3/LD3D2 LD4/LD4D2 Latch with Active LD5/LD5D2 LD5Q/LD5QD2 LD6/LD6D2 LD6Q/LD6QD2 Cell Name Page 3-402 3-404 3-406 3-408 3-411 3-413 3-416 3-419 3-421 3-423 3-426
ASIC
STD110
SUMMARY TABLES
INTERNAL MACROCELLS
Cell Type LD7/LD7D2 LD8/LD8D2 Latch with Active core only Latch
Cell Name
Page 3-428 3-431 3-434 3-437 3-442 3-444
OAK_LDI2/OAK_LDI2D2 OAK_LDI3/OAK_LDI3D2 LS0/LS0D2 LS1/LS1D2
Holder
Cell Type Holder BUSHOLDER Cell Name Page 3-448
Internal Clock Drivers
Cell Type Internal Clock Drivers CK(2/4/6/8) Cell Name Page 3-449
Decoders
Cell Type Non-Inverting Decoder Inverting Decoders DC4I DC8I Cell Name Page 3-452 3-454 3-456
Adders
Cell Type Full Adders Half Adders Complex Cells FADH/FA/FAD2 HADH/HA/HAD2 SCG23/SCG23D2 Cell Name Page 3-461 3-464 3-467
Multiplexers
Cell Type Non-Inverting Inverting MX2X4 MX2IDH/MX2I/MX2ID2/MX2ID4 MX2IDHA/MX2IA/MX2ID2A/MX2ID4A MX2IX4 Inverting Non-Inverting Non-Inverting MX3I/MX3ID2/MX3ID4 MX4/MX4D2/MX4D4 MX8/MX8D2/MX8D4 Cell Name MX2DH/MX2/MX2D2/MX2D4 Page 3-471 3-474 3-477 3-480 3-483 3-486 3-490 3-494
STD110
ASIC
LOGIC CELLS
Cell Names Function Descriptions
Cell Name AD2DH AD2D2 AD2D4 AD3DH AD3D2 AD3D4 AD4DH AD4D2 AD4D4 AD5D2 AD5D4 ND2DH ND2D2 ND2D4 ND3DH ND3D2 ND3D4 ND4DH ND4D2 ND4D2B ND4D4 ND5D2 ND5D4 ND6D2 ND6D4 ND8D2 ND8D4 Function Description 2-Input with 0.5X Drive 2-Input with Drive 2-Input with Drive 2-Input with Drive 3-Input with 0.5X Drive 3-Input with Drive 3-Input with Drive 3-Input with Drive 4-Input with 0.5X Drive 4-Input with Drive 4-Input with Drive 4-Input with Drive 5-Input with Drive 5-Input with Drive 5-Input with Drive 2-Input NAND with 0.5X Drive 2-Input NAND with Drive 2-Input NAND with Drive 2-Input NAND with Drive 3-Input NAND with 0.5X Drive 3-Input NAND with Drive 3-Input NAND with Drive 3-Input NAND with Drive 4-Input NAND with 0.5X Drive 4-Input NAND with Drive 4-Input NAND with Drive 4-Input NAND with (Buffered) Drive 4-Input NAND with Drive 5-Input NAND with Drive 5-Input NAND with Drive 5-Input NAND with Drive 6-Input NAND with Drive 6-Input NAND with Drive 6-Input NAND with Drive 8-Input NAND with Drive 8-Input NAND with Drive 8-Input NAND with Drive
ASIC
STD110
LOGIC CELLS
Cell Names Function Descriptions (Continued)
Cell Name NR2DH NR2D2 NR2D2B NR2D4 NR2A NR3DH NR3D2 NR3D2B NR3D4 NR3A NR4DH NR4D2 NR4D4 NR5D2 NR5D4 NR6D2 NR6D4 NR8D2 NR8D4 OR2DH OR2D2 OR2D4 OR3DH OR3D2 OR3D4 OR4DH OR4D2 OR4D4 Function Description 2-Input with 0.5X Drive 2-Input with Drive 2-Input with Drive 2-Input with (Buffered) Drive 2-Input with Drive with P-Transistor, N-Transistor 3-Input with 0.5X Drive 3-Input with Drive 3-Input with Drive 3-Input with (Buffered) Drive 3-Input with Drive with P-Transistor, N-Transistor 4-Input with 0.5X Drive 4-Input with Drive 4-Input with Drive 4-Input with Drive 5-Input with Drive 5-Input with Drive 5-Input with Drive 6-Input with Drive 6-Input with Drive 6-Input with Drive 8-Input with Drive 8-Input with Drive 8-Input with Drive 2-Input with 0.5X Drive 2-Input with Drive 2-Input with Drive 2-Input with Drive 3-Input with 0.5X Drive 3-Input with Drive 3-Input with Drive 3-Input with Drive 4-Input with 0.5X Drive 4-Input with Drive 4-Input with Drive 4-Input with Drive
STD110
ASIC
LOGIC CELLS
Cell Names Function Descriptions (Continued)
Cell Name OR5D2 OR5D4 XN2D2 XN2D4 XN3D2 XN3D4 XO2D2 XO2D4 XO3D2 XO3D4 AO21DH AO21 AO21D2 AO21D2B AO21D4 AO211DH AO211 AO211D2 AO211D2B AO211D4 AO2111 AO2111D2 AO22DH AO22 AO22D2 AO22D2B AO22D4 AO22DHA AO22A AO22D2A AO22D4A Function Description 5-Input with Drive 5-Input with Drive 5-Input with Drive 2-Input Exclusive-NOR with Drive 2-Input Exclusive-NOR with Drive 2-Input Exclusive-NOR with Drive 3-Input Exclusive-NOR with Drive 3-Input Exclusive-NOR with Drive 3-Input Exclusive-NOR with Drive 2-Input Exclusive-OR with Drive 2-Input Exclusive-OR with Drive 2-Input Exclusive-OR with Drive 3-Input Exclusive-OR with Drive 3-Input Exclusive-OR with Drive 3-Input Exclusive-OR with Drive 2-AND into 2-NOR with 0.5X Drive 2-AND into 2-NOR with Drive 2-AND into 2-NOR with Drive 2-AND into 2-NOR with 2X(Buffered) Drive 2-AND into 2-NOR with Drive 2-AND into 3-NOR with 0.5X Drive 2-AND into 3-NOR with Drive 2-AND into 3-NOR with Drive 2-AND into 3-NOR with 2X(Buffered) Drive 2-AND into 3-NOR with Drive 2-AND into 4-NOR with Drive 2-AND into 4-NOR with Drive 2-ANDs into 2-NOR with 0.5X Drive 2-ANDs into 2-NOR with Drive 2-ANDs into 2-NOR with Drive 2-ANDs into 2-NOR with 2X(Buffered) Drive 2-ANDs into 2-NOR with Drive 2-AND 2-NOR into 2-NOR with 0.5X Drive 2-AND 2-NOR into 2-NOR with Drive 2-AND 2-NOR into 2-NOR with Drive 2-AND 2-NOR into 2-NOR with Drive
ASIC
STD110
LOGIC CELLS
Cell Names Function Descriptions (Continued)
Cell Name AO221 AO221D2 AO221D4 AO222 AO222D2 AO222D2B AO222D4 AO222A AO222D2A AO222D4A AO2222 AO2222D2 AO2222D4 AO31DH AO31 AO31D2 AO31D4 AO311 AO311D2 AO311D4 AO3111 AO3111D2 AO32 AO32D2 AO32D4 AO321 AO321D2 AO321D4 AO322 AO322D2 AO322D4 AO33 AO33D2 AO33D4 AO331 AO331D2 AO331D4 Function Description 2-ANDs into 3-NOR with Drive 2-ANDs into 3-NOR with Drive 2-ANDs into 3-NOR with Drive Three 2-ANDs into 3-NOR with Drive Three 2-ANDs into 3-NOR with Drive Three 2-ANDs into 3-NOR with 2X(Buffered) Drive Three 2-ANDs into 3-NOR with Drive Inverting 2-of-3 Majority with Drive Inverting 2-of-3 Majority with Drive Inverting 2-of-3 Majority with Drive Four 2-ANDs into 4-NOR with Drive Four 2-ANDs into 4-NOR with Drive Four 2-ANDs into 4-NOR with Drive 3-AND into 2-NOR with 0.5X Drive 3-AND into 2-NOR with Drive 3-AND into 2-NOR with Drive 3-AND into 2-NOR with Drive 3-AND into 3-NOR with Drive 3-AND into 3-NOR with Drive 3-AND into 3-NOR with Drive 3-AND into 4-NOR with Drive 3-AND into 4-NOR with Drive 3-AND 2-AND into 2-NOR with Drive 3-AND 2-AND into 2-NOR with Drive 3-AND 2-AND into 2-NOR with Drive 3-AND 2-AND into 3-NOR with Drive 3-AND 2-AND into 3-NOR with Drive 3-AND 2-AND into 3-NOR with Drive 3-AND 2-ANDs into 3-NOR with Drive 3-AND 2-ANDs into 3-NOR with Drive 3-AND 2-ANDs into 3-NOR with Drive 3-ANDs into 2-NOR with Drive 3-ANDs into 2-NOR with Drive 3-ANDs into 2-NOR with Drive 3-ANDs into 3-NOR with Drive 3-ANDs into 3-NOR with Drive 3-ANDs into 3-NOR with Drive
STD110
3-10
ASIC
LOGIC CELLS
Cell Names Function Descriptions (Continued)
Cell Name AO332 AO332D2 AO332D4 AO4111 AO4111D2 OA21DH OA21 OA21D2 OA21D2B OA21D4 OA211DH OA211 OA211D2 OA211D2B OA211D4 OA2111 OA2111D2 OA22DH OA22 OA22D2 OA22D2B OA22D4 OA22DHA OA22A OA22D2A OA22D4A OA221 OA221D2 OA221D4 OA222 OA222D2 OA222D2B OA222D4 OA2222 OA2222D2 OA2222D4 Function Description 3-ANDs 2-AND into 3-NOR 3-ANDs 2-AND into 3-NOR with Drive 3-ANDs 2-AND into 3-NOR with Drive 4-AND into 4-NOR with Drive 4-AND into 4-NOR with Drive 2-OR into 2-NAND with 0.5X Drive 2-OR into 2-NAND with Drive 2-OR into 2-NAND with Drive 2-OR into 2-NAND with 2X(Buffered) Drive 2-OR into 2-NAND with Drive 2-OR into 3-NAND with 0.5X Drive 2-OR into 3-NAND with Drive 2-OR into 3-NAND with Drive 2-OR into 3-NAND with 2X(Buffered) Drive 2-OR into 3-NAND with Drive 2-OR into 4-NAND with Drive 2-OR into 4-NAND with Drive 2-ORs into 2-NAND with 0.5X Drive 2-ORs into 2-NAND with Drive 2-ORs into 2-NAND with Drive 2-ORs into 2-NAND with 2X(Buffered) Drive 2-ORs into 2-NAND with Drive 2-OR 2-NAND into 2-NAND with 0.5X Drive 2-OR 2-NAND into 2-NAND with Drive 2-OR 2-NAND into 2-NAND with Drive 2-OR 2-NAND into 2-NAND with Drive 2-ORs into 3-NAND with Drive 2-ORs into 3-NAND with Drive 2-ORs into 3-NAND with Drive Three 2-ORs into 3-NAND with Drive Three 2-ORs into 3-NAND with Drive Three 2-ORs into 3-NAND with 2X(Buffered) Drive Three 2-ORs into 3-NAND with Drive Four 2-ORs into 4-NAND with Drive Four 2-ORs into 4-NAND with Drive Four 2-ORs into 4-NAND with Drive
ASIC
3-11
STD110
LOGIC CELLS
Cell Names Function Descriptions (Continued)
Cell Name OA31DH OA31 OA31D2 OA31D4 OA311 OA311D2 OA311D4 OA3111 OA3111D2 OA32 OA32D2 OA32D4 OA321 OA321D2 OA321D4 OA322 OA322D2 OA322D4 OA33 OA33D2 OA33D4 OA331 OA331D2 OA331D4 OA332 OA332D2 OA332D4 OA4111 OA4111D2 SCG1 SCG1D2 SCG2 SCG2D2 SCG3 SCG3D2 SCG4 SCG4D2 Function Description 3-OR into 2-NAND with 0.5X Drive 3-OR into 2-NAND with Drive 3-OR into 2-NAND with Drive 3-OR into 2-NAND with Drive 3-OR into 3-NAND with Drive 3-OR into 3-NAND with Drive 3-OR into 3-NAND with Drive 3-OR into 4-NAND with Drive 3-OR into 4-NAND with Drive 3-OR 2-OR into 2-NAND with Drive 3-OR 2-OR into 2-NAND with Drive 3-OR 2-OR into 2-NAND with Drive 3-OR 2-OR into 3-NAND with Drive 3-OR 2-OR into 3-NAND with Drive 3-OR 2-OR into 3-NAND with Drive 3-OR 2-ORs into 3-NAND with Drive 3-OR 2-ORs into 3-NAND with Drive 3-OR 2-ORs into 3-NAND with Drive 3-ORs into 2-NAND with Drive 3-ORs into 2-NAND with Drive 3-ORs into 2-NAND with Drive 3-ORs into 3-NAND with Drive 3-ORs into 3-NAND with Drive 3-ORs into 3-NAND with Drive 3-ORs 2-OR into 3-NAND with Drive 3-ORs 2-OR into 3-NAND with Drive 3-ORs 2-OR into 3-NAND with Drive 4-OR into 4-NAND with Drive 4-OR into 4-NAND with Drive 2-NAND (2-AND into 2-NOR)s into 3-NAND 2-NAND (2-AND into 2-NOR)s into 3-NAND with Drive 2-ANDs into 2-OR 2-ANDs into 2-OR with Drive 2-NANDs into 3-NAND 2-NANDs into 3-NAND with Drive (two 2-ANDs into 2-NOR)s into 2-NAND (two 2-ANDs into 2-NOR)s into 2-NAND with Drive
STD110
3-12
ASIC
LOGIC CELLS
Cell Names Function Descriptions (Continued)
Cell Name SCG5 SCG5D2 SCG6 SCG6D2 SCG7 SCG7D2 SCG8 SCG8D2 SCG9 SCG9D2 SCG10 SCG10D2 SCG11 SCG11D2 SCG12 SCG12D2 SCG13 SCG13D2 SCG14 SCG14D2 SCG15 SCG15D2 SCG16 SCG16D2 SCG17 SCG17D2 SCG18 SCG18D2 SCG19 SCG19D2 SCG20 SCG20D2 SCG21 SCG21D2 SCG22 SCG22D2 SCG23 SCG23D2 Function Description Three 2-ANDs into 3-OR Three 2-ANDs into 3-OR with Drive 2-AND into 2-OR 2-AND into 2-OR with Drive 2-NAND (2-AND into 2-NOR) into 2-NAND 2-NAND (2-AND into 2-NOR) into 2-NAND with Drive 2-AND into 3-OR 2-AND into 3-OR with Drive 2-OR into 2-AND 2-OR into 2-AND with Drive 2-ORs into 2-AND 2-ORs into 2-AND with Drive 2-NORs into 3-NOR 2-NORs into 3-NOR with Drive 2-NAND into 2-NOR 2-NAND into 2-NOR with Drive 2-NOR into 2-NAND 2-NOR into 2-NAND with Drive 2-NAND into 2-NAND 2-NAND into 2-NAND with Drive 2-NAND into 3-NAND 2-NAND into 3-NAND with Drive 2-OR with inverted input into 2-NAND 2-OR with inverted input into 2-NAND with Drive 2-AND into 2-NOR into 2-NAND 2-AND into 2-NOR into 2-NAND with Drive 2-AND into 2-NOR into 3-NAND 2-AND into 2-NOR into 3-NAND with Drive 2-AND into 2-AND into 2-NOR 2-AND into 2-AND into 2-NOR with Drive 2-NOR into 2-NOR 2-NOR into 2-NOR with Drive 2-NOR into 3-NOR 2-NOR into 3-NOR with Drive 2-NAND into 2-OR into 2-NAND 2-NAND into 2-OR into 2-NAND with Drive Full Adder with inverted input with Drive Full Adder with inverted input with Drive
ASIC
3-13
STD110
LOGIC CELLS
Cell Names Function Descriptions (Continued)
Cell Name DL1D2 DL1D4 DL2D2 DL2D4 DL3D2 DL3D4 DL4D2 DL4D4 DL5D2 DL5D4 DL10D2 DL10D4 IVDH IVD2 IVD3 IVD4 IVD6 IVD8 IVD16 IVCD11 IVCD13 IVCD22 IVCD26 IVCD44 IVTD2 IVTD4 IVTD8 IVTD16 IVTN IVTND2 IVTND4 IVTND8 IVTND16 NIDH NID2 Function Description Delay Cell with Drive Delay Cell with Drive Delay Cell with Drive Delay Cell with Drive Delay Cell with Drive Delay Cell with Drive Delay Cell with Drive Delay Cell with Drive Delay Cell with Drive Delay Cell with Drive 10ns Delay Cell with Drive 10ns Delay Cell with Drive Inverter with 0.5X Drive Inverter with Drive Inverter with Drive Inverter with Drive Inverter with Drive Inverter with Drive Inverter with Drive Inverter with Drive Inverter into Inverter Inverter into Inverter Inverter into Inverter Inverter into Inverter Inverter into Inverter Inverting Tri-State Buffer with Enable High, Drive Inverting Tri-State Buffer with Enable High, Drive Inverting Tri-State Buffer with Enable High, Drive Inverting Tri-State Buffer with Enable High, Drive Inverting Tri-State Buffer with Enable High, Drive Inverting Tri-State Buffer with Enable Low, Drive Inverting Tri-State Buffer with Enable Low, Drive Inverting Tri-State Buffer with Enable Low, Drive Inverting Tri-State Buffer with Enable Low, Drive Inverting Tri-State Buffer with Enable Low, Drive Non-Inverting Buffer with 0.5X Drive Non-Inverting Buffer with Drive Non-Inverting Buffer with Drive
STD110
3-14
ASIC
LOGIC CELLS
Cell Names Function Descriptions (Continued)
Cell Name NID3 NID4 NID6 NID8 NID16 OAK_NID10P OAK_NID20P NITD2 NITD4 NITD8 NITD16 NITN NITND2 NITND4 NITND8 NITND16 OAK_DUCLK10 OAK_DUCLK16 CTSB CTSBD2 CTSBD3 CTSBD4 CTSBD6 CTSBD8 CTSBD16 Function Description Non-Inverting Buffer with Drive Non-Inverting Buffer with Drive Non-Inverting Buffer with Drive Non-Inverting Buffer with Drive Non-Inverting Buffer with Drive Clock Buffer 10pF Drive (for core only) Clock Buffer 20pF Drive (for core only) Non-Inverting Tri-State Buffer with Enable High, Drive Non-Inverting Tri-State Buffer with Enable High, Drive Non-Inverting Tri-State Buffer with Enable High, Drive Non-Inverting Tri-State Buffer with Enable High, Drive Non-Inverting Tri-State Buffer with Enable High, Drive Non-Inverting Tri-State Buffer with Enable Low, Drive Non-Inverting Tri-State Buffer with Enable Low, Drive Non-Inverting Tri-State Buffer with Enable Low, Drive Non-Inverting Tri-State Buffer with Enable Low, Drive Non-Inverting Tri-State Buffer with Enable Low, Drive Phase Clock Generator (1ns Non-overlapped, core only) Phase Clock Generator (1.6ns Non-overlapped, core only) Clock Tree Synthesis Buffer with Drive Clock Tree Synthesis Buffer with Drive Clock Tree Synthesis Buffer with Drive Clock Tree Synthesis Buffer with Drive Clock Tree Synthesis Buffer with Drive Clock Tree Synthesis Buffer with Drive Clock Tree Synthesis Buffer with Drive
ASIC
3-15
STD110
NOTE
STD110
3-16
ASIC
AD2DH/AD2/AD2D2/AD2D4
2-Input with 0.5X/1X/2X/4X Drive Logic Symbol
Truth Table
Cell Data
AD2DH
Input Load (SL) AD2D2
AD2D4
AD2DH
1.33
Gate Count AD2D2 AD2D4 1.33 1.67 2.33
Switching Characteristics
AD2DH
Path
(Typical process, 25°C, 2.5V, tR/tF 0.21ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.060 0.065*SL 0.049 0.052*SL 0.132 0.029*SL 0.136 0.027*SL 0.060 0.065*SL 0.052 0.051*SL 0.128 0.029*SL 0.151 0.027*SL
Parameter
Delay [ns]
Group3*
0.052 0.066*SL 0.043 0.052*SL 0.133 0.029*SL 0.137 0.027*SL 0.053 0.066*SL 0.044 0.052*SL 0.129 0.029*SL 0.152 0.027*SL
0.195 0.068 0.063*SL 0.156 0.056 0.050*SL 0.187 0.128 0.030*SL 0.188 0.131 0.029*SL 0.194 0.067 0.064*SL 0.159 0.060 0.049*SL 0.183 0.123 0.030*SL 0.203 0.145 0.029*SL *Group1 *Group2 *Group3
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.059 0.029*SL 0.051 0.025*SL 0.126 0.014*SL 0.131 0.014*SL 0.058 0.029*SL 0.052 0.025*SL 0.120 0.014*SL 0.145 0.014*SL
Group3*
0.052 0.030*SL 0.044 0.026*SL 0.129 0.013*SL 0.133 0.014*SL 0.052 0.030*SL 0.047 0.026*SL 0.124 0.013*SL 0.148 0.014*SL
0.118 0.061 0.028*SL 0.103 0.055 0.024*SL 0.150 0.120 0.015*SL 0.155 0.124 0.016*SL 0.118 0.061 0.029*SL 0.104 0.055 0.025*SL 0.144 0.114 0.015*SL 0.169 0.138 0.016*SL *Group1 *Group2 *Group3
ASIC
3-17
STD110
AD2DH/AD2/AD2D2/AD2D4
2-Input with 0.5X/1X/2X/4X Drive Switching Characteristics
AD2D2
Path
(Typical process, 25°C, 2.5V, tR/tF 0.21ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.062 0.014*SL 0.054 0.013*SL 0.142 0.007*SL 0.150 0.008*SL 0.063 0.014*SL 0.056 0.013*SL 0.135 0.007*SL 0.163 0.008*SL
Parameter
Delay [ns]
Group3*
0.055 0.015*SL 0.050 0.014*SL 0.152 0.007*SL 0.159 0.007*SL 0.055 0.015*SL 0.053 0.013*SL 0.145 0.007*SL 0.173 0.007*SL
0.090 0.062 0.014*SL 0.079 0.052 0.014*SL 0.154 0.136 0.009*SL 0.162 0.142 0.010*SL 0.091 0.061 0.015*SL 0.081 0.054 0.014*SL 0.147 0.129 0.009*SL 0.175 0.155 0.010*SL *Group3 *Group1 *Group2
AD2D4
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.067 0.007*SL 0.058 0.007*SL 0.157 0.004*SL 0.159 0.004*SL 0.068 0.007*SL 0.063 0.007*SL 0.149 0.004*SL 0.170 0.004*SL
Group3*
0.064 0.008*SL 0.057 0.007*SL 0.171 0.003*SL 0.173 0.004*SL 0.064 0.008*SL 0.060 0.007*SL 0.164 0.003*SL 0.185 0.004*SL
0.083 0.068 0.007*SL 0.071 0.057 0.007*SL 0.162 0.151 0.005*SL 0.164 0.153 0.006*SL 0.082 0.066 0.008*SL 0.074 0.059 0.008*SL 0.155 0.144 0.005*SL 0.176 0.164 0.006*SL *Group3 *Group1 *Group2
STD110
3-18
ASIC
AD3DH/AD3/AD3D2/AD3D4
3-Input with 0.5X/1X/2X/4X Drive Logic Symbol
Truth Table
Cell Data
AD3DH
Input Load (SL) AD3D2
AD3D4
Gate Count AD3DH AD3D2 AD3D4 1.67 1.67 2.00 2.67
Switching Characteristics
AD3DH
Path
(Typical process, 25°C, 2.5V, tR/tF 0.21ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.079 0.064*SL 0.060 0.051*SL 0.178 0.029*SL 0.168 0.027*SL 0.079 0.0

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