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NT7705

160 Output LCD Segment / Common Driver

NT7705
160 Output LCD Segment / Common Driver
Features
General Description
Ver1.0
NT7705
Pad Configuration
NT7705
Dummy Pad
Block Diagram
V12R V43R
Y159 Y160
FR Level Shifter
DISPOFF
160 Bits 4 Level Driver
V43L V12L
160 Bits Level Shifter
EIO1 Active Control EIO2
8Bits x 2 Data Latch
160 Bits Line Latch / Shift Register
CMD LP XCK Control Logic
Data Latch Control
SP Conversion & Data Control (4 to 8 or 8 to 8)
Ver1.0
NT7705
Pad Description
Pad No. 224-226 227-229 230-232 1-2 3-6, 49-52 7-8 9-10 11-16 17-18 19-20 21-34 35-36 37-38 39-40
Designation V0L V12L V43L V5L VSS CMD L / R VDD S / C EIO2 D0 - D6 D7 XCK
DISPOFF LP EIO1 FR MD V5R V43R V12R V0R Y1 - Y160
Description Power supply for LCD driver Power supply for LCD driver Power supply for LCD driver Power supply for LCD driver Ground (0V), these pads must be connected to each other Common mode output selection pin Display data shift direction selection Power supply for the logic system (+2.5 to + 5.5V) Segment mode / common mode selection Input / output for chip select or data of shift register Display data input for segment mode Display data input for Segment mode / Dual mode data input Display data shift clock input for segment mode
Control input for deselect output level Latch pulse input / shift clock input for the shift register Input / output for chip select or data of the shift register AC-converting signal input for LCD driver waveform Mode selection input Power supply for LCD driver Power supply for LCD driver Power supply for LCD driver Power supply for LCD driver LCD driver output
Ver1.0
NT7705
Input / Output Circuits
Input Signal
Applicable Pins L / R, S / C, D0 - D6, DUTY DISPOFF , LP, FR, MD
Input Circuit (1)
I Control Signal
Input Signal
Applicable Pins D7, XCK
Input Circuit (2)
Ver1.0
NT7705
Input Signal Control Signal
VSS VDD
VSS Output Signal
Control Signal
Input / Output Circuit
Applicable Pins EIO1, EIO2
Control Signal 1 O Control Signal 3
Control Signal 2
Control Signal 4
Applicable Pins Y1 to Y160
V43 VSS V5
LCD Driver Output circuit
Ver1.0
NT7705
Pad Description
Segment mode
Symbol
VDD VSS VOR, VOL V12R, V12L V43R, V43L V5R, V5L
Function
XCK LP
# While DISPOFF is set to "L", the contents of the line latch are reset, but the display data in the data latch
Ver1.0
NT7705
Segment mode continued
Symbol
Function
Segment mode / common mode selection pin # When set to VDD level "H", segment mode is set. # When set to VSS level "L", common mode is set. Input / output pin for chip selection # When L / R input is at VSS level "L", EIO1 is set for output, and EIO2 is set for input. # When L / R input is at VDD level "H", EIO1 is set for input, and EIO2 is set for output. # During output, it is set to "H" while LP XCK is "H" and after 160-bits of data have been read, it is set to "L" for one cycle (from falling edge to falling edge of XCK), after which it returns to "H" # During input, after the LP signal is input, the chip is selected while EI is set to "L". After 160-bits of data have been read, the chip is deselected
EIO1, EIO2
Y1 - Y160
LCD driver output pins These corresponding directly to each bit of the data latch, one level (V0, V12, V43, or V5) is selected and output
Common mode
Symbol Function
VDD VSS V0R, V0L V12R, V12L V43R, V43L V5R, V5L
Ver1.0
NT7705
Common mode continued
Symbol Function
Control input pin for output deselect level # The input signal is level-shifted from the logic voltage level to the LCD driver voltage level and it controls the LCD driver circuit # When set to VSS level "L", the LCD driver output pins (Y1 - Y160) are set to level V5 DISPOFF
# While set to "L", the contents of the shift resister are reset and not reading data. When the DISPOFF function is canceled, the driver outputs deselect level (V12 or V34), and the shift data is read on the falling
Y1 - Y160
Ver1.0
NT7705
Functional Description
1. Block description 1.1. Active Control In the case of segment mode, controls the selection or deselection of the chip. Following a LP signal input, and after the select signal is input, a select signal is generated internally until 160 bits of data have been read in. Once data input has been completed, a select signal for cascade connection is output, and the ship is deselected. 1.5. Line Latch / Shift Register
In the case of the segment mode, all 160 bits which have been read into the data latch, are simultaneously latched on to the falling edge of the LP signal, and output to the level shift block. In the case of the common mode, shifts data from the data input pin on to the falling edge of the LP signal.
1.6. Level Shifter
In the case of common mode, controls the input / output data of bidirectional pins. 1.2. SP Conversion & Data Control In the case of segment mode, keep input data which are 2 clocks of XCK at 4-bit parallel mode into latch circuit, or keep input data which are 1 clock of XCK at 8-bit parallel mode into latch circuit, after that they are put on the internal data bus 8 bits at a time. 1.3. Data Latch Control In the case of the segment mode, it selects the state of the data latch, which reads in the data bus signals. The shift direction is controlled by the control logic and for every 16 bits of data read in, the selection signal shifts one bit, based on the state of the control circuit. 1.4. Data Latch In the case of the segment mode, it latches the data on the data bus. The latched state of each LCD driver output pin is controlled by the control logic and the data latch control 160 bits of data are read in 20 sets of 8 bits.
The logic voltage signal is level-shifted to the LCD driver voltage level, and output to the driver block.
1.7. 4-Level Driver
It drives the LCD driver output pins from the line latch / shift register data, selecting one of 4 levels (V0, V12, V43, V5) based on the S / C, FR and DISPOFF signals.
1.8. Control Logic
It controls the operation of each block. In the case of the segment mode, when an LP signal has been input, all blocks are reset and the control logic waits for the selection signal output from the active control block. Once the selection signal has been output, operation of the data latch and data transmission are controlled, 160 bits of data are read in, and the chip is deselected. In the case of the common mode, it controls the direction of the data shift.
Ver1.0
NT7705
2. LCD Driver Output Voltage Level
The relationship amongst the data bus signal, AC converted signal FR and LCD driver output voltage is as shown in the table below:
2.1. Segment Mode FR Latch Data
DISPOFF Driver Output Voltage Level (Y1 - Y160)
V43 V5 V12 V0 V5
2.2. Common Mode FR Latch Data DISPOFF Driver Output Voltage Level (Y1 - Y160)
V43 V0 V12 V5 V5
Ver1.0
NT7705
3. Relationship between the Display Data and Driver Output Pins 3.1. Segment Mode:
(a) 4-bit Parallel Mode
MD L / R EIO1 EIO2 Data Input 40clock Y1 Y2 Y3 Y4 Y160 Y159 Y158 Y157 39clock Y5 Y6 Y7 Y8 Y156 Y155 Y154 Y153 Number of Clock 38clcok ~ 3clock ~ Y9 Y149 ~ Y10 Y150 ~ Y11 Y151 ~ Y12 Y152 ~ Y152 Y12 ~ Y151 Y11 ~ Y150 Y10 ~ Y149 Y9 2clock Y153 Y154 Y155 Y156 Y8 Y7 Y6 Y5 1clock Y157 Y158 Y159 Y160 Y4 Y3 Y2 Y1
Output Input
Input Output
(b) 8-bit Parallel Mode
MD L / R EIO1 EIO2 Data Input 20clock Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y160 Y159 Y158 Y157 Y156 Y155 Y154 Y153 19clock Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y152 Y151 Y150 Y149 Y148 Y147 Y146 Y145 Number of Clock 18clcok ~ 3clock Y17 ~ Y137 Y18 ~ Y138 Y19 ~ Y139 Y20 ~ Y140 Y21 ~ Y141 Y22 ~ Y142 Y23 ~ Y143 Y24 ~ Y144 Y144 ~ Y24 Y143 ~ Y23 Y142 ~ Y22 Y141 ~ Y21 Y140 ~ Y20 Y139 ~ Y19 Y138 ~ Y18 Y137 ~ Y17 2clock Y145 Y146 Y147 Y148 Y149 Y150 Y151 Y152 Y16 Y15 Y14 Y13 Y12 Y11 Y10 Y9 1clock Y153 Y154 Y155 Y156 Y157 Y158 Y159 Y160 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1
Output Input
Input Output
Ver1.0
NT7705
3.2. Common Mode MD CMD L / R Data Transfer Direction Y1~Y60 Output pins Y61~Y100 Y101~Y160 EIO1 EIO2 D7
L (Single) L (Single)
L (shift to left) H (shift to right)
Y160 to Y1 Y1 to Y160
Output Output Output Output Output
Output Output NC NC Output
Output Output Output Output Output
Output Input Output Input Output
Input Output Input Output Input
L (shift to left) Y160 to Y101, Y60 to Y1 H (shift to right) Y1 to Y60 , Y101 to Y160 L (shift to left) Y160 to Y81 Y80 to Y1 Y1 to Y80 Y81 to Y160
H (Dual)
X H (shift to right)
Output
Input
Output
Input
Ver1.0
NT7705
D0~D7
XCK LP MD FR D0~D7 VSS / 8
V SS V DD D0~D7 FR MD LP XCK
D0~D7
L / R EIO1 EIO2
last data
Ver1.0
NT7705
5. Timing Waveform of 4-Device Cascade Connection of Segment Drivers.
First data D0 - D7 n 1 2 device A EI (device A) n 1 2 device B n 1 2 device C n 1 2 device D
Last data n 1 2
EO (device A)
EO (device B)
EO (device C) n: 4-bit parallel mode 40 8-bit parallel mode 20
Ver1.0
NT7705
6. Connection Examples for Common Drivers
First
DISPOFF
LP VSS (VDD) VSS VSS DISPOFF FR
Single Mode (Shifting towards the left)
FR DISPOFF VDD VSS VSS (VDD) LP
DISPOFF
First
Single Mode (Sifting towards the right)
Ver1.0
NT7705
First
Y101 Y60
DISPOFF
LP V SS VSS VDD DISPOFF FR
Dual Mode (Shifting towards the left)
FR DISPOFF VDD VSS VSS LP
DISPOFF DISPOFF DISPOFF MD MD MD LP LP LP
Y101 Y60
First
Dual Mode (Sifting towards the right)
Ver1.0
NT7705
7. Precaution
Be careful when connecting or disconnecting the power This LSI has a high-voltage LCD driver, so it may be permanently damaged by a high current, which may occur, if a voltage is supplied to the LCD driver power supply while the logic system power supply is floating. The details are as follows:
When connecting the power supply, connect the LCD driver power after connecting the logic system power. Furthermore, when disconnecting the power, disconnect the logic system power after disconnecting the LCD driver power. We recommend that you connect a serial resistor (50-100) or fuse to the LCD driver power V0 of the system as a current limiting device. Also, set a suitable value for the resistor in consideration of the LCD display grade.
In addition, when connecting the logic power supply, the logic condition of the LSI inside is insecure. Therefore connect the LCD driver power supply after resetting logic condition of this LSI inside on DISPOFF function. After that, the DISPOFF cancel the function after the LCD driver power supply has become stable. Furthermore, when disconnecting the power, set the LCD driver output pins to level VSS on the DISPOFF function. After that, disconnect the logic system power after disconnecting the LCD driver power. When connecting the power supply, follow the recommended sequence shown.
VDD VSS VDD
DISPOFF
VSS V0
V0 VSS
Ver1.0
NT7705
Absolute Maximum Rating
DC Supply Voltage VDD . . . . . . . . . . . . -0.3V to +7.0V DC Supply Voltage V0 . . . . . . . . . . . . . -0.3V to +42.0V Input Voltage . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V Operating Ambient Temperature . . . . -30°C to +85°C Storage Temperature . . . . . . . . . . . . .-45°C to +125°C
Comments
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device under these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
Electrical Characteristics
DC Characteristics
Parameter Symbol Min. Typ. Max. Unit Condition
Operating Voltage Operating Voltage Input high voltage Input low voltage Output high voltage Output low voltage Input leakage current 1
VDD V0 VIH VIL VOH VOL IIH
2.5 15 0.8 VDD VDD - 0.4 -
5.5 40 0.2 VDD +0.4 +1
Input leakage current 2
Output resistance
Stand-by current Consumed current (1) (Deselection) Consumed current (2) (Selection) Consumed current Note:
ISB IDD1 IDD2 I0
VSS pin, Note 1 VDD pin, Note 2 VDD pin, Note 3 V0 pin, Note 4
Ver1.0
NT7705
Parameter
Operating Voltage Operating Voltage Input high voltage Input low voltage Output high voltage Output low voltage Input leakage current 1
Symbol
VDD V0 VIH VIL VOH VOL IIH
2.5 15 0.8 VDD VDD - 0.4 -
5.5 40 0.2 VDD +0.4 +1.0
Condition
Input leakage current 2
Output resistance Stand-by current Consumed current (1) Consumed current (2) Note:
RON ISB IDD I0
Ver1.0
NT7705
AC Characteristics
Parameter
Shift clock period Shift clock "H" pulse width Shift clock "L" pulse width Data setup time Data hole time Latch pulse "H" pulse width Shift clock rise to Latch pulse rise time Shift clock fall to Latch pulse fall time Latch pulse rise to Shift clock rise time Latch pulse fall to Shift clock rise time Input signal rise time Input signal fall time Enable setup time
Symbol
tWCK tWCKH tWCKL tDS tDH tWLPH tLD tSL tLS tLH tr tf tS tSD tWDL tD tpd1, tpd2 tpd3
Condition
tr, tf 10ns, Note 1
Note 2 Note 2
DISPOFF Removal time DISPOFF enable pulse width
Output delay time (1) Output delay time (2) Output delay time (3) Note
1. Take the cascade connection into consideration. 2. (Tck - tWCKII - twckl) / 2 is the maximum in the case of high speed operation.
Ver1.0
NT7705
Parameter
Shift clock period Shift clock "H" pulse width Shift clock "L" pulse width Data setup time Data hole time Latch pulse "H" pulse width Shift clock rise to Latch pulse rise time Shift clock fall to Latch pulse fall time Latch pulse rise to Shift clock rise time Latch pulse fall to Shift clock fall time Input signal rise time Input signal fall time Enable setup time DISPOFF Removal time DISPOFF enable pulse width Output delay time (1) Output delay time (2) Output delay time (3) Note
Symbol
tWCK tWCKH tWCKL tDS tDH tWLPH tLD tSL tLS tLH tr tf tS tSD tWDL tD tpd1, tpd2 tpd3
Condition
tr, tf 11ns, Note 1
Note 2 Note 2
1. Take the cascade connection into consideration. 2. (tCK - tWCKII - tWCKL) / 2 is the maximum in the case of high speed operation.
Ver1.0
NT7705
Timing waveform of the Segment Mode
tWLPH
tLD tLS
tLH tWCKH
tWCKL
tr tWCK
LAST DATA
TOP DATA
DISPOFF
n: 4-bit parallel mode 40 8-bit parallel mode 20
DISPOFF
Y1 - Y160
Ver1.0
NT7705
Parameter
Shift clock period Shift clock "H" pulse width Data setup time Data hole time Input signal rise time Input signal fall time DISPOFF Removal time DISPOFF enable pulse width Output delay time (1) Output delay time (2) Output delay time (3)
Symbol
tWLP tWLPH tSU tH tr tf tSD tWDL tDL tpd1, tpd2 tpd3
Condition
Ver1.0
NT7705
Timing Characteristics of Common Mode
tWLPH tSU
EIO2 (D7)
tWDL tSD
DISPOFF
Y1 - Y160
Ver1.0
NT7705
Application Circuit (for reference only)
SEG480 SEG479
Y1~Y160
FR LP DISPOFF CMD XCK
EIO1 MD S / C L / R D0~D7 EIO2
Y1~Y160
480320 DOT MATRIX LCD PANEL
FR LP DISPOFF CMD XCK S / C L / R D0~D7 EIO2
Y1~Y160
EIO1 MD LP DISPOFF CMD XCK S / C L / R D0~D7 EIO2
Y1~Y160
NT77052
DISPOFF
D0~D7
DISPOFF
D0~D7
(case of 1 / n bias)
DISPOFF
VSS V0 R R (n-4)R R R
LCD controller
V5 VDD VSS
XD0~XD7
Ver1.0
NT77053
NT7705
SEG640 SEG639
Y1~Y160
FR LP DISPOFF CMD XCK
EIO1 MD S / C L / R D0~D7 EIO2
Y1~Y160
FR LP DISPOFF CMD
EIO1 MD S / C L / R D0~D7 EIO2
640480 DOT MATRIX LCD PANEL
Y1~Y160
FR LP DISPOFF CMD XCK
EIO1 MD S / C L / R D0~D7 EIO2
Y1~Y160
EIO1 FR LP DISPOFF CMD XCK MD S / C L / R D0~D7 EIO2
Y1~Y240
NT77062
DISPOFF
D0~D7
DISPOFF
D0~D7
(case of 1 / n bias)
DISPOFF
VSS V0 R R (n-4)R R R
LCD controller
V5 VDD VSS
XD0~XD7
Ver1.0
NT77054
NT7705
Application and ITO Layout Notice(for reference only) Application Notices
ITO Layout NoticeIt is for application of COG type
Reference figure and characteristic of ITO Layout a). VDD / VSS of IC and VDD / VSS of FPC are almost at the same vertical level. ITO is very straight b). Closer IC to FPC, shorter the length of ITO
Ver1.0
NT7705
Bonding Diagram
9230um
NT7705
Dummy Pad
Pad Location
Pad No.
Designation
V5L V5L VSS VSS VSS VSS CMD CMD L / R L / R VDD VDD VDD VDD VDD VDD S / C S / C EIO2 EIO2 D0 D0 D1 D1 D2 D2 D3 D3 D4 D4
Pad No.
Designation
D5 D5 D6 D6 D7 D7 XCK XCK DISPOFF
DISPOFF
LP LP EIO1 EIO1 FR FR MD MD VSS VSS VSS VSS V5R V5R V43R V43R V43R V12R V12R V12R
1072um
Ver1.0
NT7705
Pad Location (continued)
Pad No.
Designation
V0R V0R V0R Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y25 Y26 Y27 Y28 Y29 Y30 Y31 Y32 Y33 Y34 Y35 Y36 Y37
Pad No.
Designation
Y38 Y39 Y40 Y41 Y42 Y43 Y44 Y45 Y46 Y47 Y48 Y49 Y50 Y51 Y52 Y53 Y54 Y55 Y56 Y57 Y58 Y59 Y60 Y61 Y62 Y63 Y64 Y65 Y66 Y67 Y68 Y69 Y70 Y71 Y72 Y73 Y74 Y75 Y76 Y77
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NT7705
Pad Location (continued)
Pad No.
Designation
Y78 Y79 Y80 Y81 Y82 Y83 Y84 Y85 Y86 Y87 Y88 Y89 Y90 Y91 Y92 Y93 Y94 Y95 Y96 Y97 Y98 Y99 Y100 Y101 Y102 Y103 Y104 Y105 Y106 Y107 Y108 Y109 Y110 Y111 Y112 Y113 Y114 Y115 Y116 Y117
Pad No.
Designation
Y118 Y119 Y120 Y121 Y122 Y123 Y124 Y125 Y126 Y127 Y128 Y129 Y130 Y131 Y132 Y133 Y134 Y135 Y136 Y137 Y138 Y139 Y140 Y141 Y142 Y143 Y144 Y145 Y146 Y147 Y148 Y149 Y150 Y151 Y152 Y153 Y154 Y155 Y156 Y157
Ver1.0
NT7705
Pad Location (continued)
Pad No.
Designation
Y158 Y159 Y160 V0L V0L V0L V12L
Pad No.
Designation
Dummy Pad Location (Total: 3 pad)
Ver1.0
NT7705
Package Information
NT7705
Chip Outline Dimensions
Symbol
unit: m
Dimensions in um
Symbol
Dimensions in um
58 38 70 78 35 24 23 51 153 unit: m
Pad Dimensions
Pad No.
Size X
Ver1.0
NT7705
Product Spec. Change Notice NT7705 Specification Revision History Version 1.0 0.3 0.2 0.0 Content Formal version released Operation Voltage V0 changed (30V to 40V) (Page 19, 20) Reference circuit modified (Page 26, 27) Pad Location Addition Original Date Apr. 2003 Mar. 2002 Jan. 2002 Jun. 2001
Ver1.0