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Output Segment/Common Driver (Segment mode) Shift Clock frequency


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NT7705
Output Segment/Common Driver
(Segment mode) Shift Clock frequency (Max.) (VDD 10%) (Max.) (VDD 2.5V 4.5V) Adopts data system 4-bit/8-bit parallel input modes selectable with mode (MD) Automatic transfer function with enable signal Automatic counting function when chip select mode, causes internal clock stopped automatically counting bits input data (Common mode) Shift clock frequency: 4.0MHz (Max.) Built-in 160-bits bidirectional shift register (divisible into 80-bits Available single mode (160-bits shift register) dual mode (80-bits shift register Y160 Single mode Y160 Single mode Y80, Y160 Dual mode Y160 Y81, Dual mode above shift directions pin-selectable Available outputs mode outputs mode option easier layout (Both segment mode common mode) Supply voltage drive: 15.0 40.0V Number driver outputs: output impedance power consumption Supply voltage logic system: +2.5 +5.5V CMOS process Package Gold bump designed rated radiation hardened
General Description
NT7705 160-bit output segment/common driver suitable driving large-scale matrix panels used PDA's, personal computers workstations example. Through technology, ideal substantially decreasing size frame section module. NT7705 good both segment driver common driver, power consuming, high-precision panel display assembled using NT7705. segment mode, data input selected 4bit parallel input mode 8bit parallel input mode mode (MD) pin. common mode, data input/output pins bi-directional four data shift directions pin-selectable.
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NT7705
Configuration
NT7705
ALK_L
Dummy
ALK_R
Block Diagram
V12R V43R
Y159 Y160
Level Shifter
DISPOFF
Bits Level Driver
/160
V43L V12L
Bits Level Shifter
EIO1 Active Control EIO2
8Bits Data Latch
/160
Bits Line Latch/Shift Register
Control Logic
Data Latch Control
Conversion Data Control
2/33
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NT7705
Description
224-226 227-229 230-232 3-6, 49-52 9-10 11-16 17-18 19-20 21-34 35-36 37-38 39-40
41-42 43-44 45-46 47-48 53-54 55-57 58-60 61-63 64-223
Designation V12L V43L EIO2
DISPOFF EIO1 V43R V12R Y160
Description Power supply driver Power supply driver Power supply driver Power supply driver Ground (0V), these pads must connected each other Common mode output selection Display data shift direction selection Power supply logic system (+2.5 5.5V) Segment mode/common mode selection Input/output chip select data shift register Display data input segment mode Display data input Segment mode Dual mode data input Display data shift clock input segment mode
Control input deselect output level Latch pulse input shift clock input shift register Input/output chip select data shift register AC-converting signal input driver waveform Mode selection input Power supply driver Power supply driver Power supply driver Power supply driver driver output
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NT7705
Input Output Circuits
Input Signal
Applicable Pins L/R, S/C, DUTY DISPOFF
Input Circuit
Control Signal
Input Signal
Applicable Pins
Input Circuit
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NT7705
Input Signal Control Signal
Output Signal
Control Signal
Input Output Circuit
Applicable Pins EIO1, EIO2
Control Signal Control Signal
Control Signal
Control Signal
Applicable Pins Y160
Driver Output circuit
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NT7705
Description
Segment mode
Symbol
VOR, V12R, V12L V43R, V43L V5R,
Function
Logic system power supply connects +2.5 +5.5V Ground connects Power supply driver voltage bias Normally, bias voltage used resistor divider Ensure that voltages such that further reduce differences between output waveforms driver output pins Y160, externally connect Input display data 4-bit parallel input mode, input data into pins Connect 8-bit parallel input mode, input data into pins Clock input taking display data Data read falling edge clock pulse Latch pulse input display data Data latched falling edge clock pulse Direction selection reading display data When level "L", data read sequentially from Y160 When level "H", data read sequentially from Y160 Control input output deselect level input signal level-shifted from logic voltage level driver voltage level, controls driver circuit When level "L", driver output pins Yl60) level
While DISPOFF "L", contents line latch reset, display data data latch
DISPOFF read regardless condition DISPOFF When DISPOFF function canceled, driver outputs deselect level (V12 V43), then outputs contents date latch onto next falling edge That time, DISPOFF removal time keep regulation what shown characteristics, output reading data correctly signal input driving waveform input signal level-shifted from logic voltage level driver voltage level, controls driver circuit Normally inputs frame inversion signal driver output pin's output voltage level line latch output signal signal Mode selection When level "L", 4-bit parallel input mode When level "H", 8-bit parallel input mode used Connect VDD. Avoiding floating
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Segment mode continued
Symbol
Function
Segment mode/common mode selection When level "H", segment mode set. When level "L", common mode set. Input/output chip selection When input level "L", EIO1 output, EIO2 input. When input level "H", EIO1 input, EIO2 output. During output, while after 160-bits data have been read, cycle (from falling edge falling edge XCK), after which returns During input, after signal input, chip selected while "L". After 160-bits data have been read, chip deselected
EIO1, EIO2
Y160
driver output pins These corresponding directly each data latch, level (V0, V12, V43, selected output
Common mode
Symbol Function
V0R, V12R, V12L V43R, V43L V5R,
Logic system power supply connects +2.5 +5.5V Ground connects Power supply driver voltage bias. Normally, bias voltage used resistor divider Ensure that voltages such that <V43 further reduce differences between output waveforms driver output pins Y160, externally connect Bi-directional shift register shift data input/output Output when level input when level When EIO1 used input pin, will pulled-down When EIO1 used output pin, won't pulled-down Bi-directional shift register shift data input/output Input when level output when level When EIO2 used input pin, will pulled-down When EIO2 used output pin, won't pulled-down Bi-directional shift register shift clock pulse input Data shifted falling edge clock pulse Bi-directional shift register shift direction selection Data shifted from Y160 when level "L", data shifted from Y160 when level
EIO1
EIO2
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Common mode continued
Symbol Function
Control input output deselect level input signal level-shifted from logic voltage level driver voltage level controls driver circuit When level "L", driver output pins Y160) level DISPOFF
While "L", contents shift resister reset reading data. When DISPOFF function canceled, driver outputs deselect level (V12 V34), shift data read falling
edge That time, DISPOFF removal time keep regulation what shown characteristics, shift data reading correctly signal input driving waveform input signal level-shifted from logic voltage level driver voltage level, controls driver circuit Normally, inputs frame inversion signal driver output pin's output voltage level using shift register output signal signal Mode selection When level "L", Single Mode operation selected. When level "H", Dual Mode operation selected Common mode output selection When level "L", outputs operation selected. When level "H", outputs operation selected Dual Mode data input According data shift direction data shift register, data input starting from 81st When chip used Dual Mode, will pulled-down When chip used Single Mode, won't pulled-down Segment mode/common mode selection When level "L", common mode used Connect D0-D6 VDD. Avoiding floating used pulled-down common mode, connect open driver output pins These corresponding directly Corresponding directly each shift register, level (V0, V12, V43, selected output
Y160
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NT7705
Functional Description
Block description 1.1. Active Control case segment mode, controls selection deselection chip. Following signal input, after select signal input, select signal generated internally until bits data have been read Once data input been completed, select signal cascade connection output, ship deselected. 1.5. Line Latch Shift Register
case segment mode, bits which have been read into data latch, simultaneously latched falling edge signal, output level shift block. case common mode, shifts data from data input falling edge signal.
1.6. Level Shifter
case common mode, controls input/output data bidirectional pins. 1.2. Conversion Data Control case segment mode, keep input data which clocks 4-bit parallel mode into latch circuit, keep input data which clock 8-bit parallel mode into latch circuit, after that they internal data bits time. 1.3. Data Latch Control case segment mode, selects state data latch, which reads data signals. shift direction controlled control logic every bits data read selection signal shifts bit, based state control circuit. 1.4. Data Latch case segment mode, latches data data bus. latched state each driver output controlled control logic data latch control bits data read sets bits.
logic voltage signal level-shifted driver voltage level, output driver block.
1.7. 4-Level Driver
drives driver output pins from line latch/shift register data, selecting levels (V0, V12, V43, based S/C, DISPOFF signals.
1.8. Control Logic
controls operation each block. case segment mode, when signal been input, blocks reset control logic waits selection signal output from active control block. Once selection signal been output, operation data latch data transmission controlled, bits data read chip deselected. case common mode, controls direction data shift.
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Driver Output Voltage Level
relationship amongst data signal, converted signal driver output voltage shown table below:
2.1. Segment Mode Latch Data
DISPOFF Driver Output Voltage Level Y160)
Here, <V0, (+2.5 +5.5V), (0V), Don't care
2.2. Common Mode Latch Data DISPOFF Driver Output Voltage Level Y160)
Here, (+2.5 +5.5V), (0V), Don't care Note: There kinds power supply (logic level voltage, driver voltage) driver. Please supply regular voltage, which assigned specification each power pin. That time "Don't care" should fixed "L", avoiding floating.
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Relationship between Display Data Driver Output Pins 3.1. Segment Mode:
4-bit Parallel Mode
EIO1 EIO2 Data Input 40clock Y160 Y159 Y158 Y157 39clock Y156 Y155 Y154 Y153 Number Clock 38clcok 3clock Y149 Y150 Y151 Y152 Y152 Y151 Y150 Y149 2clock Y153 Y154 Y155 Y156 1clock Y157 Y158 Y159 Y160
Output Input
Input Output
8-bit Parallel Mode
EIO1 EIO2 Data Input 20clock Y160 Y159 Y158 Y157 Y156 Y155 Y154 Y153 19clock Y152 Y151 Y150 Y149 Y148 Y147 Y146 Y145 Number Clock 18clcok 3clock Y137 Y138 Y139 Y140 Y141 Y142 Y143 Y144 Y144 Y143 Y142 Y141 Y140 Y139 Y138 Y137 2clock Y145 Y146 Y147 Y148 Y149 Y150 Y151 Y152 1clock Y153 Y154 Y155 Y156 Y157 Y158 Y159 Y160
Output Input
Input Output
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3.2. Common Mode Data Transfer Direction Y1~Y60 Output pins Y61~Y100 Y101~Y160 EIO1 EIO2
(Single) (Single)
(shift left) (shift right)
Y160 Y160
Output Output Output Output Output
Output Output Output
Output Output Output Output Output
Output Input Output Input Output
Input Output Input Output Input
Input
(shift left) Y160 Y101, (shift right) Y101 Y160 (shift left) Y160 Y160
(Dual)
(shift right)
Output
Output
Output
Input
Output
Input
Here, (0V), (+2.5V +5.5V), Don't care Note: "Don't care" should fixed "L", avoiding floating.
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NT7705
Connection Examples Segment Drivers 4.1. Case
data (data taking flow) Y160 ->Y1 Y160 ->Y1 Y160 ->Y1 last data
EIO2
EIO1
D0~D7
EIO2
EIO1
D0~D7
EIO2
EIO1
D0~D7
D0~D7
Case
D0~D7
D0~D7
D0~D7
D0~D7
EIO1 EIO2
EIO1 EIO2
EIO1 EIO2
->Y160 (data taking flow) data
->Y160
->Y160
last data
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Timing Waveform 4-Device Cascade Connection Segment Drivers.
First data device (device device device device
Last data
(device
(device
(device 4-bit parallel mode 8-bit parallel mode
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Connection Examples Common Drivers
First
Last
Y160
Y160
Y160
EIO2
DISPOFF
EIO1
EIO2
DISPOFF
EIO1
EIO2
DISPOFF
EIO1
(VDD) DISPOFF
Single Mode (Shifting towards left)
DISPOFF (VDD)
DISPOFF
DISPOFF
DISPOFF
EIO1
EIO2
EIO1
EIO2
EIO1
Y160
Y160
Y160
First
Last
Single Mode (Sifting towards right)
15/33
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EIO2
NT7705
First
Last
Y160
Y101
Y160
Y101
Y160
Y101
EIO2
DISPOFF
EIO1
EIO2
DISPOFF
EIO1
EIO2
DISPOFF
EIO1
DISPOFF
Dual Mode (Shifting towards left)
DISPOFF
DISPOFF DISPOFF DISPOFF
EIO1
EIO2
EIO1
EIO2
EIO1
Y160
Y101
Y160
Y101
Y160
Y101
EIO2
First
Last
Dual Mode (Sifting towards right)
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NT7705
Precaution
careful when connecting disconnecting power This high-voltage driver, permanently damaged high current, which occur, voltage supplied driver power supply while logic system power supply floating. details follows:
When connecting power supply, connect driver power after connecting logic system power. Furthermore, when disconnecting power, disconnect logic system power after disconnecting driver power. recommend that connect serial resistor (50-100) fuse driver power system current limiting device. Also, suitable value resistor consideration display grade.
addition, when connecting logic power supply, logic condition inside insecure. Therefore connect driver power supply after resetting logic condition this inside DISPOFF function. After that, DISPOFF cancel function after driver power supply become stable. Furthermore, when disconnecting power, driver output pins level DISPOFF function. After that, disconnect logic system power after disconnecting driver power. When connecting power supply, follow recommended sequence shown.
DISPOFF
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NT7705
Absolute Maximum Rating*
Supply Voltage -0.3V +7.0V Supply Voltage -0.3V +42.0V Input Voltage -0.3V +0.3V Operating Ambient Temperature -30°C +85°C Storage Temperature .-45°C +125°C
*Comments
Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage this device. These stress ratings only. Functional operation this device under these other conditions above those indicated operational sections this specification implied intended. Exposure absolute maximum rating conditions extended periods affect device reliability.
Electrical Characteristics
Characteristics
Segment Mode (VSS 5.5V, +85°C, unless otherwise noted)
Parameter Symbol Min. Typ. Max. Unit Condition
Operating Voltage Operating Voltage Input high voltage Input voltage Output high voltage Output voltage Input leakage current
+0.4
XCK, L/R, S/C, EIO1, EIO2, DISPOFF pins EIO1, EIO2 pins, -0.4mA EIO1, EIO2 pins, +0.4mA XCK, L/R, S/C, EIO1, EIO2 DISPOFF pins, XCK, L/R, S/C, EIO1, EIO2 DISPOFF pins, +40.0V +30.0V Y160 pins, 0.5V
Input leakage current
Output resistance
Stand-by current Consumed current (Deselection) Consumed current (Selection) Consumed current Note:
IDD1 IDD2
pin, Note pin, Note pin, Note pin, Note
+5.0V, +40V, +5.0V, +40V, fXCK 14MHz, No-load, input data turned over data taking clock (4-bit parallel input mode) +5.0V, +40V, fXCK 14MHz, No-load. input data turned over data taking clock (4-bit parallel input mode) +5.0V, +40V, fXCK 14MHz, 41.6kHz. No-load input data turned over data taking clock (4-bit parallel-input mode)
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NT7705
Common Mode (VSS 5.5V, 40V, +85°C, unless otherwise noted)
Parameter
Operating Voltage Operating Voltage Input high voltage Input voltage Output high voltage Output voltage Input leakage current
Symbol
Min.
Typ.
Max.
+0.4 +1.0
Unit
Condition
XCK, L/R, S/C, EIO1, EIO2, DISPOFF pins EIO1, EIO2 pins, -0.4mA EIO1, EIO2 pins, +0.4mA L/R, DISPOFF pins, XCK, L/R, S/C, EIO1, EIO2 DISPOFF pins, +40.0V Y160 pins, 0.5V
Input leakage current
-1.0
Output resistance Stand-by current Consumed current Consumed current Note:
+30.0V pin, Note pin, Note pin, Note
+5.0V, +40V, +5.0V, +40V, 41.6KHz, 80Hz, case 1/480 duty operation, No-load
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NT7705
Characteristics
Segment Mode (VSS 5.5V, +85°C, unless otherwise noted)
Parameter
Shift clock period Shift clock pulse width Shift clock pulse width Data setup time Data hole time Latch pulse pulse width Shift clock rise Latch pulse rise time Shift clock fall Latch pulse fall time Latch pulse rise Shift clock rise time Latch pulse fall Shift clock rise time Input signal rise time Input signal fall time Enable setup time
Symbol
tWCK tWCKH tWCKL tWLPH tWDL tpd1, tpd2 tpd3
Min.
Typ.
Max.
Unit
Condition
10ns, Note
Note Note
DISPOFF Removal time DISPOFF enable pulse width
Output delay time Output delay time Output delay time Note
15pF 15pF 15pF
Take cascade connection into consideration. (Tck tWCKII twckl)/2 maximum case high speed operation.
20/33
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NT7705
Segment Mode (VSS 4.5V, +85°C, unless otherwise noted)
Parameter
Shift clock period Shift clock pulse width Shift clock pulse width Data setup time Data hole time Latch pulse pulse width Shift clock rise Latch pulse rise time Shift clock fall Latch pulse fall time Latch pulse rise Shift clock rise time Latch pulse fall Shift clock fall time Input signal rise time Input signal fall time Enable setup time DISPOFF Removal time DISPOFF enable pulse width Output delay time Output delay time Output delay time Note
Symbol
tWCK tWCKH tWCKL tWLPH tWDL tpd1, tpd2 tpd3
Min.
Typ.
Max.
Unit
Condition
11ns, Note
Note Note
15pF 15pF 15pF
Take cascade connection into consideration. (tCK tWCKII tWCKL)/2 maximum case high speed operation.
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NT7705
Timing waveform Segment Mode
tWLPH
tWCKH
tWCKL
tWCK
LAST DATA
DATA
tWDL
DISPOFF
4-bit parallel mode 8-bit parallel mode
tpd1
tpd2
DISPOFF
tpd3
Y160
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Common Mode (VSS 5.5V, +85°C, unless otherwise noted)
Parameter
Shift clock period Shift clock pulse width Data setup time Data hole time Input signal rise time Input signal fall time DISPOFF Removal time DISPOFF enable pulse width Output delay time Output delay time Output delay time
Symbol
tWLP tWLPH tWDL tpd1, tpd2 tpd3
Min.
Typ.
Max.
Unit
Condition
20ns +5.0V +2.5 +4.5V
15pF 15pF 15Pf
23/33
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NT7705
Timing Characteristics Common Mode
tWLP
tWLPH
EIO2 (D7)
EIO1
tWDL
DISPOFF
tpd1
tpd2
DISPOFF
tpd3
Y160
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NT7705
Application Circuit (for reference only)
SEG480 SEG479
Y1~Y160
DISPOFF
EIO1 D0~D7 EIO2
Y1~Y160
EIO1
480*320 MATRIX PANEL
DISPOFF D0~D7 EIO2
Y1~Y160
SEG3 SEG2 SEG1
EIO1 DISPOFF D0~D7 EIO2
Y1~Y160
Y1~Y160
NT7705*2
DISPOFF
D0~D7
DISPOFF
D0~D7
EIO1
EIO2
EIO1
EIO2
(case bias)
DISPOFF
(n-4)R
controller
Note: V0-V1>1.5V
25/33
XD0~XD7
Ver1.0
NT7705*3
NT7705
SEG640 SEG639
Y1~Y160
DISPOFF
EIO1 D0~D7 EIO2
Y1~Y160
DISPOFF
EIO1 D0~D7 EIO2
640*480 MATRIX PANEL
Y1~Y160
DISPOFF
EIO1 D0~D7 EIO2
Y1~Y160
SEG3 SEG2 SEG1
EIO1 DISPOFF D0~D7 EIO2
Y1~Y240
Y1~Y240
NT7706*2
DISPOFF
D0~D7
DISPOFF
D0~D7
EIO1
EIO2
EIO1
EIO2
(case bias)
DISPOFF
(n-4)R
controller
Note: V0-V1>1.5V
26/33
XD0~XD7
Ver1.0
NT7705*4
NT7705
Application Layout Notice(for reference only) Application Notices
Adjust voltage V1and amend phenomena "cross talk" (V1& range adjusting less than 100mV, sure V0-V1=V4-VSS after adjusting; When NT7705 applied type LCM, recommend 0.5mm pitch 0.1µf high frequency capacitors between VSS; When OP(LP324) used follow bias voltage, sure power voltage must 1.5V more) higher than output voltage; XCK,D0-D7,LP high frequency (Max. 20MHZ) signals, attention distance between them other signals nearby avoid high frequency interference; EIO1,EIO2 enable signals connecting chips, attention distance between them other signals nearby avoid interference. distance connection between chips shorter better. must connected VSS.
Layout NoticeIt application type
suggest that panel made glass whose resistor about square power better straight, resistor value smaller better. Among interface Pins first sure resistors value VDD,VSS,V0 less than values suggest. shown below: name Other Power Pins (V0,V12,V43,V5 R/L) resistors value less than 75(when 2.7V) less than (when 2.7V) less than
Reference figure characteristic Layout VDD/VSS VDD/VSS almost same vertical level. very straight; Closer FPC, shorter length ITO;
27/33
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NT7705
Bonding Diagram
9230um
NT7705
ALK_L
Dummy
(0,0)
ALK_R
Location
Designation
EIO2 EIO2
-4320 -4160 -4000 -3840 -3680 -3520 -3360 -3200 -3040 -2880 -2720 -2560 -2400 -2240 -2080 -1920 -1760 -1600 -1440 -1280 -1120 -960 -800 -640 -480 -320 -160
-483 -483 -483 -483 -483 -483 -483 -483 -483 -483 -483 -483 -483 -483 -483 -483 -483 -483 -483 -483 -483 -483 -483 -483 -483 -483 -483 -483 -483 -483
Designation
DISPOFF
1120 1280 1440 1600 1760 1920 2080 2240 2400 2560 2720 2880 3040 3200 3520 3680 3840 4000 4160 4320 4558 4558 4558 4558 4558 4558
DISPOFF
EIO1 EIO1 V43R V43R V43R V12R V12R V12R
28/33
1072um
-483 -483 -483 -483 -483 -483 -483 -483 -483 -483 -483 -483 -483 -483 -483 -483 -483 -483 -483 -483 -483 -483 -483 -483 -470 -390 -330 -270 -210 -150
Ver1.0
NT7705
Location (continued)
Designation
4558 4558 4558 4558 4558 4558 4558 4558 4558 4430 4350 4290 4230 4170 4110 4050 3990 3930 3870 3810 3750 3690 3630 3570 3510 3450 3390 3330 3270 3210 3150 3090 3030 2970 2910 2850 2790 2730 2670 2610
Designation
2550 2490 2430 2370 2310 2250 2190 2130 2070 2010 1950 1890 1830 1770 1710 1650 1590 1530 1470 1410 1350 1290 1230 1170 1110 1050
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Location (continued)
Designation
Y100 Y101 Y102 Y103 Y104 Y105 Y106 Y107 Y108 Y109 Y110 Y111 Y112 Y113 Y114 Y115 Y116 Y117
-150 -210 -270 -330 -390 -450 -510 -570 -630 -690 -750 -810 -870 -930 -990 -1050 -1110 -1170 -1230 -1290 -1350 -1410 -1470 -1530 -1590 -1650 -1710 -1770 -1830 -1890 -1950 -2010 -2070 -2130 -2190
Designation
Y118 Y119 Y120 Y121 Y122 Y123 Y124 Y125 Y126 Y127 Y128 Y129 Y130 Y131 Y132 Y133 Y134 Y135 Y136 Y137 Y138 Y139 Y140 Y141 Y142 Y143 Y144 Y145 Y146 Y147 Y148 Y149 Y150 Y151 Y152 Y153 Y154 Y155 Y156 Y157
-2250 -2310 -2370 -2430 -2490 -2550 -2610 -2670 -2730 -2790 -2850 -2910 -2970 -3030 -3090 -3150 -3210 -3270 -3330 -3390 -3450 -3510 -3570 -3630 -3690 -3750 -3810 -3870 -3930 -3990 -4050 -4110 -4170 -4230 -4290 -4350 -4430 -4558 -4558 -4558
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NT7705
Location (continued)
Designation
Y158 Y159 Y160 V12L
-4558 -4558 -4558 -4558 -4558 -4558 -4558
-150
Designation
V12L V12L V43L V43L V43L ALK_L ALK_R
-4558 -4558 -4558 -4558 -4558 -4462 4462
-210 -270 -330 -390 -470 -485 -485
Dummy Location (Total: pad)
3360 4558 -4558
-483
31/33
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NT7705
Package Information
NT7705
Chip Outline Dimensions
Symbol
unit:
Dimensions
Symbol
Dimensions
unit:
Dimensions
Chip size 1~54 pitch 56~6971~216218~231 55~5670~71216~217 231~232 1~54 55232 Bump size 56~69218~231 70217 71~216 Bump height 15±3
Size
9230
1072
32/33
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NT7705
Product Spec. Change Notice NT7705 Specification Revision History Version Content Formal version released Operation Voltage changed (30V 40V) (Page Reference circuit modified (Page Location Addition Original Date Apr. 2003 Mar. 2002 Jan. 2002 Jun. 2001
33/33
Ver1.0

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