Single-Chip Dolby Logic Surround Decoder Description CXD2724AQ-1

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Single-Chip Dolby Logic Surround Decoder Description CXD2724AQ-1

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CXD2724AQ-1
Single-Chip Dolby Logic Surround Decoder
Description CXD2724AQ-1 CMOS developed Dolby Logic Surround. SRAM short delay AD/DA converters built functions necessary Dolby Logic Surround such adaptive matrix, passive decoder including BNR, auto input balance, noise sequencer center channel mode control contained single chip. Further, this also supports Dolby Stereo Virtual Dolby Surround. Features Dolby Logic Surround decoding with single chip 2-channel 1-bit converter, decimation filter prefilter operational amplifier 4-channel 1-bit converter, oversampling filter post filter Analog switch bypass Analog electronic attenuator (+1.5 -29.5dB) center/surround channel trim 24K-bit SRAM short delay separation other variance digital processing External parts reduced incorporating analog circuits Functions Adaptive matrix Center channel mode control (Normal/Phantom/Wide) Dolby Stereo Auto input balance control (ON/OFF) Noise sequencer Variable delay time 34.8ms) low-pass filter (12dB/Oct) Modified Dolby B-type Simple function Virtual Dolby Surround mode bypass mode R-channel through) Structure Silicon gate CMOS Applications Equipment having Dolby Logic Surround function such amplifiers, receivers compact music systems (Plastic)
Absolute Maximum Ratings 25°C, Supply voltage +7.0 Input voltage Output voltage Operating temperature Topr Storage temperature Tstg +150 Recommended Operating Conditions Supply voltage Analog system 4.75 5.25 (5.0 typ.) Digital system 4.50 5.25 (5.0 typ.) Operating temperature Input/Output Capacitance Input capacitance (max.) Output capacitance COUT (max.) Input/output capacitance CI/O (max.) Measurement conditions: 1MHz Maximum Current Consumption 25°C, 5.25V) Digital/analog block total: 166.7mA Dolby level During analog input: 300mVrms During digital input: -20dBFS Analog characteristics Logic Dolby level 300mVrms Prefilter gain -3.52dB S/N: 80dB, 72dB 0.015%, 0.03% values typ.
This device available only arties obtaining license from Dolby Laboratories Licensing oration. "Dolby", double-D symbol "Pro Logic" trademarks Dolby Laboratories Licensing Corporation.
Sony reserves right change products specifications without prior notice. This information does convey license implication otherwise under patents other right. Application circuits shown, any, typical examples illustrating operation devices. Sony cannot assume responsibility problems arising these circuits.
E98829-PS
CXD2724AQ-1
Block Diagram
DELAY
RVDT XLAT REDY LRCK SERIAL DATA MICROCOMPUTER
ADC1
ADC2
DAC1 Analog DAC2 Analog DAC3 Trim
LOUT
ROUT
XCOUT (Phase Inverted Output) XSOUT (Phase Inverted Output)
XMST
CLOCK GENERATOR /TIMING CIRCUIT
DAC4
Trim
XTLO
XTLI
Configuration
XMST ROUT RVDT REDY LRCK AVS4 AVD4 VSS5 VSS4 AVD2
AVS2 AVD6 AVS6 XSOUT AVSX XTLI XTLO AVDX XCOUT AVS5 AVD5 AVS1
BFOT
VDD1
XS24
XLAT
VSS6
VDD2 VSS7
VSS3
BFOT
XRST
LOUT
VSS1
AVS3
AVD3
VDD0
TST0
TST4
VSS0
TST3
CSL2
TST2
VSS2
AVD1
CSL1
TST1
CXD2724AQ-1
Description Symbol VSS0 TST0 VDD0 VSS1 TST1 TST2 TST3 TST4 XRST BFOT CSL1 CSL2 VSS2 AVS3 AVD3 LOUT AVD1 AVS1 AVD5 AVS5 XCOUT AVDX XTLO XTLI AVSX XSOUT AVS6 AVD6
Notations parentheses indicate fixed connection status. Description Test monitor. Normally outputs Low. Digital GND. Test monitor. Normally outputs Low. Test. Normally fixed Low. Digital power supply. Digital GND. Test. Normally fixed Low. Test. Normally fixed Low. Test. Normally fixed Low. Test. Normally fixed Low. System reset input. Reset when Low. Clock, frequency-division output. [384/768/256/512fs] Test. Normally fixed High. Test. Normally fixed Low. Digital GND. L-ch converter GND. L-ch converter power supply. L-ch converter output. L-ch converter power supply. L-ch converter GND. L-ch converter operational amplifier inverted output. L-ch converter analog input. C-ch converter power supply. C-ch converter GND. C-ch converter output. Analog power supply master clock. Crystal oscillator circuit output. Crystal oscillator circuit input. Analog master clock. S-ch converter output. S-ch converter GND. S-ch converter power supply. (AVSS) (AVDD) (AVSS) (AVDD) (AVDD) (AVSS) (AVDD) (AVSS) (VDD) (VSS) (VSS) (AVSS) (AVDD) (OPEN) (VSS) (OPEN) (VSS) (VDD) (VSS) (VSS) (VSS) (VSS) (VSS)
(OPEN): Open, (VDD): digital power supply, (AVDD): analog power supply, (VSS): Digital GND, (AVSS): Analog
CXD2724AQ-1
Notations parentheses indicate fixed connection status. Symbol AVS2 AVD2 ROUT AVD4 AVS4 VSS3 REDY XLAT RVDT XS24 VDD1 VSS4 LRCK VSS5 XMST R-ch converter analog input. R-ch converter operational amplifier inverted output. R-ch converter GND. R-ch converter power supply. R-ch converter output. R-ch converter power supply. R-ch converter GND. Digital GND. Shift clock input microcomputer interface. Transfer enabling signal output microcomputer interface. Transfer prohibited when Low. Test monitor. Normally outputs Hi-Z. Latch input microcomputer interface. Data input microcomputer interface. Serial data 24-/32-bit slot selection. 24-bit slot when Low. (valid slave mode) Digital power supply. Digital GND. Test monitor. Normally outputs Low. 1-sampling 2-channel serial data input. Test input. Normally inputs Low. Serial transfer clock serial data Sampling frequency clock serial data Digital GND. BCK, LRCK master/slave mode switching input. Master mode when Low. Test monitor. Normally outputs Low. Digital GND. Test monitor. Normally outputs Low. Digital power supply. Digital GND. Test monitor. Normally outputs Low. (OPEN) (VSS) (OPEN) (VDD) (VSS) (OPEN) (VSS) (VSS) (VDD) (VSS) (OPEN) (OPEN) (AVDD) (AVSS) (VSS) (AVSS) (AVDD) Description
VSS6
VDD2 VSS7
(OPEN): Open, (VDD): digital power supply, (AVDD): analog power supply, (VSS): Digital GND, (AVSS): Analog There three digital seven analog power supplies, power-on sequence specified.
CXD2724AQ-1
Characteristics (AVD1 AVDX VDD0 AVS1 AVSX VSS0 +70°C) Item Input voltage Input voltage Input voltage Input voltage Symbol High level level Conditions CMOS input Min. 0.7VDD 0.3VDD 0.8VDD 0.2VDD VDD/2 VDD/2 250k 2.5M Typ. Max. Unit Applicable pins Resistance between
High level level
Schmitt input
High level level
input Analog input -2.0mA 4.0mA -12.0mA 12.0mA VDD, VDD, VDD,
Output voltage High level level Output voltage High level level Input leak current Input leak current Output leak current Feedback resistance
CSL2, CSL1, TST0 TST4, XMST XLAT, RVDT, XS24, LIN, XRST During input bidirectional pins BCK, LRCK XTLI During output from bidirectional pins BCK, LRCK BFOT REDY XTLO
CXD2724AQ-1
Characteristics (AVD1 AVDX VDD0 AVS1 AVDX VSS0 +70°C) Input Timing from Power-on Input
0.95VDD
Determined crystal other external circuit conditions Stable (clock applied correctly) 1/fs more
XTLI
XRST 1/fs more Input pins First input
0.8VDD 0.2VDD 0.7VDD 0.3VDD
Serial Audio Interface Timing [Slave mode]
tSSI tHLR LRCK tHSI 0.7VDD 0.3VDD tSLR 0.7VDD 0.3VDD 0.7VDD 0.3VDD
[Master mode]
tDLR LRCK
Item setup time hold time LRCK setup time LRCK hold time LRCK delay time
Symbol
Conditions Slave mode Slave mode Slave mode Slave mode Master mode, 120pF
Min.
Max.
Unit
tSSI tHSI tSLR tHLR tDLR
CXD2724AQ-1
Microcomputer Interface Timing Transfer timing address section, transfer mode section data section
RVDT Address tSWL tSLP XLAT tLWL REDY tSWH Mode 0.7VDD 0.3VDD 0.7VDD 0.3VDD Data Data
tLSD 0.7VDD 0.3VDD
Transfer timing from data section address section transfer mode section
RVDT Data tSLD XLAT tSBD tBSP REDY tLDR 0.7VDD 0.3VDD tRLP 0.7VDD 0.3VDD Address Mode 0.7VDD 0.3VDD
Item RVDT data setup time relative rise RVDT data hold time from rise level width High level width XLAT level width XLAT High level width rise preceding time relative XLAT rise rise wait time relative XLAT rise Delay time REDY fall relative rise REDY fall preceding time relative rise REDY rise preceding time relative XLAT rise REDY rise preceding time relative fall XLAT fall wait time relative rise XLAT fall delay time relative REDY fall rise wait time next transfer
Symbol tSWL tSWH tLWL tLWH tSLP tLSD tSBD tBSP tRLP tRSDP tSLD tLDR
Min.
Max.
Unit
Notes) cycle clock frequency applied XTLI pin. (512fs) REDY value 60pF.
CXD2724AQ-1
Analog Characteristics (AVD0 VDD0 AVDX 5.0V, AVS0 VSS0 AVSX 0.0V, 44.1kHz, 25°C) When Logic mode input signal level while measuring center surround channels should -3dB smaller than input level while measuring left right channels. Note that channel input in-phase channel, channel input reversed phase channel. input level same measurement items when Logic mode off. Connection Total Characteristics addition DAC, total characteristics include prefilter with built-in operational amplifier, built-in post filter, trim volume. analog circuits Application Circuit measurement circuit. 1-1. When Logic mode Unless otherwise specified, measurement conditions given below. 300mVrms, 212mVrms 0dB) 1kHz Item Measurement conditions CCIR/ARM filter ratio1 10Hz 500kHz Channels 10Hz 20kHz 16.5dB2 10Hz 20kHz 0dB3 10Hz 20kHz -3.52dB4 10Hz 500kHz Head room Matrix rejection Output level Level difference between channels Current consumption Power supply rejection ratio6 Analog system (including oscillator circuit) Digital system 1mVrms, 100Hz sine wave 10Hz 20kHz, (all) (all) Min. Typ. 0.04 1.00 Max. Unit
0.007 1.00 0.015 0.03 0.02 0.04 0.12 0.18 0.04 16.5 ±0.2 -13.2 Vrms
When 200mVrms -3.52dB), ratio 3.52dB smaller than values noted table above. 2.0Vrms, 1.414Vrms 300mVrms, 212mVrms 200mVrms, 141mVrms When channel gain deviation 0.1dB less front-end prefilter output. Includes amplification (L/Rch.5.27dB, C/Sch.13.72dB) external amplifier. trim volume 0dB.
CXD2724AQ-1
1-2. When Logic mode Unless otherwise specified, measurement conditions given below. 2.0Vrms 0dB) 1kHz Item ratio Measurement conditions EIAJ (with weighting filter) EIAJ (0dB) EIAJ (-3dB) Channels (all) (all) (all) Min. Typ. 0.03 0.004 0.01 1.33 1.85 Vrms Vrms 1.00 Max. Unit
Dynamic range12 maximum input level13 Output level14
EIAJ (-60dB) (Full-scale output)
Graphs during input analog input level which outputs full scale varies according supply voltage AVDn. When supply voltage AVDn contains deviation, calculate maximum input level from (Formula below adjust level with front-end prefilter, etc., that waveform clipped minimum voltage. maximum input level [Vrms] 1.33 [Vrms] Minimum supply voltage (Formula
Like ADC, conversion gain also varies according supply voltage AVDn. However, reverse characteristics ADC, total gain between constant.
2Vrms 1kHz 2Vrms 1kHz
Analog input level [dB]
0.01
0.01
0.001
0.001
Analog input level [dB]
Graph Channel Characteristics
Graph Channel Characteristics
CXD2724AQ-1
Characteristics addition DAC, these characteristics include built-in post filter trim volume. digital input analog output circuits Application Circuit measurement circuit. 2-1. When Logic mode Unless otherwise specified, measurement conditions given below. Digital data -20dBFS 3kHz Item Measurement conditions CCIR/ARM filter Data -20dBFS ratio 10Hz 500kHz Data -20dBFS Channels 10Hz 20kHz Data -20dBFS 10Hz 500kHz Data -20dBFS Dolby level Output level31 Data -20dBFS R-in Matrix rejection 3kHz C-in S-in Level difference between channels (all) Min. Typ. 0.05 0.08 0.06 0.15 0.08 ±0.2 dBFS mVrms Max. Unit
output level depends supply voltage AVDn shown (Formula below. Output level [mVrms] [mVrms] Supply voltage AVDn (Formula
CXD2724AQ-1
2-2. When Logic mode Unless otherwise specified, measurement conditions given below. Digital data Full scale (0dBFS) 1kHz Item ratio Measurement conditions EIAJ (with weighting filter) EIAJ (0dB) EIAJ (-3dB) Dynamic range42 Output level43 Channels (all) Min. Typ. 0.03 0.007 0.007 0.01 Vrms Max. Unit
EIAJ (-60dB)
Graphs during -60dB input output level depends supply voltage AVDn shown (Formula below. Output level [Vrms] [Vrms] Supply voltage AVDn (Formula
Full scale 1kHz
Full scale 1kHz
Digital input level [dB]
0.01
0.01
0.001
0.001
Digital input level [dB]
Graph Channel Characteristics
Graph Channel Characteristics
CXD2724AQ-1
Bypass Mode Characteristics channels only) These characteristics without passing through DSP, including prefilter with built-in operational amplifier built-in post filter. analog circuits Application Circuit measurement circuit. Unless otherwise specified, measurement conditions given below. 1kHz 2.0Vrms 0dB) Item Measurement conditions CCIR/ARM filter ratio 10Hz 20kHz, weighting filter 10Hz 500kHz 10Hz 500kHz Dynamic range51 Maximum input level Output level Level difference between channels Channel separation Power supply rejection ratio52 1mVrms, 100Hz sine wave during -60dB input Includes amplification (5.27dB) external amplifier. Filter Characteristics Item Prefilter Measurement conditions Feedback resistance value Maximum amplification rate (100kHz less) Load resistance value Cut-off frequency Min. Typ. Max. Unit 10Hz 20kHz 10Hz 20kHz, -60dB 0.05% Min. Typ. 0.008 0.005 ±0.2 Vrms Vrms Max. Unit
Post filter
Trim Volume Characteristics Item Maximum gain Minimum gain Variable step TRIMmax TRIMmin TRIMstep Symbol Min. Typ. -29.5 Max. Unit
CXD2724AQ-1
Description Functions Master/Slave Modes [Relevant pins] XMST, LRCK, When using CXD2724AQ alone without digital input, CXD2724AQ-1 master mode. When using digital input, CXD2724AQ-1 either master mode slave mode. clock applied LRCK slave mode must synchronized either crystal oscillator clock XTLI XTLO pins external clock input from XTLI pin. XMST Mode Slave mode Master mode LRCK, Input Output
Table 1-1. LRCK, Mode Setting Master Clock System [Relevant pins] XTLI, XTLO, BFOT 768fs 44.1kHz) assumed master clock system, connection shown below. BFOT outputs clock obtained frequency dividing master clock. frequency division ratio changed setup register (SQC04, SQC05). (See Setup Register".) SQC05 SQC04 Master BFOT 384fs 256fs 512fs 768fs Slave
512fs Frequency divider
BFOT 256fs/384fs/512fs/768fs 512fs
Frequency divider
768fs XTLI
OPEN XTLO
768fs XTLI Setup Register XTLO
Note) Oscillation circuits differ according peripheral circuit substrate. Consult with crystal oscillator manufacturers about selecting oscillation circuits. Fig. 2-1.
CXD2724AQ-1
Reset Circuit [Relevant pins] XRST, XTLI, XTLO This must reset after power turned Reset done setting XRST 1/fs more after supply voltage satisfies recommended operating condition, crystal oscillator clock XTLI XTLO pins external clock input from XTLI correctly applied. (See Characteristics".)
Serial Audio Interface (SIF) [Relevant pins] BCK, LRCK, XS24, XMST Serial data used external communication digital audio data. CXD2724AQ-1 only input system, channels data input each sampling cycle. Either 32-bit clock mode 24-bit clock mode selected. master mode, mode fixed 32-bit clock mode. Configuration (The pins shown table below assigned SIF.) Symbol LRCK XS24 Function Serial input; taken with synchronized BCK. I/O; either 32-bit clock mode (64fs) 24-bit clock mode (48fs). output supports 32-bit clock mode only. LRCK (1fs). slot number (24/32) selection input. Low: 24-bit slot; High: 32-bit slot. Valid only slave mode. High master mode. switch between High during operation. BCK, LRCK master mode/slave mode switching input. Low: master mode; High: slave mode. Table 4-1. Configuration
XMST
Operation Modes LRCK/BCK mode selected setup register settings follows. (See Setup Register".) LRCK/BCK Mode Setting Setup register SQC15 SQC14 SQC13 LRCK format LRCK polarity selection polarity selection relative LRCK edge Valid only slave mode. master mode. Function "0": normal, Contents "1":
"0": "H", "1": "0": edge edge
Table 4-2. LRCK/BCK Mode Setting
CXD2724AQ-1
Format serial audio interface only input system, except slot number, following formats setting setup register. serial audio interface also support format enable connection Philips other company's devices. timing charts each data format given following page. SQC12 SQC11 Data arrangement/Frontward rearward truncation/Data word length first/Frontward truncation/24 bits first/Rearward truncation/16 bits first/Rearward truncation/18 bits first/Rearward truncation/20 bits formats support either 32-bit slot slave mode. Table 4-3. Setup Register Settings
Digital Audio Data Input Timing (with polarities: SQC15 SQC14 SQC13
32-bit slot
LRCK
first bits frontward truncation (SQC12,
first bits rearward truncation (SQC12, Iavalid
Iavalid
Iavalid
Iavalid first bits rearward truncation (SQC12, Iavalid
Iavalid first bits rearward truncation (SQC12,
Iavalid
Iavalid
24-bit slot
LRCK
first bits (SQC12,
first bits rearward truncation (SQC12,
Iavalid
Iavalid first bits rearward truncation (SQC12,
Iavalid first bits rearward truncation (SQC12,
Iavalid
CXD2724AQ-1
Iavalid
Iavalid
CXD2724AQ-1
Microcomputer Interface [Relevant pins] RVDT, SCK, XLAT, REDY CXD2724AQ-1 performs serial audio interface format setting coefficient settings such volume filter serial data from microcomputer. Configuration four external pins indicated table below assigned microcomputer interface. Symbol RVDT XLAT REDY Serial data input from microcomputer. Shift clock serial data. Input data from RVDT taken according rise. Interprets bits RVDT before this signal rises transfer mode data, bits before that address data. Transfer prohibited while level. Transfer enabled High. This open drain, must pulled externally. Table 5-1. Microcomputer Interface External Pins Description Communication Formats internal data transfer timing from microcomputer interface coefficient setup register called cycle, generated once LRCK. cycle generated immediately preceding signal processing program, absolutely effect signal processing, there risk sound being cut. Address section Mode section Data section package data transfer data from microcomputer CXD2724AQ-1. [Write] coefficient
Address section bits) Mode section bits) RVDT Data section bits)
Function
XLAT
REDY
Fig. 5-1. Example Communication
CXD2724AQ-1
Data Structure data structure classified into three types, shown table below. data communication done with first. Symbol D15/SQ00 SQ15 length Contents Address section Transfer mode section Data section Coefficient setup register both bits Remarks
Table 5-2. Data Structure (3)-1. Transfer Mode Section transfer mode section bits following functions. Table 5-3. Transfer Mode Section (3)-2. Address Section coefficient 256-word structure, address section bits. setup register 4word structure field (address) specified mode section, address section data optional. (3)-3. Data Section coefficient setup register both have 16-bit structure, required. Reserve Normally fixed Symbol Reserve Normally fixed Field Field Field Field Setup register Coefficient Function
Setup Reg. type
Data type
CXD2724AQ-1
Details Communication Methods definitions signal timing required control from microcomputer given below. (4)-1. Initializing Microcomputer Interface microcomputer interface must initialized after resetting After resetting 1/fs), input rising edges. After that, REDY goes within 50ns (t2), initialization completed when REDY goes High again. RVDT while inputting SCK. Note that REDY time (t3) maximum 1/fs. following page restrictions. same restrictions apply during data transfer. When REDY goes initialization: first transfer rise. XLAT first transfer fall. However, XLAT first transfer must rise after REDY goes High.
RVDT
XRST
rising edges
REDY
Microcomputer interface used
Fig. 5-2. Initialize Specifications
CXD2724AQ-1
(4)-2. Signal Timing First, address section data mode section data sent from microcomputer, synchronized SCK, RVDT pin. address section data bits both coefficient setup register, setup register length word, optional data transferred. Address section data sent with first. Mode section data fixed bits regardless transfer contents. phase relationship between data (data applied RVDT pin) following restrictions: data must established before rises (tDS 20ns). data must held 20ns more after rises (tDH). itself following restrictions: level must 20ns more (tSWL). High level must 20ns more (tSWH). After rise which corresponds mode section final data, XLAT rises (tSLP 20ns). XLAT level width must maintained 20ns more (tLWL). fall timing restricted that even REDY falls during preceding transfer, 20ns more (tSLD) required from rise which corresponds data section final data. Further, preceding transfers have been performed REDY Low, XLAT must rise after REDY High.
D0/SQ00 SQ00 D15/SQ15 SQ15
RVDT
tSWL XLAT tSLD tLWH REDY tLDR tRLP tSBD tLDR tRLP tLWL tSLD tSWH tSLP tLSD tBSP tSLP
Fig. 5-3. Write Timing cycle clock frequency applied XTLI pin. (512fs)
CXD2724AQ-1
Data section write begins after XLAT rises, here also transfer must performed with first, with restrictions. addition, after XLAT rises starting point sending data section, wait 20ns more first rise (tLSD). When bits this write repeated, REDY goes within 50ns, microcomputer informed waiting status cycle, which dedicated data rewrite cycle, microcomputer interface (tSBD). When REDY goes High again, corresponding data written. next communication restarted using REDY signal follows. When REDY Low, next transfer rise (tBSP 20ns). same way, when REDY Low, XLAT next transfer fall (tLDR 20ns). REDY will fall this communication, prohibited XLAT rise next transfer before REDY rises. Make sure that next XLAT rises after REDY rises (tRLP 20ns). order restart next transfer without using REDY signal, following conditions must observed: There should 40ns more left between rise final data section rise next transfer (tSS). same way, XLAT next transfer fall after waiting 20ns more after final data section rise (tSLD). tSLD here shorter times than tSBD 50ns, these rather loose restrictions. However, even this case XLAT rise next transfer must come after REDY rises (tRLP 20ns). Further, restriction XLAT fall starting point this transfer from tSLD tSLD 20ns
CXD2724AQ-1
Setup Register When setup register selected microcomputer interface transfer mode, following settings possible hardware such serial audio interface DAC, software such Dolby Logic Surround decoder. setup register total four fields, bits setup information stored field. However, when this reset, setup register contents also reset settings shown "When reset" column Tables below. Field Data section SQA15 SQA14 SQA13 SQA12 bypass mode Noise sequencer Virtualizer Compensation filter Control contents When reset
SQA11, SQA10
Decimation ratio setting SQA11 SQA10 (SFC mode only) decimation) sure also decimation SQC07 SQC06. decimation Dolby Stereo SQA09 SQA08 sure both bits when changing setup register Field settings. SQA05 SQA04 sure both bits when changing setup register Field settings. Table 6-1. Setup Register Field
decimation)
SQA09, SQA08 SQA07, SQA06 SQA05, SQA04 SQA03 SQA00
Reserve mode
Reserve
names indicated field name number. names Field SQA00 SQA15, first three letters names Fields SQB, SQD, respectively.
CXD2724AQ-1
Field Data section Center channel trim volume bits, analog) SQB15 SQB11 Control contents 00000: 00001: -1dB 00010: -2dB 11101: -29dB 11110: -30dB 11111: -31dB 00000: 00001: -1dB 00010: -2dB 11101: -29dB 11110: -30dB 11111: -31dB sure these bits when changing setup register Field settings. Table 6-2. Setup Register Field When reset
Center channel trim volume bits, analog) SQB10 SQB06
SQB05 Reserve SQB00
CXD2724AQ-1
Field Data section SQC15 SQC14 SQC13 LRCK format Control contents normal When reset normal Falling edge
LRCK polarity selection polarity selection relative LRCK edge Serial audio interface setting Falling edge Rising edge
SQC12, SQC11
SQC12 SQC11 first/Frontward truncation/24 bits first/Rearward truncation/16 bits first/Rearward truncation/18 bits first/Rearward truncation/20 bits sure both bits when changing setup register Field settings.
first/Frontward truncation/24 bits
SQC10 SQC09, SQC08 SQC07, SQC06
forced mute Reserve
Decimation ratio setting SQC07 SQC06 (SFC mode only) decimation) sure also decimation SQA11 SQA10. decimation BFOT output clock frequency division ratio setting SQC05 SQC04 384Fs 256Fs 512Fs 768Fs sure these bits when changing setup register Field settings. Table 6-3. Setup Register Field
decimation)
SQC05, SQC04
384Fs
SQC03 Reserve SQC00
Note) polarity selection (SQC13) valid only slave mode. master mode.
CXD2724AQ-1
Field Data section SQD15 SQD03 Reserve Control contents sure these bits when changing setup register Field settings. only (ROM ffH) ROM/RAM mixed (ROM dfH/RAM ffH) ROM/RAM mixed (ROM bfH/RAM ffH) ROM/RAM mixed (ROM 9fH/RAM ffH) ROM/RAM mixed (ROM 7fH/RAM ffH) ROM/RAM mixed (ROM 3fH/RAM ffH) ROM/RAM mixed (ROM 1fH/RAM ffH) only (RAM ffH) When reset
Coefficient memory SQD02 type setting SQD02 SQD00
only
Table 6-4. Setup Register Field
CXD2724AQ-1
Coefficient RAM/ROM When coefficient selected microcomputer interface transfer mode, various application functions turned off, coefficient parameters such each section's volume delay time set. Coefficient addresses other than those given these specifications "don't care". However, cleared entirely when this reset, there initial values setup register. sure necessary data; otherwise misoperation result. Configuration coefficient have capacity words bits each. However, address space coefficient data from (256 words), possible access coefficient data same time. That say, total words both coefficient ROM, only specified words handled. coefficient areas allocated setting SQD02 SQD00 setup register Field Coefficient data transferred microcomputer interface stored only coefficient area specified these bits. (Even area address specified transfer performed, transfer ignored.)
Coefficient address space
Fig. 7-1. Coefficient Data ROM/RAM Allocation when SQD02 SQD00 "010" (Setting Example) contents data transferred coefficient area differ each mode. (See Applications" detailed contents.) area also differ, SQD02 SQD00 must sent when switching mode.
Mode
Setting item SQD02 SQD00
Remarks Coefficient area Coefficient area Coefficient area
Logic simple mode Virtual Dolby Surround mode mode
Table 7-1. Coefficient Area
CXD2724AQ-1
Applications CXD2724Q equipped with various applications such Dolby Logic Surround mode (Pro Logic mode), Virtual Dolby Surround mode (Virtual mode), Dolby Stereo mode, noise sequencer mode, mode, bypass mode. methods setting each mode changing mode described below. Note) filter other parameter values each application assume sampling frequency (fs) 44.1 [kHz]. Consult your Sony representative with regard other 8-1. Dolby Logic Surround Mode (Pro Logic Mode) Logic mode realized using adaptive matrix, passive decoder including BNR, auto input balance, center channel mode control, simple other functions. Setting Logic Mode Logic mode must following procedures order achieve stable adaptive matrix operation. Setting Logic mode procedures other than those given below aggravate decoder characteristics. Immediately after power-on reset Transfer following setup data. 0030H (Field 7ee7H (Field Field "All forced mute applied. Transfer Logic mode coefficient data. iii) Transfer setup data Logic mode. Changing Logic mode from Virtual mode Note) coefficients Logic mode soft mute1 status must coefficient addresses before shifting Virtual mode. Apply soft mute Virtual mode. Transfer setup data Logic mode. iii) Cancel Logic mode soft mute. Changing Logic mode from different mode (other than Virtual mode) Apply soft mute current mode. coefficients following addresses "0000H". Addresses: iii) Transfer following setup data. 0030H (Field 7ee7H (Field forced mute applied Field Transfer Logic mode coefficients soft mute status. Transfer setup data Logic mode. Cancel Logic mode soft mute. Soft mute: "Appendix Soft Mute".
CXD2724AQ-1
Setting Data (2)-1. Setup Data Table 8-1-1 lists registers most closely related Logic mode. Setup data listed Table 8-1-1 desired, with consideration given contents Fields noted Setup Register". Register name Setting value SQA14 SQA13 SQA09, SQA05, SQB15 SQB10 SQD02 "00" "00" Don't care Don't care "111" Noise sequencer mode Virtual mode Dolby Stereo mode mode Center channel (C-ch) trim volume Surround channel (S-ch) trim volume Coefficient area setting (111: Other than Virtual mode, 100: Virtual mode) Table 8-1-1. Logic Mode Setup Register Settings Remarks
CXD2724AQ-1
(2)-2. Coefficient Data coefficient area Logic mode from addresses (all areas). coefficient data consists "fixed values" shown Table 8-1-2 "setting values" shown Table 8-1-3 which user. coefficient values must sent coefficient microcomputer interface. Note that once data been transferred coefficient RAM, coefficient data (00H 7fH) saved unless power turned off, even area changed setting SQD02 SQD00 (even mode changed Virtual mode). Fixed values during Logic mode initialization following fixed values must coefficient ensure proper internal operation. Address Fixed value 0000H 051eH ff86H 02a0H f6c0H 2715H 4000H 5149H e571H 0f4eH f5b8H 075cH fa97H 0402H fd0bH 0225H fe7cH 01d3H f312H 4b85H 850fH 7d6bH 7d72H 22b6H 3a94H 0074H 7f18H a000H 8000H febfH 04f9H eb83H 7b01H cae0H 0400H 0074H Address Fixed value 7f18H 0400H 001eH 7fc5H 0002H 7ffdH 8000H dd1eH da82H 109cH 2641H 3441H dd1eH 109cH da82H 2641H 3441H 0bbfH e755H 4000H f619H e57eH 36dcH 5a82H 10c9H 2641H 7f18H 7e30H 4cbaH c216H 0aa4H 27b4H 7e14H 7ff9H 0063H 0000H Address Fixed value 43b9H 0400H 401eH ec00H 8000H a000H 0024H ff92H 010aH fce2H 097bH e38dH 1555H 0400H 1400H 2000H c000H ffe4H febcH f520H c144H a57eH 0757H 0012H 7f00H 7fffH fc00H 68a9H 5121H 7ff4H 7fe8H 8000H c400H 0000H 0000H 0000H Address Fixed value 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 7fffH 8000H b800H ffffH
Table 8-1-2. Logic Mode Fixed Value Coefficients
CXD2724AQ-1
Logic mode user setting coefficients relationships between coefficient each function during Logic mode operation follows. Address Symbol KLm1 KRm1 KLm2 KRm2 KDin KDout KDV1 KDV2 KDV3 KLRm1 Function Simple SFC: L-ch L-ch volume Simple SFC: R-ch R-ch volume Simple SFC: C-ch C-ch volume Simple SFC: (HPF1) S-ch volume Simple SFC: L-ch LPF1 volume Simple SFC: R-ch LPF1 volume Simple SFC: LPF1 coefficient Simple SFC: LPF1 coefficient Simple SFC: LPF1 coefficient Simple SFC: L-ch HPF1 volume Simple SFC: R-ch HPF1 volume Simple SFC: HPF1 coefficient Simple SFC: HPF1 coefficient Simple SFC: HPF1 coefficient Simple SFC: L-ch Delay volume Simple SFC: R-ch Delay volume Simple SFC: C-ch Delay volume Simple SFC: S-ch Delay volume Simple SFC: Delay feedback volume Simple SFC: HPF2 coefficient Simple SFC: HPF2 coefficient Simple SFC: HPF2 coefficient Simple SFC: LPF2 coefficient Simple SFC: LPF2 coefficient Simple SFC: LPF2 coefficient Simple SFC: Delay write address Simple SFC: Delay read Tap1 address Simple SFC: Delay read Tap2 address Simple SFC: Delay read Tap3 address Simple SFC: Delay read Tap4 address Simple SFC: Delay read Tap5 address Simple SFC: Delay read Tap6 address Simple SFC: Delay feedback address Simple SFC: Delay S-ch volume Simple SFC: Delay R-ch volume Simple SFC: Delay L-ch volume Simple SFC: LPF1 L-ch volume Table 8-1-3 (1). Logic Mode Setting Value Coefficients Setting value Table 8-1-13. Table 8-1-13. Table 8-1-13. Table 8-1-13. Table 8-1-13. Table 8-1-13. Table 8-1-16. Table 8-1-16. Table 8-1-16. Table 8-1-13. Table 8-1-13. Table 8-1-16. Table 8-1-16. Table 8-1-16. Table 8-1-13. Table 8-1-13. Table 8-1-13. Table 8-1-13. Table 8-1-13. Table 8-1-16. Table 8-1-16. Table 8-1-16. Table 8-1-16. Table 8-1-16. Table 8-1-16. Table 8-1-15. Table 8-1-15. Table 8-1-15. Table 8-1-15. Table 8-1-15. Table 8-1-15. Table 8-1-15. Table 8-1-15. Table 8-1-13. Table 8-1-13. Table 8-1-13. Table 8-1-13.
CXD2724AQ-1
Address
Symbol KLRm2 KLRm3 KTP1 KTP2 KTP3 KTP4 KTP5 KTP6 aslw Kdlb
Function Simple SFC: LPF1 R-ch volume Simple SFC: HPF1 S-ch volume Simple SFC: Tap1 volume Simple SFC: Tap2 volume Simple SFC: Tap3 volume Simple SFC: Tap4 volume Simple SFC: Tap5 volume Simple SFC: Tap6 volume parameter parameter parameter parameter Passive decoder M-BNR Passive decoder M-BNR Auto input balance ON/OFF Serial audio interface input volume De-emphasis ON/OFF Analog input volume Digital input volume Center mode control volume Center mode control volume Center mode control volume Center mode control volume Center mode control volume Center mode control volume Passive decoder volume Passive decoder M-BNR ON/OFF Passive decoder delay time adjustment
Setting value Table 8-1-13. Table 8-1-13. Table 8-1-13. Table 8-1-13. Table 8-1-13. Table 8-1-13. Table 8-1-13. Table 8-1-13. 0000 OFF, df66 0000 OFF, 5723 0000 OFF, 125e 8000 OFF, eda2 Table 8-1-12. Table 8-1-12. 0000 OFF, 00ff Table 8-1-5. 0000 OFF, ac19 Table 8-1-4. Table 8-1-5. Tables 8-1-7, Tables 8-1-7, Tables 8-1-7, Tables 8-1-7, Tables 8-1-7, Tables 8-1-7, Table 8-1-8. 0000 OFF, 2000 Table 8-1-9.
Table 8-1-3 (2). Logic Mode Setting Value Coefficients
(2)-3. Signal Flow Dolby Logic Mode
-Kia (dcH)
Decimation
-Kis (ddH) Over Sampling
LOUT
Decimation
SIA1 -Kia (dcH) Logic Decoder Simple
DeEmphasis
ROUT
-KiA (d6H)
Over Sampling
-Kis (ddH)
SIA2
DeEmphasis
XCOUT Over Sampling Trim
-KiA (d6H)
XSOUT Over Sampling Trim
CXD2724AQ-1
Fig. 8-1-1
CXD2724AQ-1
Volume Coefficient Settings [Relevant data] Coefficients: (d6H), (dcH), (ddH) levels volumes complement format with decimal point between D14, hexadecimal notation with LSB. coefficient level relationships follows. negative values, calculation (-1) (D15 D0). (3)-1. (dcH): c000H levels 8000H ffffH obtained following formulas. (Coefficient value) [(-1) 15)] (-2)
8000H a599H c000H d2b2H e000H eff6H ffffH 0000H
Level [dB] +6.02 +3.00 0.00 -3.00 -6.02 -12.00 -84.29
level [coefficient value]
Table 8-1-4. (dcH) Setting Value Examples
(3)-2. (d6H), (ddH): 8000H levels 8000H ffffH obtained following formulas. (Coefficient value) [(-1) 15)] (-1)
8000H a563H c000H e000H ffffH 0000H
Level [dB] 0.00 -3.00 -6.02 -12.04 -90.31
level [coefficient value]
Table 8-1-5. (d6H), (ddH) Setting Value Examples Unless otherwise specified, subsequent setting examples (Pro Logic mode) these specifications assume either: d2b2H, 0000H, 0000H 0000H, 8000H, a563H Auto Input Balance Control [Relevant data] Coefficient: (d4H) auto input balance function turned coefficient (d4H). Coefficient (d4H) 00ffH 0000H
Table 8-1-6. Auto Input Balance ON/OFF
CXD2724AQ-1
Center Mode Control [Relevant data] Coefficients: (f5H), (f4h), (f2H), (f3H), (f7H), (f6H) center channel output mode Normal, Wide Phantom mode shown Table 8-1-7 below. Mode Coefficient Normal Wide Phantom (f5H) e000H 0000H e000H (f4H) e000H 0000H 0000H (f2H) d2cdH d2cdH d2cdH (f3H) d2cdH d2cdH d2cdH (f7H) 0000H e000H 0000H (f6H) e000H 0000H 0000H
Table 8-1-7. Center Mode Control Setting Value Examples
(f2H)
(f3H)
(f4H), (f5H) -KCH (f6H) -KCP (f7H)
Note) 0000H Phantom center channel mode, data through status data added channels
Fig. 8-1-2. Signal Flow Center Mode Control C-ch) Note) Phantom center channel mode, center channel information divided equally between left right speakers. level each channel adjusted changing setting values. these cases, sure change only shaded portions each mode Table 8-1-7. However, make sure that Normal mode. Phantom mode, 0000H adjust level left right channels using levels 8000H ffffH obtained following formulas. (Coefficient value) [(-1) 15)] (-4)
8000H c000H d2cdH e000H e959H eff6H f7f6H ffffH 0000H
Level [dB] +12.04 +6.02 +3.00 -3.00 -6.00 -12.00 -78.27
level [coefficient value]
Table 8-1-8. KCP, Setting Value Examples
Table 8-1-7, lowering input level using (dcH) (ddH) raises output level channels 3dB. this case, attaching external parts shown Application Circuit recommended increase channel gains.
CXD2724AQ-1
Passive Decoder (Surround Channel) surround channel processed according flow shown Fig. 8-1-3. setting method each section described below.
(f8H) M-BNR Delay
7kHz
Fig. 8-1-3. Passive Decoder Signal Flow (S-ch)
(6)-1. Delay Time Setting [Relevant data] Coefficient: (fbH) surround channel delay time varied setting coefficient value. (Dly delay line read address.) Only upper coefficient bits used. lower bits used, ignored even set. That say, 0020H increments, delay time approximately 0.022 increments. following condition also applies. 0020H bfa0H coefficient value calculated follows. (Dly) Decimal (Delay [Hz] Example) 20ms 44100 [Hz])
Setting value (fbH) 0020H 0040H 52b0H 6e40H 89d0H a560H bf80H bfa0H
Delay 44.1kHz) 0.022ms 0.045ms 15.000ms 20.000ms 25.000ms 30.000ms 34.739ms 34.762ms
Table 8-1-9. Surround Channel (S-ch) Delay Time Setting Value Examples
0.02 44100 28224 (6)-2. 7kHz Low-Pass Filter
Hexadecimal conversion
6e40H
[Relevant data] Coefficients: (afH), (b0H), (b1H), (b2H) 7kHz passive decoder turned setting coefficients Table 8-1-10. df66 0000 5723 0000 125e 0000 eda2 8000
Table 8-1-10. Passive Decoder 7kHz ON/OFF Setting
CXD2724AQ-1
(6)-3. Modified Dolby B-type [Relevant data] Coefficients: aslw (b5H), (b7H), (d6H), (dcH), (ddH), Kdlb (faH) aslw coefficients ON/OFF coefficient Kdlb must Modified Dolby B-type This function turned setting Kdlb shown Table 8-1-11. aslw coefficient values differ according Dolby level, prefilter coefficient Kia/Kis (KiA) conditions. Table 8-1-12 shows typical setting value examples based these three conditions. prefilter gain -3.52dB) value when using Application Circuit given these specifications. Consult your Sony representative with regard under conditions other than those noted Table 8-1-12. Coefficient Kdlb (faH) 2000H 0000H
Table 8-1-11. Modified Dolby B-type ON/OFF Setting
Prefilter -3.52dB -3.52dB -3.52dB (Digital input)
Dolby level 300mVrms 300mVrms 200mVrms -20dBFS
(dcH) d2b2H c000H d2b2H 0000H
(ddH) 0000H 0000H 0000H a563H
aslw (b5H) 00caH 009eH 00caH 00caH
(b7H) 0033H 004aH 0023H 0023H
Table 8-1-12. Modified Dolby B-type Coefficient Value Examples Different Input Level Conditions (during digital input: (d6H) 8000H)
(6)-4. Volume [Relevant data] Coefficient: (f8H) (f8H) volume values shown Table 8-1-8. Center Mode Control" calculation method.
CXD2724AQ-1
Simple Simple effects added after Dolby Logic Surround decoder processing. (See Fig. 8-1-1.) Fig. 8-1-4 shows signal flow simple block. When using simple SFC, coefficients follows simple block through status. (00H), (01H), (02H), (03H) 8000H KDV1 (21H), KDV2 (22H), KDV3 (23H), KLRm1 (24H), KLRm2 (25H), KLRm3 (26H) 0000H
-KCV (02H) -KLV (00H) -KRV (01H) -KCd (10H) -KRd (0fH) HPF2 LPF2 -KLd (0eH) -KSd (11H) -KTP1 -KTP6 (28H 2dH) -KRm1 (05H) LPF1 -KLm1 (04H) -KRm2 (0aH) HPF1 -KLm2 (09H) -KLRm3 (26H) -KDV1 (21H) -Kfb (12H) Delay KDin KDout -KDV3 (23H) -KLRm1 (24H)
-KDV2 (22H)
-KLRm2 (25H)
-KSV (03H)
Fig. 8-1-4. Simple Signal Flow
CXD2724AQ-1
(7)-1. Volume Settings Each Section [Relevant data] Coefficients: (00H), (01H), (02H), (03H), KLm1 (04H), KRm1 (05H), KLm2 (09H), KRm2 (0aH), (0eH), (0fH), (10H), (11H), (12H), KDV1 (21H), KDV2 (22H), KDV3 (23H), KLRm1 (24H), KLRm2 (25H), KLRm3 (26H), KTP1 (28H), KTP2 (29H), KTP3 (2aH), KTP4 (2bH), KTP5 (2cH), KTP6 (2dH) format same that described "(3) Volume Coefficient Settings". levels follows when 8000H. levels 8000H ffffH obtained following formulas. (Coefficient value) [(-1) 15)] (-1)
8000H a563H c000H d2b2H e000H f000H ffffH 0000H
Level [dB] 0.00 -3.00 -6.02 -9.02 -12.04 -18.06 -90.31
level [coefficient value]
Table 8-1-13. Setting Value Examples Each Volume (Negative Values)
above coefficients normally applied negative values, positive values should applied when intentionally inverting phase with TP6, etc. this case, levels follows when 7fffH. levels 7fffH 0001H obtained following formulas. (Coefficient value) [D15 15)]
7fffH 5a9dH 4000H 2d4eH 2000H 1000H 0001H 0000H
Level [dB] 0.00 -3.00 -6.02 -9.02 -12.04 -18.06 -90.31
level [coefficient value]
Table 8-1-14. Setting Value Examples Each Volume (Positive Values)
CXD2724AQ-1
(7)-2. Delay Line Settings [Relevant data] Coefficients: KDin (19H), (1aH), (1bH), (1cH), (1dH), (1eH), (1fH), KDout (20H) Logic mode delay lines used both passive decoder short delay simple reverberation, thus subject following restrictions: 0020H KDin (0020H KDin 0020H) 0020H KDout KDin KDout bfe0H (fbH): Logic delay line read address KDin (19H): Simple delay line write address (1aH 1fH): Simple read addresses (determine delay time each tap) KDout (20H): Simple feedback loop read address (determines maximum delay time) Note) minimum unit above coefficients "0020H". Values smaller than this ignored. KDout addresses specified different manner than KDin. These addresses specified address value assuming KDin reference 0000H). That say, actual address KDin KDout, etc. coefficient values calculated follows. (Dly) Decimal (Delay [s]) [Hz] Example) When using 20ms passive decoder, remaining delay lines reverberation 20ms 6e40H KDin 6e40H 0020H 6e60H KDout bfe0H 6e60H 5180H 0020H 5180H Delay Setting value KDout, 44.1kHz) 0020H 0040H 1a60H 35f0H 5180H 6d10H bf80H bfa0H 0.022ms 0.045ms 4.784ms 9.784ms 14.784ms 19.784ms 34.739ms 34.762ms
Table 8-1-15. Simple Delay Time Setting Value Examples
Passive decoder 0000H 20.0ms
6e40H
KDin 6e60H
Simple 14.8ms
KDout 5180H
34.8ms (0000H bfe0H)
Fig. 8-1-5. Logic Mode Delay Line Setting Example
CXD2724AQ-1
(7)-3. Filters [Relevant data] Coefficients: (06H, 0bH, 13H, 16H), (07H, 0cH, 14H, 17H), (08H, 0dH, 15H, 18H) LPF1, HPF1, LPF2 HPF2 comprised primary filters, coefficient setting cut-off frequency relationship shown Table 8-1-16. Cut-off frequency [Hz] 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000 3200 3400 3600 3800 4000 4200 4400 4600 4800 5000 LPF1, FF19 FE34 FD53 FC74 FB99 FAC1 F9EB F918 F848 F77A F5E6 F45C F2DB F162 EFF2 EE89 ED28 EBCE EA7A E92D E7E6 E6A5 E569 E432 E301 E1D4 E0AB DF87 DE67 DD4B 00E7 01CC 02AD 038C 0467 053F 0615 06E8 07B8 0886 0A1A 0BA4 0D25 0E9E 100E 1177 12D8 1432 1586 16D3 181A 195B 1A97 1BCE 1CFF 1E2C 1F55 2079 2199 22B5 7E30 7C67 7AA4 78E7 7731 7580 73D4 722E 708E 6EF2 6BCB 68B6 65B4 62C3 5FE2 5D11 5A4E 579A 54F3 5259 4FCB 4D48 4AD0 4863 4600 43A6 4155 3F0D 3CCD 3A94 80E8 81CD 82AE 838D 8468 8540 8616 86E9 87B9 8887 8A1B 8BA5 8D26 8E9F 900F 9178 92D9 9433 9587 96D4 981B 995C 9A98 9BCF 9D00 9E2D 9F56 A07A A19A A2B6 HPF1, 7F18 7E33 7D52 7C73 7B98 7AC0 79EA 7917 7847 7779 75E5 745B 72DA 7161 6FF1 6E88 6D27 6BCD 6A79 692C 67E5 66A4 6568 6431 6300 61D3 60AA 5F86 5E66 5D4A 7E30 7C67 7AA4 78E7 7731 7580 73D4 722E 708E 6EF2 6BCB 68B6 65B4 62C3 5FE2 5D11 5A4E 579A 54F3 5259 4FCB 4D48 4AD0 4863 4600 43A6 4155 3F0D 3CCD 3A94 Cut-off frequency [Hz] 5200 5400 5600 5800 6000 6200 6400 6600 6800 7000 7200 7400 7600 7800 8000 8200 8400 8600 8800 9000 9200 9400 9600 9800 10000 10200 10400 10600 10800 11000 LPF1, DC32 DB1D DA0C D8FD D7F2 D6E9 D5E3 D4DF D3DE D2DF D1E3 D0E8 CFEF CEF8 CE03 CD0F CC1D CB2B CA3B C94D C85F C772 C685 C59A C4AF C3C5 C2DA C1F1 C107 C01E 8000 23CE 24E3 25F4 2703 280E 2917 2A1D 2B21 2C22 2D21 2E1D 2F18 3011 3108 31FD 32F1 33E3 34D5 35C5 36B3 37A1 388E 397B 3A66 3B51 3C3B 3D26 3E0F 3EF9 3FE2 0000 3863 3639 3416 31F9 2FE2 2DD0 2BC4 29BD 27BB 25BD 23C4 21CF 1FDD 1DEF 1C04 1A1C 1838 1655 1475 1298 10BC 0EE2 0D09 0B32 095C 0788 05B3 03E0 020D 003A 0000 A3CF A4E4 A5F5 A704 A80F A918 AA1E AB22 AC23 AD22 AE1E AF19 B012 B109 B1FE B2F2 B3E4 B4D6 B5C6 B6B4 B7A2 B88F B97C BA67 BB52 BC3C BD27 BE10 BEFA BFE3 8000 HPF1, 5C31 5B1C 5A0B 58FC 57F1 56E8 55E2 54DE 53DD 52DE 51E2 50E7 4FEE 4EF7 4E02 4D0E 4C1C 4B2A 4A3A 494C 485E 4771 4684 4599 44AE 43C4 42D9 41F0 4106 401D 0000 3863 3639 3416 31F9 2FE2 2DD0 2BC4 29BD 27BB 25BD 23C4 21CF 1FDD 1DEF 1C04 1A1C 1838 1655 1475 1298 10BC 0EE2 0D09 0B32 095C 0788 05B3 03E0 020D 003A 0000
Table 8-1-16. Simple Setting Coefficients
CXD2724AQ-1
8-2. Virtual Dolby Surround Mode (Virtual Mode) Virtual mode comprised Dolby Logic Surround decoder Virtualizer shown Fig. 8-2-1. Virtual Dolby Surround realized Virtualizer block. Setting Virtual Mode Virtual mode must following procedures order achieve stable adaptive matrix operation. Setting Virtual mode procedures other than those given below aggravate decoder characteristics. Immediately after power-on reset Transfer following setup data. 0030H (Field 7ee7H (Field Field "All forced mute applied. Transfer Virtual mode coefficient data. iii) Transfer setup data Virtual mode. Changing Virtual mode from different mode Apply soft mute current mode. coefficients following addresses "0000H". Addresses: iii) Transfer following setup data. 0030H (Field 7ee7H (Field forced mute applied Field Transfer Virtual mode coefficients soft mute status. Transfer setup data Virtual mode. Cancel Virtual mode soft mute. Setting Data (2)-1. Setup Data Table 8-2-1 lists registers most closely related Virtual mode. Setup data listed Table 8-2-1 desired, with consideration given contents Fields noted Setup Register". Register name Setting value SQA14 SQA13 SQA09, SQA05, SQD02 "00" "00" "100" Noise sequencer mode Virtual mode Dolby Stereo mode mode Coefficient area setting (111: Other than Virtual mode, 100: Virtual mode) Table 8-2-1. Virtual Mode Setup Register Settings Remarks
CXD2724AQ-1
(2)-2. Coefficient Data coefficient area Virtual mode from addresses ffH. Addresses data. (The contents mainly coefficients used Virtualizer.) Like Logic mode, coefficient data consists fixed values setting values, with fixed values exactly same Logic mode. area from address Table 8-1-2. setting values shown Table 8-2-2, consist adding Virtualizer attenuation coefficient attV (f1H) setting Wide center mode settings Logic mode. Address Symbol aslw attV Kdlb Function parameter parameter parameter parameter Passive decoder M-BNR Passive decoder M-BNR Auto input balance ON/OFF Serial audio interface input volume De-emphasis ON/OFF Analog input switch Digital input switch Virtual Dolby Surround attenuator Center mode control volume Center mode control volume Center mode control volume Center mode control volume Center mode control volume Center mode control volume Passive decoder volume Passive decoder M-BNR ON/OFF Passive decoder delay time setting Table 8-2-2. Virtual Mode Setting Value Coefficients Setting value 0000 OFF, df66 0000 OFF, 5723 0000 OFF, 125e 8000 OFF, eda2 Table 8-1-12. Table 8-1-12 0000 OFF, 00ff Table 8-1-5. 0000 OFF, ac19 Table 8-1-4. Table 8-1-5. Table 8-2-3. Tables 8-1-7, Tables 8-1-7, Tables 8-1-7, Tables 8-1-7, Tables 8-1-7, Tables 8-1-7, Table 8-1-8. 0000 OFF, 2000 Table 8-1-9.
(2)-3. Signal Flow Dolby Virtual Surround Mode
-Kia (dcH)
Virtualizer
Decimation
-Kis (ddH) -Kia (dcH) Logic Decoder Mixing
Decimation
Over Sampling
LOUT
SIA1
DeEmphasis
-Kis (ddH) Virtual Surround Process
-KiA (d6H)
Over Sampling
ROUT
SIA2
DeEmphasis
-KiA (d6H)
CXD2724AQ-1
Fig. 8-2-1
CXD2724AQ-1
Volume Coefficient Settings [Relevant data] Coefficients: attV (f1H), (f2H), (f3H), (f7H), (f8H) Adjust levels Virtual mode channels amount four Logic decoder output channels using (f2H), (f3H), (f7H) (f8H). (See Table 8-1-7.) mixing level surround channel adjusted with coefficient attV (f1H). attV range 7fffH 0000H shown Table 8-2-3.
Coefficient value Level [dB] 7fffH 5a67H 3fffH 2d4eH 2000H 1000H 0001H 0000H +6.02 +3.00 0.00 -3.00 -6.02 -12.04 -84.29
levels 7fffH 0001H obtained following formulas. (Coefficient value) [D15 15)]
Sony recommended value: 5333H (+2.28dB) Table 8-2-3. attV (f1H) Setting Value Examples
level [coefficient value] Also, most effective listening area shown Fig. 8-2-3.
(f2H) Logic Decoder -KCP (f7H) (f8H) Virtual Surround Process attV (f1H) Listening center attV (f1H) Virtual surround Virtual surround (f3H) Rout 2.0m Lout Phantom center
Mixing
Fig. 8-2-2. Volume Setting Coefficients
Fig. 8-2-3. Listening Area
CXD2724AQ-1
8-3. Dolby Stereo Mode This mode part Logic adaptive matrix functions. Specifically, surround output muted surround signal directionality harmonized. Setting Dolby Stereo Mode Dolby Stereo mode must following procedures order achieve stable adaptive matrix operation. Setting Dolby Stereo mode procedures other than those given below aggravate decoder characteristics. Immediately after power-on reset Transfer following setup data. 0030H (Field 7ee7H (Field Field "All forced mute applied. Transfer Dolby Stereo mode coefficient data. iii) Transfer setup data Dolby Stereo mode. Changing Dolby Stereo mode from Virtual mode Note) coefficients Dolby Stereo mode Logic mode soft mute status must coefficient addresses when shifting Virtual mode. Apply soft mute Virtual mode. Transfer setup data Logic mode. iii) Cancel Logic mode soft mute. Changing Dolby Stereo mode from different mode Apply soft mute current mode. coefficients following addresses "0000H". Addresses: iii) Transfer following setup data. 0030H (Field 7ee7H (Field forced mute applied Field Transfer Dolby Stereo mode coefficients soft mute status. Transfer setup data Dolby Stereo mode. Cancel Dolby Stereo mode soft mute.
CXD2724AQ-1
Setting Data (2)-1. Setup Data Table 8-3-1 lists registers most closely related Dolby Stereo mode. Setup data listed Table 8-3-1 desired, with consideration given contents Fields noted Setup Register". Register name Setting value SQA14 SQA13 SQA09, SQA05, SQB15 SQD02 "01" "00" Don't care "111" Noise sequencer mode Virtual mode Dolby Stereo mode mode Center channel (C-ch) trim volume Coefficient area setting (111: Other than Virtual mode, 100: Virtual mode) Table 8-3-1. Dolby Stereo Mode Setup Register Settings (2)-2. Coefficient Data coefficient data used Dolby Stereo mode entirely same that Logic mode. "8-1. Dolby Logic Surround Mode". Remarks
CXD2724AQ-1
8-4. Noise Sequencer Mode Setting Noise Sequencer Mode noise sequencer mode following procedures. Immediately after power-on reset Transfer setup data noise sequencer mode. Transfer noise sequencer mode coefficient data. Changing noise sequencer mode from different mode Apply soft mute current mode. Transfer setup data noise sequencer mode. iii) Transfer noise sequencer mode coefficient data. Setting Data (2)-1. Setup Data Table 8-4-1 lists registers most closely related noise sequencer mode. Setup data listed Table 8-4-1 desired, with consideration given contents Fields noted Setup Register". Register name Setting value SQA14 SQA13 SQA09, SQA05, SQB15 SQB10 SQD02 "00" "00" Don't care Don't care "111" Noise sequencer mode Virtual mode Dolby Stereo mode mode Center channel (C-ch) trim volume Surround channel (S-ch) trim volume Coefficient area setting (111: Other than Virtual mode, 100: Virtual mode) Remarks
Table 8-4-1. Noise Sequencer Mode Setup Register Settings
CXD2724AQ-1
(2)-2. Coefficient Data Noise sequencer mode allows both Logic Virtual processing. coefficients these types processing, change coefficients from addresses shown tables below. other coefficients left Logic mode Virtual mode coefficient settings. (d0H) L-ch C-ch R-ch S-ch LCRS 2000 0000 0000 0000 2000 2000 (d1H) 2000 3000 0000 0000 3000 3000 (d2H) 2000 3000 4000 0000 4000 4000 (d3H) 2000 3000 4000 5000 5000 4000 Address Fixed value 1000H 0040H c000H d2b1H 0000H 2d4fH 0000H d2b1H c000H d2b1H 8000H 7789H 6f12H 0876H 6f14H
Table 8-4-2. Noise Sequencer Mode Coefficient Setting Values
Table 8-4-3. Noise Sequencer Mode Coefficient Fixed Values Output Level Adjustment [Relevant data] Coefficients: (f2H), (f3H), (f4H), (f5H), (f6H), (f7H), (f8H) noise output level noise sequencer mode adjusted center mode control coefficients (f2H f7H) passive decoder volume coefficient (f8H) (6)-4 "8-1. Logic Mode". 8-5. Mode mode used 2-channel stereo input, realizes reverberation effects using delay lines, dynamics processing using decimation compressor. This separate application from simple Logic mode. Setting Mode mode following procedures. Immediately after power-on reset Transfer setup data mode. Transfer mode coefficient data. Changing mode from different mode Apply soft mute current mode. Transfer setup data mode. iii) Transfer mode coefficient data.
CXD2724AQ-1
Setting Data (2)-1. Setup Data Table 8-5-1 lists registers most closely related mode. Setup data listed Table 8-5-1 desired, with consideration given contents Fields noted Setup Register". Register name SQA11, SQA05, SQB15 SQB10 SQC07, SQD02 Setting value Don't care "01" Don't care Don't care Don't care "111" Remarks decimation, 1/2, mode Center channel (C-ch) trim volume Surround channel (S-ch) trim volume decimation, 1/2, Coefficient area setting (111: mode) Table 8-5-1. Mode Setup Register Settings
(2)-2. Coefficient Data mode coefficient data uses entire area. Also, like other modes, coefficient data consists fixed values setting values. Fixed values during mode initialization following fixed values must coefficient ensure proper internal operation. Address Fixed value 7fe8H 7fd1H 0000H 0092H 0209H 02cdH 0109H fda9H fd19H 0189H 058aH 016dH f7beH f72aH 0a4eH 2706H Address Fixed value 34eeH 0000H 6000H ff80H 00a1H 016eH 01f8H 0193H 0024H fe70H fdbaH fed8H 015aH 037fH 0344H ffffH Address Fixed value fb5cH f8e3H fbf6H 0575H 129cH 1e0dH 2294H 051eH ff86H 02a0H f6c0H 2715H 4000H 5149H e571H 0f4eH Address Fixed value f5b8H 075cH fa97H 0402H fd0bH 0225H fe7cH 01d3H f312H 4b85H 0000H 7fffH 68a9H 5121H 7ff4H 7fe8H
Table 8-5-2. Mode Fixed Value Coefficients
CXD2724AQ-1
mode user setting coefficients relationships between coefficient each function during mode operation follows. Address Symbol XthP XthM KLsri KRsri KLtp0 KLtp1 KLtp2 KLtp3 KLtp4 KRtp0 KRtp1 KRtp2 KRtp3 KRtp4 KStp0 KStp1 KStp2 KStp3 KLdry KRdry Function Compressor gain coefficient Compressor threshold value Compressor threshold value Compressor ON/OFF Compressor parameter Compressor parameter Compressor parameter Compressor parameter Compressor parameter Compressor parameter Delay line L-ch input volume Delay line R-ch input volume Delay line feedback coefficient Feedback loop internal Hi-dump filter coefficient Feedback loop internal LPF0 parameter Feedback loop internal LPF0 parameter Feedback loop internal LPF0 parameter Feedback loop internal LPF0 parameter Feedback loop internal LPF0 parameter Delay line L-ch Tap0 volume Delay line L-ch Tap1 volume Delay line L-ch Tap2 volume Delay line L-ch Tap3 volume Delay line L-ch Tap4 volume Delay line R-ch Tap0 volume Delay line R-ch Tap1 volume Delay line R-ch Tap2 volume Delay line R-ch Tap3 volume Delay line R-ch Tap4 volume Delay line S-ch Tap0 volume Delay line S-ch Tap1 volume Delay line S-ch Tap2 volume Delay line S-ch Tap3 volume pass filter coefficient pass filter coefficient L-ch direct sound volume R-ch direct sound volume Table 8-5-3 (1). Mode Setting Value Coefficients Setting value Table 8-5-7. Table 8-5-7. Table 8-5-7. 0000 OFF, 8000 Table 8-5-7. Table 8-5-7. Table 8-5-7. Table 8-5-7. Table 8-5-7. Table 8-5-7. Table 8-5-5. Table 8-5-5. Tables 8-5-5, Table 8-2-8. Tables 8-5-9, Tables 8-5-9, Tables 8-5-9, Tables 8-5-9, Tables 8-5-9, Tables 8-5-5, Tables 8-5-5, Tables 8-5-5, Tables 8-5-5, Tables 8-5-5, Tables 8-5-5, Tables 8-5-5, Tables 8-5-5, Tables 8-5-5, Tables 8-5-5, Tables 8-5-5, Tables 8-5-5, Tables 8-5-5, Tables 8-5-5, Tables 8-5-5, Tables 8-5-5, Table 8-5-5. Table 8-5-5.
CXD2724AQ-1
Address
Symbol KLeff KReff KLlpi KRlpi KLlpo KRlpo KLod KRod KSod KCod Ltp0 Ltp1 Ltp2 Ltp3 Ltp4 Rtp0 Rtp1 Rtp2 Rtp3 Rtp4 Stp0 Stp1 Stp2 Stp3 tp_fb ap0_in ap0_out ap1_in ap1_out
Function L-ch reflected sound volume R-ch reflected sound volume LPF1 L-ch input volume LPF1 R-ch input volume LPF1 parameter LPF1 parameter LPF1 parameter LPF1 parameter LPF1 parameter LPF1 L-ch volume LPF1 R-ch volume L-ch output total volume R-ch output total volume S-ch output total volume L-ch C-ch volume R-ch C-ch volume C-ch output total volume Compressor input volume (both Delay line L-ch Tap0 read address Delay line L-ch Tap1 read address Delay line L-ch Tap2 read address Delay line L-ch Tap3 read address Delay line L-ch Tap4 read address Delay line R-ch Tap0 read address Delay line R-ch Tap1 read address Delay line R-ch Tap2 read address Delay line R-ch Tap3 read address Delay line R-ch Tap4 read address Delay line S-ch Tap0 read address Delay line S-ch Tap1 read address Delay line S-ch Tap2 read address Delay line S-ch Tap3 read address Delay line feedback read address pass filter delay write address pass filter delay read address pass filter delay write address pass filter delay read address Serial audio interface input volume De-emphasis ON/OFF Analog input switch Digital input switch
Setting value Table 8-5-5. Table 8-5-5. Table 8-5-5. Table 8-5-5. Table 8-5-9. Table 8-5-9. Table 8-5-9. Table 8-5-9. Table 8-5-9. Table 8-5-5. Table 8-5-5. Table 8-5-5. Table 8-5-5. Table 8-5-5. Table 8-5-5. Table 8-5-5. Table 8-5-5. Table 8-5-5. Table 8-5-12. Table 8-5-12. Table 8-5-12. Table 8-5-12. Table 8-5-12. Table 8-5-12. Table 8-5-12. Table 8-5-12. Table 8-5-12. Table 8-5-12. Table 8-5-12. Table 8-5-12. Table 8-5-12. Table 8-5-12. Table 8-5-12. Table 8-5-12. Table 8-5-12. Table 8-5-12. Table 8-5-12. Table 8-5-5. 0000 OFF, ac19 Table 8-5-4. Table 8-5-5.
Table 8-5-3 (2). Coefficient Setting Data Mode
(2)-3. Signal Flow
-Kis (ddH) (5dH) -KLd (35H) Compressor -Kia (dcH) DC_Cut1 DC_Cut1 (5dH) -KRd (36H) Compressor (02H 0bH) -Kia (dcH) -Kis (ddH) Over Sampling (02H 0bH) -KCod (37H) XCOUT C-ch
SIA1
-KiA (d6H)
DeEmphasis
SIA2
-KiA (d6H)
DeEmphasis
Decimation
Decimation
settings this section same mode. (Same coefficients addresses)
-KLdry (25H) -KLod (32H) Hi-Sampling -Kfb (0eH) -KLeff (27H) -KLlpi (29H) -KLlpo (30H) Delay -KStp (1fH 22H) -KReff (28H) Hi-Sampling -KRod (33H) (23H) -KRdry (26H) (24H) -KSod (34H) Delay PASS FILTER (REVERVE) (23H) (24H) Delay Hi-Sampling Over Sampling XSOUT S-ch Over Sampling LPF1 -KLtp (15H 19H) LPF0 Dump -ahd (0fH) (10H 14H) -KRtp (1aH 1eH)
Secondary
Over Sampling
LOUT L-ch
-KLsri (0cH)
Down Sampling
1/2,
Secondary
(2bH 2fH) -KRlpo (31H) -KRlpi (2aH) ROUT R-ch
-KRsri (0dH)
CXD2724AQ-1
Fig. 8-5-1. Signal Flow Mode
CXD2724AQ-1
Volume Settings [Relevant data] Coefficients: KLsri (0cH), KRsri (0dH), (0eH), KLtp0 (15H), KLtp1 (16H), KLtp2 (17H), KLtp3 (18H), KLtp4 (19H), KRtp0 (1aH), KRtp1 (1bH), KRtp2 (1cH), KRtp3 (1dH), KRtp4 (1eH), KStp0 (1fH), KStp1 (20H), KStp2 (21H), KStp3 (22H), (23H), (24H), KLdry (25H), KRdry (26H), KLeff (27H), KReff (28H), KLlpi (29H), KRlpi (2aH), KLlpo (30H), KRlpo (31H), KLod (32H), KRod (33H), KSod (34H), (35H), (36H), KCod (37H), (5dH), (d6H), (dcH), (ddH) levels volumes complement format with decimal point between D14, hexadecimal notation with LSB. coefficient level relationships follows. (3)-1. (dcH): c000H levels 8000H ffffH obtained following formulas. (Coefficient value) [(-1) 15)] (-2)
8000H c000H e000H eff6H ffffH 0000H
Level [dB] +6.02 0.00 -6.02 -12.00 -84.29
level [coefficient value]
Table 8-5-4. (dcH) Setting Value Examples (3)-2. Other Coefficients Except Kia, coefficients listed [Relevant data] above basically specified negative values (D15 with "0dB 8000H". When intentionally inverting phase, however, specify positive values with "0dB 7fffH". calculation coefficient values other than (-1) (D15 D0). levels 8000H ffffH obtained following formulas. (Coefficient value) [(-1) 15)] (-1)
8000H a563H c000H d2b2H e000H f000H ffffH 0000H
Level [dB] 0.00 -3.00 -6.02 -9.02 -12.04 -18.06 -90.31
level [coefficient value]
Table 8-5-5. Setting Value Examples Each Volume (Other than Kia, Negative Values) Level [dB] 0.00 -3.00 -6.02 -9.02 -12.04 -18.06 -90.31
levels 7fffH 0001H obtained following formulas. (Coefficient value) [D15 15)]
level [coefficient value]
7fffH 5a9dH 4000H 2d4eH 2000H 1000H 0001H 0000H
Table 8-5-6. Setting Value Examples Each Volume (Other than Kia, Positive Values)
CXD2724AQ-1
Compressor [Relevant data] Coefficients: (02H), XthP (03H), XthM (04H), (05H), (06H), (07H), (08H), (09H), (0aH), (0bH) parameter table shown Table 8-5-7, characteristics Fig. 8-5-2. Compressor (05H) 8000H Compressor OFF: (05H) 0000H Threshold XthM Comp_5 XthP Gain [dB] 4000 [dB] 20/11 3A2E [dB] 3555 [dB] 2CCC [dB] 2666 -1.0 E000 2000 Coefficient 4000 4000 0000 0000
[dB] 0000 0000
[dB] Comp_4 -1/10 F334 1/10 0CCC
-100/99 DFAE
100/99 2052
200/99 40A5
200/99 40A5
-1/99 FEB6
1/99 014A
[dB] Comp_3 -1/7 EDB7 1249
-49/54 E2F7
49/54 1D09
52/27 3DA1
52/27 3DA1
-1/54 FDA2
1/54 025E
[dB] Comp_2 -1/5 E667 1999
-5/8 EC00
1400
33/20 34CC
33/20 34CC
-1/40 FCCD
1/40 0333
-9.5 [dB] Comp_1 -1/3 D556 2AAA
-9/20 F19A
9/20 0E66
3000
3000
-1/20 F99A
1/99 0666
Table 8-5-7. Compressor Parameter Table
CXD2724AQ-1
Input Level [dB]
Comp5 Comp4 Comp3 Comp2 Comp1 [dB] Linear
Output Level [dB]
Comp4
Comp3
Comp2
-9.5 Comp1
Threshold Level [dB]
Fig. 8-5-2. Compressor Characteristics
CXD2724AQ-1
Hi-Dump Filter Setting [Relevant data] Coefficient: (0fH) This filter used attenuate high frequencies. mainly used delay line feedback loop prevent alleviate noise generated when high frequency components multiplied. Table 8-5-8 shows parameter table. turn this filter, "ahd 8000H". [Hz] -ahd EF46 FEEA FE8D FE31 FC68 F8EA F585 F23A FE8D FDD5 FD1E FC68 F8EA F23A EBEE E603 FDD5 FCC3 FBB3 FAA6 F585 EBEE E32F DB3B [Hz] -ahd EF08 E073 C97A B91E AD94 A578 9FC6 9BCC E073 C97A AD94 9FC6 9912 D404 B91E 9FC6 974D
Table 8-5-8. Hi-Dump Filter Parameter Table
Secondary Settings [Relevant data] Coefficients: (10H), (11H), (12H), (13H), (14H), (2bH), (2cH), (2dH), (2eH), (2fH) These comprised from same secondary filters. parameter tables shown Tables 8-5-9 8-5-11. These tables show parameters decimation, decimation decimation, respectively. Table 8-5-9 decimation) LPF1. coefficients used LPF0 LPF1 parameters follows. LPF0: (10H), (11H), (12H), (13H), (14H) LPF1: (2bH), (2cH), (2dH), (2eH), (2fH) turn filters, only "8000H" other four coefficient values "0000H".
CXD2724AQ-1
Cut-off frequency [Hz] 5200 5300 5400 5500 5600 5700 5800 5900 6000 6100 6200 6300 6400 6500 6600 6700 6800 6900 7000 7100 7200 7300 7400 7500 7600 7700 7800 7900 8000 8100 F4A5 F448 F3EB F38D F32D F2CD F26D F20B F1A8 F145 F0E0 F07B F016 EFAF EF47 EEDF EE76 EE0D EDA2 ED37 ECCB EC5E EBF0 EB82 EB13 EAA4 EA33 E9C2 E950 E8DD
16B6 176F 182A 18E7 19A5 1A65 1B27 1BEA 1CB0 1D77 1E3F 1F09 1FD5 20A2 2171 2241 2313 23E7 24BC 2593 266B 2744 281F 28FC 29DA 2AB9 2B9A 2C7C 2D60 2E45
0B5B 0BB8 0C15 0C73 0CD3 0D33 0D93 0DF5 0E58 0EBB 0F20 0F85 0FEA 1051 10B9 1121 118A 11F3 125E 12C9 1335 13A2 1410 147E 14ED 155C 15CD 163E 16B0 1723
7FDF 7D90 7B43 78F7 76AD 7464 721C 6FD6 6D91 6B4D 690B 66CA 648A 624B 600D 5DD1 5B96 595C 5723 54EA 52B3 507D 4E48 4C14 49E1 47AF 457E 434D 411E 3EEF
D2B4 D391 D469 D53B D609 D6D2 D796 D855 D910 D9C6 DA77 DB24 DBCD DC71 DD10 DDAC DE43 DED6 DF66 DFF0 E077 E0FA E179 E1F4 E26C E2DF E34F E3BA E422 E487
Cut-off frequency [Hz] 8200 8300 8400 8500 8600 8700 8800 8900 9000 9100 9200 9300 9400 9500 9600 9700 9800 9900 10000 10100 10200 10300 10400 10500 10600 10700 10800 10900 11000 E86A E7F6 E781 E70C E696 E61F E5A7 E52F E4B6 E43C E3C1 E346 E2CA E24D E1D0 E152 E0D3 E053 DFD3 DF52 DED0 DE4D DDCA DD45 DCC0 DC3B DBB4 DB2D DAA5 8000
2F2C 3014 30FD 31E8 32D5 33C3 34B2 35A3 3695 3788 387D 3974 3A6C 3B65 3C60 3D5C 3E5A 3F5A 405A 415D 4261 4366 446D 4575 467F 478B 4898 49A6 4AB7 0000
1796 180A 187F 18F4 196A 19E1 1A59 1AD1 1B4A 1BC4 1C3F 1CBA 1D36 1DB3 1E30 1EAE 1F2D 1FAD 202D 20AE 2130 21B3 2236 22BB 2340 23C5 244C 24D3 255B 0000
3CC1 3A93 3867 363B 3410 31E5 2FBB 2D92 2B69 2941 2719 24F2 22CB 20A5 1E7F 1C5A 1A35 1810 15EB 13C7 11A3 0F7F 0D5C 0B38 0915 06F2 04CF 02AC 0089 0000
E4E8 E545 E59E E5F4 E647 E695 E6E1 E729 E76D E7AE E7EC E826 E85D E890 E8C0 E8ED E917 E93D E960 E980 E99C E9B5 E9CB E9DD E9ED E9F9 EA02 EA07 EA0A 0000
Table 8-5-9. Secondary Parameter Table Decimation, 0.707107)
CXD2724AQ-1
Cut-off frequency [Hz] 2600 2700 2800 2900 3000 3100 3200 3300 3400 3500 3600 3700 3800 3900 4000 F4A5 F3EB F32D F26D F1A8 F0E0 F016 EF47 EE76 EDA2 ECCB EBF0 EB13 EA33 E950
16B6 182A 19A5 1B27 1CB0 1E3F 1FD5 2171 2313 24BC 266B 281F 29DA 2B9A 2D60
0B5B 0C15 0CD3 0D93 0E58 0F20 0FEA 10B9 118A 125E 1335 1410 14ED 15CD 16B0
7FDF 7B43 76AD 721C 6D91 690B 648A 600D 5B96 5723 52B3 4E48 49E1 457E 411E
D2B4 D469 D609 D796 D910 DA77 DBCD DD10 DE43 DF66 E077 E179 E26C E34F E422
Cut-off frequency [Hz] 4100 4200 4300 4400 4500 4600 4700 4800 4900 5000 5100 5200 5300 5400 5500 E86A E781 E696 E5A7 E4B6 E3C1 E2CA E1D0 E0D3 DFD3 DED0 DDCA DCC0 DBB4 DAA5 8000
2F2C 30FD 32D5 34B2 3695 387D 3A6C 3C60 3E5A 405A 4261 446D 467F 4898 4AB7 0000
1796 187F 196A 1A59 1B4A 1C3F 1D36 1E30 1F2D 202D 2130 2236 2340 244C 255B 0000
3CC1 3867 3410 2FBB 2B69 2719 22CB 1E7F 1A35 15EB 11A3 0D5C 0915 04CF 0089 0000
E4E8 E59E E647 E6E1 E76D E7EC E85D E8C0 E917 E960 E99C E9CB E9ED EA02 EA0A 0000
Table 8-5-10. Secondary Parameter Table (1/2 Decimation, 0.707107)
Cut-off frequency [Hz] 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 2800 2900 3000 3100 3200 3300 3400 3500 3600 F3EB F2CD F1A8 F07B EF47 EE0D ECCB EB82 EA33 E8DD E781 E61F E4B6 E346 E1D0 E053 DED0 DD45 DBB4 8000
182A 1A65 1CB0 1F09 2171 23E7 266B 28FC 2B9A 2E45 30FD 33C3 3695 3974 3C60 3F5A 4261 4575 4898 0000
0C15 0D33 0E58 0F85 10B9 11F3 1335 147E 15CD 1723 187F 19E1 1B4A 1CBA 1E30 1FAD 2130 22BB 244C 0000
7B43 7464 6D91 66CA 600D 595C 52B3 4C14 457E 3EEF 3867 31E5 2B69 24F2 1E7F 1810 11A3 0B38 04CF 0000
D469 D6D2 D910 DB24 DD10 DED6 E077 E1F4 E34F E487 E59E E695 E76D E826 E8C0 E93D E99C E9DD EA02 0000
Table 8-5-11. Secondary Parameter Table (1/3 Decimation, 0.707107)
CXD2724AQ-1
Delay Time Settings [Relevant data] Coefficients: Ltp0 (81H), Ltp1 (82H), Ltp2 (83H), Ltp3 (84H), Ltp4 (85H), Rtp0 (86H), Rtp1 (87H), Rtp2 (88H), Rtp3 (89H), Rtp4 (8aH), Stp0 (8bH), Stp1 (8cH), Stp2 (8dH), Stp3 (8eH), tp_fb (8fH), ap0_in (90H), ap0_out (91H), ap1_in (92H), ap1_out (93H) Setup: SQA05, SQA04, SQC07, SQC06 First, select decimation, decimation decimation. decimation): SQA11, "00", SQC07, "00" decimation: SQA11, "01", SQC07, "01" decimation: SQA11, "10", SQC07, Don't care) Next, tp_fb (8fH) which determines comb filter delay time, ap0_in (90H), ap0_out (91H), ap1_in (92H) ap1_out (93H) which determine pass filter delay times. following conditions apply. tp_fb, tp_fb 0020H ap0_in ap0_out, ap0_out 0020H ap1_in ap1_out bfe0H Comb filter (Ltp0 Stp3) tp_fb Note) minimum unit above coefficients "0020H". Values larger than this ignored. (7)-1. Comb Filter First, comb filter maximum delay time tp_fb (8fH). coefficient value calculated follows. (Dly) Decimal (Delay [s]) [Hz] (The delay value multiplied during decimation, respectively.) Next delay times comb filter taps, calculate coefficient values same manner tp_fb. tp_fb) Example) maximum delay time 36ms (1/2 decimation, 44100Hz) 0.036 (1/2) 44100 25401.6 Rounding 25402 converting hexadecimal notation: 633aH However, address specified 0020H increments, this becomes: 6340H Therefore, (14) channel taps 6340H less. example, channel settings could Ltp0 1ba0H (10ms) Ltp1 2960H (15ms) Ltp2 3720H (20ms) Ltp3 44e0H (25ms) Ltp4 52c0H (30ms) channels same manner.
CXD2724AQ-1
Setting value 0020H 0040H 3720H 6e40H a560H bf80H bfa0H
Delay 44.1kHz) decimation) 0.022ms 0.045ms 10.000ms 20.000ms 30.000ms 34.739ms 34.761ms decimation 0.045ms 0.090ms 20.000ms 40.000ms 60.000ms 69.478ms 69.523ms decimation 0.068ms 0.136ms 30.000ms 60.000ms 90.000ms 104.217ms 104.285ms
Table 8-5-12. Mode Delay Time Setting Value Examples (7)-2. Pass Filters (APF0, APF1) pass filter delay times determined (read address) (write address 0020H). ap_in ap_out that this subtraction results target delay time setting value. calculation method same that tp_fb. Example) When setting maximum comb filter delay time 36ms splitting remainder evenly between APF0 APF1. (1/2 decimation) (bfe0H 6340H)/2 2e50H address specified 0020H increments, 2e40H used APF0, 2e60H APF1. tp_fb 6340H, ap0_in 6360H, ap0_out 6340H 2e40H 9180H ap1_in 91a0H, ap1_out 9180H 2e60H bfe0H
tp_fb 0000H 36.0ms 6340H
ap0_in
ap0_out
ap1_in
ap1_out
6360H 9180H 16.8ms
91a0H bfe0H 16.8ms
69.6ms (0000H bfe0H)
Fig. 8-5-3. Delay Time Setting Example (1/2 Decimation) Note) Assuming read address 0000H, comb filter delay time "0". However, pass filters delayed sample after reading from delay RAM. Therefore, perfect through operation possible even (write address) (read address).
CXD2724AQ-1
8-6. Bypass Mode this mode, bypassed. used both channels analog-to-analog through status. Setting Bypass Mode uppermost (SQA15) setup register Field "1". other setup data coefficient data "Don't care".
LOUT
ROUT
Fig. 8-6-1. Bypass Mode bypass mode, output after prefilter output after postfilter swtiched analog switch. popping noise occurs switching difference these filter's reference voltages (500mV). Therefore, countermeasure against noise, such system muting, required when using this mode.
CXD2724AQ-1
Appendix Soft Mute condition where final volume coefficient data connected CXD2724Q output each mode 0000H) called "soft mute". (Soft mute cannot applied bypass mode.) Table shows coefficients that should 0000H each mode during soft mute. Table also includes loop input volume coefficients feedback volume coefficients modes which contain feedback loop. Mode name Logic mode Virtual mode Dolby Stereo mode Noise sequencer mode mode Coefficient name (Address [H]) (00), (01), (02), (03), (0e), (0f), (10), (11), (12), KDV1 (21), KDV2 (22), KDV3 (23), KLRm1 (24), KLRm2 (25), KLRm3 (26), (f2), (f3), (f4), (f5), (f6), (f7), (f8) attV (f1), (f2), (f3), (f7), (f8) Same Logic mode Same Logic Virtual mode KLsri (0c), KRsri (0d), (0e), KLod (32), KRod (33), KSod (34), KCod (37) Table Recommended Mute Coefficients
Initialization Although this contains number RAM, there clear function like. Therefore, impossible predict type data existing after power-on. Also, previous mode's data remains even after mode changed, possibly causing momentary noise. these problems cannot handled system mute, apply soft mute time equal maximum delay time delay (varies according mode coefficient settings) during power-on when changing mode. This clears RAM. Example When using 20.0ms passive decoder 14.8ms simple delay line maximum delay time 20.0ms, soft mute must applied continuously 20.0ms. Example When using delay mode with decimation Comb filter delay time 36.0ms pass filter delay time 16.8ms maximum delay time 36.0ms, soft mute must applied 36.0ms.
CXD2724AQ-1
Appendix Compensation Filter This filter compensates shoulder characteristics digital filters. Fig. shows frequency response measured under following conditions. 300mVrms (sine wave) Output level 1kHz filter cut-off 5kHz
Level [dB]
Frequency [Hz] Hosho filter [L-ch] 300mVrms (1kHz sin)
Fig. Compensation Filter Frequency Response (Dotted line: Without compensation filter)
Operation Turn filter each mode except bypass mode using SQA12 setup register Field Setup Register".
Application Circuit
XTAI CXD2500AQ LRCK DA15 DA16 DGND DGND AGND AGND 1000p AGND AGND 100p 330p AGND 100p 5.6k 2200p AGND AGND 8.2k AGND 1.2k 1000p 5.6k 1000p AGND AGND AVS1 100p DGND 0.1µ DGND 330p AGND 0.1µ AGND AGND 3.3k 1000p AGND 330p AGND 330p AGND 100k AGND AGND Lout AGND 100k AGND AGND 0.1µ 8.2k AGND Cout 100k AGND AGND Sout 100k AGND AGND 100k AGND AGND AGND 330p 100k AGND AGND 3.3k AGND 0.1µ 330p Rout DGND DGND DGND DGND 0.1µ 0.1µ Microcomputer AGND
0.1µ
DGND
DGND
VSS5
VSS4
VSS6
VDD1
XS24
XLAT
VSS3
AVS4
AVD4
LRCK
XMST
RVDT
REDY
ROUT AVD2
AVS2 AVD6 AVS6 XSOUT AVSX 1.2k
AGND
CXD2724AQ-1 XTLO AVDX XCOUT AVS5 AVD5 0.1µ AGND
10000p
XTLI
4.7µ
AGND 0.1µ 100k AGND AGND AGND AGND 2200p AGND 100k
0.1µ
VDD2
VSS7
TST2
TST1
CSL1
VSS1
BFOT
VDD0
XRST
VSS0
TST0
TST4
TST3
DGND
CSL2
VSS2
AVS3
AVD3
LOUT AVD1
DGND
XRST
AGND DGND 0.1µ 0.1µ DGND
DGND DGND
AGND AGND
ROUT power supply power supply XSOUT power supply Crystal oscillator circuit power supply XCOUT power supply power supply LOUT power supply Digital power supply
NE5522, containing amplifiers, used operational amplifiers. Take care their combinations. ±12V power supplies operational amplifiers connect 0.1µF bypass capacitors. Daishinku (AT- 33.8688MHz) crystal oscillator. Wiring indicated bold lines should thick, short, shielded around periphery GND. Resistor deviation: ±1%, capacitor deviation:
CXD2724AQ-1
(Especially deviation converter front-stage resistor influence separation when using Logic) phases center surround channels invertedand output. Therefore, sure invert them external amplifier.
Application circuits shown typical examples illustrating operation devices. Sony cannot assume responsibility problems arising these circuits infringement third party patent other right same.
CXD2724AQ-1
Package Outline
Unit:
80PIN (PLASTIC)
23.9 20.0 0.15 0.05 0.15
14.0
17.9
0.05
0.15 0.35
0.35 2.75 0.15
DETAIL
PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 1.6g LEAD TREATMENT LEAD MATERIAL PACKAGE MASS
SONY CODE EIAJ CODE JEDEC CODE
QFP-80P-L01 QFP080-P-1420
16.3

Single-Chip Dolby Logic Surround Decoder Description CXD2724AQ-1

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