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User Manual HVS/UM9704 REVISION HISTORY Version Remarks


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HVS/UM9704
User Manual HVS/UM9704
REVISION HISTORY Version
Remarks
DRAFT; 14.08.96 Update REGs 24,25; 20.08.96 Update REG7: ENA_HWE_ROUGH; 21.08.96 First Release; refers BESIC-SW from V0.34 until V1.0; 31.10.96 (This describes interface BESIC single memory concept PROZONIC concept. first BESIC samples contain this interface. MELZONIC control (SAA4991) possible interface described this document)
Second Release; refers BESIC-SW starting with V2.0; 28.02.97 This document describes interface BESIC including MELZONIC control addition features described first release document. external first BESIC samples will contain this interface. BESIC version, which will developed, contains interface.
HVS/UM9704, 12.12.97, update UM9701 V2.0
Philips Electronics N.V. 1997 rights reserved. Reproduction whole part prohibited without prior written consent copyright owner. information presented this document does form part quotation contract, believed accurate reliable changed without notice. liability will accepted publisher consequence use. Publication thereof does convey imply license under patent- other industrial intellectual property rights.
Register Specification 4977
User Manual HVS/UM9704
HVS/UM9704 Register Specification 4977
Report No.: HVS/UM9704
Keywords BESIC Memory Controller PROZONIC MELZONIC
Date: 12th december, 1997
Register Specification 4977
Preface
User Manual HVS/UM9704
specification describes register interface slave microcontroller (80C51 core), which part BESIC (SAA 4977). described interface refers BESIC software version which implemented first BESIC samples. (see Revision History). This interface will replace future. BESIC videoprocessing providing analog interfacing, video enhancing features, memory controlling embedded 80C51 microprocessor core. slave used interpreter between main (master) Datapath Control BESIC well direct control internal memory controller case field memory concept, also PROZONIC (SAA4990; external) MELZONIC (SAA4991;external).
Register Specification 4977
User Manual HVS/UM9704
Introduction Definitions, Acronyms Abbreviations. References General interface Definition interface Sending data 3.2.1 transmission protocol 3.2.2 register tables 3.2.3 translater register data format 3.2.4 Acknowledgement bytes Receiving data from 3.3.1 Contents status byte 3.3.2 Contents datapath read registers. Timing aspects
Evaluation register data Field memory control modes 4.1.1 Priorities 4.1.2 Field Control modes. AABB Mode Mode Natural Motion (Video Movie) ABAB Movie Mode Satellite Mode Generator Mode (G_Mode) Auto Movie Detection routine Multi-PIP (MPIP) Vertical Zoom Still Picture Mode Non-Interlace Mode INIT 4.1.3 Secondary control commands 4.1.4 Selection Hardware configuration 4.1.5 Datapath translator registers 4.1.6 SNERT interface
Default control settings INDEX.
Register Specification 4977
Introduction
User Manual HVS/UM9704
UM9701 V2.1 describes interface 4977 V1B. software this evaluation samples completed support possible functions described AN97057 97071. mainly supports Melzonic concept. single field concept runs Prozonic concept chosen software. register cannot controlled Prozonic option set. compression modes might show some data failures luminance signal. This problem eliminated supply voltage BESIC reduced 4.2V. sources problems with picture stability occur. above mentioned restrictions solved next version 4977 interface final 4977 described document HVS/CR9705.
Definitions, Acronyms Abbreviations
HOST interface IPQCS MELZONIC
Hexadecimal BESIC Interface towards 8051 microprocessor core Improved Picture Quality Control Software Improved Picture Quality slave microcontroller Line Flicker Reduction median filtering Motion Estimation/compensation, Line flicker reduction, ZOom Noise reduction
MPIP PROZONIC
Multi picture picture with external processor Noise reduction (adaptive) Progressive Scan, Zoom Noise Reduction
References
Philips Semiconductors Software Creation Process V1.0; Wilko Asseldonk, Marc Smet; April 9th, 1996
Tentative Device Specification BESIC; 06.08.96; Kannengiesser Tentative Device Specification Control Part BESIC; 24.06.96; Waterholter
80C51 microcontroller order form 80C51 microcontroller Core Specification V1.2; 22.02.96; Klapproth Datapath Control Register; 13.08.96; Kannengiesser
Register Specification 4977
Application Note, Module, AN97057; Waterholter Application Note, Module, AN97071, Waterholter
User Manual HVS/UM9704
General
reads register bytes from master sends itself status byte plus following read registers whenever addressed with register bytes received written into RAM.
interface Definition interface
interface realized with hardware slave address 68h: Slave address R/W. either slave receiver slave transmitter. slave receiver mode reads register data bytes from main controller which then acts master transmitter. slave transmitter mode sends status information main which works master receiver reading byte information.
3.2.1
Sending data transmission protocol
transmission protocol following format:
Start
Slave address
Subaddress
REG1
REGx
Stop
After having addressed with slave address master transmits subaddress plus following register bytes over number register bytes which transmitted after transmission subaddress free choosable. possible transmit just single register byte after having sent slaveaddress plus subaddress bytes package). acknowledges always register bytes independent their contents. master transmits more than maximum number register bytes, slave will acknowledge following bytes, will store them internal RAM. Subaddresses starting from onwards indicate, that datapath control registers serviced.
Register Specification 4977
3.2.2 register tables
User Manual HVS/UM9704
[Default values brackets]
Table REG1 (FREQUENCY SELECT): Subaddress [00]
Name reserved reserved G_MODE Function cleared cleared normal mode generator mode reserved reserved reserved INIT initialize SAA4977 MELZONIC applied): off, cleared acquisition field frequency (50/60 Hz):
Table REG2 (FIELD CONTROL); Subaddress [01]
reserved reserved MOVIE Forced Movie mode (ABAB raster) PHASE Forced Phase Flag combination with CINE normal mode deg. phase shift (BCBC) Name Function line flicker reduction mode: (AABB mode), (AA*B*B, ABAB raster) cleared
Register Specification 4977
Table REG2 (FIELD CONTROL); Subaddress [01]
Name AUTO_MOVIE Function normal mode
User Manual HVS/UM9704
automatic movie mode activated. case detected movie source, field processing will switch cine(movie) mode correct movie phase will processed (MOVIE, PHASE_FLAG readable STATUS register) still picture mode (one field AABB, full frame median filtered LFR)
Table REG3 (VZOOM): Subaddress [10]
Name VZOOM_0 VZOOM_1 VZOOM_2 VZOOM_3 Function Vertival zoom Vertical zoom Vertical zoom Vertical zoom
Register Specification 4977
Table REG3 (VZOOM): Subaddress [10]
Name Function NATURAL_MOTION Conversion factor reserved 1,25 reserved 1,33 reserved reserved reserved reserved reserved reserved reserved reserved
User Manual HVS/UM9704
Natural Motion Natural Motion aktiv
SAT_MODE
cleared Satellite Mode (removes wiping dots) (LFR, AABB, AUTO_MOVIE CINE mode active) (LFR, AABB, AUTO_MOVIE CINE active)
VZOOM
Vertical Zoom mode active Vertical Zoom mode active
Register Specification 4977
User Manual HVS/UM9704
Table REG4 (External Multi PIP): Subaddress [00]
NPIP MPIP SPIP Name POS0 POS1 POS2 POS3 Function position position position position cleared number PIP's: PIP's, PIP's External Multi-PIP: off, NTSC PIP: PIP,
Table REG5 (NR, SCREEN FADE): Subaddress [02]
Name Function noise reduction noise reduction SPS0 SPS1 noise reduction middle high
split screen split screen SPS1 SPS0 split screen horizontal vertical
SCF0
screen fade
Register Specification 4977
User Manual HVS/UM9704
Table REG5 (NR, SCREEN FADE): Subaddress [02]
Name SCF1 Function screen fade SCF1 reserved cleared SCF0 screen fade fade fade
Table REG6 (ENABLE DIRECT REG. ACCESS): Subaddress [00]
Name SET_HOR_DEL Function normal mode (HOR_DELAYS=0) HOR_DELAYS value taken from REG12 (direct PROZONIC/ MELZONIC access). SET_HWE SET_HRE SET_HDDEL normal mode take HWESTA/STO settings from REGs normal mode take HRESTA/STO settings from REGs normal mode take HDDEL setting from REG17 SET_HDMSB normal mode take HDMSB setting from REG18 SET_VDMSB normal mode take VDMSB setting from REG19 SET_HBDA normal mode HBDASTA/STO values direct REGs SET_HWE_MAIN_ DELAY normal mode main delay
Register Specification 4977
User Manual HVS/UM9704
Table REG7: Subaddress [00]
Name SET_HBOX Function default mode direct control HBOX_START/STOP REGs SET_VBDA cleared clerared default mode direct VBDASTA/STO REGs SET_HDAV cleared cleared default direct HDAVSTA/STO control REGs cleared
Table REG8 (VWE DELAY): Subaddress [00]
Name VWED0 VWED1 VWED2 VWED3 VWED4 VWED5 VWED6 VWEX Function delay delay delay delay delay delay delay off, normal mode reduced vertical write window shiftable VWED0.D6
Register Specification 4977
User Manual HVS/UM9704
Table REG9 (Test-REG: BLANK FIELDS): Subaddress [80]
Name BLANK_F0 BLANK_F1 BLANK_F2 BLANK_F3 reserved Function blank field blank field blank field blank field
Table REG10: Subaddress [00]
DIGITAL_COLOR_ DECODER_ CONCEPT CLR_MOVIE Name Function cleared cleared cleared cleared Analog color decoder concept Digital color decoder concept (internal acquisition switched off; external clock, line locked expected) default mode clear AUTO_MOVIE flag (forced) NPIP_4x4 PIP, take NPIP cleared
Register Specification 4977
User Manual HVS/UM9704
Table REG11 (Port Settings): Subaddress [30]
Name Function clear port P1.1 port P1.1 clear port P1.2 port P1.2 clear port P1.4 port P1.4 clear port P1.5 port P1.5 MELZ_PROZ Software selection, only valid SW_HW=1 PROZONIC MELZONIC SW_HW enable software selection between PROZONIC/MELZONIC Hardware selection P1.3 Software selection with MELZ_PROZ reserved cleared
Table Register REG12 (HOR_DELAYS): Subaddress [28]
Name IN_DEL HD_DEL (Prozonic) WE_HDEL (Melzonic) WE2_DEL (Prozonic) RE_HDEL (Melzonic) Function input luminance delay clock shift hor. reference clock shift output signal clock shift output signal clock shift output signals reserved
Register Specification 4977
User Manual HVS/UM9704
Table Register REG13 (HWESTA): Subaddress [xx]
Name HWESTA Function start value horizontal write enable (lower bits)
Table Register REG14 (HWESTO): Subaddress [xx]
Name HWESTO Function stop value horizontal write enable (lower bits)
Table Register REG15 (HRESTA): Subaddress [1F]
Name HRESTA Function start value horizontal read enable (lower bits)
Table Register REG16 (HRESTO): Subaddress [C3]
Name HRESTO Function stop value horizontal read enable (lower bits)
Table Register REG17 (HDDEL): Subaddress [00]
Name Function
HDDEL: horizontal fine delay 4977 display signals HDAV_DEL fine delay HDAV additional delay signal delayed display clock
Register Specification 4977
Table Register REG17 (HDDEL): Subaddress [00]
Name HBDA_DEL Function fine delay HBDA additional delay signal delayed display clock HRE_DEL fine delay additional delay signal delayed display clock HBLND_DEL fine delay HBLND additional delay signal delayed display clock
User Manual HVS/UM9704
Table Register REG18 (HDMSB): Subaddress [AA]
Name HDMSB Function HDAVSTA HDAVSTO HBDASTA HBDASTO HRESTA HRESTO HBLNDSTA HBLNDSTO
Register Specification 4977
User Manual HVS/UM9704
Table Register REG19 (VDMSB): Subaddress [0A]
Name VDMSB Function cleared VBDASTA VBDASTO reserved
Table Register REG20 (HBDASTA): Subaddress [52]
Name HBDASTA Function start value horizontal blanking (lower bits)
Table Register REG21 (HBDASTO): Subaddress [F2]
Name HBDASTO Function stop value horizontal blanking (lower bits)
Table Register REG22 (HWE MAIN DELAY): Subaddress [32]
Name HWE_MAIN_DELAY Function horizontal shift signal
Register Specification 4977
User Manual HVS/UM9704
Table Register REG23 Subaddress [xx]
Name reserved Function
Table Register REG24: Subaddress [xx]
Name reserved Function
Table Register REG25 (HDAVSTA): Subaddress [05]
Name HDAVSTA Function start value gating signal chrominance display data (lower bits)
Table Register REG26 (HDAVSTO): Subaddress [A9]
Name HDAVSTO Function stop value gating signal chrominance display data (lower bits)
Table Register REG27 Subaddress [xx]
Name reserved Function
Register Specification 4977
User Manual HVS/UM9704
Table Register REG28 Subaddress [xx]
Name reserved Function
Table Register REG29 (VBDASTA): Subaddress [15]
Name VBDASTA Function start value vertical blanking (lower bits)
Table Register REG30 (VBDASTO): Subaddress [31]
Name VBDASTO Function stop value vertical blanking (lower bits)
Table Register REG31 (HBOX_START): Subaddress [00]
Name HBOX_START Function direct PROZONIC/MELZONIC register access
Table Register REG32 (HBOX_STOP): Subaddress [00]
Name HBOX_STOP Function direct PROZONIC/MELZONIC register access
Register Specification 4977
User Manual HVS/UM9704
Table Register REG33: Subaddress [xx]
Name reserved Function
Table Register REG34: Subaddress [xx]
Name reserved Function
3.2.3
translater register data format
Next subaddress following registers will
Acquisition part:
Table Translater Register (ACQ_0): Subaddress
Name Host address (hex) AGC_Y 0150 Default value (hex) gain channel complement dB): upper bits Function
Table Translater Register (ACQ_1): Subaddress
Name Host address (hex) AGC_UV 0151 Default value (hex) gain channel complement dB): upper bits Function
Register Specification 4977
User Manual HVS/UM9704
Table Translater Register (ACQ_2): Subaddress
Name Host address (hex) AGC_Y_LSB AGC_UV_LSB standby_f aaf_bypass 0152 Default value (hex) gain channel gain channel frontend standby mode bypass prefilter reserved reserved reserved reserved Function
Register Specification 4977
User Manual HVS/UM9704
Table Translater Register (ACQ_3): Subaddress
Name Host address (hex) UVclcorrect_mode 0153 Default value (hex) Bit1 Uclcorrect_fval Bit2 Vclcorrect_fval Bit2 Bit0 Bit1 Bit1 clamp mode auto fixed keep Bit0 Bit0 fixed value clamp corr. channel fixed value clamp corr. channel Function
Register Specification 4977
User Manual HVS/UM9704
Table Translater Register (ACQ_4): Subaddress
Name Host address (hex) UVcoring 0154 Default value (hex) Bit1 mff_width Bit1 UVcl_tau Bit1 compress Bit0 Bit0 Bit0 coring level majority filter setting vertical filtering measured clamp Function
compression compression
comp_mode
14:9 compression mode 16:9 compression mode
Register Specification 4977
User Manual HVS/UM9704
Table Translater Register (ACQ_5): Subaddress
Name Host address (hex) ydelay 0155 Default value (hex) Bit2 overl_comp Bit1 fill_mem Bit1 Bit0 Bit0 variable Y-delay Function
overload threshold
default fill memory with constant value
reserved reserved
Register Specification 4977 Display part:
Table Translater Register (DCTI_0): Subaddress
Name Host address (hex) dcti_gain 01D1 Default value (hex) Bit2 dcti_threshold dcti_ddx_sel 0000 Bit1 Bit0 Function
User Manual HVS/UM9704
dcti gain
DCTI threshold (0,1,2,.,14,15) DCTI ddx_sel high
Table Translater Register (DCTI_1): Subaddress
Name Host address (hex) dcti limit 01D2 Default value (hex) Bit1 dcti_separate Bit0 DCTI limit Function
Register Specification 4977
Table Translater Register (DCTI_1): Subaddress
Name Host address (hex) dcti_protection Default value (hex) dcti_filteron dcti_superhill nrln_0 Function
User Manual HVS/UM9704
DCTI number lines LSBs)
Table Translater Register (DCTI_2): Subaddress
Name Host address (hex) nrln_1 01D3 Default value (hex) DCTI number lines upper bits Function
Table Translater Register (DCTI_3): Subaddress
Name Host address (hex) nrpx 01D4 Default value (hex) DCTI number pixels Function
Register Specification 4977
User Manual HVS/UM9704
Table Translater Register (SIDEP_OVL_UV): Subaddress
Name Host address (hex) overlay_u overlay_v 01D5 Default value (hex) 1000 1000 sidepanels overlay sidepanels overlay Function
Table Translater Register (SIDEP_OVL_Y): Subaddress
Name Host address (hex) overlay_y 01D6 Default value (hex) sidepanels overlay Function
Register Specification 4977
User Manual HVS/UM9704
Table Translater Register (PEAKING): Subaddress
Name Host address (hex) peak_a 01D7 Default value (hex) Bit1 peak_b Bit1 peak_limit Bit1 peak_coring Bit1 Bit0 Bit0 Bit0 Bit0 peaking peaking peak limiter setting peak coring settings Function
peaking function will improved next 4977 version.
Table Translater Register (SIDEP_START) Subaddress
Name Host address (hex) sidepanel_start 01D8 Default value (hex) sidepanel start position MSB) Function
Register Specification 4977
User Manual HVS/UM9704
Table Translater Register (SIDEP_STOP): Subaddress
Name Host address (hex) sidepanel_stop 01D9 Default value (hex) sidepanels stop position MSB) Function
Table Translater Register (SIDEP_FDEL): Subaddress
Name Host address (hex) sidepanel_fdel 01DAh Default value (hex) Bit1 display_mode Bit0 sidepanel fine delay Function
display mode bit, blanking level bit, blanking level
reserved reserved reserved reserved reserved
register, subaddress only controlled Melzonic mode (subaddress hex, MELZ_PROZ
3.2.4
Acknowledgement bytes
acknowledges always register bytes independent from their contents. master transmits more than maximum number register bytes, slave will acknowledge following bytes, will store them internal RAM.
Register Specification 4977
Receiving data from
User Manual HVS/UM9704
able transmit status byte plus additional read bytes main then works slave transmitter.
transmission protocol transmitting status byte plus read registers following format:
Start
Slave address
Status byte ReadReg1
Nack
Stop
3.3.1
Contents status byte
status byte contains following information:
Table Read Register (STATUS): Subaddress
Name Default value (hex) NON_IL interlaced mode active interlaced mode active AUTO_MOVIE_FLAG reserved normal mode automatic movie mode activated MOVIE movie mode detected movie detected PHASE_FLAG standard mode (ABAB case MOVIE=1) 180° phase shift (BCBC, MOVIE=1) PORT setting read from port P2.4 P2.4 P2.4 READY ready accept command ready accept command WATCH Watchdog bit: will toggled when status byte read master initialized with Function
Register Specification 4977
User Manual HVS/UM9704
will cleared after received register bytes. will again after evaluation bytes completed external interrupt (V100) initiating data transfer from ECO5, datapath additional registers, PROZONIC/MELZONIC currently serviced.
3.3.2
Contents datapath read registers
Table Read Register (MPD MSByte1): Subaddress
Name MOVIE_PHASE_A Function direct PROZONIC register read, MSByte; Movie phase detection byte
Table Read Register (MPD MSByte2): Subaddress
Name MOVIE_PHASE_B Function direct PROZONIC register read, MSByte; Movie phase detection byte
Table Read Register (read_Uclerror): Subaddress
Name Host address (hex) 0170 Function (NOT IMPLEMENTED !!!)
read_Uclerror
Read channel clamp error (+3/-4 resolution 1/16 LSB) reserved
Table Read Register (read_Vclerror): Subaddress
Name Host address (hex) 0171 Function (NOT IMPLEMENTED !!!)
read_Vclerror
Read channel clamp error (+3/-4 resolution 1/16 LSB)
Register Specification 4977
Table Read Register (read_Vclerror): Subaddress
Name Host address (hex)
User Manual HVS/UM9704
Function (NOT IMPLEMENTED !!!)
reserved
Table Read Register (read_Ygain): Subaddress
Name Host address (hex) 0172 Function (NOT IMPLEMENTED !!!)
read_Ygain
Read overflow indication channel
Table Read Register (AGC_Y_read): Subaddress
Name Host address (hex) 0173 Function (NOT IMPLEMENTED !!!)
AGC_Y_read
gain channel, upper bits (for functional test only)
Timing aspects
maximum allowed response time between accepting register bytes execution commands handled This time only relevant when field memory control modes changed. Field memory control modes are: Cine, LFR, Still, Multi-PIP mode. When field memory control mode been activated, waits max. until frame starts mode 100Hz field repetition time). Then takes another until frame been completely transmitted order mode. maximum allowed total clock stretch time within message minimum wait time between sending register data packages varies from field memory control modes have changed) (field memory control modes have changed). user wants make sure that complete register data package transmitted without being interrupted VDFL routine slave free after master transmits data, data package should transmitted between after VDFL occured. slave sets status byte when ready accept commands.
Register Specification 4977
Multi-PIP:
User Manual HVS/UM9704
time between live picture register command another should shorter than Screen fade: long this mode active fields normal mode), other mode changes ignored.
Evaluation register data
evaluation register data done with respect certain priority structure. following sections certain restrictions settings register bytes which limit possibilities combining field memory control modes (Cine, LFR, Still, Multi-PIP mode) and/or secondary control commands listed. There different application concepts BESIC, which taken into account: MELZONIC concept: field memory concept with Natural Motion (Movement Estimation Compensation), LFR, Adaptive External Multi PROZONIC concept: field memory concept with LFR, Adaptive External Multi Single memory concept: simple AABB processing functions which related only concepts, indicated.
Register Specification 4977
4.1.1 Field memory control modes Priorities
User Manual HVS/UM9704
different Field Control Modes module have different priorities. following table shows which mode highest which mode lowest priority. priority structure must taken into account when activating field control modes.
Table Mode Priorities Mode
INIT SCREEN FADE (not implemented) MPIP VZOOM GENERATOR mode FEATURE mode NON_IL mode Natural Motion (MELZONIC concept) mode (MELZONIC/PROZONIC concept) AABB mode lowest
Priority
highest
4.1.2
Field Control modes
AABB Mode
Software control: Mode with lowest priority (all other field control bits switched off). AABB mode most simple conversion mode Only field memory implemented. video data incoming field simply doubled AABB sequence. low-end concept this mode default conversion mode. This mode also used PROZONIC MELZONIC concept. mode even work correctly PROZONIC MELZONIC removed. This demand means that vertical display read control realized memory controller part 4977 control external processing ICs. live AABB mode DR-Bit toggled field field generate AABB raster with field length sequence 313, 312.5, 312.5 lines.
Mode
Software Control: subaddress (LFR) Line Flicker Reduction (LFR) mode default control mode PROZONIC concept used with MELZONIC well. makes medianfilter generate output sequence: original field medianfiltered medianfiltered original field
Register Specification 4977
Natural Motion (Video Movie)
Software Control: subaddress (NATURAL_MOTION)
User Manual HVS/UM9704
This function only realized high-end Melzonic concept. MELZONIC will compensate movement artefacts which caused e.g. simple field doubling mode. video sources with motion resolution constant motion calculated vector based motion estimation compensation. movie sources which have motion resolution only MELZONIC able increase motion frequency This provides remarkable improvement display movies even compared standard TVs. recursive block matching algorithm implemented 4991. Beside simple field control these natural motion modes software check quality motion compensation. 4977 reads MELZONIC register NR_BAD_RANGES. This register will compared with constant threshold value BAD_LIMIT. NR_BAD_RANGES greater than BAD_LIMIT Natural Motion Mode will disabled, even NATURAL_MOTION equals conversion mode will switched into mode, which would have been chosen NATURAL_MOTION cleared (fallback mode). control mode with lower priority, which vector based processing performed. mentioned above natural motion processing adapted motion resolution source. this requirement necessary detect movie video source motion compensated. correct mode (video movie processing) controlled user himself automatic routine (see AUTO_MOVIE).
ABAB Movie Mode
Software Control: subaddress (MOVIE), NATURAL_MOTION cleared This mode supported PROZONIC MELZONIC approach. converter performs frame repetition. phase relation between movie pictures incoming video signal standardized. additional control PHASE subaddress processing into correct phase relation incoming movie (ABAB BCBC).
Satellite Mode
Software Control: subaddress (SAT_MODE) satellite mode four display fields derived from output median filter. median filter will filter details occurring only line. This fact used attenuate typical noise dropouts which normally occur uncorrelated field. satellite signal reception improved quite effectively this mode without deteriorating picture quality.
Generator Mode (G_Mode)
Software Control: subaddress 2(G_MODE) G_MODE activates stable display with fixed field length 312.5 lines AFF=0 262.5 lines AFF=1. display field length adapted according video source. conversion mode reduced single field repetition mode (AAAA). This special mode used stable picture without source with very noisy source. does also improve picture stability tuner channel search.
Auto Movie Detection routine
Software Control: subaddress (AUTO_MOVIE) Auto Movie Detection Melzonic concept
Register Specification 4977
User Manual HVS/UM9704
AUTO_MOVIE activates automatic movie source detection natural motion mode switched detection based read values Melzonic registers "vector_sum". This vector absolutes represents amount motion found between incoming fields. software investigates vector sums whole frame detect whether video movie source connected. values show large difference converter switched vector based movie processing increasing movement resolution from annoying motion judder movies eliminated. phase relation between movie pictures video fields taken into account. case video source scenes with small motion video processing active, increasing movement resolution from This removes unsharpness moving edges compared simple field repetition converter. AUTO_MOVIE zero, converter performing motion compensation processing video sources long MOVIE cleared. MOVIE movie motion compensation activated. phase relation incoming movie adapted control MOVIE_PHASE. user able adapt natural motion processing source bits MOVIE MOVIE_PHASE himself automatic movie detection routine been switched off. Auto Movie Detection Prozonic concept (not implemented 4977 V1B) AUTO_MOVIE Prozonic concept same routine descibed above will investigate whether movie source applied which phase relation transmitted. software uses Prozonic read register motion information which based vector absolute differences luminance channel. With Prozonic movie detection used activate movie mode. sequence AA*B*B adapted phase movie switched BB*C*C processing automatically. This results improved performance vertical rolling titles. time constant Auto Movie routine increased compared Melzonic approach. There need fast detection because severe artefacts occur detection delay.
Multi-PIP (MPIP)
Software Control: subaddress (MPIP) field memories converter used generate MPIP picture MPIP set. assumed that contains Module which generates compressed picture bottom right side screen. picture supplied module written into field memories placed according chosen position MPIP control subaddress POS0-POS3). complete MPIP picture shows small pictures. those display live source, others frozen. With control SPIP register subaddress window adapted source. vertical size window reduced SPIP set.The MPIP feature makes boxing function Prozonic Melzonic. noise reduction circuitry (k-factor control) together with defined boxes support function. MPIP feature used channel overview show frozen motion phases channel (photo finish).
Vertical Zoom
Software Control: subaddress (VZOOM_0 VZOOM_3, VZOOM, vertical zoom function realized interpolation lines activated control VZOOM. zoom factor defined bits VZOOM_0 VZOOM_3. factors 1.1, 1.25, 1.33 supported control software. zoom function combined with natural motion feature (video movie source). AABB mode chosen together with vertical zoom software switches automatically processing.
Still Picture Mode
Software Control Register subaddress 7(STP)
Register Specification 4977
User Manual HVS/UM9704
Still Picture function combined with every conversion mode. modes Natural Motion frozen picture processed based frame displaying original field median filtered AABB mode, MPIP, Mode Generator Mode only field still picture generated.
Non-Interlace Mode
Software Control: control non-interlace source detected software field processing switches automatically into NonInterlace Mode. detection criteria field length which complete lines. memory controller counts half lines starting with zero non-interlace source will field length read register (PAL standard hex, NTSC standard hex). non-interlace source additionally indicated status read register (NON_IL).
INIT
Software Control Register subaddress (INIT) Init 4977 module will initialized with default values. module initialized Melzonic concept natural motion mode with AUTO_MOVIE=1. Furthermore 4977 initialized digital colour deccoder mode. this reason picture will appear disturbed analog concept after initialization been done.
Register Specification 4977
4.1.3 Secondary control commands
User Manual HVS/UM9704
secondary control commands combined with above described field control modes
Acquisition Field Frequency selection (AFF)
Software Control Register subaddress 4(AFF) user according vertical frequency incoming source. case source cleared, sources set. vertical writing window adapted (VWE1STA VWE1STO). also changes reference field length feature mode detection. generator mode field length 312.5 lines AFF=0 262.5 lines AFF=1.
Horizontal Compression
Software Control: directly supported 4977 supports different compression modes 14:9 16:9 display modes (1.17 1.33). These modes activated datapath register subaddress bits Additionally correct setting horizontal memory controller settings done (see control table chapter
Noise reduction
Software Control: subaddress (NR0, NR1) recursive noise reduction three levels (low, medium, high). investigation purposes direct control PROZONIC/MELZONIC noise reduction registers possible.
Split Screen
Software Control: subaddress Bits (SPS0, SPS1) screen split into halves Split Screen feature. half showing noise reduced picture other performance original source. splitting done horizontal vertical direction. mode allows direct comparison original noise reduced picture screen.
Screen fade
Software Control: subaddress (SCF0, SCF1) screen fade feature used "fade out" picture like closing curtains. This done control continuously changing setting side panel start stop values 4977 until homogenous coloured picture visible. function also available other round where picture "faded starting from complete display.
Delay
Software Control: subaddress (SET_HWE_MAIN_DELAY), subaddress (HWE_MAIN_DELAY) horizontal writing window delayed register HWE_MAIN_DELAY control SET_HWE_MAIN_DELAY set.
Register Specification 4977
Delay
Software Control: subaddress 07,bits VWE1D0 VWE1D6 VWEX
User Manual HVS/UM9704
vertical writing window delayed steps lines register Delay register VWEX set. possible delay range to127 lines. delay function needed centre vertical zoomed picture.
Blank Field Mode
Software Control: subaddress bits 0-3, (BLANK_F0 BLANK_F3) Blank Field Mode allows user define which fields sequence display fields displayed blanked. four control bits cleared normal active display appears. corresponding display field will blanked. AABB mode blanking every second field generates display which similar normal screen. elimination large area flicker demonstrated switching from this mode normal display. blank field mode normally used testing purposes.
Selection Colour Decoder Concept
Software Control: subaddress (DIGITAL_COLOR_DECODER_CONCEPT) Normally 4977 implemented concept with analog colour decoder. this case acquisition Colour_Decoder_Concept) acquisition clock supplied from external. digital data directly into first field memory. From point software control horizontal acquisition register values have divided factor two. analog frontend part 4977 should switched into stand-by mode.
Port Control
Software Control: subaddress hex, free port pins µ-Controller core 4977 controlled bus. polarity port pins switched synchronized VDFL this means synchronized display. port pins P1.1, P1.2, P1.4 P1.5 controlled.
Direct control PROZONIC/MELZONIC register HOR_DEL
Software Control: subaddress (SET_ HOR_DEL) control SET_HOR_DEL direct control PROZONIC/MELZONIC register HOR_DELAY enabled (see Prozonic/Melzonic data sheet) register subaddress hex. This register allows fine delay Prozonic/Melzonic memory control output signals with clock accuracy. further more allows adjustment chrominance reformatting correct internal chroma processing. correct setup should checked with noise reduction switched
Direct control PROZONIC/MELZONIC register HBOX_START/STOP
Software Control: subaddress (SET_ HBOX) control SET_HBOX direct control PROZONIC/MELZONIC registers HBOXSTART HBOXSTOP enabled (see Prozonic/Melzonic data sheet) registers subaddress hex. settings used split screen function Multi PIP.
Register Specification 4977
Direct change memory controller settings 4977
User Manual HVS/UM9704
enable bits most important signals memory controller defined user. This allows very flexible 4977 also changed conditions application. Many signals values. signal switched direct user control corresponding registers signal start stop values enabled. These registers define lower complete values. MSBs defined additional register which enabled necessary.
blanking control
Software Control: subaddress (SET_VBDA), subaddress (SET_HBDA) SET_VBDA enables direct control vertical blanking time 4977 registers subaddress (VBDASTA, start value) subaddress (VBDASTO, stop value). sensible programming range VBDA depends field length source (PAL hex, NTSC hex). programmed values higher than number lines source (VCR fast forward) memory controller stops signal automatically. horizontal signal part blanking controlled same way. SET_HBDA enables direct control horizontal blanking time registers subaddress (HBDASTA, start value) subaddress (HBDASTO, stop value). programming range HBDA hex. programming step width display clocks. signal refers rising edge HDFL signal. MSBs start stop values controlled additional registers (see chapter control). Normally user does have change settings long small changes done compared default settings.
control
Software Control: subaddress hex, (SET_HWE) control SET_HWE direct control horizontal write enable signal first field memory enabled. start value defined register subaddress (HWESTA). stop value defined register subaddress (HWESTO). HWESTA/STO values values. Only lower bits changed user. programming steps have clock accuracy acquisition clock. signal refers rising edge horizontal reference 4977 (HA, 22).
control
Software Control: subaddress hex, (SET_HRE) control SET_HRE direct control horizontal read enable signal PROZONIC, MELZONIC first field memory single field concept enabled. start value defined register subaddress (HRESTA). stop value defined register subaddress (HRESTO). MSBs controlled register HDMSB (see chapter control).
HDAV control
Software Control: subaddress hex, (SET_HDAV) control SET_HDAV enables direct control horizontal display signal HDAV (Horizontal Data Valid Chrominance). signal gates chrominance display signals. wrong setting results partly uncoulored picture. start value defined register subaddress (HDAVSTA). stop value defined register subaddress (HDAVSTO). signal refers rising edge HRDFL.
Register Specification 4977
HDDEL control
Software Control: subaddress hex, (SET_HDDEL)
User Manual HVS/UM9704
direct control memory controller register HDDEL register subaddress enabled control SET_HDDEL set. register HDDEL defines fine delay horizontal output signals 4977 with display clock accuracy. delay adjustment necessary changes concept ensure correct processing colour difference signals which coded serial format (4:1:1). Every signal shifted clock none.
HDMSB control
Software Control: subaddress hex, (SET_HDMSB) SET_HDMSB memory controller register HDMSB directly controlled subaddress hex. contains MSBs start stop values display related horizontal control signals. detailes definition register bits described table.
VDMSB control
Software Control: subaddress hex, (SET_VDMSB) SET_VDMSB memory controller register VDMSB directly controlled subaddress hex. contains MSBs start stop values display related vertical control signals. detailes definition register bits described table.
4.1.4
Selection Hardware configuration
Software Control: subaddress hex, (MELZ_PROZ), bit5 (SW_HW) hardware configuration selected port P1.3 control SW_HW cleared. case P1.3 level Prozonic single field concept chosen. P1.3 high level Melzonic concept active. control SW_HW concept determined control MELZ_PROZ. MELZ_PROZ cleared Prozonic single field concept chosen. MELZ_PROZ Melzonic concept active.
4.1.5
Datapath translator registers
Software Control: subaddress registers with subaddress 4977 datapath registers directly accessed. datapath registers initialized after power-on changed other routines than bus. detailed functional description datapath please refer application notes AN97057 AN97071.
4.1.6
SNERT interface
SNERT interface register data PROZONIC, MELZONIC LIMERIC dependant chosen hardware configuration transmitted. internal SNERT pins Core SAA4977 directly connected pins SAA4977 V1C.
Register Specification 4977
Default control settings
User Manual HVS/UM9704
Table Default settings
reg. subaddr. (hex) Single field concept standard comp. 1.10 comp. 1.33 Prozonic concept standard comp. 1.10 comp. 1.33 Melzonic concept standard comp. 1.10 comp. 1.33
Register Specification 4977
Table Default settings
reg. subaddr. (hex) Single field concept standard comp. 1.10 comp. 1.33 Prozonic concept standard comp. 1.10 comp. 1.33
User Manual HVS/UM9704
Melzonic concept standard comp. 1.10 comp. 1.33
Register Specification 4977
INDEX
User Manual HVS/UM9704
aaf_bypass ACQ_0 ACQ_1 ACQ_2 ACQ_3 ACQ_4 ACQ_5 AGC_UV AGC_UV_LSB AGC_Y AGC_Y_LSB AGC_Y_read AUTO_MOVIE AUTO_MOVIE_FLAG BLANK FIELDS comp_mode compress dcti limit DCTI_0 DCTI_1 DCTI_2 DCTI_3 dcti_ddx_sel dcti_filteron dcti_gain dcti_protection dcti_separate dcti_superhill dcti_threshold display_mode ENABLE DIRECT REGISTER ACCESS External Multi
Register Specification 4977
User Manual HVS/UM9704
FIELD CONTROL Field memory control modes field memory control modes fill_mem FREQUENCY SELECT HBDASTA HBDASTO HDDEL HDMSB HOR_DELAYS HRESTA HRESTO MAIN DELAY INIT mff_width MOVIE MOVIE_PHASE MSByte1 MPIP Multi-PIP NON_IL NPIP nrln nrln_1 nrpx overl_comp overlay_u overlay_v overlay_y
Register Specification 4977
User Manual HVS/UM9704
peak_a peak_b peak_coring peak_limit PEAKING PHASE PHASE_FLAG PORT Port Settings read_Uclerror read_Vclerror read_Ygain READY Receiving data SAT_MODE SCREEN FADE Screen fade SET_HBDA SET_HBOX SET_HDAV SET_HDDEL SET_HDMSB SET_HOR_DEL SET_HRE SET_HWE_MAIN_DELAY SET_VDMSB SIDEP_FDEL SIDEP_OVL_UV SIDEP_OVL_Y SIDEP_START sidepanel_fdel sidepanel_start sidepanel_stop SPIP standby_f STATUS
Register Specification 4977
User Manual HVS/UM9704
Timing Uclcorrect_fval UVcl_tau UVclcorrect_mode UVcoring VAMSB Vclcorrect_fval VDMSB VWE1 DELAY VZOOM WATCH ydelay

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