P89LPC933/934/935/936 User manual Rev. March 2005 User manual
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UM10116
P89LPC933/934/935/936 User manual
Rev. March 2005 User manual
Document information Info Keywords Abstract Content P89LPC933/934/935/936 Technical information P89LPC933/934/935/936 devices.
Philips Semiconductors
UM10116
P89LPC933/934/935/936 User manual
Revision history Date 20050304 Description Initial version
Koninklijke Philips Electronics N.V. 2004. rights reserved.
User manual
Rev. March 2005
Philips Semiconductors
UM10116
P89LPC933/934/935/936 User manual
Introduction
P89LPC933/934/935/936 single-chip microcontrollers designed applications demanding high-integration, cost solutions over wide range performance requirements. P89LPC933/934/935/936 based high performance processor architecture that executes instructions four clocks, times rate standard 80C51 devices. Many system-level functions have been incorporated into P89LPC933/934/935/936 order reduce component count, board space, system cost.
Product comparison overview
Table highlights differences between four devices.
Table Device P89LPC933 P89LPC934 P89LPC935 P89LPC936 Product comparison overview Flash memory Sector size ADC1 ADC0 Data EEPROM
configuration
P2.0/DAC0 P2.1 P0.0/CMP2/KBI0 P1.7 P1.6 P1.5/RST P3.1/XTAL1 P3.0/XTAL2/CLKOUT
P2.7 P2.6 P0.1/CIN2B/KBI1/AD10 P0.2/CIN2A/KBI2/AD11 P0.3/CIN1B/KBI3/AD12 P0.4/CIN1A/KBI4/DAC1/AD13 P0.5/CMPREF/KBI5 P0.6/CMP1/KBI6 P0.7/T1/KBI7 P1.0/TXD P1.1/RXD P2.5/SPICLK P2.4/SS
002aab071
P89LPC933FDH P89LPC934FDH
P1.4/INT1 P1.3/INT0/SDA P1.2/T0/SCL P2.2/MOSI P2.3/MISO
P89LPC933/934 TSSOP28 configuration.
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UM10116
P89LPC933/934/935/936 User manual
P2.0/ICB/DAC0/AD03 P2.1/OCD/AD02 P0.0/CMP2/KBI0/AD01 P1.7/OCC/AD00 P1.6/OCB P1.5/RST P3.1/XTAL1 P3.0/XTAL2/CLKOUT
P2.7/ICA P2.6/OCA P0.1/CIN2B/KBI1/AD10 P0.2/CIN2A/KBI2/AD11 P0.3/CIN1B/KBI3/AD12 P0.4/CIN1A/KBI4/DAC1/AD13 P0.5/CMPREF/KBI5 P0.6/CMP1/KBI6 P0.7/T1/KBI7 P1.0/TXD P1.1/RXD P2.5/SPICLK P2.4/SS
002aab072
P89LPC935FDH P89LPC936FDH
P1.4/INT1 P1.3/INT0/SDA P1.2/T0/SCL P2.2/MOSI P2.3/MISO
P89LPC935/936 TSSOP28 configuration.
P2.7/ICA
P2.6/OCA
P0.1/CIN2B/KBI1/AD10 P0.2/CIN2A/KBI2/AD11 P0.3/CIN1B/KBI3/AD12 P0.4/CIN1A/KBI4/DAC1/AD13 P0.5/CMPREF/KBI5 P0.6/CMP1/KBI6 P0.7/T1/KBI7 P1.0/TXD
002aab074
P0.0/CMP2/KBI0/AD01
P1.6/OCB P1.5/RST P3.1/XTAL1 P3.0/XTAL2/CLKOUT
P1.4/INT1 P1.3/INT0/SDA P2.5/SPICLK P1.2/T0/SCL P2.2/MOSI P2.3/MISO P1.1/RXD P2.4/SS
P89LPC935 PLCC28 configuration.
P89LPC935FA
P2.0/ICB/DAC0/AD03
P1.7/OCC/AD00
P2.1/OCD/AD02
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UM10116
P89LPC933/934/935/936 User manual
terminal index area
P1.6/OCB P1.5/RST P3.1/XTAL1 P3.0/XTAL2/CLKOUT P1.4/INT1 P1.3/INT0/SDA
P2.3/MISO P2.4/SS P2.5/SPICLK P1.1/RXD P1.0/TXD
P0.1/CIN2B/KBI1/AD10 P0.2/CIN2A/KBI2/AD11 P0.3/CIN1B/KBI3/AD12 P0.4/CIN1A/KBI4/DAC1/AD13
P0.0/CMP2/KBI0/AD01
P2.0/ICB/DAC0/AD03
P1.7/OCC/AD00
P2.1/OCD/AD02
P89LPC935FHN
P2.6/OCA
P2.7/ICA
P0.5/CMPREF/KBI5
P0.6/CMP1/KBI6 P0.7/T1/KBI7
P1.2/T0/SCL
P2.2/MOSI
002aab076
Transparent view
P89LPC935/936 HVQFN28 configuration.
1.2.1
Table Symbol description TSSOP28, HVQFN28 PLCC28 P0.0 P0.7 Port Port 8-bit port with user-configurable output type. During reset Port latches configured input only mode with internal pull-up disabled. operation Port pins inputs outputs depends upon port configuration selected. Each port configured independently. Refer Section details. Keypad Interrupt feature operates with Port pins. pins have Schmitt trigger inputs. Port also provides various special functions described below: P0.0/CMP2/ KBI0/AD01 P0.1/CIN2B/ KBI1/AD10 P0.0 Port CMP2 Comparator output. KBI0 Keyboard input AD01 ADC0 channel analog input. (P89LPC935/936) P0.1 Port CIN2B Comparator positive input KBI1 Keyboard input AD10 ADC1 channel analog input. Type Description
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P89LPC933/934/935/936 User manual
Table Symbol
description .continued TSSOP28, HVQFN28 PLCC28 Type Description
P0.2/CIN2A/ KBI2/AD11
P0.2 Port CIN2A Comparator positive input KBI2 Keyboard input AD11 ADC1 channel analog input. P0.3 Port CIN1B Comparator positive input KBI3 Keyboard input AD12 ADC1 channel analog input. P0.4 Port CIN1A Comparator positive input KBI4 Keyboard input DAC1 Digital-to-analog converter output AD13 ADC1 channel analog input. P0.5 Port CMPREF Comparator reference (negative) input. KBI5 Keyboard input P0.6 Port CMP1 Comparator output. KBI6 Keyboard input P0.7 Port Timer/counter external count input overflow output. KBI7 Keyboard input
P0.3/CIN1B/ KBI3/AD12
P0.4/CIN1A/ KBI4/DAC1
P0.5/ CMPREF/ KBI5 P0.6/CMP1/ KBI6
P0.7/T1/ KBI7
I/O,
P1.0 P1.7
Port Port 8-bit port with user-configurable output type, except three pins noted below. During reset Port latches configured input only mode with internal pull-up disabled. operation configurable Port pins inputs outputs depends upon port configuration selected. Each configurable port pins programmed independently. Refer Section details. P1.2 P1.3 open drain when used outputs. P1.5 input only. pins have Schmitt trigger inputs. Port also provides various special functions described below:
P1.0/TXD P1.1/RXD
P1.0 Port Transmitter output serial port. P1.1 Port Receiver input serial port. P1.2 Port (open-drain when used output). Timer/counter external count input overflow output (open-drain when used output). serial clock input/output.
P1.2/T0/SCL
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UM10116
P89LPC933/934/935/936 User manual
Table Symbol
description .continued TSSOP28, HVQFN28 PLCC28 Type Description
P1.3/INT0/
P1.3 Port (open-drain when used output). INT0 External interrupt input. serial data input/output. P1.4 Port INT1 External interrupt input.t P1.5 Port (input only). External Reset input during power-on selected UCFG1. When functioning reset input, this resets microcontroller, causing ports peripherals take their default states, processor begins execution address Also used during power-on sequence force mode. When using oscillator frequency above MHz, reset input function P1.5 must enabled. external circuit required hold device reset power-up until reached specified level. When system power removed will fall below minimum specified operating voltage. When using oscillator frequency above MHz, some applications, external brownout detect circuit required hold device reset when falls below minimum specified operating voltage. P1.6 Port Output Compare (P89LPC935/936) P1.7 Port Output Compare (P89LPC935/936) AD00 ADC0 channel analog input. (P89LPC935/936)
P1.4/INT1 P1.5/RST
P1.6/OCB P1.7/OCC/ AD00
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P89LPC933/934/935/936 User manual
Table Symbol
description .continued TSSOP28, HVQFN28 PLCC28 Type Description
P2.0 P2.7
Port Port 8-bit port with user-configurable output type. During reset Port latches configured input only mode with internal pull-up disabled. operation Port pins inputs outputs depends upon port configuration selected. Each port configured independently. Refer Section details. pins have Schmitt trigger inputs. Port also provides various special functions described below:
P2.0/ICB/ DAC0/AD03
P2.0 Port Input Capture (P89LPC935/936) DAC0 Digital-to-analog converter output. AD03 ADC0 channel analog input. (P89LPC935/936) P2.1 Port Output Compare (P89LPC935/936) AD02 ADC0 channel analog input. (P89LPC935/936) P2.2 Port MOSI master slave When configured master, this output; when configured slave, this input. P2.3 Port MISO When configured master, this input, when configured slave, this output. P2.4 Port Slave select. P2.5 Port SPICLK clock. When configured master, this output; when configured slave, this input. P2.6 Port Output Compare (P89LPC935/936) P2.7 Port Input Capture (P89LPC935/936)
P2.1/OCD/ AD02
P2.2/MOSI
P2.3/MISO
P2.4/SS
P2.5/SPICLK
P2.6/OCA P2.7/ICA
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P89LPC933/934/935/936 User manual
Table Symbol
description .continued TSSOP28, HVQFN28 PLCC28 Type Description
P3.0 P3.1
Port Port 2-bit port with user-configurable output type. During reset Port latches configured input only mode with internal pull-up disabled. operation Port pins inputs outputs depends upon port configuration selected. Each port configured independently. Refer Section details. pins have Schmitt trigger inputs. Port also provides various special functions described below:
P3.0/XTAL2/ CLKOUT
P3.0 Port XTAL2 Output from oscillator amplifier (when crystal oscillator option selected FLASH configuration. CLKOUT clock divided when enabled (ENCLK TRIM.6). used clock internal oscillator, watchdog oscillator external clock input, except when XTAL1/XTAL2 used generate clock source RTC/system timer. P3.1 Port XTAL1 Input oscillator circuit internal clock generator circuits (when selected FLASH configuration). port internal oscillator watchdog oscillator used clock source, XTAL1/XTAL2 used generate clock RTC/system timer. Ground: reference. Power Supply: This power supply voltage normal operation well Idle Power-down modes.
P3.1/XTAL
Input/Output P1.0 P1.4, P1.6, P1.7. Input P1.5.
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UM10116
P89LPC933/934/935/936 User manual
1.2.2 Logic symbols
DAC1
AD10 AD11 AD12 AD13
KBI0 KBI1 KBI2 KBI3 KBI4 KBI5 KBI6 KBI7 CLKOUT
CMP2 CIN2B CIN2A CIN1B CIN1A CMPREF CMP1 XTAL2
PORT
PORT
INT0 INT1
P89LPC933 P89LPC934
PORT DAC0 MOSI MISO SPICLK
XTAL1 PORT
002aab077
P89LPC933/934 logic symbol.
DAC1
AD01 AD10 AD11 AD12 AD13
KBI0 KBI1 KBI2 KBI3 KBI4 KBI5 KBI6 KBI7 CLKOUT
CMP2 CIN2B CIN2A CIN1B CIN1A CMPREF CMP1 XTAL2
PORT
PORT
P89LPC935 P89LPC936
PORT
INT0 INT1 MOSI MISO SPICLK
AD00 AD03 AD02 DAC0
XTAL1 PORT
002aab078
P89LPC935/936 logic symbol.
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UM10116
P89LPC933/934/935/936 User manual
1.2.3 Block diagram
P89LPC933/934/935/936
ACCELERATED 2-CLOCK 80C51
kb/8 kB/16 CODE FLASH 256-BYTE DATA 512-BYTE AUXILIARY 512-BYTE DATA EEPROM (P89LPC935/936) P3[1:0] PORT CONFIGURABLE I/Os PORT CONFIGURABLE I/Os PORT CONFIGURABLE I/Os PORT CONFIGURABLE I/Os
UART internal I2C-BUS
SPICLK MOSI MISO
REAL-TIME CLOCK/ SYSTEM TIMER TIMER TIMER CMP2 CIN2B CIN2A CMP1 CIN1A CIN1B AD10 AD11 AD12 AD13 DAC1 AD00 AD01 AD02 AD03 DAC1
P2[7:0]
ANALOG COMPARATORS
P1[7:0]
P0[7:0]
(CAPTURE/ COMPARE UNIT) (P89LPC935/936)
KEYPAD INTERRUPT WATCHDOG TIMER OSCILLATOR
ADC1/DAC1
PROGRAMMABLE OSCILLATOR DIVIDER
clock
ADC0/DAC0 (P89LPC935/936)
CRYSTAL RESONATOR
CONFIGURABLE OSCILLATOR
ON-CHIP OSCILLATOR
POWER MONITOR (POWER-ON RESET, BROWNOUT RESET)
002aab070
Block diagram.
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P89LPC933/934/935/936 User manual
Special function registers
Remark: accesses restricted following ways:
User must attempt access locations defined. Accesses defined locations must strictly functions SFRs. bits labeled `-', logic logic only written read follows:
Unless otherwise specified, must written with logic return value when read (even written with logic reserved used future derivatives. Logic must written with logic will return logic when read. Logic must written with logic will return logic when read.
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Table Special function registers P89LPC933/934 indicates SFRs that addressable. Name Description functions addresses addr. address ACC* ADCON0 ADCON1 ADINS ADMODA ADMODB AD0DAT3 AD1BH AD1BL AD1DAT0 AD1DAT1 AD1DAT2 AD1DAT3 AUXR1 BRGR0[2] BRGR1[2] BRGCON CMP1 CMP2 DIVM DPTR FMADRH FMADRL Accumulator control register control register input select mode register mode register A/D_0 data register A/D_1 boundary high register A/D_1 boundary register A/D_1 data register A/D_1 data register A/D_1 data register A/D_1 data register Auxiliary function register register Baud rate generator rate Baud rate generator rate high Baud rate generator control Comparator control register Comparator control register clock divide-by-M control Data pointer bytes) Data pointer high Data pointer Program Flash address high Program Flash address 00000000 00000000 00000000 00000000 SBRGS BRGEN CMF1 CMF2 CLKLP EBRR ENT1 ENT0 SRST 00[2] 00[1] 00[1] 00000000 address ENBI1 ADI13 BNDI1 CLK2 ENADCI ADI12 BURST1 CLK1 TMM1 ADI11 SCC1 CLK0 EDGE1 ADI10 SCAN1 ADCI1 ENADC0 ENADC1 ADCS11 BSA1 Reset value ADCS10 00000000 00000000 00000000 00000000 00000000 000x0000 00000000 11111111 00000000 00000000 00000000 00000000 00000000 000000x0 Binary
ENDAC1 ENDAC0
P89LPC933/934/935/936 User manual
00000000 00000000 xxxxxx00 xx000000 xx000000 00000000
UM10116
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Table Special function registers P89LPC933/934 .continued indicates SFRs that addressable. Name FMCON Description Program Flash control (Read) Program Flash control (Write) FMDATA I2ADR I2CON* I2DAT I2SCLH I2SCLL I2STAT ICRAH ICRAL ICRBH ICRBL IEN0* IEN1*
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functions addresses addr. PADH EWDRT PWDRT PWDRT PSTH PBOH ES/ESR PS/PSR PSH/ PSRH ESPI PT1H PSPI PSPIH PX1H EKBI PT0H PKBI PKBIH PATN _SEL STA.4 STA.3 STA.2 STA.1 STA.0 I2ADR.6 I2ADR.5 I2EN I2ADR.4 I2ADR.3 I2ADR.2 I2ADR.1 I2ADR.0 BUSY FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. FMCMD.
Reset value FMCMD. CRSEL EI2C PX0H PI2C PI2CH KBIF 00[1] 00[1] 00[1] 00x00000 00x00000 xxxxxx00 00[1] 00[1] x0000000 x0000000 00[1] 00x00000 00000000 x00000x0 00000000 00000000 11111000 00000000 00000000 00000000 00000000 00000000 00000000 Binary 01110000
Program Flash data slave address register
address control register data register Serial clock generator/SCL duty cycle register high Serial clock generator/SCL duty cycle register status register Input capture register high Input capture register Input capture register high Input capture register Interrupt enable Interrupt enable Interrupt priority Interrupt priority high
address address address IP0* IP0H address IP1* IP1H KBCON Interrupt priority Interrupt priority high Keypad control register
P89LPC933/934/935/936 User manual
UM10116
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Table Special function registers P89LPC933/934 .continued indicates SFRs that addressable. Name KBMASK KBPATN Description Keypad interrupt mask register Keypad pattern register Port functions addresses addr. address address Port address
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Reset value Binary 00000000 11111111
T1/KB7
CMP1 /KB6
CMPREF /KB5 SPICLK
CIN1A /KB4 INT1
CIN1B /KB3 INT0/ MISO
CIN2A /KB2 T0/SCL MOSI
CIN2B /KB1 XTAL1
CMP2 /KB0 XTAL2 00[1] D3[1] 00[1] 00[1] 03[1] 00[1] 00[1] 60[1][6] 00[6] 00[6]
Port Port Port output mode Port output mode Port output mode Port output mode Port output mode Port output mode Port output mode Port output mode Power control register Power control register Program status word Port digital input disable Reset source register Real-time clock control Real-time clock register high Real-time clock register
address address
P0M1 P0M2 P1M1 P1M2 P2M1 P2M2 P3M1 P3M2 PCON PCONA PSW* PT0AD RSTSRC RTCCON RTCH RTCL
(P0M1.7) (P0M1.6) (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M1.0) FF[1] (P0M2.7) (P0M2.6) (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) (P0M2.0) (P1M1.7) (P1M1.6) (P1M2.7) (P1M2.6) (P1M1.4) (P1M1.3) (P1M1.2) (P1M1.1) (P1M1.0) (P1M2.4) (P1M2.3) (P1M2.2) (P1M2.1) (P1M2.0)
11111111 00000000 11x1xx11 00x0xx00 11111111 00000000 xxxxxx11 xxxxxx00 00000000 00000000 00000000 xx00000x
(P2M1.7) (P2M1.6) (P2M1.5) (P2M1.4) (P2M1.3) (P2M1.2) (P2M1.1) (P2M1.0) FF[1] (P2M2.7) (P2M2.6) (P2M2.5) (P2M2.4) (P2M2.3) (P2M2.2) (P2M2.1) (P2M2.0) SMOD1 RTCPD RTCF SMOD0 RTCS1 BOPD VCPD RTCS0 ADPD I2PD R_BK SPPD R_WD (P3M1.1) (P3M1.0) (P3M2.1) (P3M2.0) PMOD1 R_SF ERTC PMOD0 R_EX RTCEN
P89LPC933/934/935/936 User manual
UM10116
PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2 PT0AD.1
011xxx00 00000000 00000000
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Table Special function registers P89LPC933/934 .continued indicates SFRs that addressable. Name SADDR SADEN SBUF SCON* SSTAT SPCTL SPSTAT SPDAT TAMOD TCON* TMOD TRIM WDCON
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Description Serial port address register Serial port address enable Serial Port data buffer register Serial port control Serial port extended status register Stack pointer control register status register data register Timer auxiliary mode Timer control Timer high Timer high Timer Timer Timer mode Internal oscillator trim register Watchdog control register
functions addresses addr. SM0/FE DBMOD INTLO CIDIS DBISEL
Reset value STINT 00000000 00000000 00000111 00000100 00xxxxxx 00000000 xxx0xxx0 00000000 00000000 00000000 00000000 00000000 Binary 00000000 00000000 xxxxxxxx
address
SSIG SPIF
SPEN WCOL
DORD
MSTR T1M2
CPOL
CPHA
SPR1
SPR0 T0M2
address
P89LPC933/934/935/936 User manual
T1GATE RCCLK PRE2
T1C/T ENCLK PRE1
T1M1 TRIM.5 PRE0
T1M0 TRIM.4
T0GATE TRIM.3
T0C/T TRIM.2 WDRUN
T0M1 TRIM.1 WDTOF
T0M0 TRIM.0 WDCLK
00000000
UM10116
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Table Special function registers P89LPC933/934 .continued indicates SFRs that addressable. Name WFEED1 WFEED2
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Description Watchdog load Watchdog feed Watchdog feed
functions addresses addr.
Reset value Binary 11111111
ports input only (high-impedance) state after power-up. BRGR1 BRGR0 must only written BRGEN BRGCON logic written while BRGEN result unpredictable. RSTSRC register reflects cause UM10116 reset. Upon power-up reset, reset source flags cleared except BOF; power-on reset value xx110000. After reset, value 111001x1, i.e., PRE2 PRE0 logic WDRUN WDCLK WDTOF logic after watchdog reset logic after power-on reset. Other resets will affect WDTOF. power-on reset, TRIM initialized with factory preprogrammed value. Other resets will cause initialization TRIM register. only reset source that affects these SFRs power-on reset.
P89LPC933/934/935/936 User manual
UM10116
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Table Special function registers P89LPC935/936 indicates SFRs that addressable. Name Description functions addresses addr. address ACC* ADCON0 ADCON1 ADINS ADMODA ADMODB AD0BH AD0BL AD0DAT0 AD0DAT1 AD0DAT2 AD0DAT3 AD1BH AD1BL AD1DAT0 AD1DAT1 AD1DAT2 AD1DAT3 AUXR1 BRGR0[2] BRGR1[2] BRGCON CCCRA Accumulator control register control register input select mode register mode register A/D_0 boundary high register A/D_0 boundary register A/D_0 data register A/D_0 data register A/D_0 data register A/D_0 data register A/D_1 boundary high register A/D_1 boundary register A/D_1 data register A/D_1 data register A/D_1 data register A/D_1 data register Auxiliary function register register Baud rate generator rate Baud rate generator rate high Baud rate generator control Capture compare control register ICECA2 ICECA1 ICECA0 ICESA ICNFA FCOA SBRGS OCMA1 BRGEN OCMA0 CLKLP EBRR ENT1 ENT0 SRST 00[2] 00000000 00000000 00000000 xxxxxx00 00000000 address ENBI0 ENBI1 ADI13 BNDI1 CLK2 ENADCI ENADCI ADI12 BURST1 CLK1 TMM0 TMM1 ADI11 SCC1 CLK0 EDGE0 EDGE1 ADI10 SCAN1 ADCI0 ADCI1 ADI03 BNDI0 ENADC0 ADCS01 ENADC1 ADCS11 ADI02 BURST0 ADI01 SCC0 BSA1 Reset value ADCS00 ADCS10 ADI00 SCAN0 BSA0 00000000 00000000 00000000 00000000 00000000 000x0000 11111111 00000000 00000000 00000000 00000000 00000000 11111111 00000000 00000000 00000000 00000000 00000000 000000x0 Binary
ENDAC1 ENDAC0
P89LPC933/934/935/936 User manual
UM10116
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Table Special function registers P89LPC935/936 .continued indicates SFRs that addressable. Name CCCRB CCCRC CCCRD CMP1 CMP2 DEECON DEEDAT
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Description Capture compare control register Capture compare control register Capture compare control register Comparator control register Comparator control register Data EEPROM control register Data EEPROM data register Data EEPROM address register clock divide-by-M control Data pointer bytes) Data pointer high Data pointer Program Flash address high Program Flash address Program Flash control (Read) Program Flash control (Write)
functions addresses addr. I2ADR.6 I2ADR.5 I2EN I2ADR.4 I2ADR.3 I2ADR.2 I2ADR.1 I2ADR.0 BUSY FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. ICECB2 EEIF ICECB1 HVERR ICECB0 ECTL1 ICESB ECTL0 ICNFB FCOB FCOC FCOD OCMB1 OCMC1 OCMD1
Reset value OCMB0 OCMC0 OCMD0 CMF1 CMF2 EADR8 00[1] 00[1] FMCMD. CRSEL x00000x0 00000000 00000000 00000000 00000000 Binary 00000000 xxxxx000 xxxxx000 xx000000 xx000000 00001110 00000000 00000000 00000000 00000000 00000000 00000000 00000000
DEEADR DIVM DPTR FMADRH FMADRL FMCON
P89LPC933/934/935/936 User manual
01110000
FMDATA I2ADR I2CON* I2DAT I2SCLH I2SCLL
Program Flash data slave address register
address control register data register Serial clock generator/SCL duty cycle register high Serial clock generator/SCL duty cycle register
UM10116
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Table Special function registers P89LPC935/936 .continued indicates SFRs that addressable. Name I2STAT ICRAH ICRAL ICRBH ICRBL IEN0* IEN1*
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Description status register
functions addresses addr. EADEE PADEE PAEEH EWDRT PWDRT PWDRT PSTH PBOH ES/ESR ECCU PS/PSR PSH/ PSRH PCCU PCCUH ESPI PT1H PSPI PSPIH PX1H EKBI PT0H PKBI PKBIH PATN _SEL STA.4 STA.3 STA.2 STA.1 STA.0
Reset value EI2C PX0H PI2C PI2CH KBIF 00[1] 00[1] 00[1] 00x00000 00x00000 xxxxxx00 00000000 11111111 00000000 00000000 00000000 00000000 00000000 00[1] 00[1] x0000000 x0000000 00[1] 00x00000 00000000 Binary 11111000 00000000 00000000 00000000 00000000
Input capture register high Input capture register Input capture register high Input capture register Interrupt enable Interrupt enable Interrupt priority Interrupt priority high
address address address IP0* IP0H address IP1* IP1H KBCON KBMASK KBPATN OCRAH OCRAL OCRBH OCRBL OCRCH Interrupt priority Interrupt priority high Keypad control register Keypad interrupt mask register Keypad pattern register Output compare register high Output compare register Output compare register high Output compare register Output compare register high
P89LPC933/934/935/936 User manual
UM10116
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Table Special function registers P89LPC935/936 .continued indicates SFRs that addressable. Name OCRCL OCRDH OCRDL Description Output compare register Output compare register high Output compare register Port functions addresses addr. T1/KB7 CMP1 /KB6 CMPREF /KB5 SPICLK CIN1A /KB4 INT1 CIN1B /KB3 INT0/ MISO CIN2A /KB2 T0/SCL MOSI CIN2B /KB1 XTAL1 CMP2 /KB0 XTAL2
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Reset value Binary 00000000 00000000 00000000
address address Port address P0M1 P0M2 P1M1 P1M2 P2M1 P2M2 P3M1 P3M2 PCON PCONA PSW* PT0AD RSTSRC Port Port Port output mode Port output mode Port output mode Port output mode Port output mode Port output mode Port output mode Port output mode Power control register Power control register Program status word Port digital input disable Reset source register address address
(P0M1.7) (P0M1.6) (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M1.0) FF[1] (P0M2.7) (P0M2.6) (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) (P0M2.0) 00[1] (P1M1.7) (P1M1.6) (P1M2.7) (P1M2.6) (P1M1.4) (P1M1.3) (P1M1.2) (P1M1.1) (P1M1.0) (P1M2.4) (P1M2.3) (P1M2.2) (P1M2.1) (P1M2.0) D3[1] 00[1] FF[1] 03[1] 00[1] 00[1]
11111111 00000000 11x1xx11
P89LPC933/934/935/936 User manual
00x0xx00 11111111 00000000 xxxxxx11 xxxxxx00 00000000 00000000 00000000 xx00000x
(P2M1.7) (P2M1.6) (P2M1.5) (P2M1.4) (P2M1.3) (P2M1.2) (P2M1.1) (P2M1.0) SMOD1 RTCPD SMOD0 DEEPD BOPD VCPD ADPD I2PD R_BK SPPD R_WD (P3M1.1) (P3M1.0) (P3M2.1) (P3M2.0) PMOD1 R_SF PMOD0 CCUPD R_EX
(P2M2.7) (P2M2.6) (P2M2.5) (P2M2.4) (P2M2.3) (P2M2.2) (P2M2.1) (P2M2.0) 00[1]
UM10116
PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2 PT0AD.1
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Table Special function registers P89LPC935/936 .continued indicates SFRs that addressable. Name RTCCON RTCH RTCL SADDR SADEN SBUF SCON* SSTAT SPCTL SPSTAT SPDAT TAMOD TCON* TCR20* TCR21 TICR2 TIFR2 TISE2
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Description Real-time clock control Real-time clock register high Real-time clock register Serial port address register Serial port address enable Serial Port data buffer register Serial port control Serial port extended status register Stack pointer control register status register data register Timer auxiliary mode Timer control control register control register Timer high Timer high timer high interrupt control register interrupt flag register interrupt status encode register Timer Timer timer
functions addresses addr. SM0/FE DBMOD INTLO CIDIS DBISEL RTCF RTCS1 RTCS0 ERTC
Reset value RTCEN 60[1][6] 00[6] 00[6] STINT 00000000 00000000 00000111 00000100 00xxxxxx 00000000 xxx0xxx0 00000000 00000000 Binary 011xxx00 00000000 00000000 00000000 00000000 xxxxxxxx
address
SSIG SPIF PLEEN TCOU2
SPEN WCOL HLTRN
DORD HLTEN
MSTR T1M2 ALTCD
CPOL ALTAB PLLDV.3
CPHA TDIR2 PLLDV.2
SPR1 PLLDV.1
SPR0 T0M2
address
TMOD21 TMOD20 PLLDV.0
P89LPC933/934/935/936 User manual
0xxx0000 00000000 00000000 00000000 00000x00 00000x00 xxxxx000 00000000 00000000 00000000
TOIE2 TOIF2
TOCIE2
TOCIE2
TOCIE2B TOCIE2A TOCF2B TOCF2A
ENCINT.
TICIE2B TICF2B ENCINT.
TICIE2A TICF2A
TOCF2D TOCF2C
UM10116
ENCINT.
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Table Special function registers P89LPC935/936 .continued indicates SFRs that addressable. Name TMOD TOR2H TOR2L TPCR2H TPCR2L TRIM WDCON WFEED1 WFEED2
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Description Timer mode reload register high reload register
functions addresses addr. T1GATE T1C/T T1M1 T1M0 T0GATE T0C/T T0M1
Reset value T0M0 TPCR2H. TPCR2H. Binary 00000000 00000000 00000000 xxxxxx00 00000000
Prescaler control register high Prescaler control register Internal oscillator trim register Watchdog control register Watchdog load Watchdog feed Watchdog feed
TPCR2L. TPCR2L. TPCR2L. TPCR2L. TPCR2L. TPCR2L. TPCR2L. TPCR2L. RCCLK PRE2 ENCLK PRE1 TRIM.5 PRE0 TRIM.4 TRIM.3 TRIM.2 WDRUN TRIM.1 WDTOF TRIM.0 WDCLK
11111111
ports input only (high-impedance) state after power-up. BRGR1 BRGR0 must only written BRGEN BRGCON logic written while BRGEN result unpredictable. RSTSRC register reflects cause UM10116 reset. Upon power-up reset, reset source flags cleared except BOF; power-on reset value xx110000. After reset, value 111001x1, i.e., PRE2 PRE0 logic WDRUN WDCLK WDTOF logic after watchdog reset logic after power-on reset. Other resets will affect WDTOF. power-on reset, TRIM initialized with factory preprogrammed value. Other resets will cause initialization TRIM register.
P89LPC933/934/935/936 User manual
only reset source that affects these SFRs power-on reset.
UM10116
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UM10116
P89LPC933/934/935/936 User manual
Memory organization
read-protected calls only entrypoints
IDATA routines FFEFh FF1Fh FF00h
FF00h FFEFh
entry points for: ASM. code code
entry points
SPECIAL FUNCTION REGISTERS (DIRECTLY ADDRESSABLE)
IDATA (incl. DATA)
BYTES ON-CHIP DATA MEMORY (STACK INDIR. ADDR.)
DATA
1FFFh 1E00h 1C00h 1BFFh 1800h 17FFh 1400h 13FFh 1000h 0FFFh 0C00h 0BFFh 0800h 07FFh 0400h 03FFh 0000h
CODE (512B)(1) SECTOR SECTOR SECTOR SECTOR SECTOR SECTOR SECTOR SECTOR
serial loader
1FFFh
entry points for: -UART (auto-baud) -I2C, SPI, etc.(1)
BYTES ON-CHIP DATA MEMORY (STACK, DIRECT INDIR. ADDR.) REG. BANKS R[7:0]
1E00h
data memory (DATA, IDATA)
002aab228
code located Sector P89LPC933 device.
P89LPC933/934/935/936 memory map.
Memory organization
various P89LPC933/934/935/936 memory spaces follows:
DATA
bytes internal data memory space (00H:7FH) accessed direct indirect addressing, using instructions other than MOVX MOVC. part Stack this area.
IDATA
Indirect Data. bytes internal data memory space (00H:FFH) accessed indirect addressing using instructions other than MOVX MOVC. part Stack this area. This area includes DATA area bytes immediately above
Selected registers peripheral control status registers, accessible only direct addressing.
XDATA (P89LPC935/936)
`External' Data Auxiliary RAM. Duplicates classic 80C51 memory space addressed MOVX instruction using SPTR, part this space could implemented on-chip. P89LPC935/936 bytes on-chip XDATA memory.
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CODE
Code memory space, accessed part program execution MOVC instruction. UM10116 have KB/8 kB/16 on-chip Code memory. P89LPC935/936 also bytes on-chip Data EEPROM that accessed SFRs (see Section "Data EEPROM (P89LPC935/936)").
Clocks
Enhanced
P89LPC933/934/935/936 uses enhanced 80C51 which runs times speed standard 80C51 devices. machine cycle consists clock cycles, most instructions execute machine cycles.
Clock definitions
P89LPC933/934/935/936 device several internal clocks defined below: OSCCLK Input DIVM clock divider. OSCCLK selected from four clock sources also optionally divided slower frequency (see Figure Section "CPU Clock (CCLK) modification: DIVM register"). Note: fosc defined OSCCLK frequency. CCLK clock; output DIVM clock divider. There CCLK cycles machine cycle, most instructions executed machine cycles (two four CCLK cycles). RCCLK internal 7.373 oscillator output. PCLK Clock various peripheral devices CCLK/2.
2.2.1 Oscillator Clock (OSCCLK)
P89LPC933/934/935/936 provides several user-selectable oscillator options. This allows optimization range needs from high precision lowest possible cost. These options configured when FLASH programmed include on-chip watchdog oscillator, on-chip oscillator, oscillator using external crystal, external clock source. crystal oscillator optimized low, medium, high frequency crystals covering range from MHz.
2.2.2 speed oscillator option
This option supports external crystal range kHz. Ceramic resonators also supported this configuration.
2.2.3 Medium speed oscillator option
This option supports external crystal range MHz. Ceramic resonators also supported this configuration.
2.2.4 High speed oscillator option
This option supports external crystal range MHz. Ceramic resonators also supported this configuration. When using oscillator frequency above MHz, reset input function P1.5 must enabled. external circuit
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required hold device reset power-up until reached specified level. When system power removed will fall below minimum specified operating voltage. When using oscillator frequency above MHz, some applications, external brownout detect circuit required hold device reset when falls below minimum specified operating voltage.
Clock output
P89LPC933/934/935/936 supports user-selectable clock output function XTAL2 CLKOUT when crystal oscillator being used. This condition occurs different clock source been selected (on-chip oscillator, watchdog oscillator, external clock input Real-time Clock using crystal oscillator clock source. This allows external devices synchronize P89LPC933/934/935/936. This output enabled ENCLK TRIM register frequency this clock output that CCLK. clock output needed Idle mode, turned prior entering Idle, saving additional power. Note: reset, TRIM initialized with factory preprogrammed value. Therefore when setting clearing ENCLK bit, user should retain contents other bits TRIM register. This done reading contents TRIM register (into example), modifying writing this result back into TRIM register. Alternatively, `ANL direct' `ORL direct' instructions used clear TRIM register.
On-chip oscillator option
P89LPC933/934/935/936 TRIM register that used tune frequency oscillator. During reset, TRIM value initialized factory pre-programmed value adjust oscillator frequency 7.373 MHz, (Note: initial value better than please refer P89LPC933/934/935/936 data sheet behavior over temperature). user applications write TRIM register adjust on-chip oscillator other frequencies. Increasing TRIM value will decrease oscillator frequency.
Table Symbol Reset On-chip oscillator trim register (TRIM address 96h) allocation RCCLK ENCLK TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0
Bits loaded with factory stored value during reset.
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Table
On-chip oscillator trim register (TRIM address 96h) description Symbol TRIM.0 TRIM.1 TRIM.2 TRIM.3 TRIM.4 TRIM.5 ENCLK RCCLK when CCLK/2 output XTAL2 provided crystal oscillator being used. when selects Oscillator output clock (CCLK). This allows fast switching between clock source internal oscillator without needing through reset cycle. Description Trim value. Determines frequency internal oscillator. During reset, these bits loaded with stored factory calibration value. When writing either this register, care should taken preserve current TRIM value reading this register, modifying bits required, writing result this register.
Watchdog oscillator option
watchdog separate oscillator which frequency kHz. This oscillator used save power when high clock frequency needed.
External clock input option
this configuration, processor clock derived from external source driving XTAL1 P3.1 pin. rate from MHz. XTAL2 P3.0 used standard port clock output. When using oscillator frequency above MHz, reset input function P1.5 must enabled. external circuit required hold device reset power-up until reached specified level. When system power removed will fall below minimum specified operating voltage. When using oscillator frequency above MHz, some applications, external brownout detect circuit required hold device reset when falls below minimum specified operating voltage.
quartz crystal ceramic resonator P89LPC93x XTAL1
XTAL2
002aab229
Note: oscillator must configured following modes: frequency crystal, medium frequency crystal, high frequency crystal. series resistor required limit crystal drive levels. This especially important frequency crystals.
Using crystal oscillator.
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XTAL1 XTAL2
HIGH FREQUENCY MEDIUM FREQUENCY FREQUENCY
ADC1
ADC0 (P89LPC935/936)
OSCCLK OSCILLATOR (7.3728 WATCHDOG OSCILLATOR (400 TIMER TIMER PCLK RCCLK
DIVM
CCLK PCLK
(P89LPC935/936)
002aab079
I2C-BUS
UART
Block diagram oscillator control.
Oscillator Clock (OSCCLK) wake-up delay
P89LPC933/934/935/936 internal wake-up timer that delays clock until stabilizes depending clock source used. clock source three crystal selections, delay OSCCLK cycles plus clock source either internal oscillator Watchdog oscillator, delay OSCCLK cycles plus
Clock (CCLK) modification: DIVM register
OSCCLK frequency divided down, integer, times configuring dividing register, DIVM, provide CCLK. This produces CCLK frequency using following formula: CCLK frequency fosc (2N) Where: fosc frequency OSCCLK, value DIVM. Since ranges from 255, CCLK frequency range fosc fosc/510. (for CCLK fosc). This feature makes possible temporarily lower rate, reducing power consumption. dividing clock, retain ability respond events other than those that cause interrupts (i.e. events that allow exiting Idle mode) executing normal program lower rate. This often result lower power consumption than Idle mode. This allow bypassing oscillator start-up time cases where Power-down mode would otherwise used. value DIVM changed program time without interrupting code execution.
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power select
P89LPC933/934/935/936 designed (CCLK) maximum. However, CCLK slower, CLKLP (AUXR1.7) logic lower power consumption further. reset, CLKLP logic allowing highest performance. This then software CCLK running slower.
converter
P89LPC935/936 have 8-bit, 4-channel multiplexed successive approximation analog-to-digital converter modules sharing common control logic. P89LPC933/934 have single 8-bit, 4-channel multiplexed analog-to-digital converter (ADC1) additional module (DAC0). block diagram converter shown Figure Each consists 4-input multiplexer which feeds sample-and-hold circuit providing input signal comparator inputs. control logic combination with drives digital-to-analog converter which provides other input comparator. output comparator SAR.
features (P89LPC935/936) 8-bit, 4-channel multiplexed input, successive approximation
converters with common control logic (one P89LPC933/934).
Four result registers each A/D. operating modes
Fixed channel, single conversion mode Fixed channel, continuous conversion mode Auto scan, single conversion mode Auto scan, continuous conversion mode Dual channel, continuous conversion mode Single step mode
Four conversion start modes
Timer triggered start Start immediately Edge triggered Dual start immediately (P89LPC935/936)
8-bit conversion time clock Interrupt polled operation Boundary limits interrupt output port with high output impedance Clock divider Power down mode
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3.2.1 operating modes
3.2.1.1 Fixed channel, single conversion mode single input channel selected conversion. single conversion will performed result placed result register which corresponds selected input channel (see Table interrupt, enabled, will generated after conversion completes. input channel selected ADINS register. This mode selected setting SCANx ADMODA register.
comp INPUT
DAC1
CONTROL LOGIC comp INPUT
DAC0
CCLK
002aab080
block diagram. Table Input channels result registers fixed channel single, auto scan single, auto scan continuous conversion modes Input channel AD00 AD01 AD02 AD03 Result register AD1DAT0 AD1DAT1 AD1DAT2 AD1DAT3 Input channel AD10 AD11 AD12 AD13
Result register AD0DAT0 AD0DAT1 AD0DAT2 AD0DAT3
3.2.1.2
Fixed channel, continuous conversion mode single input channel selected continuous conversion. results conversions will sequentially placed four result registers (see Table interrupt, enabled, will generated after every four conversions. Additional conversion results will again cycle through four result registers, overwriting previous results. Continuous conversions continue until terminated user. This mode selected setting SCCx ADMODA register.
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UM10116
P89LPC933/934/935/936 User manual
Result registers conversion results fixed channel, continuous conversion mode Contains Selected channel, first conversion result Selected channel, second conversion result Selected channel, third conversion result Selected channel, fourth conversion result
Table
Result register ADxDAT0 ADxDAT1 ADxDAT2 ADxDAT3
3.2.1.3
Auto scan, single conversion mode combination four input channels selected conversion setting channel's respective ADINS register. channels converted from order ADINS). single conversion each selected input will performed result placed result register which corresponds selected input channel (See Table interrupt, enabled, will generated after selected channels have been converted. only single channel selected this equivalent single channel, single conversion mode.This mode selected setting SCANx ADMODA register.
3.2.1.4
Auto scan, continuous conversion mode combination four input channels selected conversion setting channel's respective ADINS register. channels converted from order ADINS). conversion each selected input will performed result placed result register which corresponds selected input channel (See Table interrupt, enabled, will generated after selected channels have been converted. process will repeat starting with first selected channel. Additional conversion results will again cycle through result registers selected channels, overwriting previous results.Continuous conversions continue until terminated user.This mode selected setting BURSTx ADMODA register.
3.2.1.5
Dual channel, continuous conversion mode co.Any combination four input channels selected conversion. result conversion first channel placed first result register. result conversion second channel placed second result register.The first channel again converted result stored third result register. second channel again converted result placed fourth result register (See Table interrupt generated, enabled, after every four conversions (two conversions channel).This mode selected setting SCCx ADMODA register.
Table Result registers conversion results dual channel, continuous conversion mode Contains First channel, first conversion result Second channel, first conversion result First channel, second conversion result Second channel, second conversion result
Result register ADxDAT0 ADxDAT1 ADxDAT2 ADxDAT3
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3.2.1.6
Single step mode This special mode allows "single-stepping" auto scan conversion mode. combination four input channels selected conversion. After each channel converted, interrupt generated, enabled, waits next start condition. result each channel placed result register which corresponds selected input channel (See Table used with start modes. This mode selected clearing BURSTx, SCCx, SCANx bits ADMODA register which correspond use.
3.2.2 Conversion mode selection bits
Each uses three bits ADMODA select conversion mode that A/D. These mode bits summarized Table 10,below. Combinations three bits, other than combinations shown, undefined.
Table Burst1 Conversion mode bits SCC1 Scan1 ADC1 conversion mode Single step Fixed channel, single Auto scan, single Fixed channel, continuous Dual channel, continuous Auto scan, continuous Burst0 SCC0 Scan0 ADC0 conversion mode Single step Fixed channel, single Auto scan, single Fixed channel, continuous Dual channel, continuous Auto scan, continuous
3.2.3 Conversion start modes
3.2.3.1 Timer triggered start conversion started overflow Timer Once conversion started, additional Timer triggers ignored until conversion completed. Timer triggered start mode available operating modes.This mode selected TMMx ADCSx1 ADCSx0 bits (See Table Table 14). 3.2.3.2 Start immediately Programming this mode immediately starts conversion.This start mode available operating modes.This mode selected setting ADCSx1 ADCSx0 bits ADCONx register (See Table Table 14). 3.2.3.3 Edge triggered conversion started rising falling edge P1.4. Once conversion started, additional edge triggers ignored until conversion completed. edge triggered start mode available operating modes.This mode selected setting ADCSx1 ADCSx0 bits ADCONx register (See Table Table 14).
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3.2.3.4
Dual start immediately (P89LPC935/936) Programming this mode starts synchronized conversion both converters.This start mode available operating modes. Both converters must same operating mode. autoscan single conversion modes, both converters must select identical number channels. Writing ADCSx1, ADCSx0 bits either ADCONx register will start simultaneous conversion both A/Ds. Both A/Ds must enabled.
3.2.4 Boundary limits interrupt
Each converters both high boundary limit register. After four MSBs have been converted, these four bits compared with four MSBs boundary high registers. four MSBs conversion outside limit interrupt will generated, enabled. conversion result within limits, boundary limits will again compared after bits have been converted. interrupt will generated, enabled, result outside boundary limits. boundary limit disabled clearing boundary limit interrupt enable.
3.2.5 output port with high output impedance
Each converter's block output port pin. this mode, ADxDAT3 register used hold value DAC. After value been written (written ADxDAT3), output will appear channel pin. output enabled ENDAC1 ENDAC0 bits ADMODB register (See Table 18).
3.2.6 Clock divider
converter requires that internal clock source range 500kHz 3.3MHz maintain accuracy. programmable clock divider that divides clock from provided this purpose (See Table 18).
3.2.7 pins used with functions
analog input pins maybe used either digital inputs thus have digital input output function. order give best analog performance, pins that being used with should have their digital outputs inputs disabled have tolerance disconnected. Digital outputs disabled putting port pins into input-only mode described Port Configurations section (see Table 24). Digital inputs will disconnected automatically from these pins when been selected setting corresponding ADINS register corresponding been enabled When used digital these pins tolerant. selected input signals ADINS, these pins will tolerant corresponding enabled device power down. Otherwise will remain tolerant. Please refer P89LPC933/934/935/936 data sheet specifications.
3.2.8 Power-down Idle mode
Idle mode converter, enabled, will continue function cause device exit Idle mode when conversion completed interrupt enabled. Power-down mode Total Power-down mode, does function. enabled, will consume power. Power reduced disabling A/D.
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Table Symbol Reset Table
Control register (ADCON0 address 8Eh) allocation ENBI0 ENADCI0 TMM0 EDGE0 ADCI0 ENADC0 ADCS01 ADCS00
Control register (ADCON0 address 8Eh) description Symbol Description Timer Trigger Mode when TMM0 Conversions starts overflow Timer When TMM0 start occurs (stop mode). Immediate Start Mode. Conversion starts immediately. Edge Trigger Mode. Conversion starts when edge condition defined EDGE0 occurs. Dual Immediate Start Mode. Both ADC's start conversion immediately. ADCS01,ADCS00 start mode bits, below.(P89LPC935/936)
ENADC0 ADCI0 EDGE0 TMM0 ENADCI0 ENBI0
Enable channel When enables ADC0. Must also operation this channel. Conversion complete Interrupt when conversion multiple conversions completed. Cleared software.(P89LPC935/936) When Edge conversion start triggered falling edge P1.4 When Edge conversion start triggered rising edge P1.4. (P89LPC935/936) Timer Trigger Mode Selects either stop mode (TMM0 timer trigger mode (TMM0 when ADCS01 ADCS00 bits (P89LPC935/936) Enable Conversion complete Interrupt When set, will cause interrupt ADCI0 flag interrupt enabled. (P89LPC935/936) Enable boundary interrupt When set, will cause interrupt boundary interrupt flag, BNDI0, interrupt enabled. (P89LPC935/936)
Table Symbol Reset Table
Control register 1(ADCON1 address 97h) allocation ENBI1 ENADCI1 TMM1 EDGE1 ADCI1 ENADC1 ADCS11 ADCS10
Control register 1(ADCON1 address 97h) description Symbol Description Timer Trigger Mode when TMM1 Conversions starts overflow Timer When TMM1 start occurs (stop mode). Immediate Start Mode. Conversion starts immediately. Edge Trigger Mode. Conversion starts when edge condition defined EDGE1 occurs. Dual Immediate Start Mode. Both ADC's start conversion immediately (P89LPC935/936). ADCS11,ADCS10 start mode bits, below.
ENADC1 ADCI1
Enable channel When enables ADC1. Must also operation this channel. Conversion complete Interrupt when conversion multiple conversions completed. Cleared software.(P89LPC935/936)
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Table
Control register 1(ADCON1 address 97h) description .continued Symbol EDGE1 TMM1 ENADCI1 ENBI1 Description When Edge conversion start triggered falling edge P1.4 When Edge conversion start triggered rising edge P1.4. (P89LPC935/936) Timer Trigger Mode Selects either stop mode (TMM1 timer trigger mode (TMM1 when ADCS11 ADCS10 bits (P89LPC935/936) Enable Conversion complete Interrupt When set, will cause interrupt ADCI1 flag interrupt enabled. (P89LPC935/936) Enable boundary interrupt When set, will cause interrupt boundary interrupt 1flag, BNDI1, interrupt enabled. (P89LPC935/936)
Table Symbol Reset Table
Mode register (ADMODA address 0C0h) allocation BNDI1 BURST1 SCC1 SCAN1 BNDI0 BURST0 SCC0 SCAN0
Mode register (ADMODA address 0C0h) description Symbol SCAN0 SCC0 BURST0 BNDI0 SCAN1 SCC1 BURST1 BNDI1 Description When selects single conversion mode (auto scan fixed channel) ADC0 (P89LPC935/936). When selects fixed channel, continuous conversion mode ADC0 (P89LPC935/936). When selects auto scan, continuous conversion mode ADC0 (P89LPC935/936). ADC0 boundary interrupt flag. When set, indicates that converted result outside range defined ADC0 boundary registers (P89LPC935/936). When selects single conversion mode (auto scan fixed channel) ADC1. When selects fixed channel, continuous conversion mode ADC1. When selects auto scan, continuous conversion mode ADC1. ADC1 boundary interrupt flag. When set, indicates that converted result outside range defined ADC1 boundary registers.
Table Symbol Reset Table
Mode register (ADMODB address A1h) allocation CLK2 CLK1 CLK0 ENDAC1 ENDAC0 BSA1 BSA0
Mode register (ADMODB address A1h) description Symbol BSA0 Description ADC0 Boundary Select All. When BNDI0 will ADC0 input exceeds boundary limits. When BNDI0 will only AD00 input exceeded boundary limits.(P89LPC935) ADC1 Boundary Select All. When BNDI1 will ADC1 input exceeds boundary limits. When BNDI1 will only AD10 input exceeded boundary limits. When selects mode ADC0; when selects mode. (Note: This must
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ENDAC0
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Table
Mode register (ADMODB address A1h) description .continued Symbol ENDAC1 Description When selects mode ADC1; when selects mode. reserved
CLK2,CLK1,CLK0 Clock divider produce clock. Divides CCLK value indicated below. resulting clock should 3.3MHz less. minimum 0.5MHz required maintain accuracy. CLK2:0 Divisor
Table Symbol Reset Table
Input select (ADINS address A3h) allocation AIN13 AIN12 AIN11 AIN10 AIN03 AIN02 AIN01 AIN00
Input select (ADINS address A3h) description Symbol AIN00 AIN01 AIN02 AIN03 AIN10 AIN11 AIN12 AIN13 Description When set, enables AD00 sampling conversion (P89LPC935/936). When set, enables AD01 sampling conversion (P89LPC935/936). When set, enables AD02 sampling conversion (P89LPC935/936). When set, enables AD03 sampling conversion (P89LPC935/936). When set, enables AD10 sampling conversion. When set, enables AD11 sampling conversion. When set, enables AD12 sampling conversion. When set, enables AD13 sampling conversion.
Interrupts
P89LPC933/934/935/936 uses four priority level interrupt structure. This allows great flexibility controlling handling P89LPC933/934/935/936's interrupt sources. Each interrupt source individually enabled disabled setting clearing interrupt enable registers IEN0 IEN1. IEN0 register also contains global enable bit, which enables interrupts. Each interrupt source individually programmed four priority levels setting clearing bits interrupt priority registers IP0, IP0H, IP1, IP1H. interrupt service routine progress interrupted higher priority interrupt,
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another interrupt same lower priority. highest priority interrupt service cannot interrupted other interrupt source. requests different priority levels received simultaneously, request higher priority level serviced. requests same priority level pending start instruction cycle, internal polling sequence determines which request serviced. This called arbitration ranking. Note that arbitration ranking only used pending requests same priority level. Table summarizes interrupt sources, flag bits, vector addresses, enable bits, priority bits, arbitration ranking, whether each interrupt wake-up from Power-down mode.
Interrupt priority structure
Table IPxH Interrupt priority level Interrupt priority level Level (lowest priority) Level Level Level Priority bits
There four SFRs associated with four interrupt levels: IP0, IP0H, IP1, IP1H. Every interrupt bits IPxH therefore assigned four levels, shown Table P89LPC933/934/935/936 external interrupt inputs addition Keypad Interrupt function. interrupt inputs identical those present standard 80C51 microcontrollers. These external interrupts programmed level-triggered edge-triggered clearing setting Register TCON. external interrupt triggered level detected INTn pin. external interrupt edge triggered. this mode consecutive samples INTn show high level cycle level next cycle, interrupt request flag TCON set, causing interrupt request. Since external interrupt pins sampled once each machine cycle, input high level should held least machine cycle ensure proper sampling. external interrupt edge-triggered, external source hold request high least machine cycle, then hold least machine cycle. This ensure that transition detected that interrupt request flag set. automatically cleared when service routine called. external interrupt level-triggered, external source must hold request active until requested interrupt generated. external interrupt still asserted when interrupt service routine completed, another interrupt will generated. necessary clear interrupt flag when interrupt level sensitive, simply tracks input level.
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external interrupt been programmed level-triggered enabled when P89LPC933/934/935/936 into Power-down mode Idle mode, interrupt occurrence will cause processor wake-up resume operation. Refer Section "Power reduction modes" details. Note: external interrupt must programmed level-triggered wake-up from Power-down mode.
External Interrupt glitch suppression
Most P89LPC933/934/935/936 pins have glitch suppression circuits reject short glitches (please refer P89LPC933/934/935/936 data sheet, Dynamic characteristics glitch filter specifications). However, pins SDA/INT0/P1.3 SCL/T0/P1.2 have glitch suppression circuits. Therefore, INT1 glitch suppression while INT0 does not.
Table Summary interrupts Interrupt flag bit(s) WDOVF/RTCF KBIF CMF1/CMF2 SPIF ADCI1, BNDI1 002Bh 0053h 0033h 003Bh 0043h 004Bh 005Bh 006Bh 0073h (IEN0.5) EWDRT (IEN0.6) EI2C (IEN1.0) EKBI (IEN1.1) (IEN1.2) ESPI (IEN1.3) ECCU(IEN1.4) (IEN1.6) (IEN1.7) IP0H.5, IP0.5 IP0H.6, IP0.6 IP0H.0, IP0.0 IP0H.0, IP0.0 IP0H.0, IP0.0 IP1H.3, IP1.3 IP1H.4, IP1.4 IP0H.0, IP0.0 IP1H.7, IP1.7 (lowest) Vector address 0003h 000Bh 0013h 001Bh 0023h Interrupt enable bit(s) (IEN0.0) (IEN0.1) (IEN0.2) (IEN0.3) ES/ESR (IEN0.4) Interrupt priority IP0H.0, IP0.0 IP0H.1, IP0.1 IP0H.2, IP0.2 IP0H.3, IP0.3 IP0H.4, IP0.4 Arbitration ranking (highest) Powerdown wake-up
Description
External interrupt Timer interrupt External interrupt Timer interrupt Serial port Serial port Brownout detect Watchdog timer/Real-time clock interrupt interrupt Comparators interrupts interrupt Capture/Compare Unit Serial port ADC, Data EEPROMwrite complete (P89LPC935/936)
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RTCF ERTC (RTCCON.1) WDOVF KBIF EKBI EWDRT CMF2 CMF1 (IE0.7) RI/RI ES/ESR EI2C SPIF ESPI interrupt(1) ECCU
EEIF(2) ENADCI0(2) ADCI0(2) ENADCI1 ADCI1 ENBI0(2) BNDI0(2) ENBI1 BNDI1 EADEE (P89LPC935) (P89LPC933/934)
wake-up power-down)
interrupt
002aab081
Section "Capture/Compare Unit (CCU)" P89LPC935/936
Interrupt sources, interrupt enables, power-down wake-up sources.
ports
P89LPC933/934/935/936 four ports: Port Port Port Port Ports 8-bit ports Port 2-bit port. exact number pins available depends upon clock reset options chosen (see Table 23).
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Number pins available Reset option Number pins
Table
Clock source On-chip oscillator watchdog oscillator External clock input
external reset (except during power External supported External supported[1] external reset (except during power
Low/medium/high speed oscillator external reset (except during power (external crystal resonator) External supported[1]
required operation above MHz.
Port configurations
three port pins P89LPC933/934/935/936 configured software four types pin-by-pin basis, shown Table These are: quasi-bidirectional (standard 80C51 port outputs), push-pull, open drain, input-only. configuration registers each port select output type each port pin. P1.5 (RST) only input cannot configured. P1.2 (SCL/T0) P1.3 (SDA/INT0) only configured either input-only open drain.
Table PxM1.y Port output configuration settings PxM2.y Port output mode Quasi-bidirectional Push-pull Input only (high-impedance) Open drain
Quasi-bidirectional output configuration
Quasi-bidirectional outputs used both input output without need reconfigure port. This possible because when port outputs logic high, weakly driven, allowing external device pull low. When driven low, driven strongly able sink large current. There three pull-up transistors quasi-bidirectional output that serve different purposes. these pull-ups, called `very weak' pull-up, turned whenever port latch contains logic This very weak pull-up sources very small current that will pull high left floating. second pull-up, called `weak' pull-up, turned when port latch contains logic itself also logic level. This pull-up provides primary source current quasi-bidirectional that outputting this pulled external device, weak pull-up turns off, only very weak pull-up remains order pull under these conditions, external device sink enough current overpower weak pull-up pull port below input threshold voltage.
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third pull-up referred `strong' pull-up. This pull-up used speed low-to-high transitions quasi-bidirectional port when port latch changes from logic logic When this occurs, strong pull-up turns clocks quickly pulling port high. quasi-bidirectional port configuration shown Figure Although P89LPC933/934/935/936 device most pins V-tolerant. applied configured quasi-bidirectional mode, there will current flowing from causing extra power consumption. Therefore, applying pins configured quasi-bidirectional mode discouraged. quasi-bidirectional port Schmitt-triggered input that also glitch suppression circuit (Please refer P89LPC933/934/935/936 data sheet, Dynamic characteristics glitch filter specifications).
CLOCK DELAY
strong
very weak
weak
PORT port latch data
input data glitch rejection
002aaa914
Quasi-bidirectional output.
Open drain output configuration
open drain output configuration turns pull-ups only drives pull-down transistor port when port latch contains logic used logic output, port configured this manner must have external pull-up, typically resistor tied VDD. pull-down this mode same quasi-bidirectional mode. open drain port configuration shown Figure open drain port Schmitt-triggered input that also glitch suppression circuit. Please refer P89LPC933/934/935/936 data sheet, Dynamic characteristics glitch filter specifications.
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PORT port latch data
input data glitch rejection
002aaa915
Open drain output.
Input-only configuration
input port configuration shown Figure Schmitt-triggered input that also glitch suppression circuit. (Please refer P89LPC933/934/935/936 data sheet, Dynamic characteristics glitch filter specifications).
input data glitch rejection
PORT
002aaa916
Input only.
Push-pull output configuration
push-pull output configuration same pull-down structure both open drain quasi-bidirectional output modes, provides continuous strong pull-up when port latch contains logic push-pull mode used when more source current needed from port output. push-pull port configuration shown Figure push-pull port Schmitt-triggered input that also glitch suppression circuit. (Please refer P89LPC933/934/935/936 data sheet, Dynamic characteristics glitch filter specifications).
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strong
port latch data
PORT
input data
glitch rejection
002aaa917
Push-pull output.
Port Analog Comparator functions
P89LPC933/934/935/936 incorporates Analog Comparators. order give best analog performance minimize power consumption, pins that being used analog functions must have both digital outputs digital inputs disabled. Digital outputs disabled putting port pins into input-only mode described Port Configurations section (see Figure 15). Digital inputs Port disabled through PT0AD register. Bits through this register correspond pins P0.1 through P0.5 Port respectively. Setting corresponding PT0AD disables that pin's digital input. Port bits that have their digital inputs disabled will read instruction that accesses port. reset, PT0AD bits through default logic enable digital functions.
Additional port features
After power-up, pins Input-only mode. Please note that this different from LPC76x series devices.
After power-up, pins except P1.5, configured software. P1.5 input only. Pins P1.2 P1.3 configurable either input-only
open drain. Every output P89LPC933/934/935/936 been designed sink typical drive current. However, there maximum total output current ports which must exceeded. Please refer P89LPC933/934/935/936 data sheet detailed specifications. ports pins that function output have slew rate controlled outputs limit noise generated quickly switching output signals. slew rate factory-set approximately rise fall times.
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Port output configuration Configuration bits PxM1.y PxM2.y P0M2.0 P0M2.1 P0M2.2 P0M2.3 P0M2.4 P0M2.5 P0M2.6 P0M2.7 P1M2.0 P1M2.1 P1M2.2 P1M2.3 P1M2.4 P1M2.5 P1M2.6 P1M2.7 P1M2.0 P1M2.1 P1M2.2 P1M2.3 P1M2.4 P1M2.5 P1M2.6 P1M2.7 P3M2.0 P3M2.1 Alternate usage KBIO, CMP2, AD01 KBI1, CIN2B, AD10 Refer Section "Port KBI2, CIN2A, AD11 Analog Comparator functions" usage analog inputs. KBI3, CIN1B, AD12 KBI4, CIN1A, AD13, DAC1 KBI5, CMPREF KBI6, CMP1 KBI7, INTO, INT1 OCC, AD00 ICB, AD03, DAC0 OCD, AD02 MOSI MISO SPICLK CLKOUT, XTAL2 XTAL1 Input-only open-drain input-only open-drain Notes P0M1.0 P0M1.1 P0M1.2 P0M1.3 P0M1.4 P0M1.5 P0M1.6 P0M1.7 P1M1.0 P1M1.1 P1M1.2 P1M1.3 P1M1.4 P1M1.5 P1M1.6 P1M1.7 P2M1.0 P2M1.1 P2M1.2 P2M1.3 P2M1.4 P2M1.5 P2M1.6 P2M1.7 P3M1.0 P3M1.1
Table Port P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P3.1
Power monitoring functions
P89LPC933/934/935/936 incorporates power monitoring functions designed prevent incorrect operation during initial power-on power loss reduction during operation. This accomplished with hardware functions: Power-on Detect Brownout Detect.
Brownout detection
Brownout Detect function determines power supply voltage drops below certain level. default operation Brownout Detection cause processor reset. However, alternatively configured generate interrupt setting (PCON.4) (IEN0.5) bit.
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Enabling disabling Brownout Detection done BOPD (PCON.5) bit, field PMOD1/PMOD0 (PCON[1:0]) user configuration (UCFG1.5). unprogrammed state, brownout disabled regardless PMOD1/PMOD0 BOPD. programmed state, PMOD1/PMOD0 BOPD will used determine whether Brownout Detect will disabled enabled. PMOD1/PMOD0 used select power reduction mode. PMOD1/PMOD0 `11', circuitry Brownout Detection disabled lowest power consumption. BOPD defaults logic indicating brownout detection enabled power-on programmed. Brownout Detection enabled brownout condition occurs when falls below Brownout trip voltage, (see P89LPC933/934/935/936 data sheet, Static characteristics), negated when rises above VBO. P89LPC933/934/935/936 device operate with power supply that below should left unprogrammed state that device operate otherwise continuous brownout reset prevent device from operating. Brownout Detect enabled (BOE programmed, PMOD1/PMOD0 `11', BOPD (RSTSRC.5) will when brownout detected, regardless whether reset interrupt enabled. will stay until cleared software writing logic bit. Note that unprogrammed, meaningless. programmed, initial power-on occurs, will addition power-on flag (POF RSTSRC.4). correct activation Brownout Detect, certain rise fall times must observed. Please data sheet specifications.
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Table (UCFG1.5) (erased) 1(program med)
Brownout options[1] PMOD1/ PMOD0 (PCON[1:0]) (total power-down) BOPD (PCON.5) (PCON.4) (IEN0.5) (IEN0.7) Description
Brownout disabled. operating range Brownout disabled. operating range However, BOPD default logic upon power-up. Brownout reset enabled. operating range Upon brownout reset, (RSTSRC.5) will indicate reset source. cleared writing logic bit. Brownout interrupt enabled. operating range Upon brownout interrupt, (RSTSRC.5) will set. cleared writing logic bit. Both brownout reset interrupt disabled. operating range However, (RSTSRC.5) will when falls Brownout Detection trip point. cleared writing logic bit.
(any mode (brownout other than total detect power-down) power-down)
(brownout (brownout detect active) detect generates reset)
(brownout (enable detect brownout generates interrupt) interrupt)
(global interrupt enable)
Cannot used with operation above this requires above.
Power-on detection
Power-On Detect function similar Brownout Detect, designed work power initially comes before power supply voltage reaches level where Brownout Detect function. flag (RSTSRC.4) indicate initial power-on condition. flag will remain until cleared software writing logic bit. Note that (UCFG1.5) programmed, (RSTSRC.5) will when set. unprogrammed, meaningless.
Power reduction modes
P89LPC933/934/935/936 supports three different power reduction modes determined bits PCON[1:0] (see Table 27).
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Table
Power reduction modes
PMOD1 PMOD0 Description (PCON.1) (PCON.0) Normal mode (default) power reduction. Idle mode. Idle mode leaves peripherals running order allow them activate processor when interrupt generated. enabled interrupt source reset terminate Idle mode. Power-down mode: Power-down mode stops oscillator order minimize power consumption. P89LPC933/934/935/936 exits Power-down mode reset, certain interrupts external pins INT0/INT1, brownout Interrupt, keyboard, Real-time Clock/System Timer), watchdog, comparator trips. Waking reset only enabled corresponding reset enabled, waking interrupt only enabled corresponding interrupt enabled (IEN0.7) set. External interrupts should programmed level-triggered mode used exit Power-down mode. Power-down mode internal oscillator disabled unless both oscillator been selected system clock enabled. Power-down mode, power supply voltage reduced keep-alive voltage VRAM. This retains contents point where Power-down mode entered. contents guaranteed after been lowered VRAM, therefore recommended wake-up processor Reset this situation. must raised within operating range before Power-down mode exited. When processor wakes from Power-down mode, will start oscillator immediately begin execution when oscillator stable. Oscillator stability determined counting 1024 clocks after start-up when crystal oscillator configurations used, clocks after start-up internal external clock input configurations. Some chip functions continue operate draw power during Power-down mode, increasing total power used during power-down. These include:
Brownout Detect Watchdog Timer WDCLK (WDCON.0) logic Comparators (Note: Comparators powered down separately with PCONA.5 logic comparators disabled); Real-time Clock/System Timer (and crystal oscillator circuitry this block using unless RTCPD, i.e., PCONA.7 logic
Total Power-down mode: This same Power-down mode except that Brownout Detection circuitry voltage comparators also disabled conserve additional power. Note that brownout reset interrupt will occur. Voltage comparator interrupts Brownout interrupt cannot used wake-up source. internal oscillator disabled unless both oscillator been selected system clock enabled. following wake-up options supported:
Watchdog Timer WDCLK (WDCON.0) logic Could generate Interrupt Reset, either wake device External interrupts INTO/INT1 (when programmed level-triggered mode). Keyboard Interrupt Real-time Clock/System Timer (and crystal oscillator circuitry this block using unless RTCPD, i.e., PCONA.7 logic
Note: Using internal RC-oscillator clock during power-down result relatively high power consumption. Lower power consumption achieved using external frequency clock when Real-time Clock running during power-down.
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Table Symbol Reset Table
Power Control register (PCON address 87h) allocation SMOD1 SMOD0 BOPD PMOD1 PMOD0
Power Control register (PCON address 87h) description Symbol PMOD0 PMOD1 BOPD General Purpose Flag read written user software, effect operation General Purpose Flag read written user software, effect operation Brownout Detect Interrupt Enable. When logic Brownout Detection will generate interrupt. When logic Brownout Detection will cause reset Brownout Detect power-down. When logic Brownout Detect powered down therefore disabled. When logic Brownout Detect enabled. (Note: BOPD must logic before programming erasing commands issued. Otherwise these commands will aborted.) Framing Error Location: Description Power Reduction Mode (see Section 6.3)
SMOD0
SMOD1
When logic SCON accessed UART. When logic SCON accessed framing error status (FE) UART
Double Baud Rate serial port (UART) when Timer used baud rate source. When logic Timer overflow rate supplied UART. When logic Timer overflow rate divided before being supplied UART. (See Section
Table Symbol Reset Table
Power Control register (PCONA address B5h) allocation RTCPD DEEPD VCPD ADPD I2PD SPPD CCUPD
Power Control register (PCONA address B5h) description Symbol CCUPD Description Compare/Capture Unit (CCU) power-down: When logic internal clock disabled. Note that either Power-down mode Total Power-down mode, clock will disabled regardless this bit. (Note: This overridden CCUDIS FCFG1. CCUDIS powered down.) Serial Port (UART) power-down: When logic internal clock UART disabled. Note that either Power-down mode Total Power-down mode, UART clock will disabled regardless this bit. power-down: When logic internal clock disabled. Note that either Power-down mode Total Power-down mode, clock will disabled regardless this bit. power-down: When logic internal clock I2C-bus disabled. Note that either Power-down mode Total Power-down mode, clock will disabled regardless this bit.
SPPD
I2PD
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Table
Power Control register (PCONA address B5h) description .continued Symbol ADPD Description Converter Power down: When `1', turns clock ADC. fully power-down ADC, user should also ENADC1 ENADC0 bits registers ADCON1 ADCON0. Analog Voltage Comparators power-down: When logic voltage comparators powered down. User must disable voltage comparators prior setting this bit. Data EEPROM power-down: When logic Data EEPROM powered down. Note that either Power-down mode Total Power-down mode, Data EEPROM will powered down regardless this bit. Real-time Clock power-down: When logic internal clock Real-time Clock disabled.
VCPD
DEEPD
RTCPD
Reset
P1.5/RST function either active reset input digital input, P1.5. (Reset Enable) UCFG1, when enables external reset input function P1.5. When cleared, P1.5 used input pin. Note: During power-on sequence, selection overridden this will always functions reset input. external circuit connected this should hold this during Power-on sequence this will keep device reset. After power-on this input will function either external reset input digital input defined bit. Only power-on reset will temporarily override selection defined bit. Other sources reset will override bit. Note: During power cycle, must fall below VPOR (see P89LPC933/934/935/936 data sheet, Static characteristics) before power reapplied, order ensure power-on reset. Note: When using oscillator frequency above MHz, reset input function P1.5 must enabled. external circuit required hold device reset power-up until reached specified level. When system power removed will fall below minimum specified operating voltage. When using oscillator frequency above MHz, some applications, external brownout detect circuit required hold device reset when falls below minimum specified operating voltage. Reset triggered from following sources (see Figure 17):
External reset (during power-on user configured UCFG1); Power-on Detect; Brownout Detect; Watchdog Timer; Software reset; UART break detect reset.
every reset source, there flag Reset Register, RSTSRC. user read this register determine most recent reset source. These flag bits cleared software writing logic corresponding bit. More than flag set:
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During power-on reset, both other flag bits
cleared.
other reset, previously flag bits that have been cleared will remain
set.
(UCFG1.6) WDTE (UCFG1.7) watchdog timer reset software reset SRST (AUXR1.3) chip reset power-on detect UART break detect EBRR (AUXR1.6) brownout detect reset BOPD (PCON.5)
002aaa918
Block diagram reset. Table Symbol Reset[1]
Reset Sources register (RSTSRC address DFh) allocation R_BK R_WD R_SF R_EX
value shown power-on reset. Other reset sources will their corresponding bits.
Table R_EX R_SF R_WD R_BK
Reset Sources register (RSTSRC address DFh) description external reset Flag. When this logic indicates external reset. Cleared software writing logic Power-on reset. still asserted after Power-on reset over, R_EX will set. software reset Flag. Cleared software writing logic Power-on reset Watchdog Timer reset flag. Cleared software writing logic Power-on reset.(NOTE: UCFG1.7 must break detect reset. break detect occurs EBRR (AUXR1.6) logic system reset will occur. This indicate that system reset caused break detect. Cleared software writing logic Power-on reset. Power-on Detect Flag. When Power-on Detect activated, flag indicate initial power-up condition. flag will remain until cleared software writing logic bit. (Note: Power-on reset, both this will while other flag bits cleared.) Brownout Detect Flag. When Brownout Detect activated, this set. will remain until cleared software writing logic bit. (Note: Power-on reset, both this will while other flag bits cleared.) reserved
Symbol Description
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Reset vector
Following reset, P89LPC933/934/935/936 will fetch instructions from either address 0000h Boot address. Boot address formed using Boot Vector high byte address byte address 00h. Boot address will used UART break reset occurs non-volatile Boot Status (BOOTSTAT.0) device been forced into mode. Otherwise, instructions will fetched from address 0000H.
Timers
P89LPC933/934/935/936 general-purpose counter/timers which upward compatible with 80C51 Timer Timer Both configured operate either timers event counters (see Table 35). option automatically toggle upon timer overflow been added. `Timer' function, timer incremented every PCLK. `Counter' function, register incremented response 1-to-0 transition corresponding external input T1). external input sampled once during every machine cycle. When high during cycle next cycle, count incremented. count value appears register during cycle following which transition detected. Since takes machine cycles (four clocks) recognize 1-to-0 transition, maximum count rate clock frequency. There restrictions duty cycle external input signal, ensure that given level sampled least once before changes, should held least full machine cycle. `Timer' `Counter' function selected control bits TnC/T Timers respectively) Special Function Register TMOD. Timer Timer have five operating modes (modes which selected bit-pairs (TnM1, TnM0) TMOD TnM2 TAMOD. Modes same both Timers/Counters. Mode different. operating modes described later this section.
Table Symbol Reset Table T0M0 T0M1 T0C/T Timer/Counter Mode register (TMOD address 89h) allocation T1GATE T1C/T T1M1 T1M0 T0GATE T0C/T T0M1 T0M0
Timer/Counter Mode register (TMOD address 89h) description Description Mode Select Timer These bits used with T0M2 TAMOD register determine Timer mode (see Table 37). Timer Counter selector Timer Cleared Timer operation (input from CCLK). Counter operation (input from input pin).
Symbol
T0GATE Gating control Timer When set, Timer/Counter enabled only while INT0 high control set. When cleared, Timer enabled when control set.
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Table T1M0 T1M1 T1C/T
Timer/Counter Mode register (TMOD address 89h) description .continued Description Mode Select Timer These bits used with T1M2 TAMOD register determine Timer mode (see Table 37). Timer Counter Selector Timer Cleared Timer operation (input from CCLK). Counter operation (input from input pin).
Symbol
T1GATE Gating control Timer When set, Timer/Counter enabled only while INT1 high control set. When cleared, Timer enabled when control set. Timer/Counter Auxiliary Mode register (TAMOD address 8Fh) allocation T1M2 T0M2
Table Symbol Reset Table T0M2
Timer/Counter Auxiliary Mode register (TAMOD address 8Fh) description Description Mode Select Timer These bits used with T0M2 TAMOD register determine Timer mode (see Table 37). reserved Mode Select Timer These bits used with T1M2 TAMOD register determine Timer mode (see Table 37). following timer modes selected timer mode bits TnM[2:0]: 8048 Timer `TLn' serves 5-bit prescaler. (Mode 16-bit Timer/Counter `THn' `TLn' cascaded; there prescaler.(Mode 8-bit auto-reload Timer/Counter. holds value which loaded into when overflows. (Mode Timer dual 8-bit Timer/Counter this mode. 8-bit Timer/Counter controlled standard Timer control bits. 8-bit timer only, controlled Timer control bits (see text). Timer this mode stopped. (Mode Reserved. User must configure this mode. Reserved. User must configure this mode. mode (see Section 8.5). Reserved. User must configure this mode.
Symbol
T1M2
reserved
Mode
Putting either Timer into Mode makes look like 8048 Timer, which 8-bit Counter with divide-by-32 prescaler. Figure shows Mode operation. this mode, Timer register configured 13-bit register. count rolls over from sets Timer interrupt flag TFn. count input enabled Timer when either TnGATE INTn (Setting TnGATE allows Timer controlled external input INTn, facilitate pulse width measurements). control Special Function Register TCON (Table 39). TnGATE TMOD register.
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13-bit register consists bits lower bits TLn. upper bits indeterminate should ignored. Setting flag (TRn) does clear registers. Mode operation same Timer Timer Figure There different GATE bits, Timer (TMOD.7) Timer (TMOD.3).
Mode
Mode same Mode except that bits timer register (THn TLn) used. Figure
Mode
Mode configures Timer register 8-bit Counter (TLn) with automatic reload, shown Figure Overflow from only sets TFn, also reloads with contents THn, which must preset software. reload leaves unchanged. Mode operation same Timer Timer
Mode
When Timer Mode stopped. effect same setting Timer Mode establishes separate 8-bit counters. logic Mode Timer shown Figure uses Timer control bits: T0C/T, T0GATE, TR0, INT0, TF0. locked into timer function (counting machine cycles) takes over from Timer Thus, controls `Timer interrupt. Mode provided applications that require extra 8-bit timer. With Timer Mode P89LPC933/934/935/936 device look like three Timer/Counters. Note: When Timer Mode Timer turned switching into Mode still used serial port baud rate generator, application requiring interrupt.
Mode
this mode, corresponding timer changed with full period timer clocks (see Figure 22). structure similar mode except that:
Timers respectively) cleared hardware; period THn, should between 254, and; high period always 256-THn. Loading with will force high, loading with will force low.
Note that interrupt still enabled high transition TFn, that still cleared software like other modes.
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Table Symbol Reset Table
Timer/Counter Control register (TCON) address 88h) allocation
Timer/Counter Control register (TCON address 88h) description Description Interrupt Type control bit. Set/cleared software specify falling edge/low level triggered external interrupts. Interrupt Edge flag. hardware when external interrupt edge detected. Cleared hardware when interrupt processed, software. Interrupt Type control bit. Set/cleared software specify falling edge/low level triggered external interrupts. Interrupt Edge flag. hardware when external interrupt edge detected. Cleared hardware when interrupt processed, software. Timer control bit. Set/cleared software turn Timer/Counter on/off. Timer overflow flag. hardware Timer/Counter overflow. Cleared hardware when processor vectors interrupt routine, software. (except mode where cleared hardware) Timer control bit. Set/cleared software turn Timer/Counter on/off Timer overflow flag. hardware Timer/Counter overflow. Cleared hardware when interrupt processed, software (except mode above, when cleared hardware).
Symbol
PCLK
control (5-bits) (8-bits)
overflow interrupt
toggle gate INTn ENTn
002aaa919
Timer/counter Mode (13-bit counter).
PCLK
control (8-bits) (8-bits)
overflow interrupt
toggle gate INTn ENTn
002aaa920
Timer/counter mode (16-bit counter).
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PCLK
control (8-bits) reload
overflow interrupt
toggle
gate INTn (8-bits)
ENTn
002aaa921
Timer/counter Mode (8-bit auto-reload).
PCLK
control (8-bits)
overflow toggle interrupt
gate INT0 ENT0 (AUXR1.4)
(P1.2 open drain)
osc/2 control
(8-bits)
overflow interrupt
toggle (P0.7) ENT1 (AUXR1.5)
002aaa922
Timer/counter Mode (two 8-bit counters).
PCLK control (8-bits)
overflow interrupt
reload falling transition (256 THn) rising transition
toggle gate INTn (8-bits)
ENTn
002aaa923
Timer/counter mode (PWM auto-reload).
Timer overflow toggle output
Timers configured automatically toggle port output whenever timer overflow occurs. same device pins that used count inputs outputs also used timer toggle outputs. This function enabled
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control bits ENT0 ENT1 AUXR1 register, apply Timer Timer respectively. port outputs will logic prior first timer overflow when this mode turned order this mode function, must cleared selecting PCLK clock source timer.
Real-time clock system timer
P89LPC933/934/935/936 simple Real-time Clock/System Timer that allows user continue running accurate timer while rest device powered down. Real-time Clock interrupt wake-up source (see Figure 23). Real-time Clock 23-bit down counter. clock source this counter either clock (CCLK) XTAL1-2 oscillator, provided that XTAL1-2 oscillator being used clock. XTAL1-2 oscillator used clock, then will CCLK clock source regardless state RTCS1:0 RTCCON register. There three SFRs used RTC: RTCCON Real-time Clock control. RTCH Real-time Clock counter reload high (bits 15). RTCL Real-time Clock counter reload (bits Real-time clock system timer enabled setting RTCEN (RTCCON.0) bit. Real-time Clock 23-bit down counter (initialized when RTCEN that comprised 7-bit prescaler 16-bit loadable down counter. When RTCEN written with logic counter first loaded with (RTCH, RTCL, `1111111') will count down. When reaches 0's, counter will reloaded again with (RTCH, RTCL, `1111111') flag RTCF (RTCCON.7) will set.
power-on reset
RTCH
RTCL
RESET XTAL2 XTAL1
RELOAD UNDERFLOW FREQUENCY MEDIUM FREQUENCY HIGH FREQUENCY CCLK internal oscillators RTCS1 RTCS2 select
002aaa924
7-BIT PRESCALER ÷128
23-BIT DOWN COUNTER
wake-up from power-down RTCF Interrupt enabled (shared with WDT) underflow flag ERTC RTCEN enable
Real-time clock/system timer block diagram.
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Real-time clock source
RTCS1/RTCS0 (RTCCON[6:5]) used select clock source either Internal oscillator internal oscillator used clock. internal crystal oscillator external clock input XTAL1 used clock, then will CCLK clock source.
Changing RTCS1/RTCS0
RTCS1/RTCS0 cannot changed currently enabled (RTCCON.0 Setting RTCEN updating RTCS1/RTCS0 done single write RTCCON. However, RTCEN this must first cleared before updating RTCS1/RTCS0.
Real-time clock interrupt/wake-up
ERTC (RTCCON.1), EWDRT (IEN1.0.6) (IEN0.7) logic RTCF used interrupt source. This interrupt vector shared with watchdog timer. also source wake-up device.
Reset sources affecting Real-time clock
Only power-on reset will reset Real-time Clock associated SFRs their default state.
Table FOSC2:0 Real-time Clock/System Timer clock sources RCCLK RTCS1:0 Internal oscillator Medium frequency crystal /DIVM Medium frequency crystal Internal oscillator Internal oscillator Medium frequency crystal Medium frequency crystal /DIVM High frequency crystal /DIVM High frequency crystal Internal oscillator clock source High frequency crystal clock source High frequency crystal /DIVM
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Real-time Clock/System Timer clock sources .continued RCCLK RTCS1:0 Internal oscillator Internal oscillator Medium frequency crystal /DIVM frequency crystal Internal oscillator /DIVM High frequency crystal Medium frequency crystal frequency crystal Internal oscillator High frequency crystal Watchdog oscillator Medium frequency crystal /DIVM frequency crystal Watchdog oscillator /DIVM High frequency crystal Medium frequency crystal frequency crystal Internal oscillator undefined undefined External clock input undefined undefined External clock input /DIVM Internal oscillator Internal oscillator High frequency crystal frequency crystal /DIV frequency crystal Internal oscillator clock source frequency crystal clock source frequency crystal /DIVM
Table FOSC2:0
External clock input /DIVM External clock input Internal oscillator
Internal oscillator
Table Symbol Reset
Real-time Clock Control register (RTCCON address D1h) allocation RTCF RTCS1 RTCS0 ERTC RTCEN
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Real-time Clock Control register (RTCCON address D1h) description Description Real-time Clock enable. Real-time Clock will enabled this logic Note that this will power-down Real-time Clock. RTCPD (PCONA.7) set, will power-down disable this block regardless RTCEN. Real-time Clock interrupt enable. Real-time Clock shares same interrupt watchdog timer. Note that user configuration WDTE (UCFG1.7) logic watchdog timer enabled generate interrupt. Users read RTCF (RTCCON.7) determine whether Real-time Clock caused interrupt. reserved Real-time Clock source select (see Table 40). Real-time Clock Flag. This logic when 23-bit Real-time Clock reaches count logic cleared software.
Table
Symbol RTCEN
ERTC
RTCS0 RTCS1 RTCF
Capture/Compare Unit (CCU)
This unit features:
16-bit timer with 16-bit reload overflow Selectable clock (CCUCLK), with prescaler divide clock source integer
between 1024.
Four Compare outputs with selectable polarity Symmetrical Asymmetrical selection Seven interrupts with common interrupt vector (one Overflow, 2xCapture,
4xCompare), safe 16-bit read/write shadow registers.
Capture inputs with event counter digital noise rejection filter 10.1 Clock (CCUCLK)
runs CCUCLK, which either PCLK basic timer mode output (see Figure 24). designed clock source between that multiplied produce CCUCLK between mode (asymmetrical symmetrical). contains 4-bit divider (PLLDV3:0 bits TCR21 register) help divide PCLK into frequency between
10.2 Clock prescaling
This CCUCLK further divided down prescaler. prescaler implemented 10-bit free-running counter with programmable reload overflow. Writing value prescaler will cause prescaler restart.
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16-BIT SHADOW REGISTER TOR2H TOR2L
16-BIT SHADOW REGISTER OCRxH OCRxL
16-BIT COMPARE VALUE
16-BIT TIMER RELOAD REGISTER OVERFLOW/ UNDERFLOW
TIMER COMPARE
COMPARE CHANNELS
FCOx
16-BIT UP/DOWN TIMER WITH RELOAD
16-BIT CAPTURE REGISTER ICRxH, EVENT COUNTER
ICNFx NOISE FILTER
ICESx EDGE SELECT
10-BIT DIVIDER INTERRUPT FLAG TICF2x CAPTURE CHANNELS
4-BIT DIVIDER
002aab009
Capture Compare Unit block diagram.
10.3 Basic timer operation
Timer free-running up/down counter counting pace determined prescaler. timer started setting Mode Select bits TMOD21 TMOD20 Control Register (TCR20) shown table TCR20 register description (Table 47). direction control bit, TDIR2, determines direction count. TDIR2 Count TDIR2 Count down. timer counting direction changed while counter running, count sequence will reversed CCUCLK cycle following write TDIR2. timer written read time newly-written values will take effect when prescaler overflows. timer accessible through SFRs, TL2(low byte) TH2(high byte). third 16-bit SFR, TOR2H:TOR2L, determines overflow reload value. TL2, TOR2H, TOR2L will after reset Up-counting: When timer contents FFFFH, next CCUCLK cycle will counter value contents TOR2H:TOR2L. Down-counting: When timer contents 0000H, next CCUCLK cycle will counter value contents TOR2H:TOR2L. During CCUCLK cycle when reload performed, Timer Overflow Interrupt Flag (TOIF2) Interrupt Flag Register (TIFR2) will set, and, IEN0 register ECCU IEN1 register (IEN1.4) set, program execution will vector overflow interrupt. user clear interrupt flag software writing logic When writing reload registers, TOR2H TOR2L, values written stored 8-bit shadow registers. order latch contents shadow registers into TOR2H TOR2L, user must write logic Timer Compare/Overflow Update TCOU2, Timer Control Register (TCR21). function this
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depends whether timer running mode basic timer mode. basic timer mode, writing TCOU2 will cause values latched immediately value TCOU2 will always read zero. mode, writing TCOU2 will cause contents shadow registers updated next Timer overflow. long latch pending, TCOU2 will read will return zero when latching takes place. TCOU2 also controls latching Output Compare registers OCR2A, OCR2B OCR2C. When writing timer high byte, TH2, value written stored shadow register. When written, contents TH2's shadow register transferred same time that gets updated. Thus, should written prior writing TL2. write followed another write TL2, without being written between, value will transferred directly high byte timer. 16-bit Timer used 8-bit timer, user write (for upcounting) (for downcounting) TH2. When written, FFh:TH2 (for upcounting) (for downcounting) will loaded Timer. user will need rewrite again 8-bit timer operation unless there change count direction When reading timer, must read first. When read, contents timer high byte transferred shadow register same PCLK cycle read performed. When read, contents shadow register read instead. read from followed another read from without being read between, high byte timer will transferred directly TH2.
Table Symbol Reset Table prescaler control register, high byte (TPCR2H address CBh) allocation TPCR2H.1 TPCR2H.0
prescaler control register, high byte (TPCR2H address CBh) description Description Prescaler Prescaler
Symbol TPCR2H.0 TPCR2H.1
Table Symbol Reset
prescaler control register, byte (TPCR2L address CAh) allocation TPCR2L.7 TPCR2L.6 Table TPCR2L.5 TPCR2L.4 TPCR2L.3 TPCR2L.2 TPCR2L.1 TPCR2L.0
prescaler control register, byte (TPCR2L address CAh) description Symbol TPCR2L.0 TPCR2L.1 TPCR2L.2 TPCR2L.3 TPCR2L.4 Description Prescaler Prescaler Prescaler Prescaler Prescaler
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prescaler control register, byte (TPCR2L address CAh) description Symbol TPCR2L.5 TPCR2L.6 TPCR2L.7 Description Prescaler Prescaler Prescaler
Table Table Symbol Reset Table
control register (TCR20 address C8h) allocation PLLEN HLTRN HLTEN ALTCD ALTAB TDIR2 TMOD21 TMOD20
control register (TCR20 address C8h) description Description Timer mode (TMOD21, TMOD20): Timer stopped Basic timer function Asymmetrical (uses clock source) Symmetrical (uses clock source)
Symbol TMOD20/21
TDIR2 ALTAB ALTCD HLTEN HLTRN PLLEN
Count direction Timer. When logic count When logic count down. channel alternately output enable. When this set, output channel alternately gated every counter cycle. channel alternately output enable. When this set, output channel alternately gated every counter cycle. Halt Enable. When logic capture event enabled Input Capture will immediately stop activity pins them predetermined state. Halt. When indicates halt took place. order re-activate PWM, user must clear HLTRN bit. Phase Locked Loop Enable. When logic starts operation. After lock this will read back one.
10.4 Output compare
four output compare channels controlled through four 16-bit SFRs, OCRAH:OCRAL, OCRBH:OCRBL, OCRCH:OCRCL, OCRDH: OCRDL. Each output compare channel needs enabled order operate. channel enabled selecting Compare Output Action setting OCMx1:0 bits Capture Compare Control Register CCCRx When compare channel enabled, user will have associated desired output mode connect pin. (Note: bits port pins P2.6, P1.6, P1.7, P2.1 must logic order compare channel outputs visible port pins.) When contents TH2:TL2 match that OCRxH:OCRxL, Timer Output Compare Interrupt Flag TOCFx TIFR2. This happens CCUCLK cycle after compare takes place. Timer Output Compare Interrupt Enable TOCIE2x TICR2 register), well ECCU IEN1 set, program counter will vectored corresponding interrupt. user must manually clear writing logic bits OCCRx, Output Compare Mode bits OCMx1 OCMx0 select what action taken when compare match occurs. Enabled compare actions take place even interrupt disabled.
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order Compare Output Action occur, compare values must within counting range timer. When compare channel enabled, (which must configured output) will connected internal latch controlled compare logic. value this latch zero from reset changed invoking forced compare. forced compare generated writing logic Force Compare Output FCOx OCCRx. Writing this generates transition corresponding OCMx1/OCMx0 without causing interrupt. basic timer operating mode FCOx bits always read zero. (Note: This different function mode.) When output compare enabled connected compare latch, state compare remains unchanged until compare event forced compare occurs.
Table Symbol Reset Table Capture compare control register (CCRx address Exh) allocation ICECx2 ICECx1 ICECx0 ICESx ICNFx FCOx OCMx1 OCMx0
Capture compare control register (CCRx address Exh) description Description Output Compare Mode. Force Compare Output Bit. When set, invoke force compare. Input Capture Noise Filter Enable Bit. When logic capture logic needs four consecutive samples same value order recognize edge capture event. inputs sampled every CCLK periods regardless speed timer. Input Capture Edge Select Bit. When logic Negative edge triggers capture, When logic Positive edge triggers capture. Capture Delay Setting Table details. Capture Delay Setting Table details. Capture Delay Setting Table details.
Symbol OCMx0 OCMx1 FCOx ICNFx
ICESx ICECx0 ICECx1 ICECx2
When user writes change output compare value, values written OCRH2x OCRL2x transferred 8-bit shadow registers. order latch contents shadow registers into capture compare register, user must write logic Timer Compare/Overflow Update TCOU2, Control Register TCR21. function this depends whether timer running mode basic timer mode. basic timer mode, writing TCOU2 will cause values latched immediately value TCOU2 will always read zero. mode, writing TCOU2 will cause contents shadow registers updated next Timer overflow. long latch pending, TCOU2 will read will return zero when latch takes place. TCOU2 also controls latching Output Compare registers well Timer Overflow Reload registers TOR2.
10.5 Input capture
Input capture always enabled. Each time capture event occurs input capture pins, contents timer transferred corresponding 16-bit input capture register ICRAH:ICRAL ICRBH:ICRBL. capture event defined
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Input Capture Edge Select ICESx being CCCRx register. user will have configure associated input order external event trigger capture. simple noise filter enabled input capture input. When Input Capture Noise Filter ICNFx set, capture logic needs four consecutive samples same value order recognize edge capture event. inputs sampled every CCLK periods regardless speed timer. event counter delay capture number capture events. three bits ICECx2, ICECx1 ICECx0 CCCRx register determine number edges capture logic before input capture occurs. When capture event detected, Timer Input Capture Interrupt Flag TICF2x (TIFR2.1 TIFR2.0) set. Timer Input Capture Enable TICIE2x (TICR2.1 TICR2.0) well ECCU (IEN1.4) set, program counter will vectored corresponding interrupt. interrupt flag must cleared manually writing logic When reading input capture register, ICRxL must read first. When ICRxL read, contents capture register high byte transferred shadow register. When ICRxH read, contents shadow register read instead. read from ICRxL followed another read from ICRxL without ICRxH being read between, value capture register high byte (from last ICRxL read) will shadow register).
Table ICECx2 Event delay counter input capture ICECx1 ICECx0 Delay (numbers edges)
10.6 operation
Operation main modes, asymmetrical symmetrical. These modes timer operation sel
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