P89LPC9102/9103/9107 User manual Rev. February 2005 User manual
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UM10112
P89LPC9102/9103/9107 User manual
Rev. February 2005 User manual
Document information Info Keywords Abstract Content P89LPC9102, P89LPC9103, P89LPC9107 Technical information P89LPC9102, P89LPC9103 P89LPC9107 devices.
Philips Semiconductors
UM10112
P89LPC9102/9103/9107 User manual
Revision history Date 20050211 Description Initial version (9397 13919).
9397 13919
Koninklijke Philips Electronics N.V. 2004. rights reserved.
User manual
Rev. February 2005
Philips Semiconductors
UM10112
P89LPC9102/9103/9107 User manual
Introduction
P89LPC9102/9103/9107 single-chip microcontrollers designed applications demanding high-integration, low-cost solutions over wide range performance requirements. P89LPC9102/9103/9107 based high performance processor architecture that executes instructions four clocks, times rate standard 80C51 devices. Many system-level functions have been incorporated into P89LPC9102/9103/9107 order reduce component count, board space, system cost.
Logic symbols
DAC1
AD13 CLKIN AD11 AD12 AD10 CLKOUT
CIN1A CMPREF KBI2 CIN1B KBI1
PORT PORT
P89LPC9102
002aaa971
P89LPC9102 logic symbol.
DAC1
AD13 CLKIN AD11 AD12 AD10
CIN1A CMPREF KBI2 CIN1B KBI1
PORT PORT
P89LPC9103
002aaa972
P89LPC9103 logic symbol.
DAC1
AD13 CLKIN AD11 AD12 AD10 CLKOUT
CIN1A CMPREF KBI2 CIN1B KBI1
PORT PORT
P89LPC9107
002aab084
P89LPC9107 logic symbol.
9397 13919
Koninklijke Philips Electronics N.V. 2004. rights reserved.
User manual
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Philips Semiconductors
UM10112
P89LPC9102/9103/9107 User manual
Configuration
terminal index area P0.2/KBI2/AD11 P1.5/RST P0.1/KBI1/AD10 P1.2/T0 P0.3/CIN1B/AD12 P0.4/CIN1A/AD13/DAC1 P0.5/CMPREF/CLKIN P0.7/T1/CLKOUT
LPC9102
002aaa969
Transparent view
P89LPC9102 pinning (HVSON10).
terminal index area P0.2/KBI2/AD11 P1.5/RST P0.1/KBI1/AD10 P1.0/TXD P0.3/CIN1B/AD12 P0.4/CIN1A/AD13/DAC1 P0.5/CMPREF/CLKIN P1.1/RXD
LPC9103
002aaa970
Transparent view
P89LPC9103 pinning (HVSON10).
P0.2/KBI2/AD11 n.c. P1.5/RST P0.1/KBI1/AD10 P1.0/TXD P1.2/T0
002aab083
P0.3/CIN1B/AD12 n.c. P0.4/CIN1A/AD13/DAC1
LPC9107
P0.5/CMPREF/CLKIN P1.1/RXD P0.7/T1/CLKOUT
P89LPC9107 pinning (TSSOP14).
9397 13919
Koninklijke Philips Electronics N.V. 2004. rights reserved.
User manual
Rev. February 2005
Philips Semiconductors
UM10112
P89LPC9102/9103/9107 User manual
Table Symbol
P89LPC9102 description Type Description Port Port port with user-configurable output type. During reset Port latches configured input-only mode with internal pull-up disabled. operation Port pins inputs outputs depends upon port configuration selected. Each port configured independently. Refer Section "Port configurations" details. Keypad Interrupt feature operates with Port pins. pins have Schmitt triggered inputs. Port also provides various special functions described below:
P0.1 P0.5, P0.7
P0.1/KBI1/ AD10
P0.1 Port KBI1 Keyboard input AD10 ADC1 channel analog input. P0.2 Port KBI2 Keyboard input AD11 ADC1 channel analog input. P0.3 Port CIN1B Comparator positive input. AD12 ADC1 channel analog input. P0.4 Port CIN1A Comparator positive input. AD13 ADC1 channel analog input. DAC1 Digital analog converter output. P0.5 Port CMPREF Comparator reference (negative) input. CLKIN External clock input. P0.7 Port Timer/counter external count input overflow/PWM output. CLKOUT Clock output. Port Port port with user-configurable output type. During reset Port latches configured input-only mode with internal pull-up disabled. operation configurable Port pins inputs outputs depends upon port configuration selected. Each configurable port pins programmed independently. Refer Section "Port configurations" details. P1.5 input-only. pins have Schmitt triggered inputs. Port also provides various special functions described below:
P0.2/KBI2/ AD11
P0.3/CIN1B/ AD12
P0.4/CIN1A/ AD13/DAC1
P0.5/ CMPREF/ CLKIN P0.7/T1/ CLKOUT
P1.2, P1.5
P1.2/T0
P1.2 Port Timer/counter external count input overflow/PWM output.
9397 13919
Koninklijke Philips Electronics N.V. 2004. rights reserved.
User manual
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Philips Semiconductors
UM10112
P89LPC9102/9103/9107 User manual
Table Symbol P1.5/RST
P89LPC9102 description .continued Type Description P1.5 Port (input-only). External Reset input during power-on selected UCFG1. When functioning reset input this resets microcontroller, causing ports peripherals take their default states, processor begins execution address Also used during power-on sequence force In-System Programming mode. When using oscillator frequency above MHz, reset input function P1.5 must enabled. external circuit required hold device reset power-up until reached specified level. When system power removed will fall below minimum specified operating voltage. When using oscillator frequency above MHz, some applications, external brownout detect circuit required hold device reset when falls below minimum specified operating voltage. Ground: reference. Power supply: This power supply voltage normal operation well Idle mode Power-down mode.
Table Symbol
P89LPC9103 description Type Description Port Port port with user-configurable output type. During reset Port latches configured input-only mode with internal pull-up disabled. operation Port pins inputs outputs depends upon port configuration selected. Each port configured independently. Refer Section "Port configurations" details. Keypad Interrupt feature operates with Port pins. pins have Schmitt triggered inputs. Port also provides various special functions described below:
P0.1 P0.5
P0.1/KBI1/ AD10
P0.1 Port KBI1 Keyboard input AD10 ADC1 channel analog input. P0.2 Port KBI2 Keyboard input AD11 ADC1 channel analog input. P0.3 Port CIN1B Comparator positive input. AD12 ADC1 channel analog input. P0.4 Port CIN1A Comparator positive input. AD13 ADC1 channel analog input. DAC1 Digital analog converter output. P0.5 Port CMPREF Comparator reference (negative) input. CLKIN External clock input.
P0.2/KBI2/ AD11
P0.3/CIN1B/ AD12
P0.4/CIN1A/ AD13/DAC1
P0.5/CMPREF/ CLKIN
9397 13919
Koninklijke Philips Electronics N.V. 2004. rights reserved.
User manual
Rev. February 2005
Philips Semiconductors
UM10112
P89LPC9102/9103/9107 User manual
Table Symbol
P89LPC9103 description .continued Type Description Port Port port with user-configurable output type. During reset Port latches configured input-only mode with internal pull-up disabled. operation configurable Port pins inputs outputs depends upon port configuration selected. Each configurable port pins programmed independently. Refer Section "Port configurations" details. P1.5 input-only. pins have Schmitt triggered inputs. Port also provides various special functions described below:
P1.0 P1.5
P1.0/TXD P1.1/RXD P1.5/RST
P1.0 Port Serial port transmitter data. P1.1 Port Serial port receiver data. P1.5 Port (input-only). External Reset input during Power-on selected UCFG1. When functioning reset input this resets microcontroller, causing ports peripherals take their default states, processor begins execution address Also used during power-on sequence force In-System Programming mode.When using oscillator frequency above MHz, reset input function P1.5 must enabled. external circuit required hold device reset power-up until reached specified level. When system power removed will fall below minimum specified operating voltage. When using oscillator frequency above MHz, some applications, external brownout detect circuit required hold device reset when falls below minimum specified operating voltage. Ground: reference. Power supply: This power supply voltage normal operation well Idle mode Power-down mode.
Table Symbol
P89LPC9107 description Type Description Port Port port with user-configurable output type. During reset Port latches configured input-only mode with internal pull-up disabled. operation Port pins inputs outputs depends upon port configuration selected. Each port configured independently. Refer Section "Port configurations" page details. Keypad Interrupt feature operates with Port pins. pins have Schmitt triggered inputs. Port also provides various special functions described below:
P0.1 P0.5, P0.7
P0.1/KBI1/ AD10
P0.1 Port KBI1 Keyboard input AD10 ADC1 channel analog input. P0.2 Port KBI2 Keyboard input AD11 ADC1 channel analog input. P0.3 Port CIN1B Comparator positive input. AD12 ADC1 channel analog input.
Koninklijke Philips Electronics N.V. 2004. rights reserved.
P0.2/KBI2/ AD11
P0.3/CIN1B/ AD12
9397 13919
User manual
Rev. February 2005
Philips Semiconductors
UM10112
P89LPC9102/9103/9107 User manual
Table Symbol
P89LPC9107 description .continued Type Description P0.4 Port CIN1A Comparator positive input. AD13 ADC1 channel analog input. DAC1 Digital analog converter output. P0.5 Port CMPREF Comparator reference (negative) input. CLKIN External clock input. P0.7 Port Timer/counter external count input overflow/PWM output. CLKOUT Clock output. Port Port port with user-configurable output type. During reset Port latches configured input-only mode with internal pull-up disabled. operation configurable Port pins inputs outputs depends upon port configuration selected. Each configurable port pins programmed independently. Refer Section "Port configurations" page details. P1.5 input-only. pins have Schmitt triggered inputs. Port also provides various special functions described below:
P0.4/CIN1A/ AD13/DAC1
P0.5/CMPREF/ CLKIN
P0.7/T1/ CLKOUT
P1.0 P1.2, P1.5
P1.0/TXD P1.1/RXD P1.2/T0 P1.5/RST
P1.0 Port Serial port transmitter data. P1.1 Port Serial port receiver data. P1.2 Port Timer/counter external count input overflow/PWM output. P1.5 Port (input-only). External Reset input during Power-on selected UCFG1. When functioning reset input this resets microcontroller, causing ports peripherals take their default states, processor begins execution address Also used during power-on sequence force In-System Programming mode.When using oscillator frequency above MHz, reset input function P1.5 must enabled. external circuit required hold device reset power-up until reached specified level. When system power removed will fall below minimum specified operating voltage. When using oscillator frequency above MHz, some applications, external brownout detect circuit required hold device reset when falls below minimum specified operating voltage. Ground: reference. Power supply: This power supply voltage normal operation well Idle mode Power-down mode.
9397 13919
Koninklijke Philips Electronics N.V. 2004. rights reserved.
User manual
Rev. February 2005
Philips Semiconductors
UM10112
P89LPC9102/9103/9107 User manual
P89LPC9102
ACCELERATED 2-CLOCK 80C51
FLASH internal P1.2, P1.5 PORT CONFIGURABLE I/Os
BYTE AD10 AD11 AD12 AD13 DAC1
ADC1/DAC1
P0[1:5], P0.7
PORT CONFIGURABLE I/Os
REAL-TIME CLOCK/ SYSTEM TIMER CIN1A CIN1B
KBI1 KBI2
KEYPAD INTERRUPT WATCHDOG TIMER OSCILLATOR
TIMER TIMER
ANALOG COMPARATORS
PROGRAMMABLE OSCILLATOR DIVIDER CLKOUT CLKIN
clock POWER MONITOR (POWER-ON RESET, BROWNOUT RESET)
CONFIGURABLE OSCILLATOR
ON-CHIP OSCILLATOR WITH CLOCK DOUBLER OPTION
002aaa967
P89LPC9102 block diagram.
9397 13919
Koninklijke Philips Electronics N.V. 2004. rights reserved.
User manual
Rev. February 2005
Philips Semiconductors
UM10112
P89LPC9102/9103/9107 User manual
P89LPC9103
ACCELERATED 2-CLOCK 80C51
FLASH internal P1.0, P1.1, P1.5 PORT CONFIGURABLE I/Os
UART
BYTE AD10 AD11 AD12 AD13 DAC1
P0[1:5]
PORT CONFIGURABLE I/Os
ADC1/DAC1
KBI1 KBI2
KEYPAD INTERRUPT
REAL-TIME CLOCK/ SYSTEM TIMER
WATCHDOG TIMER OSCILLATOR clock
TIMER TIMER CIN1A CIN1B
PROGRAMMABLE OSCILLATOR DIVIDER
ANALOG COMPARATORS
CLKIN
CONFIGURABLE OSCILLATOR
ON-CHIP OSCILLATOR WITH CLOCK DOUBLER OPTION
POWER MONITOR (POWER-ON RESET, BROWNOUT RESET)
002aaa968
P89LPC9103 block diagram.
9397 13919
Koninklijke Philips Electronics N.V. 2004. rights reserved.
User manual
Rev. February 2005
Philips Semiconductors
UM10112
P89LPC9102/9103/9107 User manual
P89LPC9107
ACCELERATED 2-CLOCK 80C51
FLASH internal
P1[0:2], P1.5
UART
PORT CONFIGURABLE I/Os PORT CONFIGURABLE I/Os
BYTE
AD10 AD11 AD12 AD13 DAC1
P0[1:5], P0.7
ADC1/DAC1
KBI1 KBI2
KEYPAD INTERRUPT WATCHDOG TIMER OSCILLATOR
REAL-TIME CLOCK/ SYSTEM TIMER TIMER TIMER ANALOG COMPARATORS
CIN1A CIN1B
PROGRAMMABLE OSCILLATOR DIVIDER
clock
CLKOUT CLKIN
CONFIGURABLE OSCILLATOR
ON-CHIP OSCILLATOR WITH CLOCK DOUBLER OPTION
POWER MONITOR (POWER-ON RESET, BROWNOUT RESET)
002aab100
P89LPC9107 block diagram
9397 13919
Koninklijke Philips Electronics N.V. 2004. rights reserved.
User manual
Rev. February 2005
Philips Semiconductors
UM10112
P89LPC9102/9103/9107 User manual
Special function registers
Remark: Special Function Registers (SFRs) accesses restricted following ways:
User must attempt access locations defined. Accesses defined locations must strictly functions SFRs. bits labeled `-', only written read follows:
Unless otherwise specified, must written with `0', return value when read (even written with `0'). reserved used future derivatives. must written with `0', will return when read. must written with `1', will return when read.
9397 13919
Koninklijke Philips Electronics N.V. 2004. rights reserved.
User manual
Rev. February 2005
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User manual Rev. February 2005
Koninklijke Philips Electronics N.V. 2004. rights reserved. 9397 13919
Philips Semiconductors
Table P89LPC9102 special function registers indicates SFRs that addressable. Name Description addr. address ACC* ADCON1 ADINS ADMODA ADMODB AD1BH AD1BL AD1DAT0 AD1DAT1 AD1DAT2 AD1DAT3 AUXR1 CMP1 DIVM DPTR FMADRH FMADRL FMCON Accumulator control register input select mode register mode register A/D_1 boundary high register A/D_1 boundary register A/D_1 data register A/D_1 data register A/D_1 data register A/D_1 data register Auxiliary function register register Comparator control register clock divide-by-M control Data pointer bytes) Data pointer high Data pointer Program Flash address high Program Flash address Program Flash Control (Read) Program Flash Control (Write) FMDATA IEN0* Program Flash data Interrupt enable EWDRT BUSY FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. 00000000 00000000 00000000 00000000 00000000 00000000 01110000 CMF1 CLKLP EBRR SRST 00000000 xx000000 00000000 address ENBI1 ADI13 BNDI1 CLK2 ENADCI1 AD12 BURST1 CLK1 TMM1 ADI11 SCC1 CLK0 AD10 SCAN1 ADCI1 ENDAC1 ENADC1 ADCS11 BSA1 functions addresses ADCS10 00[1] 00000000 00000000 00000000 00000000 000x0000 11111111 00000000 00000000 00000000 00000000 00000000 000000x0 Reset value Binary
P89LPC9102/9103/9107 User manual
UM10112
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Table P89LPC9102 special function registers .continued indicates SFRs that addressable. Name Description addr. address IEN1* IP0* IP0H Interrupt enable Interrupt priority Interrupt priority high address address IP1* IP1H KBCON
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functions addresses PADH PWDRT PWDRT CLKOUT/ (P0M1.7) (P0M2.7) RTCPD PBOH CMPREF /CLKIN CIN1A PT1H CIN1B EKBI PT0H PKBI PKBIH PATN _SEL KBIF PMOD0
Reset value 00[1] 00[1] 00[1] Binary 00x00000 x0000000 x0000000
Interrupt priority Interrupt priority high Keypad control register Keypad interrupt mask register Keypad pattern register
address
00[1] 00[1] 00[1]
00x00000 00x00000 xxxxxx00 xxxxx00x xxxxx11x
KBMASK KBPATN
KBMASK KBMASK KBPATN. KBPATN. CIN2A /KBI2 KBI1
Port
address
P0M1 P0M2 P1M1 P1M2 PCON PCONA PCONB
Port Port output mode Port output mode Port output mode Port output mode Power control register Power control register reserved Power control register Program status word Port digital input disable
P89LPC9102/9103/9107 User manual
(P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) BOPD VCPD PT0AD.5 ADPD PT0AD.4 PT0AD.3 (P1M1.2) (P1M2.2) PT0AD.2 PMOD1 PT0AD.1
FF[2] 00[2] 00[1] 00[1]
11111111 00000000 11111111 00000000 00000000 00000000 xxxxxxxx
UM10112
address PSW* PT0AD
00000000 xx00000x
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Table P89LPC9102 special function registers .continued indicates SFRs that addressable. Name RSTSRC RTCCON RTCH RTCL TAMOD TCON*
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User manual
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Description Reset source register Real-time clock control Real-time clock register high Real-time clock register Stack pointer Timer auxiliary mode Timer control Timer high Timer high Timer Timer Timer mode Internal oscillator trim register Watchdog control register Watchdog load Watchdog feed Watchdog feed
addr.
functions addresses RTCF RTCS1 RTCS0 R_WD R_SF ERTC R_EX RTCEN
Reset value
Binary 011xxx00 00000000 00000000 00000111 xxx0xxx0 00000000 00000000 00000000 00000000 00000000 00000000
60[2]
00[6] 00[6] T1M2 T0M2 RCCLK PRE2 ENCLK PRE1 T1M1 TRIM.5 PRE0 T1M0 TRIM.4 TRIM.3 TRIM.2 WDRUN T0M1 TRIM.1 WDTOF T0M0 TRIM.0 WDCLK
address
TMOD TRIM WDCON WFEED1 WFEED2
11111111
P89LPC9102/9103/9107 User manual
Unimplemented bits SFRs (labeled '-') (unknown) times. Unless otherwise specified, ones should written these bits since they used other purposes future derivatives. reset values shown these bits logic although they unknown when read. ports input-only (high-impedance) state after power-up. RSTSRC register reflects cause UM10112 reset. Upon power-up reset, reset source flags cleared except BOF; power-on reset value xx110000. After reset, value 111001x1, i.e., PRE2 PRE0 logic WDRUN WDCLK WDTOF logic after watchdog timer reset logic after power-on reset. Other resets will affect WDTOF. power-on reset, TRIM initialized with factory preprogrammed value. Other resets will cause initialization TRIM register. only reset source that affects these SFRs power-on reset.
UM10112
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User manual Rev. February 2005
Koninklijke Philips Electronics N.V. 2004. rights reserved. 9397 13919
Philips Semiconductors
Table P89LPC9103 special function registers indicates SFRs that addressable. Name Description addr. address ACC* ADCON1 ADINS ADMODA ADMODB AD1BH AD1BL AD1DAT0 AD1DAT1 AD1DAT2 AD1DAT3 AUXR1 BRGR0[3] BRGR1[3] BRGCON CMP1 DIVM DPTR FMADRH FMADRL FMCON Accumulator control register input select mode register mode register A/D_1 boundary high register A/D_1 boundary register A/D_1 data register A/D_1 data register A/D_1 data register A/D_1 data register Auxiliary function register register Baud rate generator rate Baud rate generator rate high Baud rate generator control Comparator control register clock divide-by-M control Data pointer bytes) Data pointer high Data pointer Program Flash address high Program Flash address Program Flash Control (Read) Program Flash Control (Write) BUSY FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. 00000000 00000000 00000000 00000000 01110000 SBRGS BRGEN CMF1 CLKLP EBRR SRST 00[3] 00[2] 00000000 00000000 00000000 xxxxxx00 address ENBI1 ADI13 BNDI1 CLK2 ENADCI1 AD12 BURST1 CLK1 TMM1 ADI11 SCC1 CLK0 AD10 SCAN1 ADCI1 ENDAC1 ENADC1 ADCS11 BSA1 functions addresses ADCS10 00[1] 00000000 00000000 00000000 00000000 000x0000 11111111 00000000 00000000 00000000 00000000 00000000 000000x0 Reset value Binary
P89LPC9102/9103/9107 User manual
xx000000 00000000
UM10112
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Table P89LPC9103 special function registers .continued indicates SFRs that addressable. Name FMDATA IEN0* IEN1* IP0* IP0H Description Program Flash data Interrupt enable Interrupt enable Interrupt priority Interrupt priority high addr. address address address IP1*
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functions addresses PADH EWDRT PWDRT PWDRT PSTH SMOD1 RTCPD SMOD0 PBOH CMPREF /CLKIN ES/ESR PS/PSR /PSRH CIN1A PT1H CIN1B EKBI PT0H PKBI PKBIH PATN _SEL KBIF
Reset value 00[1] 00[1] 00[1] Binary 00000000 00000000 00x00000 x0000000 x0000000
Interrupt priority Interrupt priority high Keypad control register Keypad interrupt mask register Keypad pattern register
address
00[1] 00[1] 00[1]
00x00000 00x00000 xxxxxx00 xxxxx00x xxxxx11x
IP1H KBCON KBMASK KBPATN
KBMASK KBMASK KBPATN. KBPATN. KBI2 KBI1
Port
address
P89LPC9102/9103/9107 User manual
P0M1 P0M2 P1M1 P1M2 PCON PCONA PCONB
Port Port output mode Port output mode Port output mode Port output mode Power control register Power control register reserved Power control register
(P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) BOPD VCPD ADPD
FF[2] 00[1] 00[1]
11111111 00000000 11111111 00000000 00000000 00000000 xxxxxxxx
(P1M1.1) (P1M1.0) PMOD1 PMOD0
UM10112
(P1M2.1) (P1M2.0) 00[2]
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Table P89LPC9103 special function registers .continued indicates SFRs that addressable. Name Description addr. address PSW* PT0AD RSTSRC RTCCON RTCH RTCL SADDR SADEN
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functions addresses RTCF RTCS1 PT0AD.5 RTCS0 PT0AD.4 PT0AD.3 R_BK PT0AD.2 R_WD PT0AD.1 R_SF ERTC R_EX RTCEN
Reset value
Binary 00000000 xx00000x 011xxx00 00000000 00000000 00000000 00000000 xxxxxxxx 00000000 00000000 00000111 00000000 00000000 00000000 00000000 00000000 00000000
Program status word Port digital input disable Reset source register Real-time clock control Real-time clock register high Real-time clock register Serial port address register Serial port address enable Serial port data buffer register Serial port control Serial port extended status register Stack pointer Timer control Timer high Timer high Timer Timer Timer mode Internal oscillator trim register Watchdog control register Watchdog load Watchdog feed Watchdog feed
60[2]
00[7] 00[7] SM0/FE DBMOD INTLO CIDIS DBISEL STINT RCCLK PRE2 ENCLK PRE1 T1M1 TRIM.5 PRE0 T1M0 TRIM.4 TRIM.3 TRIM.2 WDRUN T0M1 TRIM.1 WDTOF T0M0 TRIM.0 WDCLK
SBUF SCON* SSTAT TCON* TMOD TRIM WDCON WFEED1 WFEED2
address address
P89LPC9102/9103/9107 User manual
UM10112
11111111
Unimplemented bits SFRs (labeled '-') (unknown) times. Unless otherwise specified, ones should written these bits since they used other purposes future derivatives. reset values shown these bits logic although they unknown when read.
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ports input-only (high-impedance) state after power-up. BRGR1 BRGR0 must only written BRGEN BRGCON logic written while BRGEN result unpredictable. RSTSRC register reflects cause UM10112 reset. Upon power-up reset, reset source flags cleared except BOF; power-on reset value xx110000. After reset, value 111001x1, i.e., PRE2 PRE0 logic WDRUN WDCLK WDTOF logic 1after watchdog timer reset logic after power-on reset. Other resets will affect WDTOF. power-on reset, TRIM initialized with factory preprogrammed value. Other resets will cause initialization TRIM register. only reset source that affects these SFRs power-on reset. User manual Rev. February 2005
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P89LPC9102/9103/9107 User manual
UM10112
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User manual Rev. February 2005
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Table P89LPC9107 special function registers indicates SFRs that addressable. Name Description addr. address ACC* ADCON1 ADINS ADMODA ADMODB AD1BH AD1BL AD1DAT0 AD1DAT1 AD1DAT2 AD1DAT3 AUXR1 BRGR0[3] BRGR1[3] BRGCON CMP1 DIVM DPTR FMADRH FMADRL FMCON Accumulator control register input select mode register mode register A/D_1 boundary high register A/D_1 boundary register A/D_1 data register A/D_1 data register A/D_1 data register A/D_1 data register Auxiliary function register register Baud rate generator rate Baud rate generator rate high Baud rate generator control Comparator control register clock divide-by-M control Data pointer bytes) Data pointer high Data pointer Program Flash address high Program Flash address Program Flash Control (Read) Program Flash Control (Write) BUSY FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. 00000000 00000000 00000000 00000000 01110000 SBRGS BRGEN CMF1 CLKLP EBRR ENT1 ENT0 SRST 00[3] 00[2] 00000000 00000000 00000000 xxxxxx00 address ENBI1 ADI13 BNDI1 CLK2 ENADCI1 AD12 BURST1 CLK1 TMM1 ADI11 SCC1 CLK0 EDGE1 AD10 SCAN1 ADCI1 ENDAC1 ENADC1 ADCS11 BSA1 functions addresses ADCS10 00[1] 00000000 00000000 00000000 00000000 000x0000 11111111 00000000 00000000 00000000 00000000 00000000 000000x0 Reset value Binary
P89LPC9102/9103/9107 User manual
xx000000 00000000
UM10112
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Table P89LPC9107 special function registers .continued indicates SFRs that addressable. Name FMDATA IEN0* IEN1* IP0* IP0H Description Program Flash data Interrupt enable Interrupt enable Interrupt priority Interrupt priority high addr. address address address IP1*
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functions addresses PADH EWDRT PWDRT PWDRT PSTH SMOD1 RTCPD SMOD0 PBOH CMPREF /CLKIN ES/ESR PS/PSR /PSRH CIN1A PT1H CIN1B EKBI PT0H PKBI PKBIH PATN _SEL KBIF
Reset value 00[1] 00[1] 00[1] Binary 00000000 00000000 00x00000 x0000000 x0000000
Interrupt priority Interrupt priority high Keypad control register Keypad interrupt mask register Keypad pattern register
address
00[1] 00[1] 00[1]
00x00000 00x00000 xxxxxx00 xxxxx00x xxxxx11x
IP1H KBCON KBMASK KBPATN
KBMASK KBMASK KBPATN. KBPATN. KBI2 KBI1
Port
address
P89LPC9102/9103/9107 User manual
P0M1 P0M2 P1M1 P1M2 PCON PCONA PCONB
Port Port output mode Port output mode Port output mode Port output mode Power control register Power control register reserved Power control register
(P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) BOPD VCPD ADPD
FF[2] 00[1] 00[1]
11111111 00000000 11111111 00000000 00000000 00000000 xxxxxxxx
(P1M1.1) (P1M1.0) PMOD1 PMOD0
UM10112
(P1M2.1) (P1M2.0) 00[2]
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Table P89LPC9107 special function registers .continued indicates SFRs that addressable. Name Description addr. address PSW* PT0AD RSTSRC RTCCON RTCH RTCL SADDR SADEN
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functions addresses RTCF RTCS1 PT0AD.5 RTCS0 PT0AD.4 PT0AD.3 R_BK PT0AD.2 R_WD PT0AD.1 R_SF ERTC R_EX RTCEN
Reset value
Binary 00000000 xx00000x 011xxx00 00000000 00000000 00000000 00000000 xxxxxxxx 00000000 00000000 00000111 00000000 00000000 00000000 00000000 00000000 00000000
Program status word Port digital input disable Reset source register Real-time clock control Real-time clock register high Real-time clock register Serial port address register Serial port address enable Serial port data buffer register Serial port control Serial port extended status register Stack pointer Timer control Timer high Timer high Timer Timer Timer mode Internal oscillator trim register Watchdog control register Watchdog load Watchdog feed Watchdog feed
60[2]
00[7] 00[7] SM0/FE DBMOD INTLO CIDIS DBISEL STINT RCCLK PRE2 ENCLK PRE1 T1M1 TRIM.5 PRE0 T1M0 TRIM.4 TRIM.3 TRIM.2 WDRUN T0M1 TRIM.1 WDTOF T0M0 TRIM.0 WDCLK
SBUF SCON* SSTAT TCON* TMOD TRIM WDCON WFEED1 WFEED2
address address
P89LPC9102/9103/9107 User manual
UM10112
11111111
Unimplemented bits SFRs (labeled '-') (unknown) times. Unless otherwise specified, ones should written these bits since they used other purposes future derivatives. reset values shown these bits logic although they unknown when read.
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ports input-only (high-impedance) state after power-up. BRGR1 BRGR0 must only written BRGEN BRGCON logic written while BRGEN result unpredictable. RSTSRC register reflects cause UM10112 reset. Upon power-up reset, reset source flags cleared except BOF; power-on reset value xx110000. After reset, value 111001x1, i.e., PRE2 PRE0 logic WDRUN WDCLK WDTOF logic 1after watchdog timer reset logic after power-on reset. Other resets will affect WDTOF. power-on reset, TRIM initialized with factory preprogrammed value. Other resets will cause initialization TRIM register. only reset source that affects these SFRs power-on reset. User manual Rev. February 2005
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Memory organization
03FFh 0300h 02FFh 0200h 01FFh 0100h 00FFh 000h flash code memory space SECTOR SECTOR SECTOR SECTOR
SPECIAL FUNCTION REGISTERS (DIRECTLY ADDRESSABLE)
DATA
BYTES ON-CHIP DATA MEMORY (STACK, DIRECT INDIRECT ADDRESS) REG. BANKS R[7:0]
data memory (DATA, IDATA)
002aab049
P89LPC9102/9103/9107 memory map.
various P89LPC9102/9103/9107 memory spaces follows: DATA bytes internal data memory space (00h:7Fh) accessed direct indirect addressing, using instruction other than MOVX MOVC. part Stack this area. Special Function Registers. Selected registers peripheral control status registers, accessible only direct addressing. CODE Code memory space, accessed part program execution MOVC instruction. P89LPC9102/9103/9107 on-chip Code memory.
Table Type DATA Data arrangement Data Directly indirectly addressable memory Size (bytes)
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Clocks
Enhanced
P89LPC9102/9103/9107 uses enhanced 80C51 which runs times speed standard 80C51 devices. machine cycle consists clock cycles, most instructions execute machine cycles.
Clock definitions
P89LPC9102/9103/9107 device several internal clocks defined below: OSCCLK Input DIVM clock divider. OSCCLK selected from clock sources also optionally divided slower frequency (see Figure Section "CCLK modification: DIVM register"). Note: fosc defined OSCCLK frequency. CCLK clock; output DIVM clock divider. There CCLK cycles machine cycle, most instructions executed machine cycles (two four CCLK cycles). RCCLK internal 7.373 oscillator output (14.7456 with clock doubler enabled). PCLK Clock various peripheral devices CCLK/2.
Clock output
P89LPC9102/9103/9107 supports user-selectable clock output function CLKOUT allowing external devices synchronize P89LPC9102/9103/9107. This output enabled ENCLK TRIM register. frequency this clock output that CCLK. clock output needed Idle mode, turned prior entering Idle, saving additional power. Note: reset, TRIM initialized with factory preprogrammed value. Therefore when setting clearing ENCLK bit, user should retain contents other bits TRIM register. This done reading contents TRIM register (into example), modifying writing this result back into TRIM register. Alternatively, `ANL direct' `ORL direct' instructions used clear TRIM register.
On-chip oscillator option with clock doubler mode
P89LPC9102/9103/9107 TRIM register that used tune frequency oscillator. During reset, TRIM value initialized factory pre-programmed value adjust oscillator frequency 7.373 MHz, (Note: initial value better than please refer data sheet behavior over temperature). user applications write TRIM register adjust on-chip oscillator other frequencies. Increasing TRIM value will decrease oscillator frequency. P89LPC9102/9103/9107 clock doubling mode that doubles frequency provided internal oscillator 14.7456 MHz. This mode enabled when IRCDBL (UCFG1.3) set.
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Table Symbol Reset Table
On-chip oscillator trim register (TRIM address 96h) allocation RCCLK ENCLK TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0
Bits loaded with factory stored value during reset.
On-chip oscillator trim register (TRIM address 96h) description Symbol TRIM.0 TRIM.1 TRIM.2 TRIM.3 TRIM.4 TRIM.5 ENCLK RCCLK when CCLK/2 output CLKOUT when selects Oscillator output clock (CCLK) Description Trim value. Determines frequency internal oscillator. During reset, these bits loaded with stored factory calibration value. When writing either this register, care should taken preserve current TRIM value reading this register, modifying bits required, writing result this register.
Watchdog oscillator option
Watchdog separate oscillator which frequency kHz. This oscillator used save power when high clock frequency needed.
External clock input option
this configuration, processor clock derived from external source driving P0.5/CMPREF/CLKIN pin. rate from MHz. This also used standard port pin. When using external clock input frequency above MHz, reset input function P1.5 must enabled. external circuit required hold device reset power-up until reached specified level. When system power removed will fall below minimum specified operating voltage. When using external clock input frequency above MHz, some applications, external brownout detect circuit required hold device reset when falls below minimum specified operating voltage. These requirements clock frequencies above apply when using internal oscillator clock doubler mode.
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ADC1/ DAC1 OSCCLK DIVM CCLK
CLKIN OSCILLATOR WITH CLOCK DOUBLER OPTION (7.3728 14.7456 MHz) WATCHDOG OSCILLATOR (400 kHz) PCLK
TIMER TIMER
002aaa973
Block diagram P89LPC9102 oscillator control.
ADC1/ DAC1 OSCCLK DIVM CCLK
CLKIN OSCILLATOR WITH CLOCK DOUBLER OPTION (7.3728 14.7456 MHz) WATCHDOG OSCILLATOR (400 kHz) PCLK
TIMER TIMER
BAUD RATE GENERATOR
UART
002aaa974
Block diagram P89LPC9103, P89LPC9107 oscillator control.
Clock (CCLK) wake-up delay
P89LPC9102/9103/9107 internal wake-up timer that delays clock until stabilizes depending clock source used.
CCLK modification: DIVM register
OSCCLK frequency divided down, integer, times configuring dividing register, DIVM, provide CCLK. This produces CCLK frequency using following formula: CCLK frequency fosc (2N) Where: fosc frequency OSCCLK
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value DIVM. Since ranges from 255, CCLK frequency range fosc fosc/510. (for CCLK fosc). This feature makes possible temporarily lower rate, reducing power consumption. dividing clock, retain ability respond events other than those that cause interrupts (i.e., events that allow exiting Idle mode) executing normal program lower rate. This often result lower power consumption than Idle mode. This allow bypassing start-up time cases where Power-down mode would otherwise used. value DIVM changed program time without interrupting code execution.
power select
P89LPC9102/9103/9107 designed (CCLK) maximum. However, CCLK slower, CLKLP (AUXR1.7) logic lower power consumption further. reset, CLKLP logic allowing highest performance. This then software CCLK running slower.
converter
P89LPC9102/9103/9107 8-bit, 4-channel, multiplexed successive approximation analog-to-digital converter module (ADC1) module (DAC1). block diagram converter shown Figure consists 4-input multiplexer which feeds sample hold circuit providing input signal comparator inputs. control logic combination with successive approximation register (SAR) drives digital-to-analog converter which provides other input comparator. output comparator SAR.
comp INPUT CONTROL LOGIC
DAC1
CCLK
002aaa975
converter block diagram.
Features 8-bit, 4-channel, multiplexed input, successive approximation converter Four result registers operating modes
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Fixed channel, single conversion mode Fixed channel, continuous conversion mode Auto scan, single conversion mode Auto scan, continuous conversion mode Dual channel, continuous conversion mode Single step mode
Three conversion start modes
Timer triggered start Start immediately Edge triggered
8-bit conversion time clock Interrupt polled operation Boundary limits interrupt output port with high output impedance Clock divider Power-down mode
operating modes
3.2.1 Fixed channel, single conversion mode
single input channel selected conversion. single conversion will performed result placed result register which corresponds selected input channel (See Table 10). interrupt, enabled, will generated after conversion completes. input channel selected ADINS register. This mode selected setting SCAN1 ADMODA register.
Table Input channels Result registers fixed channel single, auto scan single, autoscan continuous conversion modes. Input channel AD10 AD11 Result register AD1DAT2 AD1DAT3 Input channel AD12 AD13
Result register AD1DAT0 AD1DAT1
3.2.2 Fixed channel, continuous conversion mode
single input channel selected continuous conversion. results conversions will sequentially placed four result registers Table interrupt, enabled, will generated after every four conversions. Additional conversion results will again cycle through four result registers, overwriting previous results. Continuous conversions continue until terminated user. This mode selected setting SCC1 ADMODA register.
3.2.3 Auto scan, single conversion mode
combination four input channels selected conversion setting channel's respective ADINS register. channels converted from order ADINS). single conversion each selected input will performed result placed result register which corresponds selected input channel
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(See Table 10). interrupt, enabled, will generated after selected channels have been converted. only single channel selected this equivalent single channel, single conversion mode. This mode selected setting SCAN1 ADMODA register.
Table Result registers conversion results fixed channel, continuous conversion mode. Contains Selected channel, first conversion result Selected channel, second conversion result Selected channel, third conversion result Selected channel, forth conversion result
Result register AD1DAT0 AD1DAT1 AD1DAT2 AD1DAT3
3.2.4 Auto scan, continuous conversion mode
combination four input channels selected conversion setting channel's respective ADINS register. channels converted from order ADINS). conversion each selected input will performed result placed result register which corresponds selected input channel (See Table 10). interrupt, enabled, will generated after selected channels have been converted. process will repeat starting with first selected channel. Additional conversion results will again cycle through result registers selected channels, overwriting previous results. Continuous conversions continue until terminated user. This mode selected setting BURST1 ADMODA register.
3.2.5 Dual channel, continuous conversion mode
combination four input channels selected conversion. result conversion first channel placed first result register. result conversion second channel placed second result register. first channel again converted result stored third result register. second channel again converted result placed fourth result register (See Table 12). interrupt generated, enabled, after every four conversions (two conversions channel). This mode selected setting SCC1 ADMODA register.
Table Result registers conversion results dual channel, continuous conversion mode. Contains First channel, first conversion result Second channel, first conversion result First channel, second conversion result Second channel, second conversion result
Result register AD1DAT0 AD1DAT1 AD1DAT2 AD1DAT3
3.2.6 Single step
This special mode allows `single-stepping' auto scan conversion mode. combination four input channels selected conversion. After each channel converted, interrupt generated, enabled, waits next start condition. result each channel placed result register which corresponds
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selected input channel (See Table 10). used with start modes. This mode selected clearing BURST1, SCC1, SCAN1 bits ADMODA register.
3.2.7 Conversion mode selection bits
uses three bits ADMODA select conversion mode. These mode bits summarized Table below. Combinations three bits, other than combinations shown, undefined.
Table Conversion mode bits. Scan1 ADC1 conversion BURST0 SCC0 mode single step fixed channel,single auto scan, single fixed channel, continuous dual channel, continuous auto scan, continuous Scan0 ADC0 conversion mode single step fixed channel,single auto scan, single fixed channel, continuous dual channel, continuous auto scan, continuous
BURST1 SCC1
Trigger modes
3.3.1 Timer triggered start
conversion started overflow Timer Once conversion started, additional Timer triggers ignored until conversion completed. Timer triggered start mode available operating modes. This mode selected TMM1 ADCS11 ADCS10 bits (See Table 15).
3.3.2 Start immediately
Programming this mode immediately starts conversion. This start mode available operating modes. This mode selected setting ADCS11 ADCS10 bits ADCON1 register (See Table 15).
3.3.3 Edge triggered
conversion started rising falling edge P1.4. Once conversion started, additional edge triggers ignored until conversion completed. edge triggered start mode available operating modes. This mode selected setting ADCS11 ADCS10 bits ADCON1 register (See Table 15).
3.3.4 Boundary limits interrupt
converter both HIGH boundary limit register. After four MSBs have been converted, these four bits compared with four MSBs boundary HIGH registers. four MSBs conversion outside limit interrupt will generated, enabled. conversion result within limits,
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boundary limits will again compared after eight bits have been converted. interrupt will generated, enabled, result outside boundary limits. boundary limit disabled clearing boundary limit interrupt enable.
output port with high-impedance
AD0DAT3 register used hold value DAC. After value been written AD0DAT3 output will appear DAC0 pin. output enabled ENDAC0 ADMODB register (See Table 19).
Clock divider
converter requires that internal clock source range maintain accuracy. programmable clock divider that divides clock from provided this purpose (See Table 19).
pins used with converter functions
analog input pins used with converter have digital input output function. order give best analog performance, pins that being used with should have their digital outputs inputs disabled have tolerance disconnected. Digital outputs disabled putting port pins into input-only mode described Port Configurations section (see Table 25). Digital inputs will disconnected automatically from these pins when been selected setting corresponding ADINS register been enabled. Pins selected ADINS will tolerant provided that enabled device power-down, otherwise will remain tolerant.
Power-down idle mode
idle mode converter, enabled, will continue function cause device exit idle mode when conversion completed interrupt enabled. Power-down mode Total Power-down mode, does function. enabled, will consume power. Power reduced disabling A/D.
Table Symbol Reset Table Control register (ADCON1 address 97h) allocation ENBI1 ENADCI1 TMM1 ADCI1 ENADC1 ADCS11 ADCS10
Control register (ADCON1 address 97h) description Symbol ADCS10 ADCS11 Description start mode bits [11:10]: Timer Trigger Mode when TMM1 Conversions starts overflow Timer Stop mode when TMM1 start occurs. Immediate Start Mode. Conversions starts immediately. Reserved.
ENADC1
Enable channel When enables ADC1. Must also operation this channel.
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Table
Control register (ADCON1 address 97h) description Symbol ADCI1 TMM1 ENADCI1 ENBI1 Description Conversion complete Interrupt when conversion multiple conversions completed. Cleared software. reserved Timer Trigger Mode Selects either stop mode (TMM1 timer trigger mode (TMM1 when ADCS11 ADCS10 bits Enable Conversion complete Interrupt When set, will cause interrupt ADCI1 flag interrupt enabled. Enable boundary interrupt When set, will cause interrupt boundary interrupt flag, BNDI1, interrupt enabled.
Table Symbol Reset Table
Mode Register (ADMODA address C0h) allocation BNBI1 BURST1 SCC1 SCAN1
Mode Register (ADMODA address C0h) description Symbol SCAN1 SCC1 BURST1 BNBI1 Description reserved when selects single conversion mode (auto scan fixed channel) ADC1 when selects fixed channel, continuous conversion mode ADC1 when selects auto scan, continuous conversion mode ADC1 ADC1 boundary interrupt flag. When set, indicates that converted result from ADC1 outside range defined ADC1 boundary registers
Table Symbol Reset Table
Mode Register (ADMODB address A1h) allocation CLK2 CLK1 CLK0 ENDAC1 BSA1
Mode Register (ADMODB address A1h) description Symbol BSA1 Description reserved ADC1 Boundary Select All. When BNDI1 will ADC1 input exceeds boundary limits. When BNDI1 will only AD10 input exceeded boundary limits. reserved When selects mode ADC1; when selects mode. reserved
ENDAC1
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Table
Mode Register (ADMODB address A1h) description Symbol CLK0 CLK1 CLK2 Description Clock divider produce clock. Divides CCLK value indicated below. resulting clock should less. minimum required maintain accuracy. CLK2:0 divisor
Table Symbol Reset Table
Input Select register (ADINS address A3h) allocation AIN13 AIN12 AIN11 AIN10
Input Select register (ADINS address A3h) description Symbol AIN10 AIN11 AIN12 AIN13 Description reserved when set, enables AD10 sampling conversion when set, enables AD11 sampling conversion when set, enables AD12 sampling conversion when set, enables AD13 sampling conversion
Interrupts
P89LPC9102 supports nine interrupt sources: timers brownout detect, watchdog timer/RTC, keyboard, comparator converter. P89LPC9103 supports nine interrupt sources: timers serial port serial port combined serial port Rx/Tx, brownout detect, watchdog timer/RTC, keyboard, comparator, converter. Each interrupt source individually enabled disabled setting clearing interrupt enable registers IEN0 IEN1. IEN0 register also contains global disable bit, which disables interrupts. Each interrupt source individually programmed four priority levels setting clearing bits interrupt priority registers IP0, IP0H, IP1, IP1H. interrupt service routine progress interrupted higher priority interrupt, another interrupt same lower priority. highest priority interrupt service cannot interrupted other interrupt source. requests different priority levels pending start instruction, request higher priority level serviced.
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requests same priority level pending start instruction, internal polling sequence determines which request serviced. This called arbitration ranking. Note that arbitration ranking only used resolve pending requests same priority level.
Interrupt priority structure
Table IPxH Interrupt priority level Interrupt priority level Level (lowest priority) Level Level Level Priority bits
There four SFRs associated with four interrupt levels: IP0, IP0H, IP1, IP1H. Every interrupt bits IPxH 0,1) therefore assigned four levels, shown Table
Table Summary interrupts Interrupt flag bit(s) KBIF CMF1 ADCI1,BNDI1 002Bh 0053h 003Bh 0043h 006Bh 0073h (IEN0.5) EWDRT (IEN0.6) EKBI (IEN1.1) (IEN1.2) (IEN1.6) (IEN1.7) IP0H.5,IP0.5 IP0H.6,IP0.6 IP0H.0,IP0.0 IP0H.0,IP0.0 IP0H.0,IP0.0 IP1H.7,IP1.7 (lowest) Vector address 000Bh 001Bh 0023h Interrupt enable bit(s) (IEN0.1) (IEN0.3) ES/ESR (IEN0.4) Interrupt priority IP0H.1,IP0.1 IP0H.3,IP0.3 IP0H.4,IP0.4 Arbitration Powerranking down wake-up
Description
Timer interrupt Timer interrupt Serial port (9103, 9107) Serial port (9103, 9107) Brownout detect interrupt Comparator interrupt Serial port (9103, 9107)
Watchdog timer/Real-time clock WDOVF/RTCF
4.1.1 External interrupt inputs
P89LPC9102/9103/9107 Keypad Interrupt function. This used external interrupt input. enabled when P89LPC9102/9103/9107 into Power-down mode Idle mode, interrupt will cause processor wake-up resume operation. Refer Section "Power reduction modes" details.
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RTCF ERTC (RTCCON.1) WDOVF KBIF EKBI EWDRT (IE0.7) interrupt wake-up power-down)
ENADCI1 ADCI1 ENBI1 BNDI1
002aaa976
Interrupt sources, interrupt enables, power-down wake-up sources (P89LPC9102).
RTCF ERTC (RTCCON.1) WDOVF KBIF EKBI EWDRT (IE0.7) RI/RI ES/ESR ENADCI1 ADCI1 ENBI1 BNDI1
002aaa977
wake-up power-down)
interrupt
Interrupt sources, interrupt enables, power-down wake-up sources (P89LPC9103/P89LPC9107).
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ports
P89LPC9102/9103/9107 three ports: Port Port Port Ports 8-bit ports Port 2-bit port. exact number pins available depends upon clock reset options chosen (see Table 24).
Table Number pins available Reset option Number pins (8-pin package) Number pins (8-pin package)
Clock source
On-chip oscillator watchdog oscillator external reset (except during power-up) External supported External clock input Clock source On-chip oscillator watchdog oscillator
external reset (except during power-up) External supported[1] Reset option external reset (except during power-up)
Required operation with external clock frequency above MHz.
Port configurations
port P89LPC9102/9103/9107 configured software four types pin-by-pin basis, shown Table These are: quasi-bidirectional (standard 80C51 port outputs), push-pull, open drain, input-only. configuration registers each port select output type each port pin. P1.5 (RST) only input cannot configured.
Table PxM1.y Port output configuration settings PxM2.y Port output mode Quasi-bidirectional Push-pull Input only (high-impedance) Open drain
Quasi-bidirectional output configuration
Quasi-bidirectional outputs used both input output without need reconfigure port. This possible because when port outputs logic HIGH, weakly driven, allowing external device pull LOW. When driven LOW, driven strongly able sink large current. There three pull-up transistors quasi-bidirectional output that serve different purposes. these pull-ups, called `very weak' pull-up, turned whenever port latch contains logic This very weak pull-up sources very small current that will pull HIGH left floating. second pull-up, called `weak' pull-up, turned when port latch contains logic itself also logic level. This pull-up provides primary source current quasi-bidirectional that outputting this pulled external device, weak pull-up turns off, only very weak
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pull-up remains order pull under these conditions, external device sink enough current overpower weak pull-up pull port below input threshold voltage. third pull-up referred `strong' pull-up. This pull-up used speed LOW-to-HIGH transitions quasi-bidirectional port when port latch changes from logic logic When this occurs, strong pull-up turns clocks quickly pulling port HIGH. quasi-bidirectional port configuration shown Figure Although P89LPC9102/9103/9107 device most pins V-tolerant. applied configured quasi-bidirectional mode, there will current flowing from causing extra power consumption. Therefore, applying pins configured quasi-bidirectional mode discouraged. quasi-bidirectional port Schmitt triggered input that also glitch suppression circuit. (Please refer P89LPC9102/9103/9107 data sheet, Dynamic characteristics glitch filter specifications).
CLOCK DELAY
strong
very weak
weak
PORT port latch data
input data glitch rejection
002aaa914
Quasi-bidirectional output.
Open drain output configuration
open drain output configuration turns pull-ups only drives pull-down transistor port when port latch contains logic used logic output, port configured this manner must have external pull-up, typically resistor tied VDD. pull-down this mode same quasi-bidirectional mode. open drain port configuration shown Figure open drain port Schmitt triggered input that also glitch suppression circuit.
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Please refer P89LPC9102/9103/9107 data sheet, Dynamic characteristics glitch filter specifications.
PORT port latch data
input data glitch rejection
002aaa915
Open drain output.
Input-only configuration
input port configuration shown Figure Schmitt triggered input that also glitch suppression circuit. (Please refer P89LPC9102/9103/9107 data sheet, Dynamic characteristics glitch filter specifications).
input data glitch rejection
PORT
002aaa916
Input only.
Push-pull output configuration
push-pull output configuration same pull-down structure both open drain quasi-bidirectional output modes, provides continuous strong pull-up when port latch contains logic push-pull mode used when more source current needed from port output. push-pull port configuration shown Figure push-pull port Schmitt triggered input that also glitch suppression circuit. (Please refer P89LPC9102/9103/9107 data sheet, Dynamic characteristics glitch filter specifications).
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strong
port latch data
PORT
input data
glitch rejection
002aaa917
Push-pull output.
Port analog functions
P89LPC9102/9103/9107 incorporates Analog Comparator. order give best analog performance minimize power consumption, pins that being used analog functions must have both digital outputs digital inputs disabled. Digital outputs disabled putting port pins into input-only mode described Port Configurations section (see Figure 18). Digital inputs Port disabled through PT0AD register. Bits through this register correspond pins P0.1 through P0.5 Port respectively. Setting corresponding PT0AD disables that pin's digital input. Port bits that have their digital inputs disabled will read logic instruction that accesses port. reset, PT0AD bits through default logic enable digital functions.
Additional port features
After power-up, pins Input-Only mode. Please note that this different from LPC76x series devices.
After power-up, pins except P1.5, configured software. P1.5 input only.
Every output P89LPC9102/9103/9107 been designed sink typical drive current. However, there maximum total output current ports which must exceeded. Please refer P89LPC9102/9103/9107 data sheet detailed specifications. ports pins that function output have slew rate controlled outputs limit noise generated quickly switching output signals. slew rate factory-set approximately rise fall times.
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Port output configuration Configuration bits PxM1.y PxM2.y P0M2.1 P0M2.2 P0M2.3 P0M2.4 P0M2.5 P0M2.7 P1M2.0 P1M2.1 P1M2.2 P1M2.5 Alternate usage KBI1, AD10 KBI2, AD11 KBI3, CIN1B, AD12 CIN1A, AD13, DAC1 KBI5, CMPREF, CLKIN CLKOUT Notes Refer Section "Port analog functions" usage analog inputs. P0M1.1 P0M1.2 P0M1.3 P0M1.4 P0M1.5 P0M1.7 P1M1.0 P1M1.1 P1M1.2 P1M1.5
Table Port P0.1 P0.2 P0.3 P0.4 P0.5 P0.7 P1.0 P1.1 P1.2 P1.5
Power monitoring functions
P89LPC9102/9103/9107 incorporates power monitoring functions designed prevent incorrect operation during initial power-on power loss reduction during operation. This accomplished with hardware functions: Power-on Detect Brownout Detect.
Brownout detection
Brownout Detect function determines power supply voltage drops below certain level. default operation Brownout Detection cause processor reset. However, alternatively configured generate interrupt setting (PCON.4) (IEN0.5) bit. Enabling disabling Brownout Detection done BOPD (PCON.5) bit, field PMOD1-0 (PCON.1-0) user configuration (UCFG1.5). unprogrammed state, brownout disabled regardless PMOD1-0 BOPD. programmed state, PMOD1-0 BOPD will used determine whether Brownout Detect will disabled enabled. PMOD1-0 used select power reduction mode. PMOD1-0 `11', circuitry Brownout Detection disabled lowest power consumption. BOPD defaults logic indicating brownout detection enabled power-on programmed. Brownout Detection enabled, brownout condition occurs when falls below Brownout trip voltage, (see P89LPC9102/9103 Static characteristics), negated when rises above VBO. Brownout Detection disabled, operating voltage range P89LPC9102/9103/9107 device operate with power supply that below should left unprogrammed state that device operate otherwise continuous brownout reset prevent device from operating.
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application that uses internal oscillator clock doubler mode uses Brownout detect should program that brownout condition will detected when falls below Brownout Detect enabled (BOE programmed, PMOD1-0 `11', BOPD (RSTSRC.5) will when brownout detected, regardless whether reset interrupt enabled. will stay until cleared software writing logic bit. Note that unprogrammed, meaningless. programmed, initial power-on occurs, will addition power-on flag (POF RSTSRC.4). correct activation Brownout Detect, certain rise fall times must observed. Please P89LPC9102/9103 Data sheet specifications.
Table (UCFG1.5) (erased) 1(program med) Brownout options PMOD1-0 (PCON.1-0) (total power-down) (any mode other than total power-down BOPD (PCON.5) 1(brownout detect powered down) (brownout detect active) (PCON.4) (IEN0.5) (IEN0.7) Description Brownout disabled. operating range Brownout disabled. operating range However, BOPD default logic upon power-up. Brownout reset enabled. operating range Upon brownout reset, (RSTSRC.5) will indicate reset source. cleared writing logic bit. Brownout interrupt enabled. operating range Upon brownout interrupt, (RSTSRC.5) will set. cleared writing logic bit. Both brownout reset interrupt disabled. operating range However, (RSTSRC.5) will when falls Brownout Detection trip point. cleared writing logic bit.
(brownout detect generates reset)
(brownout detect generates interrupt)
(enable brownout interrupt)
(global interrupt enable)
Power-on detection
Power-On Detect function similar Brownout Detect, designed work power initially comes before power supply voltage reaches level where Brownout Detect function. flag (RSTSRC.4) indicate initial power-on condition. flag will remain until cleared software writing logic bit. Note that (UCFG1.5) programmed, (RSTSRC.5) will when set. unprogrammed, meaningless.
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Power reduction modes
P89LPC9102/9103/9107 supports three different power reduction modes determined bits PCON.1-0 (see Table 28).
Table Power reduction modes
PMOD1 PMOD0 Description (PCON.1) (PCON.0) Normal mode (default) power reduction. Idle mode. Idle mode leaves peripherals running order allow them activate processor when interrupt generated. enabled interrupt source reset terminate Idle mode. Power-down mode: Power-down mode stops oscillator order minimize power consumption. P89LPC9102/9103/9107 exits Power-down mode reset, certain interrupts, brownout Interrupt, keyboard, Real-time Clock/System Timer), Watchdog, comparator trips. Waking reset only enabled corresponding reset enabled, waking interrupt only enabled corresponding interrupt enabled (IEN0.7) set. Power-down mode internal oscillator disabled unless both oscillator been selected system clock enabled. Power-down mode, power supply voltage reduced keep-alive voltage VRAM. This retains contents point where Power-down mode entered. contents guaranteed after been lowered VRAM, therefore recommended wake processor Reset this situation. must raised within operating range before Power-down mode exited. When processor wakes from Power-down mode, will start oscillator immediately begin execution when oscillator stable. Oscillator stability determined counting clocks after start-up internal external clock input configurations. Some chip functions continue operate draw power during Power-down mode, increasing total power used during power-down. These include:
Brownout Detect Watchdog timer WDCLK (WDCON.0) logic Comparator (Note: Comparator powered down separately with PCONA.5 logic comparator disabled) Real-time Clock/System Timer (unless RTCPD logic
Total Power-down mode: This same Power-down mode except that Brownout Detection circuitry voltage comparator also disabled conserve additional power. Note that brownout reset interrupt will occur. Voltage comparator interrupt Brownout interrupt cannot used wake-up source. internal oscillator disabled unless both oscillator been selected system clock enabled. following wake-up options supported:
Watchdog timer WDCLK (WDCON.0) logic Could generate Interrupt Reset, either wake device Keyboard Interrupt Real-time Clock/System Timer (unless RTCPD, i.e., PCONA.7 logic
Note: Using internal RC-oscillator clock during power-down result relatively high power consumption. Lower power consumption achieved using external frequency clock when Real-time Clock running during power-down.
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Table Symbol Reset Table
Power Control register (PCON address 87h) allocation SMOD1 SMOD0 BOPD PMOD1 PMOD0
Power Control register (PCON address 87h) description Symbol PMOD0 PMOD1 BOPD General Purpose Flag read written user software, effect operation General Purpose Flag read written user software, effect operation Brownout Detect Interrupt Enable. When logic Brownout Detection will generate interrupt. When logic Brownout Detection will cause reset Brownout Detect power-down. When logic Brownout Detect powered down therefore disabled. When logic Brownout Detect enabled. (Note: BOPD must logic before programming erasing commands issued. Otherwise these commands will aborted.) Framing Error Location: Description Power Reduction Mode (see Section 6.3)
SMOD0
SMOD1
When logic SCON accessed UART When logic SCON accessed framing error status (FE) UART (P89LPC9103)
Double Baud Rate serial port (UART) when Timer used baud rate source. When logic Timer overflow rate supplied UART. When logic Timer overflow rate divided before being supplied UART. (See Section (P89LPC9103)
Table Symbol Reset Table
Power Control register (PCONA address B5h) allocation RTCPD VCPD ADPD
Power Control register (PCONA address B5h) description Symbol Description reserved Serial Port (UART) power-down: When logic internal clock UART disabled. Note that either Power-down mode Total Power-down mode, UART clock will disabled regardless this (P89LPC9103). reserved reserved Converter power-down: When logic turns clock ADC. fully power-down ADC, user should also ENADC1 ENADC0 bits registers ADCON1 ADCON0.
ADPD
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Table
Power Control register (PCONA address B5h) description Symbol VCPD RTCPD Description Analog Voltage Comparator power-down: When logic voltage comparator powered down. User must disable voltage comparator prior setting this bit. reserved Real-time Clock power-down: When logic internal clock Real-time Clock disabled.
Reset
P1.5/RST function either active reset input digital input, P1.5. (Reset Enable) UCFG1, when enables external reset input function P1.5. When cleared, P1.5 used input pin. NOTE: During power-on sequence, selection overridden this will always functions reset input. external circuit connected this should hold this during Power-on sequence this will keep device reset. After power-on this input will function either external reset input digital input defined bit. Only power-on reset will temporarily override selection defined bit. Other sources reset will override bit. NOTE: During power cycle, must fall below VPOR (see P89LPC9102/9103 Data sheet, Static characteristics) before power reapplied, order ensure power-on reset. Reset triggered from following sources (see Figure 20):
External reset (during power-on user configured UCFG1. Required
external clock frequency above MHz.)
Power-on Detect Brownout Detect Watchdog timer Software reset UART break detect reset (P89LPC9103,P89LPC9107)
every reset source, there flag Reset Register, RSTSRC. user read this register determine most recent reset source. These flag bits cleared software writing logic corresponding bit. More than flag set:
During power-on reset, both other flag bits
cleared.
other reset, previously flag bits that have been cleared will remain
set.
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(UCFG1.6) WDTE (UCFG1.7) watchdog timer reset software reset SRST (AUXR1.3) chip reset power-on detect UART break detect EBRR (AUXR1.6) brownout detect reset BOPD (PCON.5)
002aab050
P89LPC9103, P89LPC9107
Block diagram reset. Table Symbol Reset[1]
Reset Sources register (RSTSRC address DFh) allocation R_BK R_WD R_SF R_EX
value shown power-on reset. Other reset sources will their corresponding bits.
Table R_EX
Reset Sources register (RSTSRC address DFh) description Description external reset Flag. When this logic indicates external reset. Cleared software writing logic Power-on reset. still asserted after Power-on reset over, R_EX will set. software reset Flag. Cleared software writing logic Power-on reset Watchdog timer reset flag. Cleared software writing logic Power-on reset.(NOTE: UCFG1.7 must break detect reset. break detect occurs EBRR (AUXR1.6) logic system reset will occur. This indicate that system reset caused break detect. Cleared software writing logic Power-on reset (P89LPC9103, P89LPC9107). Power-on Detect Flag. When Power-on Detect activated, flag indicate initial power-up condition. flag will remain until cleared software writing logic bit. (Note: Power-on reset, both this will while other flag bits cleared.) Brownout Detect Flag. When Brownout Detect activated, this set. will remain until cleared software writing logic bit. (Note: Power-on reset, both this will while other flag bits cleared.) reserved
Symbol
R_SF R_WD R_BK
Reset vector
Following reset, P89LPC9102/9103/9107 will fetch instructions from either address 0000h Boot address. Boot address formed using Boot Vector HIGH byte address byte address 00h. Boot address will
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used UART break reset (P89LPC9103, P89LPC9107) occurs non-volatile Boot Status (BOOTSTAT.0) device been forced into mode. Otherwise, instructions will fetched from address 0000H.
Timers
P89LPC9102/9103/9107 general-purpose counter/timers which upward compatible with 80C51 Timer Timer Both configured operate either timers event counters (see Table 36). option automatically toggle upon timer overflow been added. `Timer' function, timer incremented every PCLK. `Counter' function, register incremented response 1-to-0 transition corresponding external input T1). external input sampled once during every machine cycle. When HIGH during cycle next cycle, count incremented. count value appears register during cycle following which transition detected. Since takes machine cycles clocks) recognize 1-to-0 transition, maximum count rate clock frequency. There restrictions duty cycle external input signal, ensure that given level sampled least once before changes, should held least full machine cycle. `Timer' `Counter' function selected control bits TnC/T Timers respectively) Special Function Register TMOD. Timer Timer have five operating modes (modes which selected bit-pairs (TnM1, TnM0) TMOD TnM2 TAMOD. Modes same both Timers/Counters. Mode different. operating modes described later this section.
Table Symbol Reset Table T0M0 T0M1 T0C/T T1M0 T1M1 T1C/T Timer/Counter Mode register (TMOD address 89h) allocation T1C/T T1M1 T1M0 T0C/T T0M1 T0M0
Timer/Counter Mode register (TMOD address 89h) description Description Mode Select Timer These bits used with T0M2 TAMOD register determine Timer mode (see Table 38). Timer Counter selector Timer Cleared Timer operation (input from CCLK). Counter operation (input from input pin) (P89LPC9102, P89LPC9107). reserved Mode Select Timer These bits used with T1M2 TAMOD register determine Timer mode (see Table 38). Timer Counter Selector Timer Cleared Timer operation (input from CCLK). Counter operation (input from input pin) (P89LPC9102, P89LPC9107). reserved
Symbol
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Table Symbol Reset Table T0M2
Timer/Counter Auxiliary Mode register (TAMOD address 8Fh) allocation T1M2 T0M2
Timer/Counter Auxiliary Mode register (TAMOD address 8Fh) description Description Mode Select Timer These bits used with T0M2 TAMOD register determine Timer mode (see Table 38). reserved Mode Select Timer These bits used with T1M2 TAMOD register determine Timer mode (see Table 38). following timer modes selected timer mode bits TnM[2:0]: 8048 Timer `TLn' serves 5-bit prescaler. (Mode 16-bit Timer/Counter `THn' `TLn' cascaded; there prescaler.(Mode 8-bit auto-reload Timer/Counter. holds value which loaded into when overflows. (Mode Timer dual 8-bit Timer/Counter this mode. 8-bit Timer/Counter controlled standard Timer control bits. 8-bit timer only, controlled Timer control bits (see text). Timer this mode stopped. (Mode Reserved. User must configure this mode. Reserved. User must configure this mode. mode (see Section 8.5). Reserved. User must configure this mode.
Symbol
T1M2
reserved
Mode
Putting either Timer into Mode makes look like 8048 Timer, which 8-bit Counter with divide-by-32 prescaler. Figure shows Mode operation. this mode, Timer register configured 13-bit register. count rolls over from logic logic sets Timer interrupt flag TFn. count input enabled Timer when control Special Function Register TCON (Table 40). 13-bit register consists bits lower bits TLn. upper bits indeterminate should ignored. Setting flag (TRn) does clear registers. Mode operation same Timer Timer Figure
Mode
Mode same Mode except that bits timer register (THn TLn) used. Figure
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Mode
Mode configures Timer register 8-bit Counter (TLn) with automatic reload, shown Figure Overflow from only sets TFn, also reloads with contents THn, which must preset software. reload leaves unchanged. Mode operation same Timer Timer
Mode
When Timer Mode stopped. effect same setting Timer Mode establishes separate 8-bit counters. logic Mode Timer shown Figure uses Timer control bits: T0C/T, TR0, TF0. locked into timer function (counting machine cycles) takes over from Timer Thus, controls `Timer interrupt. Mode provided applications that require extra 8-bit timer. With Timer Mode P89LPC9102/9103/9107 device look like three Timer/Counters. Note: When Timer Mode Timer turned switching into Mode still used serial port baud rate generator, application requiring interrupt.
Mode (P89LPC9102, P89LPC9107)
this mode, corresponding timer changed with full period timer clocks (see Figure 25). structure similar mode except that:
Timers respectively) cleared hardware period THn, should between 254, HIGH period always Loading with will force HIGH, loading with will force
Note that interrupt still enabled HIGH transition TFn, that still cleared software like other modes.
Table Symbol Reset Table Timer/Counter Control register (TCON) address 88h) allocation
Timer/Counter Control register (TCON address 88h) description Description reserved reserved reserved reserved Timer control bit. Set/cleared software turn Timer/Counter on/off.
Symbol
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Table
Timer/Counter Control register (TCON address 88h) description Description Timer overflow flag. hardware Timer/Counter overflow. Cleared hardware when processor vectors interrupt routine, software. (except mode where cleared hardware) Timer control bit. Set/cleared software turn Timer/Counter on/off Timer overflow flag. hardware Timer/Counter overflow. Cleared hardware when interrupt processed, software (except mode above, when cleared hardware).
Symbol
PCLK pin(1)
TnC/T TnC/T control (5-bits) (8-bits)
overflow interrupt
toggle pin(1)
ENTn
002aab055
functions available P89LPC9102, P89LPC9107
Timer/counter Mode (13-bit counter).
PCLK pin(1)
TnC/T TnC/T control (8-bits) (8-bits)
overflow interrupt
toggle pin(1)
ENTn
002aab056
functions available P89LPC9102, P89LPC9107
Timer/counter mode (16-bit counter).
PCLK pin(1)
TnC/T TnC/T control (8-bits) reload
overflow interrupt
toggle pin(1)
(8-bits)
ENTn
002aab057
functions available P89LPC9102, P89LPC9107
Timer/counter Mode (8-bit auto-reload).
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PCLK pin(1)
T0C/T T0C/T control (8-bits)
overflow toggle interrupt
pin(1)
ENT0 overflow interrupt
PCLK control
(8-bits)
002aab058
functions available P89LPC9102, P89LPC9107
Timer/counter Mode (two 8-bit counters).
PCLK
TnC/T TLn(8-bits) control
overflow interrupt
reload falling transition (256 THn) rising transition
toggle THn(8-bits) ENTn
002aab059
pin(1)
functions available P89LPC9102, P89LPC9107
Timer/counter mode (PWM auto-reload).
Timer overflow toggle output (P89LPC9102, P89LPC9107)
Timers configured automatically toggle port output whenever timer overflow occurs. same device pins that used count inputs outputs also used timer toggle outputs. This function enabled control bits ENT0 ENT1 AUXR1 register, apply Timer Timer respectively. port outputs will logic prior first timer overflow when this mode turned order this mode function, must cleared selecting PCLK clock source timer.
Real-time clock system timer
P89LPC9102/9103/9107 simple Real-time Clock/System Timer that allows user continue running accurate timer while rest device powered down. Real-time Clock interrupt wake-up source (see Figure 26). Real-time Clock 23-bit down counter. clock source this counter either clock (CCLK) external Clock Input (CLKIN). There three SFRs used RTC:
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RTCCON Real-time Clock control. RTCH Real-time Clock counter reload HIGH (bits [22:15]). RTCL Real-time Clock counter reload (bits [14:7]). Real-time clock system timer enabled setting RTCEN (RTCCON.0) bit. Real-time Clock 23-bit down counter (initialized when RTCEN that comprised 7-bit prescaler 16-bit loadable down counter. When RTCEN written with logic counter first loaded with (RTCH, RTCL, `1111111') will count down. When reaches 0's, counter will reloaded again with (RTCH, RTCL, `1111111') flag RTCF (RTCCON.7) will set.
power-on reset
RTCH
RTCL
RESET
RELOAD UNDERFLOW
7-BIT PRESCALER ÷128 CCLK internal oscillators
23-BIT DOWN COUNTER
wake-up from power-down RTCF Interrupt enabled (shared with WDT) underflow flag ERTC
002aab227
RTCEN enable
RTCS1 RTCS2 select
Real-time clock/system timer block diagram.
Real-time clock source
RTCS1-0 (RTCCON[6:5]) used select either external clock input CCLK clock source RTC, either Internal oscillator internal oscillator used CCLK. CCLK derived from external clock input P0.5 then CCLK (external clock input/DIVM) external input clock source.
Changing RTCS1-0
RTCS1-0 cannot changed currently enabled (RTCCON.0 =1). Setting RTCEN updating RTCS1-0 done single write RTCCON. However, RTCEN this must first cleared before updating RTCS1-0.
Real-time clock interrupt/wake-up
ERTC (RTCCON.1), EWDRT (IEN1[6:0]) (IEN0.7) logic RTCF used interrupt source. This interrupt vector shared with watchdog timer. also source wake device.
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Reset sources affecting Real-time clock
Only power-on reset will reset Real-time Clock associated SFRs their default state.
Table FOSC2:0 Table Symbol Reset Internal oscillator External clock input /DIVM External clock input Internal oscillator External clock input External clock input/DIVM Internal oscillator undefined undefined Watchdog oscillator /DIVM External clock input Internal oscillator Internal oscillator External clock input Watchdog oscillator /DIVM Internal oscillator DIVM External clock input Internal oscillator External clock input Internal oscillator /DIVM Real-time Clock/System Timer clock sources RCCLK RTCS1:0 clock source undefined clock source undefined
Real-time Clock Control register (RTCCON address D1h) allocation RTCF RTCS1 RTCS0 ERTC RTCEN
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Table
Real-time Clock Control register (RTCCON address D1h) description Description Real-time Clock enable. Real-time Clock will enabled this logic Note that this will power-down Real-time Clock. RTCPD (PCONA.7) set, will power-down disable this block regardless RTCEN. Real-time Clock interrupt enable. Real-time Clock shares same interrupt watchdog timer. Note that user configuration WDTE (UCFG1.7) logic watchdog timer enabled generate interrupt. Users read RTCF (RTCCON.7) determine whether Real-time Clock caused interrupt. reserved Real-time Clock source select (see Table 41). Real-time Clock Flag. This logic when 23-bit Real-time Clock reaches count logic cleared software.
Symbol RTCEN
ERTC
RTCS0 RTCS1 RTCF
UART (P89LPC9103, P89LPC9107)
P89LPC9103/9107 enhanced UART that compatible with conventional 80C51 UART except that Timer overflow cannot used baud rate source. P89LPC9103/9107 does include independent Baud Rate Generator. baud rate selected from oscillator (divided constant), Timer overflow, independent Baud Rate Generator. addition baud rate generation, enhancements over standard 80C51 UART include Framing Error detection, break detect, automatic address recognition, selectable double buffering several interrupt options. UART operated four modes, described following sections.
10.1 Mode
Serial data enters exits through RXD. outputs shift clock. bits transmitted received, first. baud rate fixed 1/16 clock frequency.
10.2 Mode
bits transmitted (through TXD) received (through RXD): start (logic data bits (LSB first), stop (logic When data received, stop stored Special Function Register SCON. baud rate variable determined Timer overflow rate Baud Rate Generator (see Section 10.6 "Baud Rate generator selection").
10.3 Mode
bits transmitted (through TXD) received (through RXD): start (logic data bits (LSB first), programmable data bit, stop (logic When data transmitted, data (TB8 SCON) assigned value example, parity PSW) could moved into TB8. When data received, data goes into Special Function Register SCON stop saved. baud rate programmable either 1/16 1/32 CCLK frequency, determined SMOD1 PCON.
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10.4 Mode
bits transmitted (through TXD) received (through RXD): start (logic data bits (LSB first), programmable data bit, stop (logic Mode same Mode respects except baud rate. baud rate Mode variable determined Timer overflow rate Baud Rate Generator (see Section 10.6 "Baud Rate generator selection" page 55). four modes, transmission initiated instruction that uses SBUF destination register. Reception initiated Mode condition Reception initiated other modes incoming start
10.5 space
UART SFRs following locations shown Table
Table Register PCON SCON SBUF SADDR SADEN SSTAT BRGR1 BRGR0 BRGCON UART addresses Description Power Control Serial Port (UART) Control Serial Port (UART) Data Buffer Serial Port (UART) Address Serial Port (UART) Address Enable Serial Port (UART) Status Baud Rate Generator Rate HIGH Byte Baud Rate Generator Rate Byte Baud Rate Generator Control location
10.6 Baud Rate generator selection
P89LPC9103/9107 enhanced UART independent Baud Rate Generator. baud rate determined value programmed into BRGR1 BRGR0 SFRs. UART either Timer baud rate generator output determined BRGCON.2-1 (see Figure 27). Note that Timer further divided SMOD1 (PCON.7) set. independent Baud Rate Generator uses CCLK.
10.7 Updating BRGR1 BRGR0 SFRs
baud rate SFRs, BRGR1 BRGR0 must only loaded when Baud Rate Generator disabled (the BRGEN BRGCON register logic This avoids loading interim value baud rate generator. (CAUTION: either BRGR0 BRGR1 written when BRGEN result unpredictable.)
Table SCON.7 (SM0) UART baud rate generation. SCON.6 (SM1) PCON.7 (SMOD1)
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BRGCON.1 (SBRGS)
Receive/transmit baud rate UART CCLK/16 CCLK/(256 TH1)64 CCLK/(256 TH1)32 CCLK/((BRGR1,BRGR0)
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Table SCON.7 (SM0)
UART baud rate generation. SCON.6 (SM1) PCON.7 (SMOD1) BRGCON.1 (SBRGS) Receive/transmit baud rate UART CCLK/32 CCLK/16 CCLK/(256 TH1)64 CCLK/(256 TH1)32 CCLK/((BRGR1,BRGR0)
Table Symbol Reset Table
Baud Rate Generator Control register (BRGCON address BDh) allocation SBRGS BRGEN
Baud Rate Generator Control register (BRGCON address BDh) description Description Baud Rate Generator Enable. Enables baud rate generator. BRGR1 BRGR0 only written when BRGEN Select Baud Rate Generator source baud rates UART modes (see Table details) reserved
Symbol BRGEN SBRGS
Timer Overflow (PCLK-based) Baud Rate Generator (CCLK-based)
SMOD1
SBRGS Baud Rate Modes SBRGS
002aaa419
SMOD1
Baud rate generation UART (Modes
10.8 Framing error
Framing error occurs when stop sensed logic Framing error reported status register (SSTAT). addition, SMOD0 (PCON.6) framing errors made available SCON.7. SMOD0 SCON.7 SM0. recommended that (SCON.7-6) programmed when SMOD0 logic
10.9 Break detect
break detect reported status register (SSTAT). break detected when consecutive bits sensed LOW. Since break condition also satisfies requirements framing error, break condition will also result reporting framing error. Once break condition been detected, UART will into idle state remain this idle state until stop been received. break detect used reset device force device into mode setting EBRR (AUXR1.6).
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Table Symbol Reset Table
Serial Port Control register (SCON address 98h) allocation SM0/FE
Serial Port Control register (SCON address 98h) description Description Receive interrupt flag. hardware time Mode approximately halfway through stop time Mode Mode Mode SMOD0, near middle data (bit SMOD0 near middle stop (see SCON.5 exceptions). Must cleared software. Transmit interrupt flag. hardware time Mode stop (see description INTLO SSTAT register) other modes. Must cleared software. data that received Modes Mode (SM2 must stop that received. Mode undefined. data that will transmitted Modes clear software desired. Enables serial reception. software enable reception. Clear software disable reception. Enables multiprocessor communication feature Modes Mode then will activated received data (RB8) Mode should Mode must With defines serial port mode, Table this determined SMOD0 PCON register. SMOD0 this read written SM0, which with SM1, defines serial port mode. SMOD0 this read written (Framing Error). receiver when invalid stop detected. Once set, this cannot cleared valid frames cleared software. (Note: UART mode bits should programmed when SMOD0 logic default mode reset.)
Symbol
SM0/FE
Table SM0,SM1 Table Symbol Reset
Serial Port modes UART mode Mode shift register Mode 8-bit UART Mode 9-bit UART Mode 9-bit UART UART baud rate CCLK/16 (default mode reset) Variable (see Table CCLK/32 CCLK/16 Variable (see Table
Serial Port Status register (SSTAT address BAh) allocation DBMOD INTLO CIDIS DBISEL STINT
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Table
Serial Port Status register (SSTAT address BAh) description Description Status Interrupt Enable. When cause interrupt. interrupt used (vector address 0023h) shared with (CIDIS combined TI/RI (CIDIS When cleared cannot cause interrupt. (Note: often accompanied which will generate interrupt regardless state STINT). Note that cause break detect reset EBRR (AUXR1.6) logic Overrun Error flag character received receiver buffer while still full (before software read previous character from buffer), i.e., when byte received while SCON still set. Cleared software. Break Detect flag. break detected when consecutive bits sensed LOW. Cleared software. Framing error flag when receiver fails valid STOP frame. Cleared software. Double buffering transmit interrupt select. Used only double buffering enabled. This controls number interrupts that occur when double buffering enabled. When set, transmit interrupt generated after each character written SBUF, there also more transmit interrupt generated beginning (INTLO (INTLO STOP last character sent (i.e., more data buffer). This last interrupt used indicate that transmit operations over. When cleared only transmit interrupt generated character written SBUF. Must logic when double buffering disabled. Note that except first character written (when buffer empty), location transmit interrupt determined INTLO. When first character written, transmit interrupt generated immediately after SBUF written. Combined Interrupt Disable. When interrupts separate. When cleared UART uses combined Tx/Rx interrupt (like conventional 80C51 UART). This reset logic select combined interrupts. Transmit interrupt position. When cleared interrupt issued beginning stop bit. When interrupt issued stop bit. Must logic mode Note that case single buffering, interrupt occurs STOP bit, exist before next start bit.
Symbol STINT
DBISEL
CIDIS
INTLO
DBMOD Double buffering mode. When enables double buffering. Must logic UART mode order compatible with existing 80C51 devices, this reset logic disable double buffering.
10.10 More about UART Mode
Mode write SBUF will initiate transmission. transmission, (SCON.1) set, which must cleared software. Double buffering must disabled this mode. Reception initiated clearing (SCON.0). Synchronous serial transfer occurs will again transfer. When cleared, reception next character will begin. Refer Figure
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Koninklijke Philips Electronics N.V. 2004. rights reserved.
User manual
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UM10112
P89LPC9102/9103/9107 User manual
write SBUF shift (data out) (shift clock)
transmit
WRITE SCON (clear receive shift (data (shift clock)
002aaa925
Serial Port Mode (double buffering must disabled).
10.11 More about UART Mode
Reception initiated detecting 1-to-0 transition RXD. sampled rate times programmed baud rate. When transition detected, divide-by-16 counter immediately reset. Each time thus divided into counter states. 7th, 8th, counter states, detector samples value RXD. value accepted value that seen least samples. This done noise rejection. value accepted during first time receive circuits reset receiver goes back looking another 1-to-0 transition. This provides rejection false start bits. start proves valid, shifted into input shift register, reception rest frame will proceed. signal load SBUF RB8, will generated only following conditions time final shift pulse generated: either received stop either these conditions met, received frame lost. both conditions met, stop goes into RB8, data bits into SBUF, activated.
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clock write SBUF shift
INTLO INTLO start stop
transmit
clock shift
reset
start
stop receive
002aaa926
Serial Port Mode (only single transmit buffering case shown).
10.12 More about UART Modes
Reception same Mode signal load SBUF RB8, will generated only following conditions time final shift pulse generated. Either received data either these conditions met, received frame lost, set. both conditions met, received data goes into RB8, first data bits into SBUF.
clock write SBUF shift
INTLO INTLO start stop transmit
clock shift
reset
start
stop receive
SMOD0
SMOD0
002aaa927
Serial Port Mode (only single transmit buffering case shown).
10.13 Framing error Modes with
modes behaves following table.
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Table Mode
when SM2= Modes when Similar Figure with SMOD0 occurs during RB8, before when Similar Figure with SMOD0 occurs during STOP Occurs during STOP Occurs during STOP Will occur Occurs during STOP
PCON.6 (SMOD0)
10.14 Break detect
break detected when consecutive bits sensed reported status register (SSTAT). Mode this consists start bit, data bits, stop times. Modes this consists start bit, data bits, stop bit. break detect cleared software reset. break detect used reset device force device into mode. This occurs UART enabled EBRR (AUXR1.6) break occurs.
10.15 Double buffering
UART transmit double buffer that allows buffering next character written SBUF while first character being transmitted. Double buffering allows transmission string characters with only stop between characters, provided next character written between start stop previous character. Double buffering disabled. disabled (DBMOD, i.e. SSTAT.7 UART compatible with conventional 80C51 UART. enabled, UART allows writing SnBUF while previous data being shifted out.
10.16 Double buffering different modes
Double buffering only allowed Modes When operated Mode double buffering must disabled (DBMOD
10.17 Transmit interrupts with double buffering enabled (Modes 1,2,
Unlike conventional UART, when double buffering enabled, interrupt generated when double buffer ready receive data. following occurs during transmission (assuming eight data bits): double buffer empty initially. writes SBUF. SBUF data loaded shift register interrupt generated immediately. there more data, else continue. there more data, then: DBISEL logic more interrupts will occur.
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DBISEL logic INTLO logic interrupt will occur beginning STOP data currently shifter (which also last data). DBISEL logic INTLO logic interrupt will occur STOP data currently shifter (which also last data). Note that DBISEL logic writing SBUF when STOP last data shifted out, there uncertainty whether interrupt generated already with UART knowing whether there more data following. there more data, writes SBUF again. Then: INTLO logic data will loaded interrupt will occur beginning STOP data currently shifter. INTLO logic data will loaded interrupt will occur STOP data currently shifter.
write SBUF interrupt single buffering (DBMOD/SSTAT.7 early interrupt (INTLO/SSTAT.6 shown
write SBUF interrupt double buffering (DBMOD/SSTAT.7 early interrupt (INTLO/SSTAT.6 shown, ending interrupt (DBISEL/SSTAT.4
write SBUF interrupt double buffering (DBMOD/SSTAT.7 early interrupt (INTLO/SSTAT.6 shown, with ending interrupt (DBISEL/SSTAT.4
002aaa928
Transmission with without double buffering.
10.18 (bit double buffering (Modes
double buffering disabled (DBMOD, i.e. SSTAT.7 written before after SBUF written, provided updated before that shifted out. must changed again until after shifting been completed, indicated interrupt.
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double buffering enabled, MUST updated before SBUF written, will double-buffered together with SBUF data. operation described Section 10.17 becomes follows: double buffer empty initially. writes TB8. writes SBUF. SBUF/TB8 data loaded shift register interrupt generated immediately. there more data, else continue there more data, then: DBISEL logic more interrupt will occur. DBISEL logic INTLO logic interrupt will occur beginning STOP data currently shifter (which also last data). DBISEL logic INTLO logic interrupt will occur STOP data currently shifter (which also last data). there more data, writes again. writes SBUF again. Then: INTLO logic data will loaded interrupt will occur beginning STOP data currently shifter. INTLO logic data will loaded interrupt will occur STOP data currently shifter. 10.Note that DBISEL logic writing SBUF when STOP last data shifted out, there uncertainty whether interrupt generated already with UART knowing whether there more data following.
10.19 Multiprocessor communications
UART modes have special provision multiprocessor communications. these modes, data bits received transmitted. When data received, stored RB8. UART programmed such that when stop received, serial port interrupt will activated only This feature enabled setting SCON. this feature multiprocessor systems follows: When master processor wants transmit block data several slaves, first sends address byte which identifies target slave. address byte differs from data byte that address byte data byte. With slave will interrupted data byte. address byte, however, will interrupt slaves, that each slave examine received byte being addressed. addressed slave will clear prepare receive data bytes that follow. slaves that weren't being addressed leave their bits about their business, ignoring subsequent data bytes. Note that effect Mode must logic Mode
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Koninklijke Philips Electronics N.V. 2004. rights reserved.
User manual
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P89LPC9102/9103/9107 User manual
10.20 Automatic address recognition
Automatic address recognition feature which allows UART recognize certain addresses serial stream using hardware make comparisons. This feature saves great deal software overhead eliminating need software examine every serial address which passes serial port. This feature enabled setting SCON. UART modes (mode mode Receive Interrupt flag (RI) will automatically when received byte contains either `Given' address `Broadcast' address. mode requires that information indicate that received information address data. Using Automatic Address Recognition feature allows master selectively communicate with more slaves invoking Given slave address addresses. slaves contacted using Broadcast address. special Function Registers used define slave's address, SADDR, address mask, SADEN. SADEN used define which bits SADDR used which bits `don't care'. SADEN mask logically ANDed with SADDR create `Given' address which master will addressing each slaves. Given address allows multiple slaves recognized while excluding others. following examples will help show versatility this scheme:
Table Example Slave SADDR SADEN Given 1100 0000 1111 1101 1100 00X0 Slave examples Example Slave SADDR SADEN Given 1100 0000 1111 1110 1100 000X
above example SADDR same SADEN data used differentiate between slaves. Slave requires ignores Slave requires ignored. unique address Slave would 1100 0010 since slave requires unique address slave would 1100 0001 since will exclude slave Both slaves selected same time address which (for slave (for slave Thus, both could addressed with 1100 0000. more complex system following could used select slaves while excluding slave
Table Example Slave SADDR 1100 0000 SADEN 1111 1001 Given 1100 0XX0 Slave 0/1/2 examples Example Slave SADDR 1110 0000 SADEN 1111 1010 Given 1110 0X0X Example Slave SADDR SADEN Given 1100 0000 1111 1100 1110 00XX
above example differentiation among slaves lower address bits. Slave requires that uniquely addressed 1110 0110. Slave requires that uniquely addressed 1110 0101. Slave requires that unique address 1110 0011. select Slaves exclude Slave address 1110 0100, since necessary make exclude slave Broadcast Address each slave created taking logical SADDR SADEN. Zeros this result treated don't-cares. most cases,
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interpreting don't-cares ones, broadcast address will hexadecimal. Upon reset SADDR SADEN loaded with This produces given address `don't cares' well Broadcast address `don't cares'. This effectively disables Automatic Addressing mode allows microcontroller standard UART drivers which make this feature.
Analog comparator
analog comparator provided P89LPC9102/9103/9107. Input output options allow comparator number different configurations. Comparator operation such that output logic (which read register and/or routed pin) when positive input (one selectable pins) greater than negative input (selectable from internal reference voltage). Otherwise output zero. comparator configured cause interrupt when output value changes.
11.1 Comparator configuration
Each comparator control register, CMP1 shown Table overall connections comparator shown Figure There eight possible configurations comparator, determined control bits corresponding CMP1 register: CP1, CN1, OE1. These configurations shown Figure When comparator first enabled, comparator output interrupt flag guaranteed stable microseconds. corresponding comparator interrupt should enabled during that time, comparator interrupt flag must cleared before interrupt enabled order prevent immediate interrupt service.
Table Symbol Reset Table CMF1 Comparator Control register (CMP1 address ACh) allocation CMF1
Comparator Control register (CMP1 address ACh, CMP2 address ADh) description Description Comparator interrupt flag. This hardware whenever comparator output changes state. This will cause hardware interrupt enabled. Cleared software. Comparator output, synchronized clock allow reading software. reserved Comparator negative input select. When logic comparator reference CMPREF selected negative comparator input. When logic internal comparator reference, Vref, selected negative comparator input. Comparator positive input select. When logic CINnA selected positive comparator input. When logic CINnB selected positive comparator input. Comparator enable. When set, corresponding comparator function enabled. Comparator output stable microseconds after set. reserved reserved
Symbol
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comparator (P0.4) CIN1A (P0.3) CIN1B (P0.5) CMPREF VREF
002aaa979
change detect CMF1 interrupt
Comparator input output connections.
11.2 Internal reference voltage
internal reference voltage, Vref, supply default reference when single comparator input used. Please refer P89LPC9102/9103 Data sheet specifications.
11.3 Comparator interrupt
comparator interrupt flag CMF1 contained configuration register. This flag whenever comparator output changes state. flag polled software used generate interrupt. interrupt
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