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UM10112

P89LPC9102 / 9103 / 9107 User manual

UM10112
P89LPC9102 / 9103 / 9107 User manual
Rev. 01 - 11 February 2005 User manual
Document information Info Keywords Abstract Content P89LPC9102, P89LPC9103, P89LPC9107 Technical information for the P89LPC9102, P89LPC9103 and P89LPC9107 devices.
Philips Semiconductors
UM10112
P89LPC9102 / 9103 / 9107 User manual
Revision history Rev 01 Date 20050211 Description Initial version (9397 750 13919).
User manual
Rev. 01 - 11 February 2005
Philips Semiconductors
UM10112
P89LPC9102 / 9103 / 9107 User manual
1. Introduction
The P89LPC9102 / 9103 / 9107 are single-chip microcontrollers designed for applications demanding high-integration, low-cost solutions over a wide range of performance requirements. The P89LPC9102 / 9103 / 9107 is based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC9102 / 9103 / 9107 in order to reduce component count, board space, and system cost.
1.1 Logic symbols
VDD VSS
AD13 CLKIN AD11 AD12 AD10 CLKOUT
CIN1A CMPREF KBI2 CIN1B KBI1 T1
PORT 1 PORT 0
RST T0
P89LPC9102
002aaa971
Fig 1. P89LPC9102 logic symbol.
AD13 CLKIN AD11 AD12 AD10
CIN1A CMPREF KBI2 CIN1B KBI1
PORT 1 PORT 0
P89LPC9103
RST RXD TXD
002aaa972
Fig 2. P89LPC9103 logic symbol.
AD13 CLKIN AD11 AD12 AD10 CLKOUT
CIN1A CMPREF KBI2 CIN1B KBI1 T1
PORT 1 PORT 0
P89LPC9107
RST RXD TXD T0
002aab084
Fig 3. P89LPC9107 logic symbol.
User manual
Rev. 01 - 11 February 2005
Philips Semiconductors
UM10112
P89LPC9102 / 9103 / 9107 User manual
1.2 Pin Configuration
terminal 1 index area P0.2 / KBI2 / AD11 P1.5 / RST VSS P0.1 / KBI1 / AD10 P1.2 / T0 1 2 3 4 5 10 P0.3 / CIN1B / AD12 9 P0.4 / CIN1A / AD13 / DAC1 P0.5 / CMPREF / CLKIN VDD P0.7 / T1 / CLKOUT
LPC9102
002aaa969
Transparent top view
Fig 4. P89LPC9102 pinning (HVSON10).
terminal 1 index area P0.2 / KBI2 / AD11 P1.5 / RST VSS P0.1 / KBI1 / AD10 P1.0 / TXD 1 2 3 4 5 10 P0.3 / CIN1B / AD12 9 P0.4 / CIN1A / AD13 / DAC1 P0.5 / CMPREF / CLKIN VDD P1.1 / RXD
LPC9103
002aaa970
Transparent top view
Fig 5. P89LPC9103 pinning (HVSON10).
P0.2 / KBI2 / AD11 n.c. P1.5 / RST VSS P0.1 / KBI1 / AD10 P1.0 / TXD P1.2 / T0
002aab083
14 P0.3 / CIN1B / AD12 13 n.c. 12 P0.4 / CIN1A / AD13 / DAC1
LPC9107
11 P0.5 / CMPREF / CLKIN 10 VDD 9 8 P1.1 / RXD P0.7 / T1 / CLKOUT
Fig 6. P89LPC9107 pinning (TSSOP14).
User manual
Rev. 01 - 11 February 2005
Philips Semiconductors
UM10112
P89LPC9102 / 9103 / 9107 User manual
Table 1: Symbol
P89LPC9102 pin description Pin Type I / O Description Port 0: Port 0 is an I / O port with a user-configurable output type. During reset Port 0 latches are configured in the input-only mode with the internal pull-up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 5.1 "Port configurations" for details. The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt triggered inputs. Port 0 also provides various special functions as described below:
P0.1 to P0.5, P0.7
P0.1 / KBI1 / AD10
P0.1 - Port 0 bit 1. KBI1 - Keyboard input 1. AD10 - ADC1 channel 0 analog input. P0.2 - Port 0 bit 2. KBI2 - Keyboard input 2. AD11 - ADC1 channel 1 analog input. P0.3 - Port 0 bit 3. CIN1B - Comparator 1 positive input. AD12 - ADC1 channel 2 analog input. P0.4 - Port 0 bit 4. CIN1A - Comparator 1 positive input. AD13 - ADC1 channel 3 analog input. DAC1 - Digital to analog converter output. P0.5 - Port 0 bit 5. CMPREF - Comparator reference (negative) input. CLKIN - External clock input. P0.7 - Port 0 bit 7. T1 - Timer / counter 1 external count input or overflow / PWM output. CLKOUT - Clock output. Port 1: Port 1 is an I / O port with a user-configurable output type. During reset Port 1 latches are configured in the input-only mode with the internal pull-up disabled. The operation of the configurable Port 1 pins as inputs and outputs depends upon the port configuration selected. Each of the configurable port pins are programmed independently. Refer to Section 5.1 "Port configurations" for details. P1.5 is input-only. All pins have Schmitt triggered inputs. Port 1 also provides various special functions as described below:
P0.2 / KBI2 / AD11
P0.3 / CIN1B / AD12
P0.4 / CIN1A / AD13 / DAC1
P0.5 / CMPREF / CLKIN P0.7 / T1 / CLKOUT
P1.2, P1.5
P1.2 / T0
P1.2 - Port 1 bit 2. T0 - Timer / counter 0 external count input or overflow / PWM output.
User manual
Rev. 01 - 11 February 2005
Philips Semiconductors
UM10112
P89LPC9102 / 9103 / 9107 User manual
Table 1: Symbol P1.5 / RST
P89LPC9102 pin description ..continued Pin 2 Type I I Description P1.5 - Port 1 bit 5 (input-only). RST - External Reset input during power-on or if selected via UCFG1. When functioning as a reset input a LOW on this pin resets the microcontroller, causing I / O ports and peripherals to take on their default states, and the processor begins execution at address 0. Also used during a power-on sequence to force In-System Programming mode. When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until VDD has reached its specified level. When system power is removed VDD will fall below the minimum specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when VDD falls below the minimum specified operating voltage. Ground: 0 V reference. Power supply: This is the power supply voltage for normal operation as well as Idle mode and Power-down mode.
VSS VDD
Table 2: Symbol
P89LPC9103 pin description Pin Type I / O Description Port 0: Port 0 is an I / O port with a user-configurable output type. During reset Port 0 latches are configured in the input-only mode with the internal pull-up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 5.1 "Port configurations" for details. The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt triggered inputs. Port 0 also provides various special functions as described below:
P0.1 to P0.5
P0.1 / KBI1 / AD10
P0.1 - Port 0 bit 1. KBI1 - Keyboard input 1. AD10 - ADC1 channel 0 analog input. P0.2 - Port 0 bit 2. KBI2 - Keyboard input 2. AD11 - ADC1 channel 1 analog input. P0.3 - Port 0 bit 3. CIN1B - Comparator 1 positive input. AD12 - ADC1 channel 2 analog input. P0.4 - Port 0 bit 4. CIN1A - Comparator 1 positive input. AD13 - ADC1 channel 3 analog input. DAC1 - Digital to analog converter output. P0.5 - Port 0 bit 5. CMPREF - Comparator reference (negative) input. CLKIN - External clock input.
P0.2 / KBI2 / AD11
P0.3 / CIN1B / AD12
P0.4 / CIN1A / AD13 / DAC1
P0.5 / CMPREF / 6 CLKIN
User manual
Rev. 01 - 11 February 2005
Philips Semiconductors
UM10112
P89LPC9102 / 9103 / 9107 User manual
Table 2: Symbol
P89LPC9103 pin description ..continued Pin Type I / O Description Port 1: Port 1 is an I / O port with a user-configurable output type. During reset Port 1 latches are configured in the input-only mode with the internal pull-up disabled. The operation of the configurable Port 1 pins as inputs and outputs depends upon the port configuration selected. Each of the configurable port pins are programmed independently. Refer to Section 5.1 "Port configurations" for details. P1.5 is input-only. All pins have Schmitt triggered inputs. Port 1 also provides various special functions as described below:
P1.0 to P1.5
P1.0 / TXD P1.1 / RXD P1.5 / RST
P1.0 - Port 1 bit 0. TXD - Serial port transmitter data. P1.1 - Port 1 bit 1. RXD - Serial port receiver data. P1.5 - Port 1 bit 5 (input-only). RST - External Reset input during Power-on or if selected via UCFG1. When functioning as a reset input a LOW on this pin resets the microcontroller, causing I / O ports and peripherals to take on their default states, and the processor begins execution at address 0. Also used during a power-on sequence to force In-System Programming mode.When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until VDD has reached its specified level. When system power is removed VDD will fall below the minimum specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when VDD falls below the minimum specified operating voltage. Ground: 0 V reference. Power supply: This is the power supply voltage for normal operation as well as Idle mode and Power-down mode.
VSS VDD
Table 3: Symbol
P89LPC9107 pin description Pin Type I / O Description Port 0: Port 0 is an I / O port with a user-configurable output type. During reset Port 0 latches are configured in the input-only mode with the internal pull-up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 5.1 "Port configurations" on page 37 for details. The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt triggered inputs. Port 0 also provides various special functions as described below:
P0.1 to P0.5, P0.7
P0.1 / KBI1 / AD10
P0.1 - Port 0 bit 1. KBI1 - Keyboard input 1. AD10 - ADC1 channel 0 analog input. P0.2 - Port 0 bit 2. KBI2 - Keyboard input 2. AD11 - ADC1 channel 1 analog input. P0.3 - Port 0 bit 3. CIN1B - Comparator 1 positive input. AD12 - ADC1 channel 2 analog input.
P0.2 / KBI2 / AD11
P0.3 / CIN1B / AD12
User manual
Rev. 01 - 11 February 2005
Philips Semiconductors
UM10112
P89LPC9102 / 9103 / 9107 User manual
Table 3: Symbol
P89LPC9107 pin description ..continued Pin 12 Type I / O I I O Description P0.4 - Port 0 bit 4. CIN1A - Comparator 1 positive input. AD13 - ADC1 channel 3 analog input. DAC1 - Digital to analog converter output. P0.5 - Port 0 bit 5. CMPREF - Comparator reference (negative) input. CLKIN - External clock input. P0.7 - Port 0 bit 7. T1 - Timer / counter 1 external count input or overflow / PWM output. CLKOUT - Clock output. Port 1: Port 1 is an I / O port with a user-configurable output type. During reset Port 1 latches are configured in the input-only mode with the internal pull-up disabled. The operation of the configurable Port 1 pins as inputs and outputs depends upon the port configuration selected. Each of the configurable port pins are programmed independently. Refer to Section 5.1 "Port configurations" on page 37 for details. P1.5 is input-only. All pins have Schmitt triggered inputs. Port 1 also provides various special functions as described below:
P0.4 / CIN1A / AD13 / DAC1
P0.5 / CMPREF / 11 CLKIN
P0.7 / T1 / CLKOUT
P1.0 to P1.2, P1.5
P1.0 / TXD P1.1 / RXD P1.2 / T0 P1.5 / RST
P1.0 - Port 1 bit 0. TXD - Serial port transmitter data. P1.1 - Port 1 bit 1. RXD - Serial port receiver data. P1.2 - Port 1 bit 2. T0 - Timer / counter 0 external count input or overflow / PWM output. P1.5 - Port 1 bit 5 (input-only). RST - External Reset input during Power-on or if selected via UCFG1. When functioning as a reset input a LOW on this pin resets the microcontroller, causing I / O ports and peripherals to take on their default states, and the processor begins execution at address 0. Also used during a power-on sequence to force In-System Programming mode.When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until VDD has reached its specified level. When system power is removed VDD will fall below the minimum specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when VDD falls below the minimum specified operating voltage. Ground: 0 V reference. Power supply: This is the power supply voltage for normal operation as well as Idle mode and Power-down mode.
VSS VDD
User manual
Rev. 01 - 11 February 2005
Philips Semiconductors
UM10112
P89LPC9102 / 9103 / 9107 User manual
P89LPC9102
ACCELERATED 2-CLOCK 80C51 CPU
1 kB FLASH internal bus P1.2, P1.5 PORT 1 CONFIGURABLE I / Os
128 BYTE RAM AD10 AD11 AD12 AD13 DAC1
ADC1 / DAC1
P01:5, P0.7
PORT 0 CONFIGURABLE I / Os
REAL-TIME CLOCK / SYSTEM TIMER T0 T1 CIN1A CIN1B
KBI1 KBI2
KEYPAD INTERRUPT WATCHDOG TIMER AND OSCILLATOR
TIMER 0 TIMER 1
ANALOG COMPARATORS
PROGRAMMABLE OSCILLATOR DIVIDER CLKOUT CLKIN
CPU clock POWER MONITOR (POWER-ON RESET, BROWNOUT RESET)
CONFIGURABLE OSCILLATOR
ON-CHIP RC OSCILLATOR WITH CLOCK DOUBLER OPTION
002aaa967
Fig 7. P89LPC9102 block diagram.
User manual
Rev. 01 - 11 February 2005
Philips Semiconductors
UM10112
P89LPC9102 / 9103 / 9107 User manual
P89LPC9103
ACCELERATED 2-CLOCK 80C51 CPU
1 kB FLASH internal bus P1.0, P1.1, P1.5 PORT 1 CONFIGURABLE I / Os
TXD UART RXD
128 BYTE RAM AD10 AD11 AD12 AD13 DAC1
P01:5
PORT 0 CONFIGURABLE I / Os
ADC1 / DAC1
KBI1 KBI2
KEYPAD INTERRUPT
REAL-TIME CLOCK / SYSTEM TIMER
WATCHDOG TIMER AND OSCILLATOR CPU clock
TIMER 0 TIMER 1 CIN1A CIN1B
PROGRAMMABLE OSCILLATOR DIVIDER
ANALOG COMPARATORS
CLKIN
CONFIGURABLE OSCILLATOR
ON-CHIP RC OSCILLATOR WITH CLOCK DOUBLER OPTION
POWER MONITOR (POWER-ON RESET, BROWNOUT RESET)
002aaa968
Fig 8. P89LPC9103 block diagram.
User manual
Rev. 01 - 11 February 2005
Philips Semiconductors
UM10112
P89LPC9102 / 9103 / 9107 User manual
P89LPC9107
ACCELERATED 2-CLOCK 80C51 CPU
1 kB FLASH internal bus
P10:2, P1.5
PORT 1 CONFIGURABLE I / Os PORT 0 CONFIGURABLE I / Os
128 BYTE RAM
AD10 AD11 AD12 AD13 DAC1
P01:5, P0.7
ADC1 / DAC1
KBI1 KBI2
KEYPAD INTERRUPT WATCHDOG TIMER AND OSCILLATOR
REAL-TIME CLOCK / SYSTEM TIMER TIMER 0 TIMER 1 ANALOG COMPARATORS
T0 T1 CIN1A CIN1B
PROGRAMMABLE OSCILLATOR DIVIDER
CPU clock
CLKOUT CLKIN
CONFIGURABLE OSCILLATOR
ON-CHIP RC OSCILLATOR WITH CLOCK DOUBLER OPTION
POWER MONITOR (POWER-ON RESET, BROWNOUT RESET)
002aab100
Fig 9. P89LPC9107 block diagram
User manual
Rev. 01 - 11 February 2005
Philips Semiconductors
UM10112
P89LPC9102 / 9103 / 9107 User manual
1.3 Special function registers
Remark: Special Function Registers (SFRs) accesses are restricted in the following ways:
User manual
Rev. 01 - 11 February 2005
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User manual Rev. 01 - 11 February 2005
Philips Semiconductors
P89LPC9102 / 9103 / 9107 User manual
UM10112
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Table 4: P89LPC9102 special function registers ..continued indicates SFRs that are bit addressable. Name Description SFR addr. Bit address IEN1 IP0 IP0H Interrupt enable 1 Interrupt priority 0 Interrupt priority 0 high E8H Bit address B8H B7H Bit address IP1 IP1H KBCON
Rev. 01 - 11 February 2005
User manual 14 of 91
Philips Semiconductors
Reset value Hex 001 001 001 Binary 00x00000 x0000000 x0000000
Interrupt priority 1 Interrupt priority 1 high Keypad control register Keypad interrupt mask register Keypad pattern register
F8H F7H 94H 86H 93H Bit address
001 001 001 00 FF
00x00000 00x00000 xxxxxx00 xxxxx00x xxxxx11x
KBMASK KBPATN
KBMASK KBMASK .2 .1 KBPATN. KBPATN. 2 1 82 CIN2A / KBI2 92 T0 81 KBI1 91 -
Port 0
80H Bit address
P1 P0M1 P0M2 P1M1 P1M2 PCON PCONA PCONB
Port 1 Port 0 output mode 1 Port 0 output mode 2 Port 1 output mode 1 Port 1 output mode 2 Power control register Power control register A reserved for Power control register B Program status word Port 0 digital input disable
90H 84H 85H 91H 92H 87H B5H B6H
P89LPC9102 / 9103 / 9107 User manual
(P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) BOPD VCPD D5 F0 PT0AD.5 BOI ADPD D4 RS1 PT0AD.4 D3 RS0 PT0AD.3 GF1 (P1M1.2) (P1M2.2) GF0 D2 OV PT0AD.2 PMOD1 D1 F1 PT0AD.1
FF 00 FF2 002 00 001 001
11111111 00000000 11111111 00000000 00000000 00000000 xxxxxxxx
UM10112
Bit address PSW PT0AD D0H F6H
00000000 xx00000x
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Table 4: P89LPC9102 special function registers ..continued indicates SFRs that are bit addressable. Name RSTSRC RTCCON RTCH RTCL SP TAMOD TCON TH0
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User manual 15 of 91
Philips Semiconductors
Description Reset source register Real-time clock control Real-time clock register high Real-time clock register low Stack pointer Timer 0 and 1 auxiliary mode Timer 0 and 1 control Timer 0 high Timer 1 high Timer 0 low Timer 1 low Timer 0 and 1 mode Internal oscillator trim register Watchdog control register Watchdog load Watchdog feed 1 Watchdog feed 2
SFR addr. DFH D1H D2H D3H 81H 8FH 88H 8CH 8DH 8AH 8BH 89H 96H A7H C1H C2H C3H
Reset value Hex
Binary 011xxx00 00000000 00000000 00000111 xxx0xxx0 00000000 00000000 00000000 00000000 00000000 00000000
006 006 07 8F TF1 8E TR1 8D TF0 T1M2 8C TR0 8B 8A 89 T0M2 88 00 00 00 00 00 RCCLK PRE2 ENCLK PRE1 T1M1 TRIM.5 PRE0 T1M0 TRIM.4 TRIM.3 TRIM.2 WDRUN T0M1 TRIM.1 WDTOF T0M0 TRIM.0 WDCLK 00
Bit address
TH1 TL0 TL1 TMOD TRIM WDCON WDL WFEED1 WFEED2
P89LPC9102 / 9103 / 9107 User manual
UM10112
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User manual Rev. 01 - 11 February 2005
Philips Semiconductors
P89LPC9102 / 9103 / 9107 User manual
xx000000 00000000
UM10112
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Table 5: P89LPC9103 special function registers ..continued indicates SFRs that are bit addressable. Name FMDATA IEN0 IEN1 IP0 IP0H Description Program Flash data Interrupt enable 0 Interrupt enable 1 Interrupt priority 0 Interrupt priority 0 high SFR addr. E5H A8H Bit address E8H Bit address B8H B7H Bit address IP1
Rev. 01 - 11 February 2005
User manual 17 of 91
Philips Semiconductors
Reset value Hex 00 00 001 001 001 Binary 00000000 00000000 00x00000 x0000000 x0000000
Interrupt priority 1 Interrupt priority 1 high Keypad control register Keypad interrupt mask register Keypad pattern register
F8H F7H 94H 86H 93H Bit address
001 001 001 00 FF
00x00000 00x00000 xxxxxx00 xxxxx00x xxxxx11x
IP1H KBCON KBMASK KBPATN
KBMASK KBMASK .2 .1 KBPATN. KBPATN. 2 1 82 KBI2 92 81 KBI1 91 RXD
Port 0
80H Bit address
P89LPC9102 / 9103 / 9107 User manual
P1 P0M1 P0M2 P1M1 P1M2 PCON PCONA PCONB
Port 1 Port 0 output mode 1 Port 0 output mode 2 Port 1 output mode 1 Port 1 output mode 2 Power control register Power control register A reserved for Power control register B
90H 84H 85H 91H 92H 87H B5H B6H
(P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) BOPD VCPD BOI ADPD GF1 GF0 -
FF 00 FF2 00 001 001
11111111 00000000 11111111 00000000 00000000 00000000 xxxxxxxx
(P1M1.1) (P1M1.0) PMOD1 SPD PMOD0
UM10112
(P1M2.1) (P1M2.0) 002
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Table 5: P89LPC9103 special function registers ..continued indicates SFRs that are bit addressable. Name Description SFR addr. Bit address PSW PT0AD RSTSRC RTCCON RTCH RTCL SADDR SADEN
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User manual 18 of 91
Philips Semiconductors
Reset value Hex 00 00
Binary 00000000 xx00000x 011xxx00 00000000 00000000 00000000 00000000 xxxxxxxx 00000000 00000000 00000111 00000000 00000000 00000000 00000000 00000000 00000000
Program status word Port 0 digital input disable Reset source register Real-time clock control Real-time clock register high Real-time clock register low Serial port address register Serial port address enable Serial port data buffer register Serial port control Serial port extended status register Stack pointer Timer 0 and 1 control Timer 0 high Timer 1 high Timer 0 low Timer 1 low Timer 0 and 1 mode Internal oscillator trim register Watchdog control register Watchdog load Watchdog feed 1 Watchdog feed 2
D0H F6H DFH D1H D2H D3H A9H B9H 99H
007 007 00 00 xx 9F SM0 / FE DBMOD 9E SM1 INTLO 9D SM2 CIDIS 9C REN DBISEL 9B TB8 FE 9A RB8 BR 99 TI OE 98 RI STINT 00 00 07 8F TF1 8E TR1 8D TF0 8C TR0 8B 8A 89 88 00 00 00 00 00 RCCLK PRE2 ENCLK PRE1 T1M1 TRIM.5 PRE0 T1M0 TRIM.4 TRIM.3 TRIM.2 WDRUN T0M1 TRIM.1 WDTOF T0M0 TRIM.0 WDCLK 00
SBUF SCON SSTAT SP TCON TH0 TH1 TL0 TL1 TMOD TRIM WDCON WDL WFEED1 WFEED2
Bit address 98H BAH 81H Bit address 88H 8CH 8DH 8AH 8BH 89H 96H A7H C1H C2H C3H
P89LPC9102 / 9103 / 9107 User manual
UM10112
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Philips Semiconductors
P89LPC9102 / 9103 / 9107 User manual
UM10112
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
User manual Rev. 01 - 11 February 2005
Philips Semiconductors
P89LPC9102 / 9103 / 9107 User manual
xx000000 00000000
UM10112
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Table 6: P89LPC9107 special function registers ..continued indicates SFRs that are bit addressable. Name FMDATA IEN0 IEN1 IP0 IP0H Description Program Flash data Interrupt enable 0 Interrupt enable 1 Interrupt priority 0 Interrupt priority 0 high SFR addr. E5H A8H Bit address E8H Bit address B8H B7H Bit address IP1
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User manual 21 of 91
Philips Semiconductors
Reset value Hex 00 00 001 001 001 Binary 00000000 00000000 00x00000 x0000000 x0000000
Interrupt priority 1 Interrupt priority 1 high Keypad control register Keypad interrupt mask register Keypad pattern register
F8H F7H 94H 86H 93H Bit address
001 001 001 00 FF
00x00000 00x00000 xxxxxx00 xxxxx00x xxxxx11x
IP1H KBCON KBMASK KBPATN
KBMASK KBMASK .2 .1 KBPATN. KBPATN. 2 1 82 KBI2 92 81 KBI1 91 RXD
Port 0
80H Bit address
P89LPC9102 / 9103 / 9107 User manual
P1 P0M1 P0M2 P1M1 P1M2 PCON PCONA PCONB
Port 1 Port 0 output mode 1 Port 0 output mode 2 Port 1 output mode 1 Port 1 output mode 2 Power control register Power control register A reserved for Power control register B
90H 84H 85H 91H 92H 87H B5H B6H
(P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) BOPD VCPD BOI ADPD GF1 GF0 -
FF 00 FF2 00 001 001
11111111 00000000 11111111 00000000 00000000 00000000 xxxxxxxx
(P1M1.1) (P1M1.0) PMOD1 SPD PMOD0
UM10112
(P1M2.1) (P1M2.0) 002
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Table 6: P89LPC9107 special function registers ..continued indicates SFRs that are bit addressable. Name Description SFR addr. Bit address PSW PT0AD RSTSRC RTCCON RTCH RTCL SADDR SADEN
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Reset value Hex 00 00
Binary 00000000 xx00000x 011xxx00 00000000 00000000 00000000 00000000 xxxxxxxx 00000000 00000000 00000111 00000000 00000000 00000000 00000000 00000000 00000000
Program status word Port 0 digital input disable Reset source register Real-time clock control Real-time clock register high Real-time clock register low Serial port address register Serial port address enable Serial port data buffer register Serial port control Serial port extended status register Stack pointer Timer 0 and 1 control Timer 0 high Timer 1 high Timer 0 low Timer 1 low Timer 0 and 1 mode Internal oscillator trim register Watchdog control register Watchdog load Watchdog feed 1 Watchdog feed 2
D0H F6H DFH D1H D2H D3H A9H B9H 99H
007 007 00 00 xx 9F SM0 / FE DBMOD 9E SM1 INTLO 9D SM2 CIDIS 9C REN DBISEL 9B TB8 FE 9A RB8 BR 99 TI OE 98 RI STINT 00 00 07 8F TF1 8E TR1 8D TF0 8C TR0 8B 8A 89 88 00 00 00 00 00 RCCLK PRE2 ENCLK PRE1 T1M1 TRIM.5 PRE0 T1M0 TRIM.4 TRIM.3 TRIM.2 WDRUN T0M1 TRIM.1 WDTOF T0M0 TRIM.0 WDCLK 00
SBUF SCON SSTAT SP TCON TH0 TH1 TL0 TL1 TMOD TRIM WDCON WDL WFEED1 WFEED2
Bit address 98H BAH 81H Bit address 88H 8CH 8DH 8AH 8BH 89H 96H A7H C1H C2H C3H
P89LPC9102 / 9103 / 9107 User manual
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Philips Semiconductors
P89LPC9102 / 9103 / 9107 User manual
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P89LPC9102 / 9103 / 9107 User manual
1.4 Memory organization
03FFh 0300h 02FFh 0200h 01FFh 0100h 00FFh 000h 1 kB flash code memory space SECTOR 3 SECTOR 2 SECTOR 1 SECTOR 0
SPECIAL FUNCTION REGISTERS (DIRECTLY ADDRESSABLE)
80h 7Fh
128 BYTES ON-CHIP DATA MEMORY (STACK, DIRECT AND INDIRECT ADDRESS) 4 REG. BANKS R7:0
data memory (DATA, IDATA)
002aab049
Fig 10. P89LPC9102 / 9103 / 9107 memory map.
The various P89LPC9102 / 9103 / 9107 memory spaces are as follows: DATA - 128 bytes of internal data memory space (00h:7Fh) accessed via direct or indirect addressing, using instruction other than MOVX and MOVC. All or part of the Stack may be in this area. SFR - Special Function Registers. Selected CPU registers and peripheral control and status registers, accessible only via direct addressing. CODE - 64 kB of Code memory space, accessed as part of program execution and via the MOVC instruction. The P89LPC9102 / 9103 / 9107 has 1 kB of on-chip Code memory.
Table 7: Type DATA Data RAM arrangement Data RAM Directly and indirectly addressable memory Size (bytes) 128
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2. Clocks
2.1 Enhanced CPU
The P89LPC9102 / 9103 / 9107 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles.
2.2 Clock definitions
The P89LPC9102 / 9103 / 9107 device has several internal clocks as defined below: OSCCLK - Input to the DIVM clock divider. OSCCLK is selected from one of the clock sources and can also be optionally divided to a slower frequency (see Figure 12 and Section 2.8 "CCLK modification: DIVM register"). Note: fosc is defined as the OSCCLK frequency. CCLK - CPU clock output of the DIVM clock divider. There are two CCLK cycles per machine cycle, and most instructions are executed in one to two machine cycles (two or four CCLK cycles). RCCLK - The internal 7.373 MHz RC oscillator output (14.7456 MHz with clock doubler enabled). PCLK - Clock for the various peripheral devices and is CCLK / 2.
2.3 Clock output
2.4 On-chip RC oscillator option with clock doubler mode
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Table 8: Bit Symbol Reset Table 9: Bit 0 1 2 3 4 5 6 7
On-chip RC oscillator trim register (TRIM - address 96h) bit allocation 7 RCCLK 0 6 ENCLK 0 5 TRIM.5 4 TRIM.4 3 TRIM.3 2 TRIM.2 1 TRIM.1 0 TRIM.0
Bits 5:0 loaded with factory stored value during reset.
2.5 Watchdog oscillator option
The Watchdog has a separate oscillator which has a frequency of 400 kHz. This oscillator can be used to save power when a high clock frequency is not needed.
2.6 External clock input option
In this configuration, the processor clock is derived from an external source driving the P0.5 / CMPREF / CLKIN pin. The rate may be from 0 Hz up to 18 MHz. This pin may also be used as a standard port pin. When using an external clock input frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until VDD has reached its specified level. When system power is removed VDD will fall below the minimum specified operating voltage. When using an external clock input frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when VDD falls below the minimum specified operating voltage. These requirements for clock frequencies above 12 MHz do not apply when using the internal RC oscillator in clock doubler mode.
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CLKIN RC OSCILLATOR WITH CLOCK DOUBLER OPTION (7.3728 MHz or 14.7456 MHz) WATCHDOG OSCILLATOR (400 kHz) PCLK
TIMER 0 TIMER 1
002aaa973
Fig 11. Block diagram of P89LPC9102 oscillator control.
CLKIN RC OSCILLATOR WITH CLOCK DOUBLER OPTION (7.3728 MHz or 14.7456 MHz) WATCHDOG OSCILLATOR (400 kHz) PCLK
TIMER 0 TIMER 1
BAUD RATE GENERATOR
002aaa974
Fig 12. Block diagram of P89LPC9103, P89LPC9107 oscillator control.
2.7 CPU Clock (CCLK) wake-up delay
The P89LPC9102 / 9103 / 9107 has an internal wake-up timer that delays the clock until it stabilizes depending to the clock source used.
2.8 CCLK modification: DIVM register
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2.9 Low power select
The P89LPC9102 / 9103 / 9107 is designed to run at 18 MHz (CCLK) maximum. However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to a logic 1 to lower the power consumption further. On any reset, CLKLP is logic 0 allowing highest performance. This bit can then be set in software if CCLK is running at 8 MHz or slower.
3. A / D converter
The P89LPC9102 / 9103 / 9107 has an 8-bit, 4-channel, multiplexed successive approximation analog-to-digital converter module (ADC1) and one DAC module (DAC1). A block diagram of the A / D converter is shown in Figure 13. The A / D consists of a 4-input multiplexer which feeds a sample and hold circuit providing an input signal to one of two comparator inputs. The control logic in combination with the successive approximation register (SAR) drives a digital-to-analog converter which provides the other input to the comparator. The output of the comparator is fed to the SAR.
comp INPUT MUX + SAR - CONTROL LOGIC
002aaa975
Fig 13. A / D converter block diagram.
3.1 Features · An 8-bit, 4-channel, multiplexed input, successive approximation A / D converter · Four A / D result registers · Six operating modes
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- Fixed channel, single conversion mode - Fixed channel, continuous conversion mode - Auto scan, single conversion mode - Auto scan, continuous conversion mode - Dual channel, continuous conversion mode - Single step mode
· Three conversion start modes
- Timer triggered start - Start immediately - Edge triggered
8-bit conversion time of 3.9 µs at an ADC clock of 3.3 MHz Interrupt or polled operation Boundary limits interrupt DAC output to a port pin with high output impedance Clock divider Power-down mode
3.2 A / D operating modes
3.2.1 Fixed channel, single conversion mode
A single input channel can be selected for conversion. A single conversion will be performed and the result placed in the result register which corresponds to the selected input channel (See Table 10). An interrupt, if enabled, will be generated after the conversion completes. The input channel is selected in the ADINS register. This mode is selected by setting the SCAN1 bit in the ADMODA register.
Table 10: Input channels and Result registers for fixed channel single, auto scan single, and autoscan continuous conversion modes. Input channel AD10 AD11 Result register AD1DAT2 AD1DAT3 Input channel AD12 AD13
Result register AD1DAT0 AD1DAT1
3.2.2 Fixed channel, continuous conversion mode
A single input channel can be selected for continuous conversion. The results of the conversions will be sequentially placed in the four result registers Table 11. An interrupt, if enabled, will be generated after every four conversions. Additional conversion results will again cycle through the four result registers, overwriting the previous results. Continuous conversions continue until terminated by the user. This mode is selected by setting the SCC1 bit in the ADMODA register.
3.2.3 Auto scan, single conversion mode
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(See Table 10). An interrupt, if enabled, will be generated after all selected channels have been converted. If only a single channel is selected this is equivalent to single channel, single conversion mode. This mode is selected by setting the SCAN1 bit in the ADMODA register.
Table 11: Result registers and conversion results for fixed channel, continuous conversion mode. Contains Selected channel, first conversion result Selected channel, second conversion result Selected channel, third conversion result Selected channel, forth conversion result
Result register AD1DAT0 AD1DAT1 AD1DAT2 AD1DAT3
3.2.4 Auto scan, continuous conversion mode
3.2.5 Dual channel, continuous conversion mode
Any combination of two of the four input channels can be selected for conversion. The result of the conversion of the first channel is placed in the first result register. The result of the conversion of the second channel is placed in the second result register. The first channel is again converted and its result stored in the third result register. The second channel is again converted and its result placed in the fourth result register (See Table 12). An interrupt is generated, if enabled, after every set of four conversions (two conversions per channel). This mode is selected by setting the SCC1 bit in the ADMODA register.
Table 12: Result registers and conversion results for dual channel, continuous conversion mode. Contains First channel, first conversion result Second channel, first conversion result First channel, second conversion result Second channel, second conversion result
Result register AD1DAT0 AD1DAT1 AD1DAT2 AD1DAT3
3.2.6 Single step
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the selected input channel (See Table 10). May be used with any of the start modes. This mode is selected by clearing the BURST1, SCC1, and SCAN1 bits in the ADMODA register.
3.2.7 Conversion mode selection bits
The A / D uses three bits in ADMODA to select the conversion mode. These mode bits are summarized in Table 13, below. Combinations of the three bits, other than the combinations shown, are undefined.
Table 13: Conversion mode bits. Scan1 ADC1 conversion BURST0 SCC0 mode 0 1 single step fixed channel, single auto scan, single 0 1 0 fixed channel, continuous dual channel, continuous 1 0 0 auto scan, continuous 1 0 0 0 1 0 0 0 0 0 Scan0 0 1 ADC0 conversion mode single step fixed channel, single auto scan, single fixed channel, continuous dual channel, continuous auto scan, continuous
BURST1 SCC1 0 0 0 0
3.3 Trigger modes
3.3.1 Timer triggered start
An A / D conversion is started by the overflow of Timer 0. Once a conversion has started, additional Timer 0 triggers are ignored until the conversion has completed. The Timer triggered start mode is available in all A / D operating modes. This mode is selected by the TMM1 bit and the ADCS11 and ADCS10 bits (See Table 15).
3.3.2 Start immediately
Programming this mode immediately starts a conversion. This start mode is available in all A / D operating modes. This mode is selected by setting the ADCS11 and ADCS10 bits in the ADCON1 register (See Table 15).
3.3.3 Edge triggered
An A / D conversion is started by rising or falling edge of P1.4. Once a conversion has started, additional edge triggers are ignored until the conversion has completed. The edge triggered start mode is available in all A / D operating modes. This mode is selected by setting the ADCS11 and ADCS10 bits in the ADCON1 register (See Table 15).
3.3.4 Boundary limits interrupt
The A / D converter has both a HIGH and LOW boundary limit register. After the four MSBs have been converted, these four bits are compared with the four MSBs of the boundary HIGH and LOW registers. If the four MSBs of the conversion are outside the limit an interrupt will be generated, if enabled. If the conversion result is within the limits, the
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boundary limits will again be compared after all eight bits have been converted. An interrupt will be generated, if enabled, if the result is outside the boundary limits. The boundary limit may be disabled by clearing the boundary limit interrupt enable.
3.4 DAC output to a port pin with high-impedance
The AD0DAT3 register is used to hold the value fed to the DAC. After a value has been written to AD0DAT3 the DAC output will appear on the DAC0 pin. The DAC output is enabled by the ENDAC0 bit in the ADMODB register (See Table 19).
3.5 Clock divider
The A / D converter requires that its internal clock source be in the range of 500 kHz to 3.3 MHz to maintain accuracy. A programmable clock divider that divides the clock from 1 to 8 is provided for this purpose (See Table 19).
3.6 I / O pins used with A / D converter functions
The analog input pins used with for the A / D converter have a digital input and output function. In order to give the best analog performance, pins that are being used with the ADC or DAC should have their digital outputs and inputs disabled and have the 5 V tolerance disconnected. Digital outputs are disabled by putting the port pins into the input-only mode as described in the Port Configurations section (see Table 25). Digital inputs will be disconnected automatically from these pins when the pin has been selected by setting its corresponding bit in the ADINS register and the A / D or DAC has been enabled. Pins selected in ADINS will be 3 V tolerant provided that the A / D is enabled and the device is not in power-down, otherwise the pin will remain 5 V tolerant.
3.7 Power-down and idle mode
In idle mode the A / D converter, if enabled, will continue to function and can cause the device to exit idle mode when the conversion is completed if the A / D interrupt is enabled. In Power-down mode or Total Power-down mode, the A / D does not function. If the A / D is enabled, it will consume power. Power can be reduced by disabling the A / D.
Table 14: Bit Symbol Reset Table 15: Bit 0 1 A / D Control register 1 (ADCON1 - address 97h) bit allocation 7 ENBI1 0 6 ENADCI1 0 5 TMM1 0 4 0 3 ADCI1 0 2 ENADC1 0 1 ADCS11 0 0 ADCS10 0
ENADC1
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Table 16: Bit Symbol Reset Table 17: Bit 0:3 4 5 6 7
A / D Mode Register A (ADMODA - address C0h) bit allocation 7 BNBI1 0 6 BURST1 0 5 SCC1 0 4 SCAN1 0 3 0 2 0 1 0 0 0
Table 18: Bit Symbol Reset Table 19: Bit 0 1
A / D Mode Register B (ADMODB - address A1h) bit allocation 7 CLK2 0 6 CLK1 0 5 CLK0 0 4 0 3 ENDAC1 0 2 0 1 BSA1 0 0 0
ENDAC1 -
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Table 19: Bit 5 6 7
A / D Mode Register B (ADMODB - address A1h) bit description Symbol CLK0 CLK1 CLK2 Description Clock divider to produce the ADC clock. Divides CCLK by the value indicated below. The resulting ADC clock should be 3.3 MHz or less. A minimum of 0.5 MHz is required to maintain A / D accuracy. CLK2:0 - divisor 000 - 1 001 - 2 010 - 3 011 - 4 100 - 5 101 - 6 110 - 7 111 - 8
Table 20: Bit Symbol Reset Table 21: Bit 0:3 4 5 6 7
A / D Input Select register (ADINS - address A3h) bit allocation 7 AIN13 0 6 AIN12 0 5 AIN11 0 4 AIN10 0 3 0 2 0 1 0 0 0
A / D Input Select register (ADINS - address A3h) bit description Symbol AIN10 AIN11 AIN12 AIN13 Description reserved when set, enables the AD10 pin for sampling and conversion when set, enables the AD11 pin for sampling and conversion when set, enables the AD12 pin for sampling and conversion when set, enables the AD13 pin for sampling and conversion
4. Interrupts
The P89LPC9102 supports nine interrupt sources: timers 0 and 1, brownout detect, watchdog timer / RTC, keyboard, comparator 1, and the A / D converter. The P89LPC9103 supports nine interrupt sources: timers 0 and 1, serial port Tx, serial port Rx, combined serial port Rx / Tx, brownout detect, watchdog timer / RTC, keyboard, comparator, and the A / D converter. Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global disable bit, EA, which disables all interrupts. Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An interrupt service routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. The highest priority interrupt service cannot be interrupted by any other interrupt source. If two requests of different priority levels are pending at the start of an instruction, the request of higher priority level is serviced.
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If requests of the same priority level are pending at the start of an instruction, an internal polling sequence determines which request is serviced. This is called the arbitration ranking. Note that the arbitration ranking is only used to resolve pending requests of the same priority level.
4.1 Interrupt priority structure
Table 22: IPxH 0 0 1 1 Interrupt priority level IPx 0 1 0 1 Interrupt priority level Level 0 (lowest priority) Level 1 Level 2 Level 3 Priority bits
Table 23: Summary of interrupts Interrupt flag bit(s) TF0 TF1 TI and RI RI BOF KBIF CMF1 TI ADCI1, BNDI1 002Bh 0053h 003Bh 0043h 006Bh 0073h EBO (IEN0.5) EWDRT (IEN0.6) EKBI (IEN1.1) EC (IEN1.2) EST (IEN1.6) EAD (IEN1.7) IP0H.5, IP0.5 IP0H.6, IP0.6 IP0H.0, IP0.0 IP0H.0, IP0.0 IP0H.0, IP0.0 IP1H.7, IP1.7 2 3 8 11 12 15 (lowest) Yes Yes Yes Yes No No Vector address 000Bh 001Bh 0023h Interrupt enable bit(s) ET0 (IEN0.1) ET1 (IEN0.3) ES / ESR (IEN0.4) Interrupt priority IP0H.1, IP0.1 IP0H.3, IP0.3 IP0H.4, IP0.4 Arbitration Powerranking down wake-up 4 10 13 No No No
Description
Timer 0 interrupt Timer 1 interrupt Serial port Tx and Rx (9103, 9107) Serial port Rx (9103, 9107) Brownout detect KBI interrupt Comparator 1 interrupt Serial port Tx (9103, 9107) ADC
Watchdog timer / Real-time clock WDOVF / RTCF
4.1.1 External interrupt inputs
The P89LPC9102 / 9103 / 9107 has a Keypad Interrupt function. This can be used as an external interrupt input. If enabled when the P89LPC9102 / 9103 / 9107 is put into Power-down mode or Idle mode, the interrupt will cause the processor to wake-up and resume operation. Refer to Section 6.3 "Power reduction modes" for details.
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BOF EBO RTCF ERTC (RTCCON.1) WDOVF KBIF EKBI EWDRT CMF EC EA (IE0.7) TF1 ET1 TF0 ET0 interrupt to CPU wake-up (if in power-down)
ENADCI1 ADCI1 ENBI1 BNDI1 EAD
002aaa976
Fig 14. Interrupt sources, interrupt enables, and power-down wake-up sources (P89LPC9102).
BOF EBO RTCF ERTC (RTCCON.1) WDOVF KBIF EKBI EWDRT CMF EC EA (IE0.7) TF1 ET1 TI and RI / RI ES / ESR TI EST TF0 ET0 ENADCI1 ADCI1 ENBI1 BNDI1 EAD
002aaa977
wake-up (if in power-down)
interrupt to CPU
Fig 15. Interrupt sources, interrupt enables, and power-down wake-up sources (P89LPC9103 / P89LPC9107).
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The P89LPC9102 / 9103 / 9107 has three I / O ports: Port 0, Port 1, and Port 3. Ports 0 and 1 are 8-bit ports and Port 3 is a 2-bit port. The exact number of I / O pins available depends upon the clock and reset options chosen (see Table 24).
Table 24: Number of I / O pins available Reset option Number of I / O pins (8-pin package) 8 7 7 6 Number of I / O pins (8-pin package) 8
Clock source
On-chip RC oscillator or watchdog oscillator No external reset (except during power-up) External RST pin supported External clock input Clock source On-chip oscillator or watchdog oscillator
No external reset (except during power-up) External RST pin supported1 Reset option No external reset (except during power-up)
Required for operation with external clock frequency above 12 MHz.
5.1 Port configurations
All but one I / O port pin on the P89LPC9102 / 9103 / 9107 may be configured by software to one of four types on a pin-by-pin basis, as shown in Table 25. These are: quasi-bidirectional (standard 80C51 port outputs), push-pull, open drain, and input-only. Two configuration registers for each port select the output type for each port pin. P1.5 (RST) can only be an input and cannot be configured.
Table 25: PxM1.y 0 0 1 1 Port output configuration settings PxM2.y 0 1 0 1 Port output mode Quasi-bidirectional Push-pull Input only (high-impedance) Open drain
5.2 Quasi-bidirectional output configuration
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VDD 2 CPU CLOCK DELAY
P strong
very P weak
PORT PIN port latch data
input data glitch rejection
002aaa914
Fig 16. Quasi-bidirectional output.
5.3 Open drain output configuration
The open drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port pin when the port latch contains a logic 0. To be used as a logic output, a port configured in this manner must have an external pull-up, typically a resistor tied to VDD. The pull-down for this mode is the same as for the quasi-bidirectional mode. The open drain port configuration is shown in Figure 17. An open drain port pin has a Schmitt triggered input that also has a glitch suppression circuit.
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Please refer to the P89LPC9102 / 9103 / 9107 data sheet, Dynamic characteristics for glitch filter specifications.
PORT PIN port latch data
input data glitch rejection
002aaa915
Fig 17. Open drain output.
5.4 Input-only configuration
The input port configuration is shown in Figure 18. It is a Schmitt triggered input that also has a glitch suppression circuit. (Please refer to the P89LPC9102 / 9103 / 9107 data sheet, Dynamic characteristics for glitch filter specifications).
input data glitch rejection
PORT PIN
002aaa916
Fig 18. Input only.
5.5 Push-pull output configuration
The push-pull output configuration has the same pull-down structure as both the open drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains a logic 1. The push-pull mode may be used when more source current is needed from a port output. The push-pull port configuration is shown in Figure 19. A push-pull port pin has a Schmitt triggered input that also has a glitch suppression circuit. (Please refer to the P89LPC9102 / 9103 / 9107 data sheet, Dynamic characteristics for glitch filter specifications).
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VDD P strong
port latch data
PORT PIN
input data
glitch rejection
002aaa917
Fig 19. Push-pull output.
5.6 Port 0 analog functions
5.7 Additional port features
After power-up, all pins are in Input-Only mode. Please note that this is different from the LPC76x series of devices.
· After power-up, all I / O pins except P1.5, may be configured by software. · Pin P1.5 is input only.
Every output on the P89LPC9102 / 9103 / 9107 has been designed to sink typical LED drive current. However, there is a maximum total output current for all ports which must not be exceeded. Please refer to the P89LPC9102 / 9103 / 9107 data sheet for detailed specifications. All ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals. The slew rate is factory-set to approximately 10 ns rise and fall times.
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Port output configuration Configuration SFR bits PxM1.y PxM2.y P0M2.1 P0M2.2 P0M2.3 P0M2.4 P0M2.5 P0M2.7 P1M2.0 P1M2.1 P1M2.2 P1M2.5 Alternate usage KBI1, AD10 KBI2, AD11 KBI3, CIN1B, AD12 CIN1A, AD13, DAC1 KBI5, CMPREF, CLKIN T1, CLKOUT TXD RXD T0 RST Notes Refer to Section 5.6 "Port 0 analog functions" for usage as analog inputs. P0M1.1 P0M1.2 P0M1.3 P0M1.4 P0M1.5 P0M1.7 P1M1.0 P1M1.1 P1M1.2 P1M1.5
Table 26: Port pin P0.1 P0.2 P0.3 P0.4 P0.5 P0.7 P1.0 P1.1 P1.2 P1.5
6. Power monitoring functions
The P89LPC9102 / 9103 / 9107 incorporates power monitoring functions designed to prevent incorrect operation during initial power-on and power loss or reduction during operation. This is accomplished with two hardware functions: Power-on Detect and Brownout Detect.
6.1 Brownout detection
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Table 27: BOE (UCFG1.5) 0 (erased) 1(program med) Brownout options PMOD1-0 (PCON.1-0) XX 11 (total power-down) 11 (any mode other than total power-down BOPD (PCON.5) X X 1(brownout detect powered down) 0 (brownout detect active) BOI (PCON.4) X X X EBO (IEN0.5) X X X EA (IEN0.7) Description X X X Brownout disabled. VDD operating range is 2.4 V to 3.6 V. Brownout disabled. VDD operating range is 2.4 V to 3.6 V. However, BOPD is default to logic 0 upon power-up. Brownout reset enabled. VDD operating range is 2.7 V to 3.6 V. Upon a brownout reset, BOF (RSTSRC.5) will be set to indicate the reset source. BOF can be cleared by writing logic 0 to the bit. Brownout interrupt enabled. VDD operating range is 2.7 V to 3.6 V. Upon a brownout interrupt, BOF (RSTSRC.5) will be set. BOF can be cleared by writing logic 0 to the bit. Both brownout reset and interrupt disabled. VDD operating range is 2.4 V to 3.6 V. However, BOF (RSTSRC.5) will be set when VDD falls to the Brownout Detection trip point. BOF can be cleared by writing logic 0 to the bit.
0 (brownout detect generates reset)
1 (brownout detect generates an interrupt)
1 (enable brownout interrupt)
1 (global interrupt enable)
6.2 Power-on detection
The Power-On Detect has a function similar to the Brownout Detect, but is designed to work as power initially comes up, before the power supply voltage reaches a level where the Brownout Detect can function. The POF flag (RSTSRC.4) is set to indicate an initial power-on condition. The POF flag will remain set until cleared by software by writing logic 0 to the bit. Note that if BOE (UCFG1.5) is programmed, BOF (RSTSRC.5) will be set when POF is set. If BOE is unprogrammed, BOF is meaningless.
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6.3 Power reduction modes
The P89LPC9102 / 9103 / 9107 supports three different power reduction modes as determined by SFR bits PCON.1-0 (see Table 28).
Table 28: Power reduction modes
PMOD1 PMOD0 Description (PCON.1) (PCON.0) 0 0 0 1 Normal mode (default) - no power reduction. Idle mode. The Idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated. Any enabled interrupt source or reset may terminate Idle mode. Power-down mode: The Power-down mode stops the oscillator in order to minimize power consumption. The P89LPC9102 / 9103 / 9107 exits Power-down mode via any reset, or certain interrupts, brownout Interrupt, or keyboard, Real-time Clock / System Timer), Watchdog, and comparator trips. Waking up by reset is only enabled if the corresponding reset is enabled, and waking up by interrupt is only enabled if the corresponding interrupt is enabled and the EA SFR bit (IEN0.7) is set. In Power-down mode the internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock AND the RTC is enabled. In Power-down mode, the power supply voltage may be reduced to the RAM keep-alive voltage VRAM. This retains the RAM contents at the point where Power-down mode was entered. SFR contents are not guaranteed after VDD has been lowered to VRAM, therefore it is recommended to wake up the processor via Reset in this situation. VDD must be raised to within the operating range before the Power-down mode is exited. When the processor wakes up from Power-down mode, it will start the oscillator immediately and begin execution when the oscillator is stable. Oscillator stability is determined by counting 256 clocks after start-up for the internal RC or external clock input configurations. Some chip functions continue to operate and draw power during Power-down mode, increasing the total power used during power-down. These include:
Brownout Detect Watchdog timer if WDCLK (WDCON.0) is logic 1 Comparator (Note: Comparator can be powered down separately with PCONA.5 set to logic 1 and comparator disabled) Real-time Clock / System Timer (unless RTCPD is logic 1)
Total Power-down mode: This is the same as Power-down mode except that the Brownout Detection circuitry and the voltage comparator is also disabled to conserve additional power. Note that a brownout reset or interrupt will not occur. Voltage comparator interrupt and Brownout interrupt cannot be used as a wake-up source. The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock AND the RTC is enabled. The following are the wake-up options supported:
Watchdog timer if WDCLK (WDCON.0) is logic 1. Could generate Interrupt or Reset, either one can wake up the device Keyboard Interrupt Real-time Clock / System Timer (unless RTCPD, i.e., PCONA.7 is logic 1)
Note: Using the internal RC-oscillator to clock the RTC during power-down may result in relatively high power consumption. Lower power consumption can be achieved by using an external low frequency clock when the Real-time Clock is running during power-down.
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Table 29: Bit Symbol Reset Table 30: Bit 0 1 2 3 4 5
Power Control register (PCON - address 87h) bit allocation 7 SMOD1 0 6 SMOD0 0 5 BOPD 0 4 BOI 0 3 GF1 0 2 GF0 0 1 PMOD1 0 0 PMOD0 0
Power Control register (PCON - address 87h) bit description Symbol PMOD0 PMOD1 GF0 GF1 BOI BOPD General Purpose Flag 0. May be read or written by user software, but has no effect on operation General Purpose Flag 1. May be read or written by user software, but has no effect on operation Brownout Detect Interrupt Enable. When logic 1, Brownout Detection will generate a interrupt. When logic 0, Brownout Detection will cause a reset Brownout Detect power-down. When logic 1, Brownout Detect is powered down and therefore disabled. When logic 0, Brownout Detect is enabled. (Note: BOPD must be logic 0 before any programming or erasing commands can be issued. Otherwise these commands will be aborted.) Framing Error Location: Description Power Reduction Mode (see Section 6.3)
SMOD0
7 SMOD1
When logic 0, bit 7 of SCON is accessed as SM0 for the UART When logic 1, bit 7 of SCON is accessed as the framing error status (FE) for the UART (P89LPC9103)
Double Baud Rate bit for the serial port (UART) when Timer 1 is used as the baud rate source. When logic 1, the Timer 1 overflow rate is supplied to the UART. When logic 0, the Timer 1 overflow rate is divided by two before being supplied to the UART. (See Section 10) (P89LPC9103)
Table 31: Bit Symbol Reset Table 32: Bit 0 1
Power Control register A (PCONA - address B5h) bit allocation 7 RTCPD 0 6 0 5 VCPD 0 4 ADPD 0 3 0 2 0 1 SPD 0 0 0
Power Control register A (PCONA - address B5h) bit description Symbol SPD Description reserved Serial Port (UART) power-down: When logic 1, the internal clock to the UART is disabled. Note that in either Power-down mode or Total Power-down mode, the UART clock will be disabled regardless of this bit (P89LPC9103). reserved reserved A / D Converter power-down: When logic 1, turns off the clock to the ADC. To fully power-down the ADC, the user should also set the ENADC1 and ENADC0 bits in registers ADCON1 and ADCON0.
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Table 32: Bit 5 6 7
Power Control register A (PCONA - address B5h) bit description Symbol VCPD RTCPD Description Analog Voltage Comparator power-down: When logic 1, the voltage comparator is powered down. User must disable the voltage comparator prior to setting this bit. reserved Real-time Clock power-down: When logic 1, the internal clock to the Real-time Clock is disabled.
7. Reset
The P1.5 / RST pin can function as either an active LOW reset input or as a digital input, P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to 1, enables the external reset input function on P1.5. When cleared, P1.5 may be used as an input pin. NOTE: During a power-on sequence, The RPE selection is overridden and this pin will always functions as a reset input. An external circuit connected to this pin should not hold this pin LOW during a Power-on sequence as this will keep the device in reset. After power-on this input will function either as an external reset input or as a digital input as defined by the RPE bit. Only a power-on reset will temporarily override the selection defined by RPE bit. Other sources of reset will not override the RPE bit. NOTE: During a power cycle, VDD must fall below VPOR (see P89LPC9102 / 9103 Data sheet, Static characteristics) before power is reapplied, in order to ensure a power-on reset. Reset can be triggered from the following sources (see Figure 20):
· External reset pin (during power-on or if user configured via UCFG1. Required for
external clock frequency above 12 MHz.)
Power-on Detect Brownout Detect Watchdog timer Software reset UART break detect reset (P89LPC9103, P89LPC9107)
For every reset source, there is a flag in the Reset Register, RSTSRC. The user can read this register to determine the most recent reset source. These flag bits can be cleared in software by writing a logic 0 to the corresponding bit. More than one flag bit may be set:
· During a power-on reset, both POF and BOF are set but the other flag bits are
cleared.
· For any other reset, any previously set flag bits that have not been cleared will remain
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RPE (UCFG1.6) RST pin WDTE (UCFG1.7) watchdog timer reset software reset SRST (AUXR1.3) chip reset power-on detect UART break detect (1) EBRR (AUXR1.6) brownout detect reset BOPD (PCON.5)
002aab050
(1) P89LPC9103, P89LPC9107
Fig 20. Block diagram of reset. Table 33: Bit Symbol Reset1
The value shown is for a power-on reset. Other reset sources will set their corresponding bits.
Bit Symbol
7.1 Reset vector
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8. Timers 0 and 1
Table 35: Bit Symbol Reset Table 36: 0 1 2 3 4 5 6 7 T0M0 T0M1 T0C / T T1M0 T1M1 T1C / T Timer / Counter Mode register (TMOD - address 89h) bit allocation 7 0 6 T1C / T 0 5 T1M1 0 4 T1M0 0 3 0 2 T0C / T 0 1 T0M1 0 0 T0M0 0
Timer / Counter Mode register (TMOD - address 89h) bit description Description Mode Select for Timer 0. These bits are used with the T0M2 bit in the TAMOD register to determine the Timer 0 mode (see Table 38). Timer or Counter selector for Timer 0. Cleared for Timer operation (input from CCLK). Set for Counter operation (input from T0 input pin) (P89LPC9102, P89LPC9107). reserved Mode Select for Timer 1. These bits are used with the T1M2 bit in the TAMOD register to determine the Timer 1 mode (see Table 38). Timer or Counter Selector for Timer 1. Cleared for Timer operation (input from CCLK). Set for Counter operation (input from T1 input pin) (P89LPC9102, P89LPC9107). reserved
Bit Symbol
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Table 37: Bit Symbol Reset Table 38: 0 T0M2
Timer / Counter Auxiliary Mode register (TAMOD - address 8Fh) bit allocation 7 -x 6 x 5 x 4 T1M2 0 3 x 2 x 1 x 0 T0M2 0
Bit Symbol
1:3 4 T1M2
reserved
8.1 Mode 0
8.2 Mode 1
Mode 1 is the same as Mode 0, except that all 16 bits of the timer register (THn and TLn) are used. See Figure 22.
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8.3 Mode 2
Mode 2 configures the Timer register as an 8-bit Counter (TLn) with automatic reload, as shown in Figure 23. Overflow from TLn not only sets TFn, but also reloads TLn with the contents of THn, which must be preset by software. The reload leaves THn unchanged. Mode 2 operation is the same for Timer 0 and Timer 1.
8.4 Mode 3
8.5 Mode 6 (P89LPC9102, P89LPC9107)
In this mode, the corresponding timer can be changed to a PWM with a full period of 256 timer clocks (see Figure 25). Its structure is similar to mode 2, except that:
Note that interrupt can still be enabled on the LOW to HIGH transition of TFn, and that TFn can still be cleared in software like in any other modes.
Table 39: Bit Symbol Reset Table 40: 0 1 2 3 4 TR0 Timer / Counter Control register (TCON) - address 88h) bit allocation 7 TF1 0 6 TR1 0 5 TF0 0 4 TR0 0 3 0 2 0 1 0 0 0
Timer / Counter Control register (TCON - address 88h) bit description Description reserved reserved reserved reserved Timer 0 Run control bit. Set / cleared by software to turn Timer / Counter 0 on / off.
Bit Symbol
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Table 40: 5 6 7 TF0 TR1 TF1
Timer / Counter Control register (TCON - address 88h) bit description Description Timer 0 overflow flag. Set by hardware on Timer / Counter overflow. Cleared by hardware when the processor vectors to the interrupt routine, or by software. (except in mode 6, where it is cleared in hardware) Timer 1 Run control bit. Set / cleared by software to turn Timer / Counter 1 on / off Timer 1 overflow flag. Set by hardware on Timer / Counter overflow. Cleared by hardware when the interrupt is processed, or by software (except in mode 6, see above, when it is cleared in hardware).
Bit Symbol
PCLK Tn pin(1)
overflow TFn interrupt
toggle TRn Tn pin(1)
002aab055
(1) Tn pin functions available on P89LPC9102, P89LPC9107
Fig 21. Timer / counter 0 or 1 in Mode 0 (13-bit counter).
PCLK Tn pin(1)
overflow TFn interrupt
toggle TRn Tn pin(1)
002aab056
(1) Tn pin functions available on P89LPC9102, P89LPC9107
Fig 22. Timer / counter 0 or 1 in mode 1 (16-bit counter).
PCLK Tn pin(1)
overflow TFn interrupt
toggle Tn pin(1)
TRn THn (8-bits)
002aab057
(1) Tn pin functions available on P89LPC9102, P89LPC9107
Fig 23. Timer / counter 0 or 1 in Mode 2 (8-bit auto-reload).
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PCLK T0 pin(1)
overflow TF0 toggle interrupt
T0 pin(1)
ENT0 overflow TF1 interrupt
PCLK control
TH0 (8-bits)
002aab058
(1) Tn pin functions available on P89LPC9102, P89LPC9107
Fig 24. Timer / counter 0 Mode 3 (two 8-bit counters).
overflow TFn interrupt
reload THn on falling transition and (256 - THn) on rising transition
toggle TRn THn(8-bits) ENTn
002aab059
Tn pin(1)
(1) Tn pin functions available on P89LPC9102, P89LPC9107
Fig 25. Timer / counter 0 or 1 in mode 6 (PWM auto-reload).
8.6 Timer overflow toggle output (P89LPC9102, P89LPC9107)
Timers 0 and 1 can be configured to automatically toggle a port output whenever a timer overflow occurs. The same device pins that are used for the T0 and T1 count inputs and PWM outputs are also used for the timer toggle outputs. This function is enabled by control bits ENT0 and ENT1 in the AUXR1 register, and apply to Timer 0 and Timer 1 respectively. The port outputs will be a logic 1 prior to the first timer overflow when this mode is turned on. In order for this mode to function, the C / T bit must be cleared selecting PCLK as the clock source for the timer.
9. Real-time clock system timer
The P89LPC9102 / 9103 / 9107 has a simple Real-time Clock / System Timer that allows a user to continue running an accurate timer while the rest of the device is powered down. The Real-time Clock can be an interrupt or a wake-up source (see Figure 26). The Real-time Clock is a 23-bit down counter. The clock source for this counter can be either the CPU clock (CCLK) or an external Clock Input (CLKIN). There are three SFRs used for the RTC:
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power-on reset
RTC RESET
RELOAD ON UNDERFLOW
23-BIT DOWN COUNTER
wake-up from power-down RTCF Interrupt if enabled (shared with WDT) RTC underflow flag ERTC
002aab227
RTCEN RTC enable
RTCS1 RTCS2 RTC clk select
Fig 26. Real-time clock / system timer block diagram.
9.1 Real-time clock source
RTCS1-0 (RTCCON6:5) are used to select either the external clock input or CCLK as the clock source for the RTC, if either the Internal RC oscillator or the internal WD oscillator is used as the CCLK. If CCLK is derived from the external clock input on P0.5 then the RTC can use CCLK (external clock input / DIVM) or the external input as its clock source.
9.2 Changing RTCS1-0
9.3 Real-time clock interrupt / wake-up
If ERTC (RTCCON.1), EWDRT (IEN16:0) and EA (IEN0.7) are set to logic 1, RTCF can be used as an interrupt source. This interrupt vector is shared with the watchdog timer. It can also be a source to wake up the device.
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9.4 Reset sources affecting the Real-time clock
Only power-on reset will reset the Real-time Clock and its associated SFRs to their default state.
Table 41: FOSC2:0 000 001 010 011 0 00 01 10 11 1 00 01 10 11 100 0 00 01 10 11 1 00 01 10 11 101 110 111 0 00 01 10 11 1 00 01 10 11 Table 42: Bit Symbol Reset Internal RC oscillator External clock input / DIVM External clock input Internal RC oscillator External clock input External clock input / DIVM x xx Internal RC oscillator undefined undefined Watchdog oscillator / DIVM External clock input Internal RC oscillator Internal RC oscillator External clock input Watchdog oscillator / DIVM Internal RC oscillator / DIVM External clock input Internal RC oscillator External clock input Internal RC oscillator / DIVM Real-time Clock / System Timer clock sources RCCLK RTCS1:0 x xx RTC clock source undefined CPU clock source undefined
Real-time Clock Control register (RTCCON - address D1h) bit allocation 7 RTCF 0 6 RTCS1 1 5 RTCS0 1 4 x 3 x 2 x 1 ERTC 0 0 RTCEN 0
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Table 43: 0
Real-time Clock Control register (RTCCON - address D1h) bit description Description Real-time Clock enable. The Real-time Clock will be enabled if this bit is logic 1. Note that this bit will not power-down the Real-time Clock. The RTCPD bit (PCONA.7) if set, will power-down and disable this block regardless of RTCEN. Real-time Clock interrupt enable. The Real-time Clock shares the same interrupt as the watchdog timer. Note that if the user configuration bit WDTE (UCFG1.7) is logic 0, the watchdog timer can be enabled to generate an interrupt. Users can read the RTCF (RTCCON.7) bit to determine whether the Real-time Clock caused the interrupt. reserved Real-time Clock source select (see Table 41). Real-time Clock Flag. This bit is set to logic 1 when the 23-bit Real-time Clock reaches a count of logic 0. It can be cleared in software.
Bit Symbol RTCEN
2:4 5 6 7 RTCS0 RTCS1 RTCF
10. UART (P89LPC9103, P89LPC9107)
The P89LPC9103 / 9107 has an enhanced UART that is compatible with the conventional 80C51 UART except that Timer 2 overflow cannot be used as a baud rate source. The P89LPC9103 / 9107 does include an independent Baud Rate Generator. The baud rate can be selected from the oscillator (divided by a constant), Timer 1 overflow, or the independent Baud Rate Generator. In addition to the baud rate generation, enhancements over the standard 80C51 UART include Framing Error detection, break detect, automatic address recognition, selectable double buffering and several interrupt options. The UART can be operated in four modes, as described in the following sections.
10.1 Mode 0
Serial data enters and exits through RXD. TXD outputs the shift clock. 8 bits are transmitted or received, LSB first. The baud rate is fixed at 1 / 16 of the CPU clock frequency.
10.2 Mode 1
10 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8 data bits (LSB first), and a stop bit (logic 1). When data is received, the stop bit is stored in RB8 in Special Function Register SCON.