P89LPC932A1 8-bit microcontrollers with two-clock 80C51 core 8-bit
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P89LPC932A1 8-bit microcontrollers with two-clock 80C51 core 8-bit
Rev. August 2004 User manual
Document information Info Keywords Abstract Content P89LPC932, P89LPC932A1 Technical information P89LPC932A1 device.
Philips Semiconductors
UM10109
P89LPC932A1 User manual
Revision history Date 20040802 Description Initial version
9397 13858
Koninklijke Philips Electronics N.V. 2004. rights reserved.
User manual
Rev. August 2004
Philips Semiconductors
UM10109
P89LPC932A1 User manual
Introduction
P89LPC932A1 single-chip microcontroller designed applications demanding high-integration, cost solutions over wide range performance requirements. P89LPC932A1 based high performance processor architecture that executes instructions four clocks, times rate standard 80C51 devices. Many system-level functions have been incorporated into P89LPC932A1 order reduce component count, board space, system cost.
Comparison P89LPC932 device
P89LPC932A1 includes several improvements compared P89LPC932. These improvements described below.
1.1.1 Byte-erasability (IAP-Lite)
original P89LPC932 allowed from byte bytes user code memory, single page, programmed using function call. bytes programmed needed have been previously erased using either page erase, sector erase, chip erase parallel programmer) command. Thus code memory erased byte, groups. P89LPC932A1 allows from byte bytes page user code memory erased reprogrammed single operation. bytes erased reprogrammed randomly addressed within single page. Only bytes addressed will affected. Section 18.4 "Using Flash data storage: IAP-Lite" page 107.
1.1.2 Serial in-circuit programming (ICP)
In-Circuit Programming method intended allow cost commercial programmers program erase these devices without removing microcontroller from system. In-Circuit Programming facility consists series internal hardware resources facilitate remote programming P89LPC932A1 through two-wire serial interface. Philips made in-circuit programming embedded application possible with minimum additional expense components circuit board area. function uses five pins (VDD, VSS, P0.5, P0.4, RST). Only small connector needs available interface your application external programmer order this feature. This function available P89LPC932 device.
1.1.3 `On-the-fly' clock selection
Oscillator selected source clock (CCLK) using RCCLK TRIM register (TRIM.7). This allows fast `on-the-fly' switching between Oscillator clock source selected oscillator type select bits, FOSC[2:0], UCFG1, without need reset device. This functionality available P89LPC932. Table "On-chip oscillator trim register (TRIM address 96h) description" page
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Koninklijke Philips Electronics N.V. 2004. rights reserved.
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P89LPC932A1 User manual
1.1.4 Increased ISP/IAP functionality
1.1.4.1 Support watchdog timer code been modified prescaler WDCON) register their maximum values. Other WDCON bits unchanged code does explicitly enable disable WDT. Periodic feeds provided within code support applications that entered code with enabled WDT. This functionality provided code P89LPC932. 1.1.4.2 XDATA data buffer option added programming code memory "program user code page" function P89LPC932 used IDATA byte data buffer. option provided allow user specify that XDATA used instead buffer source. flag (PSW.1) set, then XDATA used. flag (PSW.1) cleared, then IDATA used. 1.1.4.3 Port initialization P89LPC932 code during initialization programmed bits Port quasi-bidirectional mode these port pins HIGH. This been changed such that only pins have their port mode programmed during initialization. other Port pins remain their previous state (for example, input-only mode following reset). 1.1.4.4 Direct load UART baud rate identified "direct load baud rate" function been fixed. baud rate source this function been changed from Timer BRG. 1.1.4.5 Boot Vector entry points modified protect against errant code execution incrementing into routines, software reset instructions have been added beginning these code blocks. This required that entry points changed. entry point changed 1F00H resulting default Boot Vector 1FH. entry point changed FF03H. 1.1.4.6 authorization functions which write erase code memory require authorization calling routine prior performing function call. This authorization writing location FFH. Section 18.13 "IAP authorization key" page After function call processed routine, authorization will cleared. Thus necessary authorization prior EACH call PGM_MTP that requires key. routine that requires authorization called without valid authorization present, will perform reset. 1.1.4.7 Hardware write enable (WE) This device hardware write enable protection. This protection applies both modes applies both user code memory space user configuration bytes (UCFG1, BOOTVEC, BOOTSTAT). This protection does apply commercial programmer modes. When enabled, user code requesting write function IAP-Lite will need explicitly Write Enable flag prior requesting write function. Section 18.14 "Flash write enable" page
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1.1.4.8
Configuration byte protection separate write protection been provided "configuration bytes". These bytes include UCFG1, BootStat, Boot Vector, sector security bytes. This write protection applies modes. does apply commercial programmer modes. Section 18.15 "Configuration byte protection" page
1.1.5 Previous errata
Most known errata P89LPC932 devices been fixed P89LPC932A1 device. current errata information P89LPC932A1, any, please P89LPC932A1 errata sheet.
configuration
ICB/P2.0 OCD/P2.1 KBI0/CMP2/P0.0 OCC/P1.7 OCB/P1.6 RST/P1.5 XTAL1/P3.1 CLKOUT/XTAL2/P3.0
P2.7/ICA P2.6/OCA P0.1/CIN2B/KBI1 P0.2/CIN2A/KBI2 P0.3/CIN1B/KBI3 P0.4/CIN1A/KBI4 P0.5/CMPREF/KBI5 P0.6/CMP1/KBI6 P0.7/T1/KBI7 P1.0/TXD P1.1/RXD P2.5/SPICLK P2.4/SS
002aaa886
P89LPC932A1FDH
INT1/P1.4 SDA/INT0/P1.3 SCL/T0/P1.2 MOSI/P2.2 MISO/P2.3
P89LPC932A1 TSSOP28 configuration.
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P2.7/ICA
P2.6/OCA
P0.1/CIN2B/KBI1 P0.2/CIN2A/KBI2 P0.3/CIN1B/KBI3 P0.4/CIN1A/KBI4 P0.5/CMPREF/KBI5 P0.6/CMP1/KBI6 P0.7/T1/KBI7 P1.0/TXD P0.1/CIN2B/KBI1 P0.2/CIN2A/KBI2 P0.3/CIN1B/KBI3 P0.4/CIN1A/KBI4
002aaa887
P0.0/CMP2/KBI0
P1.7/OCC
P2.1/OCD
P1.6/OCB P1.5/RST P3.1/XTAL1 P3.0/XTAL2/CLKOUT
P89LPC932A1FA
P1.4/INT1 P1.3/INT0/SDA P2.5/SPICLK P2.7/ICA P1.2/T0/SCL P2.2/MOSI P2.3/MISO P1.1/RXD P2.6/OCA P2.4/SS P2.0/ICB
P89LPC932A1 PLCC28 configuration.
P0.0/CMP2/KBI0
P1.7/OCC
terminal index area
P1.6/OCB P1.5/RST P3.1/XTAL1 P3.0/XTAL2/CLKOUT P1.4/INT1 P1.3/INT0/SDA
P2.3/MISO P2.4/SS P2.5/SPICLK P1.1/RXD P1.0/TXD
P89LPC932A1FHN
P2.1/OCD
P2.0/ICB
P0.5/CMPREF/KBI5
P0.6/CMP1/KBI6 P0.7/T1/KBI7
P1.2/T0/SCL
P2.2/MOSI
002aaa889
Transparent view
P89LPC932A1 HVQFN28 configuration.
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P89LPC932A1 User manual
description
Table Symbol description TSSOP28, HVQFN28 PLCC28 P0.0 P0.7 Port Port 8-bit port with user-configurable output type. During reset Port latches configured input only mode with internal pull-up disabled. operation Port pins inputs outputs depends upon port configuration selected. Each port configured independently. Refer Section "Port configurations" P89LPC932A1 data sheet, Static characteristics details. Keypad Interrupt feature operates with Port pins. pins have Schmitt triggered inputs. Port also provides various special functions described below: P0.0 Port CMP2 Comparator output. KBI0 Keyboard input P0.1 Port CIN2B Comparator positive input KBI1 Keyboard input P0.2 Port CIN2A Comparator positive input KBI2 Keyboard input P0.3 Port CIN1B Comparator positive input KBI3 Keyboard input P0.4 Port CIN1A Comparator positive input KBI4 Keyboard input P0.5 Port CMPREF Comparator reference (negative) input. KBI5 Keyboard input Type Description
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Table Symbol
description TSSOP28, HVQFN28 PLCC28 Type Description
P0.0 P0.7 (continued)
P0.6 Port CMP1 Comparator output. KBI6 Keyboard input P0.7 Port Timer/counter external count input overflow output. KBI7 Keyboard input
P1.0 P1.7
I/O,
Port Port 8-bit port with user-configurable output type, except three pins noted below. During reset Port latches configured input only mode with internal pull-up disabled. operation configurable Port pins inputs outputs depends upon port configuration selected. Each configurable port pins programmed independently. Refer Section "Port configurations" P89LPC932A1 data sheet, Static characteristics details. P1.2 P1.3 open drain when used outputs. P1.5 input only. pins have Schmitt triggered inputs. Port also provides various special functions described below:
P1.0 Port Transmitter output serial port. P1.1 Port Receiver input serial port. P1.2 Port (open-drain when used output). Timer/counter external count input overflow output (open-drain when used output). serial clock input/output. P1.3 Port (open-drain when used output). INT0 External interrupt input. serial data input/output. P1.4 Port INT1 External interrupt input. P1.5 Port (input only). External Reset input during power-on selected UCFG1. When functioning reset input, this resets microcontroller, causing ports peripherals take their default states, processor begins execution address Also used during power-on sequence force In-System Programming mode. P1.6 Port Output Compare P1.7 Port Output Compare
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P89LPC932A1 User manual
Table Symbol
description TSSOP28, HVQFN28 PLCC28 Type Description
P2.0 P2.7
Port Port 8-bit port with user-configurable output type. During reset Port latches configured input only mode with internal pull-up disabled. operation Port pins inputs outputs depends upon port configuration selected. Each port configured independently. Refer Section "Port configurations" P89LPC932A1 data sheet, Static characteristics details. pins have Schmitt triggered inputs. Port also provides various special functions described below:
P2.0 Port Input Capture P2.1 Port Output Compare P2.2 Port MOSI master slave When configured master, this output; when configured slave, this input. P2.3 Port MISO When configured master, this input, when configured slave, this output. P2.4 Port Slave select. P2.5 Port SPICLK clock. When configured master, this output; when configured slave, this input. P2.6 Port Output Compare P2.7 Port Input Capture
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Table Symbol
description TSSOP28, HVQFN28 PLCC28 Type Description
P3.0 P3.1
Port Port 2-bit port with user-configurable output type. During reset Port latches configured input only mode with internal pull-up disabled. operation Port pins inputs outputs depends upon port configuration selected. Each port configured independently. Refer Section P89LPC932A1 data sheet, Static characteristics details. pins have Schmitt triggered inputs. Port also provides various special functions described below:
P3.0 Port XTAL2 Output from oscillator amplifier (when crystal oscillator option selected FLASH configuration. CLKOUT clock divided when enabled (ENCLK TRIM.6). used clock internal oscillator, watchdog oscillator external clock input, except when XTAL1/XTAL2 used generate clock source Real-Time clock/system timer. P3.1 Port XTAL1 Input oscillator circuit internal clock generator circuits (when selected FLASH configuration). port internal oscillator watchdog oscillator used clock source, XTAL1/XTAL2 used generate clock Real-Time clock/system timer. Ground: reference. Power Supply: This power supply voltage normal operation well Idle Power-down modes.
Input/Output P1.0 P1.4, P1.6, P1.7. Input P1.5.
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P89LPC932A1 User manual
P89LPC932A1
ACCELERATED 2-CLOCK 80C51
CODE FLASH 256-BYTE DATA 512-BYTE AUXILIARY internal
UART
I2C-BUS
REAL-TIME CLOCK/ SYSTEM TIMER TIMER TIMER
512-BYTE DATA EEPROM
PORT CONFIGURABLE I/Os PORT CONFIGURABLE I/Os PORT CONFIGURABLE I/Os PORT CONFIGURABLE I/Os ANALOG COMPARATORS
(CAPTURE/ COMPARE UNIT)
KEYPAD INTERRUPT WATCHDOG TIMER OSCILLATOR POWER MONITOR (POWER-ON RESET, BROWNOUT RESET) clock ON-CHIP OSCILLATOR
002aaa885
PROGRAMMABLE OSCILLATOR DIVIDER
CRYSTAL RESONATOR
CONFIGURABLE OSCILLATOR
P89LPC932A1 block diagram.
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Special function registers
Remark: Special Function Registers (SFRs) accesses restricted following ways:
User must attempt access locations defined. Accesses defined locations must strictly functions SFRs. bits labeled `-', only written read follows:
Unless otherwise specified, must written with `0', return value when read (even written with `0'). reserved used future derivatives. must written with `0', will return when read. must written with `1', will return when read.
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Table P89LPC932A1 Special function registers indicates SFRs that addressable. Name Description functions addresses addr. address ACC* AUXR1 BRGR0[2] BRGR1[2] BRGCON CCCRA CCCRB CCCRC CCCRD CMP1 CMP2 DEECON DEEDAT DEEADR DIVM DPTR I2ADR I2CON* Accumulator Auxiliary function register register Baud rate generator rate Baud rate generator rate high Baud rate generator control Capture compare control register Capture compare control register Capture compare control register Capture compare control register Comparator control register Comparator control register Data EEPROM control register Data EEPROM data register Data EEPROM address register clock divide-by-M control Data pointer bytes) Data pointer high Data pointer slave address register I2ADR.6 I2ADR.5 I2EN I2ADR.4 I2ADR.3 I2ADR.2 I2ADR.1 I2ADR.0 CRSEL x00000x0 address control register 00000000 00000000 00000000 ICECA2 ICECB2 EEIF ICECA1 ICECB1 HVERR ICECA0 ICECB0 ECTL1 ICESA ICESB ECTL0 ICNFA ICNFB FCOA FCOB FCOC FCOD SBRGS OCMA1 OCMB1 OCMC1 OCMD1 BRGEN OCMA0 OCMB0 OCMC0 OCMD0 CMF1 CMF2 EADR8 CLKLP EBRR ENT1 ENT0 SRST 00[2] 00[1] 00[1] 00000000 00000000 00000000 xxxxxx00 00000000 00000000 xxxxx000 xxxxx000 xx000000 xx000000 00001110 00000000 00000000 address Reset value 00000000 000000x0 Binary
P89LPC932A1 User manual
00000000
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Table P89LPC932A1 Special function registers indicates SFRs that addressable. Name I2DAT I2SCLH I2SCLL I2STAT ICRAH ICRAL ICRBH ICRBL
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Description data register Serial clock generator/SCL duty cycle register high Serial clock generator/SCL duty cycle register status register Input capture register high Input capture register Input capture register high Input capture register Interrupt enable Interrupt enable Interrupt priority Interrupt priority high
functions addresses addr. EIEE PIEE PIEEH EWDRT PWDRT PWDRT PSTH PBOH ES/ESR ECCU PS/PSR PSH/ PSRH PCCU PCCUH ESPI PT1H PSPI PSPIH PX1H EKBI PT0H PKBI PKBIH PATN _SEL STA.4 STA.3 STA.2 STA.1 STA.0
Reset value EI2C PX0H PI2C PI2CH KBIF 00[1] 00[1] 00[1] 00x00000 00x00000 xxxxxx00 00000000 11111111 00000000 00000000 00[1] 00[1] x0000000 x0000000 00[1] 00x00000 00000000 Binary 00000000 00000000 11111000 00000000 00000000 00000000 00000000
address IEN0* IEN1* IP0* IP0H address address address IP1* IP1H KBCON KBMASK KBPATN OCRAH OCRAL Interrupt priority Interrupt priority high Keypad control register Keypad interrupt mask register Keypad pattern register Output compare register high Output compare register
P89LPC932A1 User manual
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Table P89LPC932A1 Special function registers indicates SFRs that addressable. Name OCRBH OCRBL OCRCH OCRCL OCRDH OCRDL
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Description Output compare register high Output compare register Output compare register high Output compare register Output compare register high Output compare register Port
functions addresses addr. T1/KB7 CMP1 /KB6 CMPREF /KB5 SPICLK CIN1A /KB4 INT1 CIN1B /KB3 INT0/ MISO CIN2A /KB2 T0/SCL MOSI CIN2B /KB1 XTAL1
Reset value CMP2 /KB0 XTAL2 00[1] 00[1] FF[1] 00[1] 00[1]
Binary 00000000 00000000 00000000 00000000 00000000 00000000
address address Port address P0M1 P0M2 P1M1 P1M2 P2M1 P2M2 P3M1 P3M2 PCON Port Port Port output mode Port output mode Port output mode Port output mode Port output mode Port output mode Port output mode Port output mode Power control register address
(P0M1.7) (P0M1.6) (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M1.0) FF[1] (P0M2.7) (P0M2.6) (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) (P0M2.0) (P1M1.7) (P1M1.6) (P1M2.7) (P1M2.6) (P1M2.4) (P1M2.3) (P1M2.2) (P1M2.1) (P1M2.0) (P1M1.4) (P1M1.3) (P1M1.2) (P1M1.1) (P1M1.0) D3[1]
11111111
P89LPC932A1 User manual
00000000 11x1xx11 00x0xx00 11111111 00000000 xxxxxx11 xxxxxx00 00000000
UM10109
(P2M1.7) (P2M1.6) (P2M1.5) (P2M1.4) (P2M1.3) (P2M1.2) (P2M1.1) (P2M1.0) (P2M2.7) (P2M2.6) (P2M2.5) (P2M2.4) (P2M2.3) (P2M2.2) (P2M2.1) (P2M2.0) SMOD1 SMOD0 BOPD (P3M2.1) (P3M2.0) PMOD1 PMOD0
(P3M1.1) (P3M1.0) 03[1]
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Table P89LPC932A1 Special function registers indicates SFRs that addressable. Name PCONA PSW* PT0AD RSTSRC RTCCON RTCH RTCL SADDR SADEN
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Description Power control register Program status word Port digital input disable Reset source register Real-time clock control Real-time clock register high Real-time clock register Serial port address register Serial port address enable Serial Port data buffer register Serial port control Serial port extended status register Stack pointer control register status register data register Timer auxiliary mode Timer control control register control register Timer high Timer high timer high interrupt control register interrupt flag register
functions addresses addr. address SM0/FE DBMOD INTLO CIDIS DBISEL RTCPD RTCF DEEPD RTCS1 VCPD RTCS0 I2PD R_BK SPPD R_WD R_SF ERTC
Reset value CCUPD R_EX RTCEN 60[1][6] 00[6] 00[6] STINT 00000000 00000000 00000111 00000100 00xxxxxx 00000000 xxx0xxx0 00000000 xx00000x
00[1]
Binary 00000000
PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2 PT0AD.1
011xxx00 00000000 00000000 00000000 00000000 xxxxxxxx
SBUF SCON* SSTAT SPCTL SPSTAT SPDAT TAMOD TCON* TCR20* TCR21 TICR2 TIFR2
address
SSIG SPIF PLEEN TCOU2
SPEN WCOL HLTRN
DORD HLTEN
MSTR T1M2 ALTCD
CPOL ALTAB PLLDV.3
CPHA TDIR2 PLLDV.2
SPR1 PLLDV.1
SPR0 T0M2
address
P89LPC932A1 User manual
00000000 00000000 0xxx0000 00000000 00000000 00000000 00000x00 00000x00
TMOD21 TMOD20 PLLDV.0
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TOIE2 TOIF2
TOCIE2
TOCIE2
TOCIE2B TOCIE2A TOCF2B TOCF2A
TICIE2B TICF2B
TICIE2A TICF2A
TOCF2D TOCF2C
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Table P89LPC932A1 Special function registers indicates SFRs that addressable. Name TISE2 TMOD TOR2H TOR2L TPCR2H TPCR2L TRIM WDCON WFEED1 WFEED2
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Description interrupt status encode register Timer Timer timer Timer mode reload register high reload register
functions addresses addr. T1GATE T1C/T T1M1 T1M0 T0GATE T0C/T T0M1 ENCINT. ENCINT.
Reset value Binary xxxxx000 00000000 00000000 00000000 00000000 00000000 00000000 xxxxxx00 00000000
ENCINT. T0M0
Prescaler control register high Prescaler control register Internal oscillator trim register Watchdog control register Watchdog load Watchdog feed Watchdog feed
TPCR2H. TPCR2H.
TPCR2L. TPCR2L. TPCR2L. TPCR2L. TPCR2L. TPCR2L. TPCR2L. TPCR2L. RCCLK PRE2 ENCLK PRE1 TRIM.5 PRE0 TRIM.4 TRIM.3 TRIM.2 WDRUN TRIM.1 WDTOF TRIM.0 WDCLK
11111111
ports input only (high-impedance) state after power-up. BRGR1 BRGR0 must only written BRGEN BRGCON logic written while BRGEN result unpredictable. RSTSRC register reflects cause P89LPC932A1 reset. Upon power-up reset, reset source flags cleared except BOF; power-on reset value xx110000. After reset, value 111001x1, i.e., PRE2-PRE0 logic WDRUN WDCLK WDTOF logic after watchdog reset logic after power-on reset. Other resets will affect WDTOF. power-on reset, TRIM initialized with factory preprogrammed value. Other resets will cause initialization TRIM register. only reset source that affects these SFRs power-on reset.
P89LPC932A1 User manual
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Memory organization
read-protected calls only entrypoints
IDATA routines FFEFh FF1Fh FF00h
FF00h FFEFh
entry points for: ASM. code code
entry points
SPECIAL FUNCTION REGISTERS (DIRECTLY ADDRESSABLE)
IDATA (incl. DATA)
BYTES ON-CHIP DATA MEMORY (STACK INDIR. ADDR.)
DATA
1FFFh 1E00h 1C00h 1BFFh 1800h 17FFh 1400h 13FFh 1000h 0FFFh 0C00h 0BFFh 0800h 07FFh 0400h 03FFh 0000h
CODE (512B)* SECTOR SECTOR SECTOR SECTOR SECTOR SECTOR SECTOR SECTOR
serial loader
1FFFh
entry points for: -UART (auto-baud) -I2C, SPI, etc.* flexible choices: supplied (UART) -Philips libraries* -user-defined
BYTES ON-CHIP DATA MEMORY (STACK, DIRECT INDIR. ADDR.) REG. BANKS R[7:0]
1E00h
data memory (DATA, IDATA)
002aaa948
P89LPC932A1 memory map.
various P89LPC932A1 memory spaces follows: DATA bytes internal data memory space (00h:7Fh) accessed direct indirect addressing, using instruction other than MOVX MOVC. part Stack this area. IDATA Indirect Data. bytes internal data memory space (00h:FFh) accessed indirect addressing using instructions other than MOVX MOVC. part Stack this area. This area includes DATA area bytes immediately above Special Function Registers. Selected registers peripheral control status registers, accessible only direct addressing. CODE Code memory space, accessed part program execution MOVC instruction. P89LPC932A1 on-chip Code memory.
Table Type DATA IDATA Data arrangement Data Directly indirectly addressable memory Indirectly addressable memory Size (bytes)
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Clocks
Enhanced
P89LPC932A1 uses enhanced 80C51 which runs times speed standard 80C51 devices. machine cycle consists clock cycles, most instructions execute machine cycles.
Clock definitions
P89LPC932A1 device several internal clocks defined below: OSCCLK Input DIVM clock divider. OSCCLK selected from four clock sources also optionally divided slower frequency (see Figure Section "CPU Clock (CCLK) modification: DIVM register"). Note: fosc defined OSCCLK frequency. CCLK clock; output DIVM clock divider. There CCLK cycles machine cycle, most instructions executed machine cycles (two four CCLK cycles). RCCLK internal 7.373 oscillator output. PCLK Clock various peripheral devices CCLKe2.
2.2.1 Oscillator Clock (OSCCLK)
P89LPC932A1 provides several user-selectable oscillator options. This allows optimization range needs from high precision lowest possible cost. These options configured when FLASH programmed include on-chip watchdog oscillator, on-chip oscillator, oscillator using external crystal, external clock source. crystal oscillator optimized low, medium, high frequency crystals covering range from MHz.
2.2.2 speed oscillator option
This option supports external crystal range kHz. Ceramic resonators also supported this configuration.
2.2.3 Medium speed oscillator option
This option supports external crystal range MHz. Ceramic resonators also supported this configuration.
2.2.4 High speed oscillator option
This option supports external crystal range MHz. Ceramic resonators also supported this configuration.
Clock output
P89LPC932A1 supports user-selectable clock output function XTAL2 CLKOUT when crystal oscillator being used. This condition occurs different clock source been selected (on-chip oscillator, watchdog oscillator, external clock input Real-time Clock using crystal oscillator clock source. This allows external devices synchronize P89LPC932A1. This output enabled ENCLK TRIM register
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frequency this clock output that CCLK. clock output needed Idle mode, turned prior entering Idle, saving additional power. Note: reset, TRIM initialized with factory preprogrammed value. Therefore when setting clearing ENCLK bit, user should retain contents other bits TRIM register. This done reading contents TRIM register (into example), modifying writing this result back into TRIM register. Alternatively, `ANL direct' `ORL direct' instructions used clear TRIM register.
On-chip oscillator option
P89LPC932A1 TRIM register that used tune frequency oscillator. During reset, TRIM value initialized factory pre-programmed value adjust oscillator frequency 7.373 MHz, (Note: initial value better than please refer P89LPC932A1 data sheet behavior over temperature). user applications write TRIM register adjust on-chip oscillator other frequencies. Increasing TRIM value will decrease oscillator frequency.
Table Symbol Reset Table On-chip oscillator trim register (TRIM address 96h) allocation RCCLK ENCLK TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0
Bits loaded with factory stored value during reset.
On-chip oscillator trim register (TRIM address 96h) description Symbol TRIM.0 TRIM.1 TRIM.2 TRIM.3 TRIM.4 TRIM.5 ENCLK RCCLK when CCLKe2 output XTAL2 provided crystal oscillator being used. when selects Oscillator output clock (CCLK). This allows fast switching between clock source internal oscillator without needing through reset cycle. original P89LPC932 required reset cycle order switch between clock sources. Description Trim value. Determines frequency internal oscillator. During reset, these bits loaded with stored factory calibration value. When writing either this register, care should taken preserve current TRIM value reading this register, modifying bits required, writing result this register.
Watchdog oscillator option
watchdog separate oscillator which frequency kHz. This oscillator used save power when high clock frequency needed.
External clock input option
this configuration, processor clock derived from external source driving XTAL1 P3.1 pin. rate from MHz. XTAL2 P3.0 used standard port clock output.
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quartz crystal ceramic resonator P89LPC932A1 XTAL1
XTAL2
002aab008
Note: oscillator must configured following modes: frequency crystal, medium frequency crystal, high frequency crystal. series resistor required limit crystal drive levels. This especially important frequency crystals (see text).
Using crystal oscillator.
XTAL1 XTAL2
HIGH FREQUENCY MEDIUM FREQUENCY FREQUENCY
OSCCLK OSCILLATOR (7.3728 WATCHDOG OSCILLATOR (400 +20% TIMER TIMER I2C-BUS PCLK RCCLK
DIVM
CCLK PCLK
(P89LPC932A1)
002aaa891
UART
Block diagram oscillator control.
Oscillator Clock (OSCCLK) wake-up delay
P89LPC932A1 internal wake-up timer that delays clock until stabilizes depending clock source used. clock source three crystal selections, delay OSCCLK cycles plus clock source either internal oscillator Watchdog oscillator, delay OSCCLK cycles plus
Clock (CCLK) modification: DIVM register
OSCCLK frequency divided down, integer, times configuring dividing register, DIVM, provide CCLK. This produces CCLK frequency using following formula: CCLK frequency fosc (2N)
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Where: fosc frequency OSCCLK, value DIVM. Since ranges from 255, CCLK frequency range fosc fosc/510. (for CCLK fosc). This feature makes possible temporarily lower rate, reducing power consumption. dividing clock, retain ability respond events other than those that cause interrupts (i.e. events that allow exiting Idle mode) executing normal program lower rate. This often result lower power consumption than Idle mode. This allow bypassing oscillator start-up time cases where Power-down mode would otherwise used. value DIVM changed program time without interrupting code execution.
power select
P89LPC932A1 designed (CCLK) maximum. However, CCLK slower, CLKLP (AUXR1.7) logic lower power consumption further. reset, CLKLP logic allowing highest performance. This then software CCLK running slower.
Interrupts
P89LPC932A1 uses four priority level interrupt structure. This allows great flexibility controlling handling P89LPC932A1's interrupt sources. Each interrupt source individually enabled disabled setting clearing interrupt enable registers IEN0 IEN1. IEN0 register also contains global enable bit, which enables interrupts. Each interrupt source individually programmed four priority levels setting clearing bits interrupt priority registers IP0, IP0H, IP1, IP1H. interrupt service routine progress interrupted higher priority interrupt, another interrupt same lower priority. highest priority interrupt service cannot interrupted other interrupt source. requests different priority levels received simultaneously, request higher priority level serviced. requests same priority level pending start instruction cycle, internal polling sequence determines which request serviced. This called arbitration ranking. Note that arbitration ranking only used pending requests same priority level. Table summarizes interrupt sources, flag bits, vector addresses, enable bits, priority bits, arbitration ranking, whether each interrupt wake-up from Power-down mode.
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Interrupt priority structure
Table IPxH Interrupt priority level Interrupt priority level Level (lowest priority) Level Level Level Priority bits
There four SFRs associated with four interrupt levels: IP0, IP0H, IP1, IP1H. Every interrupt bits IPxH therefore assigned four levels, shown Table P89LPC932A1 external interrupt inputs addition Keypad Interrupt function. interrupt inputs identical those present standard 80C51 microcontrollers. These external interrupts programmed level-triggered edge-triggered clearing setting Register TCON. external interrupt triggered level detected INTn pin. external interrupt edge triggered. this mode consecutive samples INTn show high level cycle level next cycle, interrupt request flag TCON set, causing interrupt request. Since external interrupt pins sampled once each machine cycle, input high level should held least machine cycle ensure proper sampling. external interrupt edge-triggered, external source hold request high least machine cycle, then hold least machine cycle. This ensure that transition detected that interrupt request flag set. automatically cleared when service routine called. external interrupt level-triggered, external source must hold request active until requested interrupt generated. external interrupt still asserted when interrupt service routine completed, another interrupt will generated. necessary clear interrupt flag when interrupt level sensitive, simply tracks input level. external interrupt enabled when P89LPC932A1 into Power-down mode Idle mode, interrupt occurrence will cause processor wake-up resume operation. Refer Section "Power reduction modes" details.
External Interrupt glitch suppression
Most P89LPC932A1 pins have glitch suppression circuits reject short glitches (please refer P89LPC932A1 data sheet, Dynamic characteristics glitch filter specifications). However, pins SDA/INT0/P1.3 SCL/T0/P1.2 have glitch suppression circuits. Therefore, INT1 glitch suppression while INT0 does not.
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Table
Summary interrupts Interrupt flag bit(s) WDOVF/RTCF KBIF CMF1/CMF2 SPIF ADCI1, BNDI1 002Bh 0053h 0033h 003Bh 0043h 004Bh 005Bh 006Bh 0073h (IEN0.5) EWDRT (IEN0.6) EI2C (IEN1.0) EKBI (IEN1.1) (IEN1.2) ESPI (IEN1.3) ECCU(IEN1.4) (IEN1.6) (IEN1.7) IP0H.5, IP0.5 IP0H.6, IP0.6 IP0H.0, IP0.0 IP0H.0, IP0.0 IP0H.0, IP0.0 IP1H.3, IP1.3 IP1H.4, IP1.4 IP0H.0, IP0.0 IP1H.7, IP1.7 (lowest) Vector address 0003h 000Bh 0013h 001Bh 0023h Interrupt enable bit(s) (IEN0.0) (IEN0.1) (IEN0.2) (IEN0.3) ES/ESR (IEN0.4) Interrupt priority IP0H.0, IP0.0 IP0H.1, IP0.1 IP0H.2, IP0.2 IP0H.3, IP0.3 IP0H.4, IP0.4 Arbitration ranking (highest) Powerdown wake-up
Description
External interrupt Timer interrupt External interrupt Timer interrupt Serial port Serial port Brownout detect Watchdog timer/Real-time clock interrupt interrupt Comparators interrupts interrupt Capture/Compare Unit Serial port Data EEPROM
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BOPD RTCF ERTC (RTCCON.1) WDOVF KBIF EKBI EWDRT CMF2 CMF1 (IE0.7) RI/RI ES/ESR EI2C SPIF ESPI interrupt ECCU EEIF EIEE
002aaa892
wake-up power-down)
interrupt
Section "Capture/Compare Unit (CCU)".
Interrupt sources, interrupt enables, power-down wake-up sources.
ports
P89LPC932A1 four ports: Port Port Port Port Ports 8-bit ports Port 2-bit port. exact number pins available depends upon clock reset options chosen (see Table
Table Number pins available Reset option Number pins
Clock source On-chip oscillator watchdog oscillator External clock input
external reset (except during power External supported External supported external reset (except during power
Low/medium/high speed oscillator external reset (except during power (external crystal resonator) External supported
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Port configurations
three port pins P89LPC932A1 configured software four types pin-by-pin basis, shown Table These are: quasi-bidirectional (standard 80C51 port outputs), push-pull, open drain, input-only. configuration registers each port select output type each port pin. P1.5 (RST) only input cannot configured. P1.2 (SCL/T0) P1.3 (SDA/INT0) only configured either input-only open drain.
Table PxM1.y Port output configuration settings PxM2.y Port output mode Quasi-bidirectional Push-pull Input only (high-impedance) Open drain
Quasi-bidirectional output configuration
Quasi-bidirectional outputs used both input output without need reconfigure port. This possible because when port outputs logic high, weakly driven, allowing external device pull low. When driven low, driven strongly able sink large current. There three pull-up transistors quasi-bidirectional output that serve different purposes. these pull-ups, called `very weak' pull-up, turned whenever port latch contains logic This very weak pull-up sources very small current that will pull high left floating. second pull-up, called `weak' pull-up, turned when port latch contains logic itself also logic level. This pull-up provides primary source current quasi-bidirectional that outputting this pulled external device, weak pull-up turns off, only very weak pull-up remains order pull under these conditions, external device sink enough current overpower weak pull-up pull port below input threshold voltage. third pull-up referred `strong' pull-up. This pull-up used speed low-to-high transitions quasi-bidirectional port when port latch changes from logic logic When this occurs, strong pull-up turns clocks quickly pulling port high. quasi-bidirectional port configuration shown Figure Although P89LPC932A1 device most pins V-tolerant. applied configured quasi-bidirectional mode, there will current flowing from causing extra power consumption. Therefore, applying pins configured quasi-bidirectional mode discouraged. quasi-bidirectional port Schmitt-triggered input that also glitch suppression circuit
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(Please refer P89LPC932A1 data sheet, Dynamic characteristics glitch filter specifications).
CLOCK DELAY
strong
very weak
weak
PORT port latch data
input data glitch rejection
002aaa914
Quasi-bidirectional output.
Open drain output configuration
open drain output configuration turns pull-ups only drives pull-down transistor port when port latch contains logic used logic output, port configured this manner must have external pull-up, typically resistor tied VDD. pull-down this mode same quasi-bidirectional mode. open drain port configuration shown Figure open drain port Schmitt-triggered input that also glitch suppression circuit. Please refer P89LPC932A1 data sheet, Dynamic characteristics glitch filter specifications.
PORT port latch data
input data glitch rejection
002aaa915
Open drain output.
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Input-only configuration
input port configuration shown Figure Schmitt-triggered input that also glitch suppression circuit. (Please refer P89LPC932A1 data sheet, Dynamic characteristics glitch filter specifications).
input data glitch rejection
PORT
002aaa916
Input only.
Push-pull output configuration
push-pull output configuration same pull-down structure both open drain quasi-bidirectional output modes, provides continuous strong pull-up when port latch contains logic push-pull mode used when more source current needed from port output. push-pull port configuration shown Figure push-pull port Schmitt-triggered input that also glitch suppression circuit. (Please refer P89LPC932A1 data sheet, Dynamic characteristics glitch filter specifications).
strong
port latch data
PORT
input data
glitch rejection
002aaa917
Push-pull output.
Port Analog Comparator functions
P89LPC932A1 incorporates Analog Comparators. order give best analog performance minimize power consumption, pins that being used analog functions must have both digital outputs digital inputs disabled.
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Digital outputs disabled putting port pins into input-only mode described Port Configurations section (see Figure 11). Digital inputs Port disabled through PT0AD register. Bits through this register correspond pins P0.1 through P0.5 Port respectively. Setting corresponding PT0AD disables that pin's digital input. Port bits that have their digital inputs disabled will read instruction that accesses port. reset, PT0AD bits through default logic enable digital functions.
Additional port features
After power-up, pins Input-Only mode. Please note that this different from LPC76x series devices.
After power-up, pins except P1.5, configured software. P1.5 input only. Pins P1.2 P1.3 configurable either input-only
open drain. Every output P89LPC932A1 been designed sink typical drive current. However, there maximum total output current ports which must exceeded. Please refer P89LPC932A1 data sheet detailed specifications. ports pins that function output have slew rate controlled outputs limit noise generated quickly switching output signals. slew rate factory-set approximately rise fall times.
Table Port P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P3.0 P3.1 Port output configuration Configuration bits PxM1.y P0M1.0 P0M1.1 P0M1.2 P0M1.3 P0M1.4 P0M1.5 P0M1.6 P0M1.7 P1M1.0 P1M1.1 P1M1.2 P1M1.3 P1M1.4 P1M1.5 P1M1.6 P1M1.7 P3M1.0 P3M1.1 PxM2.y P0M2.0 P0M2.1 P0M2.2 P0M2.3 P0M2.4 P0M2.5 P0M2.6 P0M2.7 P1M2.0 P1M2.1 P1M2.2 P1M2.3 P1M2.4 P1M2.5 P1M2.6 P1M2.7 P3M2.0 P3M2.1 CLKOUT, XTAL2 XTAL1 Alternate usage KBIO, CMP2 KBI1, CIN2B KBI2, CIN2A KBI3, CIN1B KBI4, CIN1A KBI5, CMPREF KBI6, CMP1 KBI7, INTO, INT1 Input-only open-drain input-only open-drain Refer Section "Port Analog Comparator functions" usage analog inputs. Notes
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Power monitoring functions
P89LPC932A1 incorporates power monitoring functions designed prevent incorrect operation during initial power-on power loss reduction during operation. This accomplished with hardware functions: Power-on Detect Brownout Detect.
Brownout detection
Brownout Detect function determines power supply voltage drops below certain level. default operation Brownout Detection cause processor reset. However, alternatively configured generate interrupt setting (PCON.4) (IEN0.5) bit. Enabling disabling Brownout Detection done BOPD (PCON.5) bit, field PMOD1/PMOD0 (PCON[1:0]) user configuration (UCFG1.5). unprogrammed state, brownout disabled regardless PMOD1/PMOD0 BOPD. programmed state, PMOD1/PMOD0 BOPD will used determine whether Brownout Detect will disabled enabled. PMOD1/PMOD0 used select power reduction mode. PMOD1/PMOD0 `11', circuitry Brownout Detection disabled lowest power consumption. BOPD defaults logic indicating brownout detection enabled power-on programmed. Brownout Detection enabled, operating voltage range brownout condition occurs when falls below Brownout trip voltage, (see P89LPC932A1 data sheet, Static characteristics), negated when rises above VBO. Brownout Detection disabled, operating voltage range P89LPC932A1 device operate with power supply that below should left unprogrammed state that device operate otherwise continuous brownout reset prevent device from operating. Brownout Detect enabled (BOE programmed, PMOD1/PMOD0 `11', BOPD (RSTSRC.5) will when brownout detected, regardless whether reset interrupt enabled. will stay until cleared software writing logic bit. Note that unprogrammed, meaningless. programmed, initial power-on occurs, will addition power-on flag (POF RSTSRC.4). correct activation Brownout Detect, certain rise fall times must observed. Please data sheet specifications.
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Table (UCFG1.5) (erased) 1(program med)
Brownout options PMOD1/ PMOD0 (PCON[1:0]) (total power-down) BOPD (PCON.5) (PCON.4) (IEN0.5) (IEN0.7) Description
Brownout disabled. operating range Brownout disabled. operating range However, BOPD default logic upon power-up. Brownout reset enabled. operating range Upon brownout reset, (RSTSRC.5) will indicate reset source. cleared writing logic bit. Brownout interrupt enabled. operating range Upon brownout interrupt, (RSTSRC.5) will set. cleared writing logic bit. Both brownout reset interrupt disabled. operating range However, (RSTSRC.5) will when falls Brownout Detection trip point. cleared writing logic bit.
(any mode (brownout other than total detect power-down) power-down)
(brownout (brownout detect active) detect generates reset)
(brownout (enable detect brownout generates interrupt) interrupt)
(global interrupt enable)
Power-on detection
Power-On Detect function similar Brownout Detect, designed work power initially comes before power supply voltage reaches level where Brownout Detect function. flag (RSTSRC.4) indicate initial power-on condition. flag will remain until cleared software writing logic bit. Note that (UCFG1.5) programmed, (RSTSRC.5) will when set. unprogrammed, meaningless.
Power reduction modes
P89LPC932A1 supports three different power reduction modes determined bits PCON[1:0] (see Table 12).
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Table
Power reduction modes Description Normal mode (default) power reduction. Idle mode. Idle mode leaves peripherals running order allow them activate processor when interrupt generated. enabled interrupt source reset terminate Idle mode. Power-down mode: Power-down mode stops oscillator order minimize power consumption. P89LPC932A1 exits Power-down mode reset, certain interrupts external pins INT0/INT1, brownout Interrupt, keyboard, Real-time Clock/System Timer), watchdog, comparator trips. Waking reset only enabled corresponding reset enabled, waking interrupt only enabled corresponding interrupt enabled (IEN0.7) set. Power-down mode internal oscillator disabled unless both oscillator been selected system clock enabled. Power-down mode, power supply voltage reduced keep-alive voltage VRAM. This retains contents point where Power-down mode entered. contents guaranteed after been lowered VRAM, therefore recommended wake-up processor Reset this situation. must raised within operating range before Power-down mode exited. When processor wakes from Power-down mode, will start oscillator immediately begin execution when oscillator stable. Oscillator stability determined counting 1024 clocks after start-up when crystal oscillator configurations used, clocks after start-up internal external clock input configurations. Some chip functions continue operate draw power during Power-down mode, increasing total power used during power-down. These include:
PMOD1 PMOD0 (PCON.1) (PCON.0)
Brownout Detect Watchdog Timer WDCLK (WDCON.0) logic Comparators (Note: Comparators powered down separately with PCONA.5 logic comparators disabled); Real-time Clock/System Timer (and crystal oscillator circuitry this block using unless RTCPD, i.e., PCONA.7 logic
Total Power-down mode: This same Power-down mode except that Brownout Detection circuitry voltage comparators also disabled conserve additional power. Note that brownout reset interrupt will occur. Voltage comparator interrupts Brownout interrupt cannot used wake-up source. internal oscillator disabled unless both oscillator been selected system clock enabled. following wake-up options supported:
Watchdog Timer WDCLK (WDCON.0) logic Could generate Interrupt Reset, either wake device External interrupts INTO/INT1 Keyboard Interrupt Real-time Clock/System Timer (and crystal oscillator circuitry this block using unless RTCPD, i.e., PCONA.7 logic
Note: Using internal RC-oscillator clock during power-down result relatively high power consumption. Lower power consumption achieved using external frequency clock when Real-time Clock running during power-down.
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Table Symbol Reset Table
Power Control register (PCON address 87h) allocation SMOD1 SMOD0 BOPD PMOD1 PMOD0
Power Control register (PCON address 87h) description Symbol PMOD0 PMOD1 BOPD General Purpose Flag read written user software, effect operation General Purpose Flag read written user software, effect operation Brownout Detect Interrupt Enable. When logic Brownout Detection will generate interrupt. When logic Brownout Detection will cause reset Brownout Detect power-down. When logic Brownout Detect powered down therefore disabled. When logic Brownout Detect enabled. (Note: BOPD must logic before programming erasing commands issued. Otherwise these commands will aborted.) Framing Error Location: Description Power Reduction Mode (see Section 5.3)
SMOD0
SMOD1
When logic SCON accessed UART. When logic SCON accessed framing error status (FE) UART
Double Baud Rate serial port (UART) when Timer used baud rate source. When logic Timer overflow rate supplied UART. When logic Timer overflow rate divided before being supplied UART. (See Section
Table Symbol Reset Table
Power Control register (PCONA address B5h) allocation RTCPD DEEPD VCPD I2PD SPPD CCUPD
Power Control register (PCONA address B5h) description Symbol CCUPD Description Compare/Capture Unit (CCU) power-down: When logic internal clock disabled. Note that either Power-down mode Total Power-down mode, clock will disabled regardless this bit. (Note: This overridden CCUDIS FCFG1. CCUDIS powered down.) Serial Port (UART) power-down: When logic internal clock UART disabled. Note that either Power-down mode Total Power-down mode, UART clock will disabled regardless this bit. power-down: When logic internal clock disabled. Note that either Power-down mode Total Power-down mode, clock will disabled regardless this bit. power-down: When logic internal clock I2C-bus disabled. Note that either Power-down mode Total Power-down mode, clock will disabled regardless this bit.
SPPD
I2PD
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Table
Power Control register (PCONA address B5h) description Symbol VCPD Description reserved Analog Voltage Comparators power-down: When logic voltage comparators powered down. User must disable voltage comparators prior setting this bit. Data EEPROM power-down: When logic Data EEPROM powered down. Note that either Power-down mode Total Power-down mode, Data EEPROM will powered down regardless this bit. Real-time Clock power-down: When logic internal clock Real-time Clock disabled.
DEEPD
RTCPD
Reset
P1.5/RST function either active reset input digital input, P1.5. (Reset Enable) UCFG1, when enables external reset input function P1.5. When cleared, P1.5 used input pin. Note: During power-on sequence, selection overridden this will always functions reset input. external circuit connected this should hold this during Power-on sequence this will keep device reset. After power-on this input will function either external reset input digital input defined bit. Only power-on reset will temporarily override selection defined bit. Other sources reset will override bit. Note: During power cycle, must fall below VPOR (see P89LPC932A1 data sheet, Static characteristics) before power reapplied, order ensure power-on reset. Reset triggered from following sources (see Figure 13):
External reset (during power-on user configured UCFG1); Power-on Detect; Brownout Detect; Watchdog Timer; Software reset; UART break detect reset.
every reset source, there flag Reset Register, RSTSRC. user read this register determine most recent reset source. These flag bits cleared software writing logic corresponding bit. More than flag set:
During power-on reset, both other flag bits
cleared.
other reset, previously flag bits that have been cleared will remain
set.
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(UCFG1.6) WDTE (UCFG1.7) watchdog timer reset software reset SRST (AUXR1.3) chip reset power-on detect UART break detect EBRR (AUXR1.6) brownout detect reset BOPD (PCON.5)
002aaa918
Block diagram reset. Table Symbol Reset[1]
Reset Sources register (RSTSRC address DFh) allocation R_BK R_WD R_SF R_EX
value shown power-on reset. Other reset sources will their corresponding bits.
Table R_EX R_SF R_WD R_BK
Reset Sources register (RSTSRC address DFh) description external reset Flag. When this logic indicates external reset. Cleared software writing logic Power-on reset. still asserted after Power-on reset over, R_EX will set. software reset Flag. Cleared software writing logic Power-on reset Watchdog Timer reset flag. Cleared software writing logic Power-on reset.(NOTE: UCFG1.7 must break detect reset. break detect occurs EBRR (AUXR1.6) logic system reset will occur. This indicate that system reset caused break detect. Cleared software writing logic Power-on reset. Power-on Detect Flag. When Power-on Detect activated, flag indicate initial power-up condition. flag will remain until cleared software writing logic bit. (Note: Power-on reset, both this will while other flag bits cleared.) Brownout Detect Flag. When Brownout Detect activated, this set. will remain until cleared software writing logic bit. (Note: Power-on reset, both this will while other flag bits cleared.) reserved
Symbol Description
Reset vector
Following reset, P89LPC932A1 will fetch instructions from either address 0000h Boot address. Boot address formed using Boot Vector high byte address byte address 00h. Boot address will used UART break reset occurs non-volatile Boot Status (BOOTSTAT.0) device been forced into mode. Otherwise, instructions will fetched from address 0000H.
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Timers
P89LPC932A1 general-purpose counter/timers which upward compatible with 80C51 Timer Timer Both configured operate either timers event counters (see Table 20). option automatically toggle upon timer overflow been added. `Timer' function, timer incremented every PCLK. `Counter' function, register incremented response 1-to-0 transition corresponding external input T1). external input sampled once during every machine cycle. When high during cycle next cycle, count incremented. count value appears register during cycle following which transition detected. Since takes machine cycles (four clocks) recognize 1-to-0 transition, maximum count rate clock frequency. There restrictions duty cycle external input signal, ensure that given level sampled least once before changes, should held least full machine cycle. `Timer' `Counter' function selected control bits TnC/T Timers respectively) Special Function Register TMOD. Timer Timer have five operating modes (modes which selected bit-pairs (TnM1, TnM0) TMOD TnM2 TAMOD. Modes same both Timers/Counters. Mode different. operating modes described later this section.
Table Symbol Reset Table T0M0 T0M1 T0C/T Timer/Counter Mode register (TMOD address 89h) allocation T1GATE T1C/T T1M1 T1M0 T0GATE T0C/T T0M1 T0M0
Timer/Counter Mode register (TMOD address 89h) description Description Mode Select Timer These bits used with T0M2 TAMOD register determine Timer mode (see Table 22). Timer Counter selector Timer Cleared Timer operation (input from CCLK). Counter operation (input from input pin).
Symbol
T0GATE Gating control Timer When set, Timer/Counter enabled only while INT0 high control set. When cleared, Timer enabled when control set. T1M0 T1M1 T1C/T Mode Select Timer These bits used with T1M2 TAMOD register determine Timer mode (see Table 22). Timer Counter Selector Timer Cleared Timer operation (input from CCLK). Counter operation (input from input pin).
T1GATE Gating control Timer When set, Timer/Counter enabled only while INT1 high control set. When cleared, Timer enabled when control set.
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Table Symbol Reset Table T0M2
Timer/Counter Auxiliary Mode register (TAMOD address 8Fh) allocation T1M2 T0M2
Timer/Counter Auxiliary Mode register (TAMOD address 8Fh) description Description Mode Select Timer These bits used with T0M2 TAMOD register determine Timer mode (see Table 22). reserved Mode Select Timer These bits used with T1M2 TAMOD register determine Timer mode (see Table 22). following timer modes selected timer mode bits TnM[2:0]: 8048 Timer `TLn' serves 5-bit prescaler. (Mode 16-bit Timer/Counter `THn' `TLn' cascaded; there prescaler.(Mode 8-bit auto-reload Timer/Counter. holds value which loaded into when overflows. (Mode Timer dual 8-bit Timer/Counter this mode. 8-bit Timer/Counter controlled standard Timer control bits. 8-bit timer only, controlled Timer control bits (see text). Timer this mode stopped. (Mode Reserved. User must configure this mode. Reserved. User must configure this mode. mode (see Section 7.5). Reserved. User must configure this mode.
Symbol
T1M2
reserved
Mode
Putting either Timer into Mode makes look like 8048 Timer, which 8-bit Counter with divide-by-32 prescaler. Figure shows Mode operation. this mode, Timer register configured 13-bit register. count rolls over from sets Timer interrupt flag TFn. count input enabled Timer when either TnGATE INTn (Setting TnGATE allows Timer controlled external input INTn, facilitate pulse width measurements). control Special Function Register TCON (Table 24). TnGATE TMOD register. 13-bit register consists bits lower bits TLn. upper bits indeterminate should ignored. Setting flag (TRn) does clear registers. Mode operation same Timer Timer Figure There different GATE bits, Timer (TMOD.7) Timer (TMOD.3).
Mode
Mode same Mode except that bits timer register (THn TLn) used. Figure
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Mode
Mode configures Timer register 8-bit Counter (TLn) with automatic reload, shown Figure Overflow from only sets TFn, also reloads with contents THn, which must preset software. reload leaves unchanged. Mode operation same Timer Timer
Mode
When Timer Mode stopped. effect same setting Timer Mode establishes separate 8-bit counters. logic Mode Timer shown Figure uses Timer control bits: T0C/T, T0GATE, TR0, INT0, TF0. locked into timer function (counting machine cycles) takes over from Timer Thus, controls `Timer interrupt. Mode provided applications that require extra 8-bit timer. With Timer Mode P89LPC932A1 device look like three Timer/Counters. Note: When Timer Mode Timer turned switching into Mode still used serial port baud rate generator, application requiring interrupt.
Mode
this mode, corresponding timer changed with full period timer clocks (see Figure 18). structure similar mode except that:
Timers respectively) cleared hardware; period THn, should between 254, and; high period always 256THn. Loading with will force high, loading with will force low.
Note that interrupt still enabled high transition TFn, that still cleared software like other modes.
Table Symbol Reset Table Timer/Counter Control register (TCON) address 88h) allocation
Timer/Counter Control register (TCON address 88h) description Description Interrupt Type control bit. Set/cleared software specify falling edge/low level triggered external interrupts. Interrupt Edge flag. hardware when external interrupt edge detected. Cleared hardware when interrupt processed, software. Interrupt Type control bit. Set/cleared software specify falling edge/low level triggered external interrupts.
Symbol
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Table
Timer/Counter Control register (TCON address 88h) description Description Interrupt Edge flag. hardware when external interrupt edge detected. Cleared hardware when interrupt processed, software. Timer control bit. Set/cleared software turn Timer/Counter on/off. Timer overflow flag. hardware Timer/Counter overflow. Cleared hardware when processor vectors interrupt routine, software. (except mode where cleared hardware) Timer control bit. Set/cleared software turn Timer/Counter on/off Timer overflow flag. hardware Timer/Counter overflow. Cleared hardware when interrupt processed, software (except mode above, when cleared hardware).
Symbol
PCLK
control (5-bits) (8-bits)
overflow interrupt
toggle gate INTn ENTn
002aaa919
Timer/counter Mode (13-bit counter).
PCLK
control (8-bits) (8-bits)
overflow interrupt
toggle gate INTn ENTn
002aaa920
Timer/counter mode (16-bit counter).
PCLK
control (8-bits) reload
overflow interrupt
toggle
gate INTn (8-bits)
ENTn
002aaa921
Timer/counter Mode (8-bit auto-reload).
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PCLK
control (8-bits)
overflow toggle interrupt
gate INT0 ENT0 (AUXR1.4)
(P1.2 open drain)
osc/2 control
(8-bits)
overflow interrupt
toggle (P0.7) ENT1 (AUXR1.5)
002aaa922
Timer/counter Mode (two 8-bit counters).
PCLK control (8-bits)
overflow interrupt
reload falling transition (256 THn) rising transition
toggle gate INTn (8-bits)
ENTn
002aaa923
Timer/counter mode (PWM auto-reload).
Timer overflow toggle output
Timers configured automatically toggle port output whenever timer overflow occurs. same device pins that used count inputs outputs also used timer toggle outputs. This function enabled control bits ENT0 ENT1 AUXR1 register, apply Timer Timer respectively. port outputs will logic prior first timer overflow when this mode turned order this mode function, must cleared selecting PCLK clock source timer.
Real-time clock system timer
P89LPC932A1 simple Real-time Clock/System Timer that allows user continue running accurate timer while rest device powered down. Real-time Clock interrupt wake-up source (see Figure 19).
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Real-time Clock 23-bit down counter. clock source this counter either clock (CCLK) XTAL1-2 oscillator, provided that XTAL1-2 oscillator being used clock. XTAL1-2 oscillator used clock, then will CCLK clock source regardless state RTCS1:0 RTCCON register. There three SFRs used RTC: RTCCON Real-time Clock control. RTCH Real-time Clock counter reload high (bits 15). RTCL Real-time Clock counter reload (bits Real-time clock system timer enabled setting RTCEN (RTCCON.0) bit. Real-time Clock 23-bit down counter (initialized when RTCEN that comprised 7-bit prescaler 16-bit loadable down counter. When RTCEN written with logic counter first loaded with (RTCH, RTCL, `1111111') will count down. When reaches 0's, counter will reloaded again with (RTCH, RTCL, `1111111') flag RTCF (RTCCON.7) will set.
power-on reset
RTCH
RTCL
RESET XTAL2 XTAL1
RELOAD UNDERFLOW FREQUENCY MEDIUM FREQUENCY HIGH FREQUENCY CCLK internal oscillators RTCS1 RTCS2 select
002aaa924
7-BIT PRESCALER ÷128
23-BIT DOWN COUNTER
wake-up from power-down RTCF Interrupt enabled (shared with WDT) underflow flag ERTC RTCEN enable
Real-time clock/system timer block diagram.
Real-time clock source
RTCS1/RTCS0 (RTCCON[6:5]) used select clock source either Internal oscillator internal oscillator used clock. internal crystal oscillator external clock input XTAL1 used clock, then will CCLK clock source.
Changing RTCS1/RTCS0
RTCS1/RTCS0 cannot changed currently enabled (RTCCON.0 Setting RTCEN updating RTCS1/RTCS0 done single write RTCCON. However, RTCEN this must first cleared before updating RTCS1/RTCS0.
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Real-time clock interrupt/wake-up
ERTC (RTCCON.1), EWDRT (IEN1.0.6) (IEN0.7) logic RTCF used interrupt source. This interrupt vector shared with watchdog timer. also source wake-up device.
Reset sources affecting Real-time clock
Only power-on reset will reset Real-time Clock associated SFRs their default state.
Table FOSC2:0 Real-time Clock/System Timer clock sources RCCLK RTCS1:0 Internal oscillator frequency crystal /DIV frequency crystal Internal oscillator Internal oscillator frequency crystal frequency crystal /DIVM Medium frequency crystal /DIVM Medium frequency crystal Internal oscillator Internal oscillator Medium frequency crystal Medium frequency crystal /DIVM High frequency crystal /DIVM High frequency crystal Internal oscillator clock source High frequency crystal clock source High frequency crystal /DIVM
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Real-time Clock/System Timer clock sources RCCLK RTCS1:0 clock source High frequency crystal frequency crystal Internal oscillator /DIVM High frequency crystal Medium frequency crystal frequency crystal Internal oscillator Watchdog oscillator /DIVM Medium frequency crystal frequency crystal Watchdog oscillator /DIVM High frequency crystal Medium frequency crystal frequency crystal Internal oscillator undefined undefined External clock input undefined undefined External clock input /DIVM Internal oscillator High frequency crystal Internal oscillator clock source Internal oscillator Medium frequency crystal /DIVM
Table FOSC2:0
External clock input /DIVM External clock input Internal oscillator
Internal oscillator
Table Symbol Reset
Real-time Clock Control register (RTCCON address D1h) allocation RTCF RTCS1 RTCS0 ERTC RTCEN
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Real-time Clock Control register (RTCCON address D1h) description Description Real-time Clock enable. Real-time Clock will enabled this logic Note that this will power-down Real-time Clock. RTCPD (PCONA.7) set, will power-down disable this block regardless RTCEN. Real-time Clock interrupt enable. Real-time Clock shares same interrupt watchdog timer. Note that user configuration WDTE (UCFG1.7) logic watchdog timer enabled generate interrupt. Users read RTCF (RTCCON.7) determine whether Real-time Clock caused interrupt. reserved Real-time Clock source select (see Table 25). Real-time Clock Flag. This logic when 23-bit Real-time Clock reaches count logic cleared software.
Table
Symbol RTCEN
ERTC
RTCS0 RTCS1 RTCF
Capture/Compare Unit (CCU)
This unit features:
16-bit timer with 16-bit reload overflow Selectable clock (CCUCLK), with prescaler divide clock source integer
between 1024.
Four Compare outputs with selectable polarity Symmetrical Asymmetrical selection Seven interrupts with common interrupt vector (one Overflow, 2xCapture,
4xCompare), safe 16-bit read/write shadow registers.
Capture inputs with event counter digital noise rejection filter
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16-BIT SHADOW REGISTER TOR2H TOR2L
16-BIT SHADOW REGISTER OCRxH OCRxL
16-BIT COMPARE VALUE
16-BIT TIMER RELOAD REGISTER OVERFLOW/ UNDERFLOW
TIMER COMPARE
COMPARE CHANNELS
FCOx
16-BIT UP/DOWN TIMER WITH RELOAD
16-BIT CAPTURE REGISTER ICRxH, EVENT COUNTER
ICNFx NOISE FILTER
ICESx EDGE SELECT
10-BIT DIVIDER INTERRUPT FLAG TICF2x CAPTURE CHANNELS
4-BIT DIVIDER
002aab009
Capture Compare Unit block diagram.
Clock (CCUCLK)
runs CCUCLK, which either PCLK basic timer mode output (see Figure 20). designed clock source between that multiplied produce CCUCLK between mode (asymmetrical symmetrical). contains 4-bit divider (PLLDV3:0 bits TCR21 register) help divide PCLK into frequency between
Clock prescaling
This CCUCLK further divided down prescaler. prescaler implemented 10-bit free-running counter with programmable reload overflow. Writing value prescaler will cause prescaler restart.
Basic timer operation
Timer free-running up/down counter counting pace determined prescaler. timer started setting Mode Select bits TMOD21 TMOD20 Control Register (TCR20) shown table TCR20 register description (Table 32). direction control bit, TDIR2, determines direction count. TDIR2 Count TDIR2 Count down. timer counting direction changed while counter running, count sequence will reversed CCUCLK cycle following write TDIR2. timer written read time newly-written values will take effect when prescaler overflows. timer accessible through SFRs, TL2(low byte) TH2(high byte). third 16-bit SFR, TOR2H:TOR2L, determines overflow reload value. TL2, TOR2H, TOR2L will after reset
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Up-counting: When timer contents FFFFH, next CCUCLK cycle will counter value contents TOR2H:TOR2L. Down-counting: When timer contents 0000H, next CCUCLK cycle will counter value contents TOR2H:TOR2L. During CCUCLK cycle when reload performed, Timer Overflow Interrupt Flag (TOIF2) Interrupt Flag Register (TIFR2) will set, and, IEN0 register ECCU IEN1 register (IEN1.4) set, program execution will vector overflow interrupt. user clear interrupt flag software writing logic When writing reload registers, TOR2H TOR2L, values written stored 8-bit shadow registers. order latch contents shadow registers into TOR2H TOR2L, user must write logic Timer Compare/Overflow Update TCOU2, Timer Control Register (TCR21). function this depends whether timer running mode basic timer mode. basic timer mode, writing TCOU2 will cause values latched immediately value TCOU2 will always read zero. mode, writing TCOU2 will cause contents shadow registers updated next Timer overflow. long latch pending, TCOU2 will read will return zero when latching takes place. TCOU2 also controls latching Output Compare registers OCR2A, OCR2B OCR2C. When writing timer high byte, TH2, value written stored shadow register. When written, contents TH2's shadow register transferred same time that gets updated. Thus, should written prior writing TL2. write followed another write TL2, without being written between, value will transferred directly high byte timer. 16-bit Timer used 8-bit timer, user write (for upcounting) (for downcounting) TH2. When written, FFh:TH2 (for upcounting) (for downcounting) will loaded Timer. user will need rewrite again 8-bit timer operation unless there change count direction When reading timer, must read first. When read, contents timer high byte transferred shadow register same PCLK cycle read performed. When read, contents shadow register read instead. read from followed another read from without being read between, high byte timer will transferred directly TH2.
Table Symbol Reset Table prescaler control register, high byte (TPCR2H address CBh) allocation TPCR2H.1 TPCR2H.0
prescaler control register, high byte (TPCR2H address CBh) description Description Prescaler Prescaler
Symbol TPCR2H.0 TPCR2H.1
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Table Symbol Reset
prescaler control register, byte (TPCR2L address CAh) allocation TPCR2L.7 TPCR2L.6 Table TPCR2L.5 TPCR2L.4 TPCR2L.3 TPCR2L.2 TPCR2L.1 TPCR2L.0
prescaler control register, byte (TPCR2L address CAh) description Symbol TPCR2L.0 TPCR2L.1 TPCR2L.2 TPCR2L.3 TPCR2L.4 TPCR2L.5 TPCR2L.6 TPCR2L.7 Description Prescaler Prescaler Prescaler Prescaler Prescaler Prescaler Prescaler Prescaler
Table Symbol Reset Table
control register (TCR20 address C8h) allocation PLLEN HLTRN HLTEN ALTCD ALTAB TDIR2 TMOD21 TMOD20
control register (TCR20 address C8h) description Description Timer mode (TMOD21, TMOD20): Timer stopped Basic timer function Asymmetrical (uses clock source) Symmetrical (uses clock source)
Symbol TMOD20/21
TDIR2 ALTAB ALTCD HLTEN HLTRN PLLEN
Count direction Timer. When logic count When logic count down. channel alternately output enable. When this set, output channel alternately gated every counter cycle. channel alternately output enable. When this set, output channel alternately gated every counter cycle. Halt Enable. When logic capture event enabled Input Capture will immediately stop activity pins them predetermined state. Halt. When indicates halt took place. order re-activate PWM, user must clear HLTRN bit. Phase Locked Loop Enable. When logic starts operation. After lock this will read back one.
Output compare
four output compare channels controlled through four 16-bit SFRs, OCRAH:OCRAL, OCRBH:OCRBL, OCRCH:OCRCL, OCRDH: OCRDL. Each output compare channel needs enabled order operate. channel enabled selecting Compare Output Action setting OCMx1:0 bits Capture Compare Control Register CCCRx When compare channel enabled, user
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will have associated desired output mode connect pin. (Note: bits port pins P2.6, P1.6, P1.7, P2.1 must logic order compare channel outputs visible port pins.) When contents TH2:TL2 match that OCRxH:OCRxL, Timer Output Compare Interrupt Flag TOCFx TIFR2. This happens CCUCLK cycle after compare takes place. Timer Output Compare Interrupt Enable TOCIE2x TICR2 register), well ECCU IEN1 set, program counter will vectored corresponding interrupt. user must manually clear writing logic bits OCCRx, Output Compare Mode bits OCMx1 OCMx0 select what action taken when compare match occurs. Enabled compare actions take place even interrupt disabled. order Compare Output Action occur, compare values must within counting range timer. When compare channel enabled, (which must configured output) will connected internal latch controlled compare logic. value this latch zero from reset changed invoking forced compare. forced compare generated writing logic Force Compare Output FCOx OCCRx. Writing this generates transition corresponding OCMx1/OCMx0 without causing interrupt. basic timer operating mode FCOx bits always read zero. (Note: This different function mode.) When output compare enabled connected compare latch, state compare remains unchanged until compare event forced compare occurs.
Table Symbol Reset Table Capture compare control register (CCRx address Exh) allocation ICECx2 ICECx1 ICECx0 ICESx ICNFx FCOx OCMx1 OCMx0
Capture compare control register (CCRx address Exh) description Description Output Compare Mode. Force Compare Output Bit. When set, invoke force compare. Input Capture Noise Filter Enable Bit. When logic capture logic needs four consecutive samples same value order recognize edge capture event. inputs sampled every CCLK periods regardless speed timer. Input Capture Edge Select Bit. When logic Negative edge triggers capture, When logic Positive edge triggers capture. Capture Delay Setting Table details. Capture Delay Setting Table details. Capture Delay Setting Table details.
Symbol OCMx0 OCMx1 FCOx ICNFx
ICESx ICECx0 ICECx1 ICECx2
When user writes change output compare value, values written OCRH2x OCRL2x transferred 8-bit shadow registers. order latch contents shadow registers into capture compare register, user must write logic Timer Compare/Overflow Update TCOU2, Control Register TCR21. function this depends whether timer running mode
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basic timer mode. basic timer mode, writing TCOU2 will cause values latched immediately value TCOU2 will always read zero. mode, writing TCOU2 will cause contents shadow registers updated next Timer overflow. long latch pending, TCOU2 will read will return zero when latch takes place. TCOU2 also controls latching Output Compare registers well Timer Overflow Reload registers TOR2.
Input capture
Input capture always enabled. Each time capture event occurs input capture pins, contents timer transferred corresponding 16-bit input capture register ICRAH:ICRAL ICRBH:ICRBL. capture event defined Input Capture Edge Select ICESx being CCCRx register. user will have configure associated input order external event trigger capture. simple noise filter enabled input capture input. When Input Capture Noise Filter ICNFx set, capture logic needs four consecutive samples same value order recognize edge capture event. inputs sampled every CCLK periods regardless speed timer. event counter delay capture number capture events. three bits ICECx2, ICECx1 ICECx0 CCCRx register determine number edges capture logic before input capture occurs. When capture event detected, Timer Input Capture Interrupt Flag TICF2x (TIFR2.1 TIFR2.0) set. Timer Input Capture Enable TICIE2x (TICR2.1 TICR2.0) well ECCU (IEN1.4) set, program counter will vectored corresponding interrupt. interrupt flag must cleared manually writing logic When reading input capture register, ICRxL must read first. When ICRxL read, contents capture register high byte transferred shadow register. When ICRxH read, contents shadow register read instead. read from ICRxL followed another read from ICRxL without ICRxH being read between, value capture register high byte (from last ICRxL read) will shadow register).
Table ICECx2 Event delay counter input capture ICECx1 ICECx0 Delay (numbers edges)
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operation
Operation main modes, asymmetrical symmetrical. These modes timer operation selected writing TMOD21:TMOD20 shown Section "Basic timer operation". asymmetrical operation, Timer operates downcounting mode regardless setting TDIR2. this case, TDIR2 will always read symmetrical mode, timer counts up/down alternately value TDIR2 effect. main difference from basic timer operation operation compare module, which mode used waveform generation. Table shows behavior compare pins mode. user will have configure output compare pins outputs order enable output. with basic timer operation, when (compare) pins connected compare logic, their logic state remains unchanged. However, since used hold halt value, only compare event change state pin.
TOR2
compare value timer value 0x0000
non-inverted
inverted
002aaa893
Asymmetrical PWM, downcounting.
TOR2
compare value timer value non-inverted
inverted
002aaa894
Symmetrical PWM.
Timer Overflow interrupt flag when counter changes direction top. example, contains 01FFH, Timer will count: .01FEH, 01FFH, 01FEH,. flag counter cycle after change from TOR-1.
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When timer changes direction bottom, this example, counts .,0001H, 0000H, 0001H,. Timer overflow interrupt flag counter CCUCLK cycle after transition from 0001H 0000H. status TDIR2 TCR20 reflects current counting direction. Writing this while operating symmetrical mode effect.
Alternating output mode
asymmetrical mode, user program channels alternating pairs bridge drive control. setting ALTAB ALTCD bits TCR20, output these channels alternately gated every counter cycle. This shown following figure:
TOR2 compare value compare value timer value
output (P2.6)
output (P1.6)
002aaa895
Alternate output mode. Table OCMx1[1] Output compare behavior. OCMx0[1] Output Compare behavior Basic timer mode Asymmetrical Symmetrical Output compare disabled. power-on, this default state, pins configured inputs. when compare operation. Cleared compare match.[2] Non-Inverted PWM. compare match. Cleared Timer underflow. Inverted PWM. Cleared compare match. Timer underflow.[2] Non-Inverted PWM. Cleared compare match, upcounting. compare match, downcounting. Inverted PWM. compare match, upcounting. Cleared compare match, downcounting.[2]
Toggles compare match[2]
`ON' means CCUCLK cycle after event takes place.
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Synchronized register update
When OCRx registers written, built mechanism ensures that value updated middle pulse. This could result odd-length pulse. When registers written, values placed shadow registers, case basic timer operation mode. Writing TCOU2 will cause contents shadow registers updated next Timer overflow. OCRxH and/or OCRxL read before value updated, most currently written value read.
HALT
Setting HLTEN TCR20 enables Halt Function. When halt function enabled, capture event enabled Input Capture will immediately stop activity pins them predetermined state defined FCOx bit. Mode, FCOx bits CCCRx register hold value forced during halt. value setting read back. capture function interrupt will still operate normal even this added functionality enabled. When unit halted, timer will still normal. HLTRN TCR20 will indicate that halt took place. order re-activate PWM, user must clear HLTRN bit. user force unit into halt writing logic HLTRN bit.
9.10 operation
module features Phase Locked Loop that used generate CCUCLK frequency between MHz. this frequency module provides ultrasonic frequency with 10-bit resolution provided that crystal frequency higher (The resolution programmable bits writing TOR2H:TOR2L). input signal generates output signal times input frequency. This signal used clock timer. user will have divider that scales PCLK factor This divider found register TCR21. frequency expressed follows: frequency PCLK (N+1) Where: value PLLDV3:0. Since ranges CCLK frequency range PCLK PCLKe16.
Table Symbol Reset control register (TCR21 address F9h) allocation TCOU2 PLLDV.3 PLLDV.2 PLLDV.1 PLLDV.0
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Table
control register (TCR21 address F9h) description Description frequency divider. Reserved. basic timer mode, writing logic TCOU2 will cause values latched immediately value TCOU2 will always read logic mode, writing logic TCOU2 will cause contents shadow registers updated next Timer overflow. long latch pending, TCOU2 will read logic will return logic when latching takes place. TCOU2 also controls latching Output Compare registers OCRAx, OCRBx OCRCx.
Symbol PLLDV.3:0 TCOU2
Setting PLLEN TCR20 starts PLL. When PLLEN set, will read back until lock. this time, unit ready operate timer enabled. following start-up sequence recommended: module without starting timer. Calculate right division factor that receives input clock signal MHz. Write this value PLLDV. PLLEN. Wait until reads Start timer writing value bits TMOD21, TMOD20 When timer runs from PLL, timer operates asynchronously rest microcontroller. Some restrictions apply:
user discouraged from writing reading timer asynchronous mode.
results unpredictable
Interrupts flags asynchronous. There will delay event
actually recognized until some CCLK cycles later (for interrupts reads)
9.11 interrupt structure
There seven independent sources interrupts CCU: timer overflow, captured input events Input Capture blocks A/B, compare match events Output Compare blocks through common interrupt vector used service routine interrupts occur simultaneously system usage. resolve this situation, priority encode function seven interrupt bits TIFR2 implemented (after each AND-ed with corresponding interrupt enable TICR2 register). order priority fixed follows, from highest lowest:
TOIF2 TICF2A TICF2B TOCF2A TOCF2B TOCF2C TOCF2D
interrupt service routine follows: Read priority-encoded value from TISE2 register determine interrupt source handled.
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After current (highest priority) event serviced, write logic corresponding interrupt flag TIFR2 register clear flag. Read TISE2 register. priority-encoded interrupt source `000', interrupts serviced return from interrupt occur. Otherwise, return step next interrupt.
(IEN0.7) ECCU (IEN1.4) TOIE2 (TICR2.7) TOIF2 (TIFR2.7) TICIE2A (TICR2.0) TICF2A (TIFR2.0) TICIE2B (TICR2.1) TICF2B (TIFR2.1) TOCIE2A (TICR2.3) TOCF2A (TIFR2.3) TOCIE2B (TICR2.4) TOCF2B (TIFR2.4) TOCIE2C (TICR2.5) TOCF2C (TIFR2.5) TOCIE2D (TICR2.6) TOCF2D (TIFR2.6) interrupt
other interrupt sources
ENCINT.0 PRIORITY ENCODER ENCINT.1 ENCINT.2
002aaa896
Capture/compare unit interrupts.
Table Symbol Reset
interrupt status encode register (TISE2 address DEh) allocation ENCINT.2 ENCINT.1 ENCINT.0
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Table
interrupt status encode register (TISE2 address DEh) description Description Interrupt Encode output. When multiple interrupts happen, more than interrupt flag Interrupt Flag Register (TIFR2). encoder output read determine which interrupt serviced. user must write logic clear corresponding interrupt flag TIFR2 register after corresponding interrupt been serviced. Refer Table TIFR2 description. interrupt pending. Output Compare Event interrupt (lowest priority) Output Compare Event interrupt. Output Compare Event interrupt. Output Compare Event interrupt. Input Capture Event interrupt. Input Capture Event interrupt. Timer Overflow interrupt (highest priority).
Symbol ENCINT.2:0
Table Symbol Reset Table
Reserved. interrupt flag register (TIFR2 address E9h) allocation TOIF2 TOCF2D TOCF2C TOCF2B TOCF2A TICF2B TICF2A
interrupt flag register (TIFR2 address E9h) description Description Input Capture Channel Interrupt Flag Bit. hardware when input capture event detected. Cleared software. Input Capture Channel Interrupt Flag Bit. hardware when input capture event detected. Cleared software. Reserved future use. Should logic user program. Output Compare Channel Interrupt Flag Bit. hardware when contents TH2:TL2 match that OCRHA:OCRLA. Compare channel must enabled order generate this interrupt. IEN0, ECCU IEN1 TOCIE2A set, program counter will vectored corresponding interrupt. Cleared software. Output Compare Channel Interrupt Flag Bit. hardware when contents TH2:TL2 match that OCRHB:OCRLB. Compare channel must enabled order generate this interrupt. IEN0, ECCU IEN1 TOCIE2B set, program counter will vectored corresponding interrupt. Cleared software. Output Compare Channel Interrupt Flag Bit. hardware when contents TH2:TL2 match that OCRHC:OCRLC. Compare channel must enabled order generate this interrupt. IEN0, ECCU IEN1 TOCIE2C set, program counter will vectored corresponding interrupt. Cleared software. Output Compare Channel Interrupt Flag Bit. hardware when contents TH2:TL2 match that OCRHD:OCRLD. Compare channel must enabled order generate this interrupt. IEN0, ECCU IEN1 TOCIE2D set, program counter will vectored corresponding interrupt. Cleared software. Timer Overflow Interrupt Flag bit. hardware Timer overflow. Cleared software.
Symbol TICF2A TICF2B TOCF2A
TOCF2B
TOCF2C
TOCF2D
TOIF2
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Table Symbol Reset Table
interrupt control register (TICR2 address C9h) allocation TOIE2 TOCIE2D TOCIE2C TOCIE2B TOCIE2A TICIE2B TICIE2A
interrupt control register (TICR2 address C9h) description Description Input Capture Channel Interrupt Enable Bit. this set, when capture event detected, program counter will vectored corresponding interrupt. Input Capture Channel Interrupt Enable Bit. this set, when capture event detected, program counter will vectored corresponding interrupt. Reserved future use. Should logic user program. Output Compare Channel Interrupt Enable Bit. this when compare channel enabled contents TH2:TL2 match that OCRHA:OCRLA, program counter will vectored corresponding interrupt. Output Compare Channel Interrupt Enable Bit. this when compare channel enabled contents TH2:TL2 match that OCRHB:OCRLB, program counter will vectored corresponding interrupt. Output Compare Channel Interrupt Enable Bit. this when compare channel enabled contents TH2:TL2 match that OCRHC:OCRLC, program counter will vectored corresponding interrupt. Output Compare Channel Interrupt Enable Bit. this when compare channel enabled contents TH2:TL2 match that OCRHD:OCRLD, program counter will vectored corresponding interrupt. Timer Overflow Interrupt Enable bit.
Symbol TICIE2A TICIE2B TOCIE2A
TOCIE2B
TOCIE2C
TOCIE2D
TOIE2
UART
P89LPC932A1 enhanced UART that compatible with conventional 80C51 UART except that Timer overflow cannot used baud rate source. P89LPC932A1 does include independent Baud Rate Generator. baud rate selected from oscillator (divided constant), Timer overflow, independent Baud Rate Generator. addition baud rate generation, enhancements over standard 80C51 UART include Framing Error detection, break detect, automatic address recognition, selectable double buffering several interrupt options. UART operated modes, described following sections.
10.1 Mode
Serial data enters exits through RxD. outputs shift clock. bits transmitted received, first. baud rate fixed 1e16 clock frequency.
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Koninklijke Philips Electronics N.V. 2004. rights reserved.
User manual
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10.2 Mode
bits transmitted (through TxD) received (through RxD): start (logic data bits (LSB first), stop (logic When data received, stop stored Special Function Register SCON. baud rate variable determined Timer overflow rate Baud Rate Generator (see Section 10.6 "Baud Rate generator selection" page 58).
10.3 Mode
bits transmitted (through TxD) received (through RxD): start (logic data bits (LSB first), programmable data bit, stop (logic When data transmitted, data (TB8 SCON) assigned value example, parity PSW) could moved into TB8. When data received, data goes into Special Function Register SCON stop saved. baud rate programmable either 1e16 1e32 CCLK frequency, determined SMOD1 PCON.
10.4 Mode
bits transmitted (through TxD) received (through RxD): start (logic data bits (LSB first), programmable data bit, stop (logic Mode same Mode respects except baud rate. baud rate Mode variable determined Timer overflow rate Baud Rate Generator (see Section 10.6 "Baud Rate generator selection" page 58). four modes, transmission initiated instruction that uses SBUF destination register. Reception initiated Mode condition Reception initiated other modes incoming start
10.5 space
UART SFRs following locations:
Table Register PCON SCON SBUF SADDR SADEN SSTAT BRGR1 BRGR0 BRGCON UART addresses Description Power Control Serial Port (UART) Control Serial Port (UART) Data Buffer Serial Port (UART) Address Serial Port (UART) Address Enable Serial Port (UART) Status Baud Rate Generator Rate High Byte Baud Rate Generator Rate Byte Baud Rate Generator Control location
9397 13858
Koninklijke Philips Electronics N.V. 2004. rights reserved.
User manual
Rev. August 2004
Philips Semiconductors
UM10109
P89LPC932A1 User manual
10.6 Baud Rate generator selection
P89LPC932A1 enhanced UART independent Baud Rate Generator. baud rate determined value programmed into BRGR1 BRGR0 SFRs. UART either Timer baud rate generator output determined BRGCON[2:1] (see Figure 25). Note that Timer further divided SMOD1 (PCON.7) set. independent Baud Rate Generator uses CCLK.
10.7 Updating BRGR1 BRGR0 SFRs
baud rate SFRs, BRGR1 BRGR0 must only loaded when Baud Rate Generator disabled (the BRGEN BRGCON register logic This avoids loading interim value baud rate generator. (CAUTION: either BRGR0 BRGR1 written when BRGEN result unpredictable.)
Table SCON.7 (SM0) UART baud rate generation. SCON.6 (SM1) PCON.7 (SMOD1) Table Symbol Reset Table BRGCON.1 (SBRGS) Receive/transmit baud rate UART
CCLKe CCLKe (256TH1)64 CCLKe (256TH1)32 CCLKe ((BRGR1, BRGR0)+16) CCLKe CCLKe CCLKe (256TH1)64 CCLKe (256TH1)32 CCLKe ((BRGR1, BRGR0)+16)
Baud Rate Generator Control register (BRGCON address BDh) allocation SBRGS BRGEN
Baud Rate Generator Control register (BRGCON address BDh) description Description Baud Rate Generator Enable. Enables baud rate generator. BRGR1 BRGR0 only written when BRGEN Select Baud Rate Generator source baud rates UART modes (see Table details) reserved
Symbol BRGEN SBRGS
timer overflow (PCLK-based) baud rate generator (CCLK-based)
SMOD1 SMOD1
SBRGS baud rate modes SBRGS
002aaa897
Baud rate generation UART (Modes
9397 13858 Koninklijke Philips Electronics N.V. 2004. rights reserved.
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10.8 Framing error
Framing error occurs when stop sensed logic Framing error reported status register (SSTAT). addition, SMOD0 (PCON.6) framing errors made available SCON.7. SMOD0 SCON.7 SM0. recommended that (SCON[7:6]) programmed when SMOD0 logic
10.9 Break detect
break detect reported status register (SSTAT). break detected when consecutive bits sensed low. Since break condition also satisfies requirements framing error, break condition will also result reporting framing error. Once break condition been detected, UART will into idle state remain this idle state until stop been received. break detect used reset device force device into mode setting EBRR (AUXR1.6)
Table Symbol Reset Table Serial Port Control register (SCON address 98h) allocation SM0/FE
Serial Port Control register (SCON address 98h) description Description Receive interrupt flag. hardware time Mode approximately halfway through stop time Mode Mode Mode SMOD0, near middle data (bit SMOD0 near middle stop (see SCON.5 exceptions). Must cleared software. Transmit interrupt flag. hardware time Mode stop (see description INTLO SSTAT register) other modes. Must cleared software. data that received Modes Mode (SM2 must stop that received. Mode undefined. data that will transmitted Modes clear software desired. Enables serial reception. software enable reception. Clear software disable reception. Enables multiprocessor communication feature Modes Mode then will activated received data (RB8) Mode should Mode must With defines serial port mode, Table this determined SMOD0 PCON register. SMOD0 this read written SM0, which with SM1, defines serial port mode. SMOD0 this read written (Framing Error). receiver when invalid stop detected. Once set, this cannot cleared valid frames cleared software. (Note: UART mode bits should programmed when SMOD0 logic default mode reset.)
Symbol
SM0/FE
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Koninklijke Philips Electronics N.V. 2004. rights reserved.
User manual
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P89LPC932A1 User manual
Serial Port modes UART mode Mode shift register Mode 8-bit UART Mode 9-bit UART Mode 9-bit UART UART baud rate
CCLKe
Table SM0, Table Symbol Reset Table
(default mode reset) CCLKe16
Variable (see Table
CCLKe
Variable (see Table
Serial Port Status register (SSTAT address BAh) allocation DBMOD INTLO CIDIS DBISEL STINT
Serial Port Status register (SSTAT address BAh) description Description Status Interrupt Enable. When cause interrupt. interrupt used (vector address 0023h) shared with (CIDIS combined TI/RI (CIDIS When cleared cannot cause interrupt. (Note: often accompanied which will generate interrupt regardless state STINT). Note that cause break detect reset EBRR (AUXR1.6) logic Overrun Error flag character received receiver buffer while still full (before software read previous character from buffer), i.e., when byte received while SCON still set. Cleared software. Break Detect flag. break detected when consecutive bits sensed low. Cleared software. Framing error flag when receiver fails valid STOP frame. Cleared software. Double buffering transmit interrupt select. Used only double buffering enabled. This controls number interrupts that occur when double buffering enabled. When set, transmit interrupt generated after each character written SBUF, there also more transmit interrupt generated beginning (INTLO (INTLO STOP last character sent (i.e., more data buffer). This last interrupt used indicate that transmit operations over. When cleared only transmit interrupt generated character written SBUF. Must logic when double buffering disabled. Note that except first character written (when buffer empty), location transmit interrupt determined INTLO. When first character written, transmit interrupt generated immediately after SBUF written. Combined Interrupt Disable. When interrupts separate. When cleared UART uses combined Tx/Rx interrupt (like conventional 80C51 UART). This reset logic select combined interrupts. Transmit interrupt position. When cleared interrupt issued beginning stop bit. When interrupt issued stop bit. Must logic mode Note that case single buffering, interrupt occurs STOP bit, exist before next start bit.
Symbol STINT
DBISEL
CIDIS
INTLO
DBMOD Double buffering mode. When enables double buffering. Must logic UART mode order compatible with existing 80C51 devices, this reset logic disable double buffering.
9397 13858
Koninklijke Philips Electronics N.V. 2004. rights reserved.
User manual
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Philips Semiconductors
UM10109
P89LPC932A1 User manual
10.10 More about UART Mode
Mode write SBUF will initiate transmission. transmission, (SCON.1) set, which must cleared software. Double buffering must disabled this mode. Reception initiated clearing (SCON.0). Synchronous serial transfer occurs will again transfer. When cleared, reception next character will begin. Refer Figure
write SBUF shift (data out) (shift clock)
transmit
WRITE SCON (clear receive shift (data (shift clock)
002aaa925
Serial Port Mode (double buffering must disabled).
10.11 More about UART Mode
Reception initiated detecting 1-to-0 transition RxD. sampled rate times programmed baud rate. When transition detected, divide-by-16 counter immediately reset. Each time thus divided into counter states. 7th, 8th, counter states, detector samples value RxD. value accepted value that seen least samples. This done noise rejection. value accepted during first time receive circuits reset receiver goes back looking another 1-to-0 transition. This provides rejection false start bits. start proves valid, shifted into input shift register, reception rest frame will proceed. signal load SBUF RB8, will generated only following conditions time final shift pulse generated: either received stop either these conditions met, received frame lost. both conditions met, stop goes into RB8, data bits into SBUF, activated.
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Koninklijke Philips Electronics N.V. 2004. rights reserved.
User manual
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UM10109
P89LPC932A1 User manual
clock write SBUF shift
INTLO INTLO start stop
transmit
clock shift
reset
start
stop receive
002aaa926
Serial Port Mode (only single transmit buffering case shown).
10.12 More about UART Modes
Reception same Mode signal load SBUF RB8, will generated only following conditions time final shift pulse generated. Either received data either these conditions met, received frame lost, set. both conditions met, received data goes into RB8, first data bits into SBUF.
clock write SBUF shift
INTLO INTLO start stop transmit
clock shift
reset
start
stop receive
SMOD0
SMOD0 002aaa927
Serial Port Mode (only single transmit buffering case shown).
10.13 Framing error Modes with
modes behaves following table.
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Koninklijke Philips Electronics N.V. 2004. rights reserved.
User manual
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P89LPC932A1 User manual
when SM2= Modes when Similar Figure with SMOD0 occurs during RB8, before when with SMOD0 occurs Similar during STOP
[28],
Table Mode
PCON.6 (SMOD0)
Occurs during STOP Occurs during STOP Will occur Occurs during STOP
10.14 Break detect
break detected when consecutive bits sensed reported status register (SSTAT). Mode this consists start bit, data bits, stop times. Modes this consists start bit, data bits, stop bit. break detect cleared software reset. break detect used reset device force device into mode. This occurs UART enabled EBRR (AUXR1.6) break occurs.
10.15 Double buffering
UART transmit double buffer that allows buffering next character written SBUF while first character being transmitted. Double buffering allows transmission string characters with only stop between characters, provided next character written between start stop previous character. Double buffering disabled. disabled (DBMOD, i.e. SSTAT.7 UART compatible with conventional 80C51 UART. enabled, UART allows writing SnBUF while previous data being shifted out.
10.16 Double buffering different modes
Double buffering only allowed Modes When operated Mode double buffering must disabled (DBMOD
10.17 Transmit interrupts with double buffering enabled (Modes
Unlike conventional UART, when double buffering enabled, interrupt generated when double buffer ready receive data. following occurs during transmission (assuming eight data bits): double buffer empty initially. writes SBUF. SBUF data loaded shift register interrupt generated immediately. there more data, else continue. there more data, then: DBISEL logic more interrupts will occur.
9397 13858 Koninklijke Philips Electronics N.V. 2004. rights reserved.
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P89LPC932A1 User manual
DBISEL logic INTLO logic interrupt will occur beginning STOP data currently shifter (which also last data). DBISEL logic INTLO logic interrupt will occur STOP data currently shifter (which also last data). Note that DBISEL logic writing SBUF when STOP last data shifted out, there uncertainty whether interrupt generated already with UART knowing whether there more data following. there more data, writes SBUF again. Then: INTLO logic data will loaded interrupt will occur beginning STOP data currently shifter. INTLO logic data will loaded interrupt will occur STOP data currently shifter.
write SBUF interrupt single buffering (DBMOD/SSTAT.7 early interrupt (INTLO/SSTAT.6 shown
write SBUF interrupt double buffering (DBMOD/SSTAT.7 early interrupt (INTLO/SSTAT.6 shown, ending interrupt (DBISEL/SSTAT.4
write SBUF interrupt double buffering (DBMOD/SSTAT.7 early interrupt (INTLO/SSTAT.6 shown, with ending interrupt (DBISEL/SSTAT.4
002aaa928
Transmission with without double buffering.
10.18 (bit double buffering (Modes
double buffering disabled (DBMOD, i.e. SSTAT.7 written before after SBUF written, provided updated before that shifted out. must changed again until after shifting been completed, indicated interrupt.
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Koninklijke Philips Electronics N.V. 2004. rights reserved.
User manual
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P89LPC932A1 User manual
double buffering enabled, MUST updated before SBUF written, will double-buffered together with SBUF data. operation described Section 10.17 "Transmit interrupts with double buffering enabled (Modes page becomes follows: double buffer empty initially. writes TB8. writes SBUF. SBUF/TB8 data loaded shift register interrupt generated immediately. there more data, else continue there more data, then: DBISEL logic more interrupt will occur. DBISEL logic INTLO logic interrupt will occur beginning STOP data currently shifter (which also last data). DBISEL logic INTLO logic interrupt will occur STOP d
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