P89LPC924/925 User manual Rev. March 2005 User manual Docume
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UM10108
P89LPC924/925 User manual
Rev. March 2005 User manual
Document information Info Keywords Abstract Content P89LPC924, P89LPC925 Technical information P89LPC924 P89LPC925 devices.
Philips Semiconductors
UM10108
P89LPC924/925 User manual
Revision history Date 20050302 20040628 Description Updated include information. Initial version (9397 13338).
Contact information
additional information, please visit: sales office addresses, please send email
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P89LPC924/925 User manual
Introduction
P89LPC924/925 single-chip microcontrollers designed applications demanding high-integration, cost solutions over wide range performance requirements. P89LPC924/925 based high performance processor architecture that executes instructions four clocks, times rate standard 80C51 devices. Many system-level functions have been incorporated into P89LPC924/925 order reduce component count, board space, system cost.
Configuration
handbook, halfpage
KBI0/CMP2/P0.0 P1.7 P1.6
P0.1/CIN2B/KBI1/AD10 P0.2/CIN2A/KBI2/AD11 P0.3/CIN1B/KBI3/AD12
XTAL1/P3.1 CLKOUT/XTAL2/P3.0 INT1/P1.4 SDA/INT0/P1.3 SCL/T0/P1.2
P89LPC924FDH P89LPC925FDH
RST/P1.5
P0.4/CIN1A/KBI4/AD13/DAC1 P0.5/CMPREF/KBI5 P0.6/CMP1/KBI6 P0.7/T1/KBI7 P1.0/TXD P1.1/RXD
002aaa787
TSSOP20 configuration.
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Table Symbol
description Type Description Port Port 8-bit port with user-configurable output type. During reset Port latches configured input only mode with internal pull-up disabled. operation Port pins inputs outputs depends upon port configuration selected. Each port configured independently. Refer Section "Port configurations" details. Keypad Interrupt feature operates with Port pins. pins have Schmitt triggered inputs. Port also provides various special functions described below: P0.0 Port CMP2 Comparator output. KBI0 Keyboard input P0.1 Port CIN2B Comparator positive input KBI1 Keyboard input AD10 ADC1 channel analog input. P0.2 Port CIN2A Comparator positive input KBI2 Keyboard input AD11 ADC1 channel 1analog input. P0.3 Port CIN1B Comparator positive input KBI3 Keyboard input AD12 ADC1 channel analog input. P0.4 Port CIN1A Comparator positive input KBI4 Keyboard input AD13 ADC1 channel analog input. DAC1 Digital-to-analog converter output P0.5 Port CMPREF Comparator reference (negative) input. KBI5 Keyboard input P0.6 Port CMP1 Comparator output. KBI6 Keyboard input P0.7 Port Timer/counter external count input overflow output. KBI7 Keyboard input
P0.0 P0.7
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P89LPC924/925 User manual
Table Symbol
description Type I/O,
Description Port Port 8-bit port with user-configurable output type, except three pins noted below. During reset Port latches configured input only mode with internal pull-up disabled. operation configurable Port pins inputs outputs depends upon port configuration selected. Each configurable port pins programmed independently. Refer Section "Port configurations" details. P1.2 P1.3 open drain when used outputs. P1.5 input only. pins have Schmitt triggered inputs. Port also provides various special functions described below:
P1.0 P1.7
P1.0 Port Transmitter output serial port. P1.1 Port Receiver input serial port. P1.2 Port (open-drain when used output). Timer/counter external count input overflow output (open-drain when used output). serial clock input/output. P1.3 Port (open-drain when used output). INT0 External interrupt input. serial data input/output. P1.4 Port INT1 External interrupt input. P1.5 Port (input only). External Reset input selected FLASH configuration). this resets microcontroller, causing ports peripherals take their default states, processor begins execution address When using oscillator frequency above MHz, reset input function P1.5 must enabled. external circuit required hold device reset powerup until reached specified level. When system power removed will fall below minimum specified operating voltage. When using oscillator frequency above MHz, some applications, external brownout detect circuit required hold device reset when falls below minimum specified operating voltage. P1.6 Port P1.7 Port
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Table Symbol
description Type Description Port Port 2-bit port with user-configurable output type. During reset Port latches configured input only mode with internal pull-up disabled. operation Port pins inputs outputs depends upon port configuration selected. Each port configured independently. Refer Section "Port configurations" details. pins have Schmitt triggered inputs. Port also provides various special functions described below: P3.0 Port XTAL2 Output from oscillator amplifier (when crystal oscillator option selected FLASH configuration. CLKOUT clock divided when enabled (ENCLK TRIM.6). used clock internal oscillator, Watchdog oscillator external clock input, except when XTAL1/XTAL2 used generate clock source real time clock/system timer. P3.1 Port XTAL1 Input oscillator circuit internal clock generator circuits (when selected FLASH configuration). port internal oscillator Watchdog oscillator used clock source, XTAL1/XTAL2 used generate clock real time clock/system timer. Ground: reference. Power Supply: This power supply voltage normal operation well Idle Power-down modes.
P3.0 P3.1
Input/Output P1.0 P1.4, P1.6, P1.7. Input P1.5.
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P89LPC924/925
HIGH PERFORMANCE ACCELERATED 2-CLOCK 80C51
kB/8 CODE FLASH INTERNAL 256-BYTE DATA PORT CONFIGURABLE I/Os PORT CONFIGURABLE I/Os PORT CONFIGURABLE I/Os
UART
REAL-TIME CLOCK/ SYSTEM TIMER
TIMER TIMER WATCHDOG TIMER OSCILLATOR
KEYPAD INTERRUPT
ANALOG COMPARATORS
PROGRAMMABLE OSCILLATOR DIVIDER
CLOCK ON-CHIP OSCILLATOR
ADC1/DAC1
CRYSTAL RESONATOR
CONFIGURABLE OSCILLATOR
POWER MONITOR (POWER-ON RESET, BROWNOUT RESET)
002aaa786
P89LPC924/925 block diagram.
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Special function registers
Remark: Special Function Registers (SFRs) accesses restricted following ways:
User must attempt access locations defined. Accesses defined locations must strictly functions SFRs. bits labeled `-', only written read follows:
Unless otherwise specified, must written with `0', return value when read (even written with `0'). reserved used future derivatives. must written with `0', will return when read. must written with `1', will return when read.
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Table Special function registers indicates SFRs that addressable. Name Description functions addresses addr. address ACC* ADCON1 ADINS ADMODA ADMODB AD1BH AD1BL AD1DAT0 AD1DAT1 AD1DAT2 AD1DAT3 AUXR1 BRGR0[2] BRGR1[2] BRGCON CMP1 CMP2 DIVM DPTR FMADRH Accumulator control register input select mode register mode register A/D_1 boundary HIGH register A/D_1 boundary register A/D_1 data register A/D_1 data register A/D_1 data register A/D_1 data register Auxiliary function register register Baud rate generator rate Baud rate generator rate HIGH Baud rate generator control Comparator control register Comparator control register clock divide-by-M control Data pointer bytes) Data pointer HIGH Data pointer Program Flash address HIGH 00000000 00000000 00000000 SBRGS BRGEN CMF1 CMF2 CLKLP EBRR ENT1 ENT0 SRST 00[1] 00[1] 00000000 00000000 00000000 address ENBI1 ADI13 BNDI1 CLK2 ENADCI ADI12 BURST1 CLK1 TMM1 ADI11 SCC1 CLK0 EDGE1 ADI10 SCAN1 ADCI1 ENDAC1 ENADC1 ADCS11 BSA1 Reset value ADCS10 00[1] 00000000 00000000 00000000 00000000 000x0000 11111111 00000000 00000000 00000000 00000000 00000000 000000x0 Binary
P89LPC924/925 User manual
xxxxxx00 xx000000 xx000000 00000000
UM10108
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Table Special function registers indicates SFRs that addressable. Name FMADRL FMCON Description Program Flash address Program Flash control (Read) Program Flash control (Write) FMDATA I2ADR I2CON* I2DAT I2SCLH
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functions addresses addr. address address address address STA.4 PADH STA.3 EWDRT PWDRT PWDRT PSTH STA.2 PBOH STA.1 ES/ESR PS/PSR PSH/ PSRH STA.0 PT1H PX1H EKBI PT0H PKBI PKBIH PATN _SEL I2ADR.6 I2ADR.5 I2EN I2ADR.4 I2ADR.3 I2ADR.2 I2ADR.1 I2ADR.0 BUSY FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. FMCMD.
Reset value FMCMD. CRSEL EI2C PX0H PI2C PI2CH KBIF 00[1] 00[1] 00[1] 00x00000 00x00000 xxxxxx00 00000000 11111111 00[1] 00[1] x0000000 x0000000 00[1] 00x00000 00[1] 00000000 x00000x0 00000000 00000000 11111000 00000000 00000000 Binary 00000000 01110000
Program Flash data slave address register control register data register
address
Serial clock generator/SCL duty cycle register HIGH Serial clock generator/SCL duty cycle register status register Interrupt enable Interrupt enable Interrupt priority Interrupt priority HIGH
I2SCLL I2STAT IEN0* IEN1* IP0* IP0H
P89LPC924/925 User manual
IP1* IP1H KBCON KBMASK KBPATN
Interrupt priority Interrupt priority HIGH Keypad control register Keypad interrupt mask register Keypad pattern register
UM10108
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Table Special function registers indicates SFRs that addressable. Name Description functions addresses addr. address Port address Port address P0M1 P0M2 P1M1 P1M2 P3M1 P3M2 PCON PCONA PSW* PT0AD RSTSRC RTCCON
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Reset value CIN1A /KB4 INT1 CIN1B /KB3 INT0/ CIN2A /KB2 T0/SCL CIN2B /KB1 XTAL1 CMP2 /KB0 XTAL2
Binary
T1/KB7
CMP1 /KB6
CMPREF /KB5
Port Port output mode Port output mode Port output mode Port output mode Port output mode Port output mode Power control register Power control register Program status word Port digital input disable Reset source register Real-time clock control Real-time clock register Serial port address register Serial port address enable Serial Port data buffer register Serial port control
address address
(P0M1.7) (P0M1.6) (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M1.0) (P0M2.7) (P0M2.6) (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) (P0M2.0) (P1M1.7) (P1M1.6) (P1M2.7) (P1M2.6) SMOD1 RTCPD RTCF SMOD0 RTCS1 BOPD VCPD RTCS0 (P1M1.4) (P1M1.3) (P1M1.2) (P1M1.1) (P1M1.0) (P1M2.4) (P1M2.3) (P1M2.2) (P1M2.1) (P1M2.0) ADPD I2PD R_BK R_WD (P3M1.1) (P3M1.0) PMOD1 R_SF ERTC PMOD0 R_EX RTCEN 60[1][6] 00[6] 00[6] SM0/FE D3[1] 00[1] 03[1] 00[1]
11111111 00000000 11x1xx11 00x0xx00 xxxxxx11 xxxxxx00 00000000 00000000 00000000 xx00000x
(P3M2.1) (P3M2.0) 00[1]
PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2 PT0AD.1
P89LPC924/925 User manual
RTCH RTCL SADDR SADEN SBUF
Real-time clock register HIGH
00000000 00000000 00000000 00000000 xxxxxxxx
UM10108
SCON*
00000000
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Table Special function registers indicates SFRs that addressable. Name SSTAT TAMOD TCON* TMOD TRIM WDCON WFEED1 WFEED2
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Description Serial port extended status register Stack pointer Timer auxiliary mode Timer control Timer HIGH Timer HIGH Timer Timer Timer mode Internal oscillator trim register Watchdog control register Watchdog load Watchdog feed Watchdog feed
functions addresses addr. T1GATE RCCLK PRE2 T1C/T ENCLK PRE1 T1M1 TRIM.5 PRE0 T1M0 TRIM.4 T0GATE TRIM.3 T0C/T TRIM.2 WDRUN T0M1 TRIM.1 WDTOF T1M2 DBMOD INTLO CIDIS DBISEL
Reset value STINT T0M2 T0M0 TRIM.0 WDCLK 00000000 00000000 00000000 00000000 00000000 00000000
Binary 00000000 00000111 xxx0xxx0
address
11111111
ports input only (high-impedance) state after power-up. BRGR1 BRGR0 must only written BRGEN BRGCON logic written while BRGEN result unpredictable. RSTSRC register reflects cause P89LPC924/925 reset. Upon power-up reset, reset source flags cleared except BOF; power-on reset value xx110000. After reset, value 111001x1, i.e., PRE2-PRE0 logic WDRUN WDCLK WDTOF logic after Watchdog reset logic after power-on reset. Other resets will affect WDTOF. power-on reset, TRIM initialized with factory preprogrammed value. Other resets will cause initialization TRIM register. only reset source that affects these SFRs power-on reset.
P89LPC924/925 User manual
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Memory organization
Read-protected calls only entrypoints
IDATA routines FFEFh FF1Fh FF00h
FF00h FFEFh
entry points for: ASM. code code
entry points
SPECIAL FUNCTION REGISTERS (DIRECTLY ADDRESSABLE)
IDATA (incl. DATA)
BYTES ON-CHIP DATA MEMORY (STACK INDIR. ADDR.)
DATA
1FFFh 1E00h 1C00h 1BFFh 1800h 17FFh 1400h 13FFh 1000h 0FFFh 0C00h 0BFFh 0800h 07FFh 0400h 03FFh 0000h
CODE (512B)* SECTOR SECTOR SECTOR SECTOR SECTOR SECTOR SECTOR SECTOR
serial loader
1FFFh
entry points for: -UART (auto-baud) -I2C, SPI, etc.* Flexible choices: supplied (UART) -Philips libraries* -user-defined
BYTES ON-CHIP DATA MEMORY (STACK, DIRECT INDIR. ADDR.) REG. BANKS R[7:0]
1E00h
data memory (DATA, IDATA)
002aaa948
Note: code located Sector LPC924, Sector LPC925.
P89LPC924/925 memory map.
various P89LPC924/925 memory spaces follows: DATA bytes internal data memory space (00h:7Fh) accessed direct indirect addressing, using instruction other than MOVX MOVC. part Stack this area. IDATA Indirect Data. bytes internal data memory space (00h:FFh) accessed indirect addressing using instructions other than MOVX MOVC. part Stack this area. This area includes DATA area bytes immediately above Special Function Registers. Selected registers peripheral control status registers, accessible only direct addressing. CODE Code memory space, accessed part program execution MOVC instruction. P89LPC924/925 kB/8 on-chip Code memory.
Table Type DATA IDATA Data arrangement Data Directly indirectly addressable memory Indirectly addressable memory Size (bytes)
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Clocks
Enhanced
P89LPC924/925 uses enhanced 80C51 which runs times speed standard 80C51 devices. machine cycle consists clock cycles, most instructions execute machine cycles.
Clock definitions
P89LPC924/925 device several internal clocks defined below: OSCCLK Input DIVM clock divider. OSCCLK selected from four clock sources also optionally divided slower frequency (see Figure Section "CPU Clock (CCLK) modification: DIVM register"). Note: fosc defined OSCCLK frequency. CCLK clock; output DIVM clock divider. There CCLK cycles machine cycle, most instructions executed machine cycles (two four CCLK cycles). RCCLK internal 7.373 oscillator output. PCLK Clock various peripheral devices CCLK/2.
2.2.1 Oscillator Clock (OSCCLK)
P89LPC924/925 provides several user-selectable oscillator options. This allows optimization range needs from high precision lowest possible cost. These options configured when FLASH programmed include on-chip Watchdog oscillator, on-chip oscillator, oscillator using external crystal, external clock source. crystal oscillator optimized low, medium, high frequency crystals covering range from MHz.
2.2.2 speed oscillator option
This option supports external crystal range kHz. Ceramic resonators also supported this configuration.
2.2.3 Medium speed oscillator option
This option supports external crystal range MHz. Ceramic resonators also supported this configuration.
2.2.4 High speed oscillator option
This option supports external crystal range MHz. Ceramic resonators also supported this configuration.When using oscillator frequency above MHz, reset input function P1.5 must enabled. external circuit required hold device reset powerup until reached specified level. When system power removed will fall below minimum specified operating voltage. When using oscillator frequency above MHz, some applications, external brownout detect circuit required hold device reset when falls below minimum specified operating voltage.
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Clock output
P89LPC924/925 supports user-selectable clock output function XTAL2 CLKOUT when crystal oscillator being used. This condition occurs different clock source been selected (on-chip oscillator, Watchdog oscillator, external clock input Real-time Clock using crystal oscillator clock source. This allows external devices synchronize P89LPC924/925. This output enabled ENCLK TRIM register. frequency this clock output that CCLK. clock output needed Idle mode, turned prior entering Idle, saving additional power. Note: reset, TRIM initialized with factory preprogrammed value. Therefore when setting clearing ENCLK bit, user should retain contents bits TRIM register. This done reading contents TRIM register (into example), modifying writing this result back into TRIM register. Alternatively, `ANL direct' `ORL direct' instructions used clear TRIM register.
quartz crystal ceramic resonator P89LPC924/925 XTAL1
XTAL2
002aaa951
Note: oscillator must configured following modes: frequency crystal, medium frequency crystal, high frequency crystal. series resistor required limit crystal drive levels. This especially important frequency crystals (see text).
Using crystal oscillator.
On-chip oscillator option
P89LPC924/925 TRIM register that used tune frequency oscillator. During reset, TRIM value initialized factory pre-programmed value adjust oscillator frequency 7.373 MHz, (Note: initial value better than please refer data sheet behavior over temperature). user applications write TRIM register adjust on-chip oscillator other frequencies. Increasing TRIM value will decrease oscillator frequency.
Table Symbol Reset On-chip oscillator trim register (TRIM address 96h) allocation RCCLK ENCLK TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0
Bits loaded with factory stored value during reset.
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Table
On-chip oscillator trim register (TRIM address 96h) description Symbol TRIM.0 TRIM.1 TRIM.2 TRIM.3 TRIM.4 TRIM.5 ENCLK RCCLK when CCLK/2 output XTAL2 provided crystal oscillator being used. when selects Oscillator output clock (CCLK) Description Trim value. Determines frequency internal oscillator. During reset, these bits loaded with stored factory calibration value. When writing either this register, care should taken preserve current TRIM value reading this register, modifying bits required, writing result this register.
Watchdog oscillator option
Watchdog separate oscillator which frequency kHz. This oscillator used save power when high clock frequency needed.
External clock input option
this configuration, processor clock derived from external source driving XTAL1 P3.1 pin. rate from MHz. XTAL2 P3.0 used standard port clock output. When using oscillator frequency above MHz, reset input function P1.5 must enabled. external circuit required hold device reset powerup until reached specified level. When system power removed will fall below minimum specified operating voltage. When using oscillator frequency above MHz, some applications, external brownout detect circuit required hold device reset when falls below minimum specified operating voltage.
XTAL1 XTAL2
High freq. Med. freq. freq.
ADC1/ DAC1
OSCCLK OSCILLATOR (7.3728 MHz) WATCHDOG OSCILLATOR (400 kHz) PCLK
DIVM
CCLK
TIMER TIMER
BAUD RATE GENERATOR
UART
002aaa790
Block diagram oscillator control.
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Oscillator Clock (OSCCLK) wake-up delay
P89LPC924/925 internal wake-up timer that delays clock until stabilizes depending clock source used. clock source three crystal selections, delay OSCCLK cycles plus clock source either internal oscillator Watchdog oscillator, delay OSCCLK cycles plus
Clock (CCLK) modification: DIVM register
OSCCLK frequency divided down, integer, times configuring dividing register, DIVM, provide CCLK. This produces CCLK frequency using following formula: CCLK frequency fosc (2N) Where: fosc frequency OSCCLK value DIVM. Since ranges from 255, CCLK frequency range fosc fosc/510. (for CCLK fosc). This feature makes possible temporarily lower rate, reducing power consumption. dividing clock, retain ability respond events other than those that cause interrupts (i.e., events that allow exiting Idle mode) executing normal program lower rate. This often result lower power consumption than Idle mode. This allow bypassing oscillator start-up time cases where Power-down mode would otherwise used. value DIVM changed program time without interrupting code execution.
power select
P89LPC924/925 designed (CCLK) maximum. However, CCLK slower, CLKLP (AUXR1.7) logic lower power consumption further. reset, CLKLP logic allowing highest performance. This then software CCLK running slower.
converter
P89LPC924/925 8-bit, 4-channel, multiplexed successive approximation analog-to-digital converter module (ADC1) module (DAC1). block diagram converter shown Figure consists 4-input multiplexer which feeds sample hold circuit providing input signal comparator inputs. control logic combination with successive approximation register (SAR) drives digital-to-analog converter which provides other input comparator. output comparator SAR.
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COMP INPUT CONTROL LOGIC
DAC1
CCLK
002aaa791
converter block diagram.
Features 8-bit, 4-channel, multiplexed input, successive approximation converter Four result registers operating modes
Fixed channel, single conversion mode Fixed channel, continuous conversion mode Auto scan, single conversion mode Auto scan, continuous conversion mode Dual channel, continuous conversion mode Single step mode
Three conversion start modes
Timer triggered start Start immediately Edge triggered
8-bit conversion time clock Interrupt polled operation Boundary limits interrupt output port with high output impedance Clock divider Power-down mode
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operating modes
3.2.1 Fixed channel, single conversion mode
single input channel selected conversion. single conversion will performed result placed result register which corresponds selected input channel (See Table interrupt, enabled, will generated after conversion completes. input channel selected ADINS register. This mode selected setting SCAN1 ADMODA register.
Table Input channels Result registers fixed channel single, auto scan single, autoscan continuous conversion modes. Input channel AD10 AD11 Result register AD1DAT2 AD1DAT3 Input channel AD12 AD13
Result register AD1DAT0 AD1DAT1
3.2.2 Fixed channel, continuous conversion mode
single input channel selected continuous conversion. results conversions will sequentially placed four result registers Table interrupt, enabled, will generated after every four conversions. Additional conversion results will again cycle through four result registers, overwriting previous results. Continuous conversions continue until terminated user. This mode selected setting SCC1 ADMODA register.
3.2.3 Auto scan, single conversion mode
combination four input channels selected conversion setting channel's respective ADINS register. channels converted from order ADINS). single conversion each selected input will performed result placed result register which corresponds selected input channel (See Table interrupt, enabled, will generated after selected channels have been converted. only single channel selected this equivalent single channel, single conversion mode. This mode selected setting SCAN1 ADMODA register.
Table Result registers conversion results fixed channel, continuous conversion mode. Contains Selected channel, first conversion result Selected channel, second conversion result Selected channel, third conversion result Selected channel, forth conversion result
Result register AD1DAT0 AD1DAT1 AD1DAT2 AD1DAT3
3.2.4 Auto scan, continuous conversion mode
combination four input channels selected conversion setting channel's respective ADINS register. channels converted from order ADINS). conversion each selected input will performed result placed result register which corresponds selected input channel (See Table interrupt, enabled, will generated after selected channels have been converted. process will repeat starting with first selected channel. Additional
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conversion results will again cycle through result registers selected channels, overwriting previous results. Continuous conversions continue until terminated user. This mode selected setting BURST1 ADMODA register.
3.2.5 Dual channel, continuous conversion mode
combination four input channels selected conversion. result conversion first channel placed first result register. result conversion second channel placed second result register. first channel again converted result stored third result register. second channel again converted result placed fourth result register (See Table interrupt generated, enabled, after every four conversions (two conversions channel). This mode selected setting SCC1 ADMODA register.
Table Result registers conversion results dual channel, continuous conversion mode. Contains First channel, first conversion result Second channel, first conversion result First channel, second conversion result Second channel, second conversion result
Result register AD1DAT0 AD1DAT1 AD1DAT2 AD1DAT3
3.2.6 Single step
This special mode allows `single-stepping' auto scan conversion mode. combination four input channels selected conversion. After each channel converted, interrupt generated, enabled, waits next start condition. result each channel placed result register which corresponds selected input channel (See Table used with start modes. This mode selected clearing BURST1, SCC1, SCAN1 bits ADMODA register.
3.2.7 Conversion mode selection bits
uses three bits ADMODA select conversion mode. These mode bits summarized Table below. Combinations three bits, other than combinations shown, undefined.
Table Conversion mode bits. Scan1 ADC1 conversion BURST0 SCC0 mode single step fixed channel,single auto scan, single fixed channel, continuous dual channel, continuous auto scan, continuous Scan0 ADC0 conversion mode single step fixed channel,single auto scan, single fixed channel, continuous dual channel, continuous auto scan, continuous
BURST1 SCC1
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Trigger modes
3.3.1 Timer triggered start
conversion started overflow Timer Once conversion started, additional Timer triggers ignored until conversion completed. Timer triggered start mode available operating modes. This mode selected TMM1 ADCS11 ADCS10 bits (See Table 11).
3.3.2 Start immediately
Programming this mode immediately starts conversion. This start mode available operating modes. This mode selected setting ADCS11 ADCS10 bits ADCON1 register (See Table 11).
3.3.3 Edge triggered
conversion started rising falling edge P1.4. Once conversion started, additional edge triggers ignored until conversion completed. edge triggered start mode available operating modes. This mode selected setting ADCS11 ADCS10 bits ADCON1 register (See Table 11).
3.3.4 Boundary limits interrupt
converter both HIGH boundary limit register. After four MSBs have been converted, these four bits compared with four MSBs boundary HIGH registers. four MSBs conversion outside limit interrupt will generated, enabled. conversion result within limits, boundary limits will again compared after eight bits have been converted. interrupt will generated, enabled, result outside boundary limits. boundary limit disabled clearing boundary limit interrupt enable.
output port with high-impedance
AD0DAT3 register used hold value DAC. After value been written AD0DAT3 output will appear DAC0 pin. output enabled ENDAC0 ADMODB register (See Table 15).
Clock divider
converter requires that internal clock source range maintain accuracy. programmable clock divider that divides clock from provided this purpose (See Table 15).
pins used with converter functions
analog input pins used with converter have digital input output function. order give best analog performance, pins that being used with should have their digital outputs inputs disabled have tolerance disconnected. Digital outputs disabled putting port pins into input-only mode described Port Configurations section (see Table 21).
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Digital inputs will disconnected automatically from these pins when been selected setting corresponding ADINS register been enabled. Pins selected ADINS will tolerant provided that enabled device power-down, otherwise will remain tolerant.
Power-down idle mode
idle mode converter, enabled, will continue function cause device exit idle mode when conversion completed interrupt enabled. Power-down mode Total Power-down mode, does function. enabled, will consume power. Power reduced disabling A/D.
Table Symbol Reset Table Control register (ADCON1 address 97h) allocation ENBI1 ENADCI1 TMM1 EDGE1 ADCI1 ENADC1 ADCS11 ADCS10
Control register (ADCON1 address 97h) description Symbol ADCS10 ADCS11 Description start mode bits [11:10]: Timer Trigger Mode when TMM1 Conversions starts overflow Timer Stop mode when TMM1 start occurs. Immediate Start Mode. Conversions starts immediately. Edge Trigger Mode. Conversion starts when edge condition defined EDGE1 occurs.
ENADC1 ADCI1 EDGE1 TMM1 ENADCI1 ENBI1
Enable channel When enables ADC1. Must also operation this channel. Conversion complete Interrupt when conversion multiple conversions completed. Cleared software. When Edge conversion start triggered falling edge P1.4. When Edge conversion start triggered rising edge P1.4. Timer Trigger Mode Selects either stop mode (TMM1 timer trigger mode (TMM1 when ADCS11 ADCS10 bits Enable Conversion complete Interrupt When set, will cause interrupt ADCI1 flag interrupt enabled. Enable boundary interrupt When set, will cause interrupt boundary interrupt flag, BNDI1, interrupt enabled.
Table Symbol Reset Table
Mode Register (ADMODA address C0h) allocation BNBI1 BURST1 SCC1 SCAN1
Mode Register (ADMODA address C0h) description Symbol SCAN1 Description reserved when selects single conversion mode (auto scan fixed channel) ADC1
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Table
Mode Register (ADMODA address C0h) description Symbol SCC1 BURST1 BNBI1 Description when selects fixed channel, continuous conversion mode ADC1 when selects auto scan, continuous conversion mode ADC1 ADC1 boundary interrupt flag. When set, indicates that converted result from ADC1 outside range defined ADC1 boundary registers
Table Symbol Reset Table
Mode Register (ADMODB address A1h) allocation CLK2 CLK1 CLK0 ENDAC1 BSA1
Mode Register (ADMODB address A1h) description Symbol BSA1 Description reserved ADC1 Boundary Select All. When BNDI1 will ADC1 input exceeds boundary limits. When BNDI1 will only AD10 input exceeded boundary limits. reserved When selects mode ADC1; when selects mode. reserved Clock divider produce clock. Divides CCLK value indicated below. resulting clock should less. minimum required maintain accuracy. start mode bits: CLK2:0 divisor
ENDAC1 CLK0 CLK1 CLK2
Table Symbol Reset Table
User manual
Input Select register (ADINS address A3h) allocation AIN13 AIN12 AIN11 AIN10
Input Select register (ADINS address A3h) description Symbol AIN10 AIN11 AIN12 AIN13 Description reserved when set, enables AD10 sampling conversion when set, enables AD11 sampling conversion when set, enables AD12 sampling conversion when set, enables AD13 sampling conversion
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Interrupts
P89LPC924/925 uses four priority level interrupt structure. This allows great flexibility controlling handling P89LPC924/925's interrupt sources. Each interrupt source individually enabled disabled setting clearing interrupt enable registers IEN0 IEN1. IEN0 register also contains global enable bit, which enables interrupts. Each interrupt source individually programmed four priority levels setting clearing bits interrupt priority registers IP0, IP0H, IP1, IP1H. interrupt service routine progress interrupted higher priority interrupt, another interrupt same lower priority. highest priority interrupt service cannot interrupted other interrupt source. requests different priority levels received simultaneously, request higher priority level serviced. requests same priority level pending start instruction cycle, internal polling sequence determines which request serviced. This called arbitration ranking. Note that arbitration ranking only used pending requests same priority level. Table summarizes interrupt sources, flag bits, vector addresses, enable bits, priority bits, arbitration ranking, whether each interrupt wake from Power-down mode.
Interrupt priority structure
Table IPxH Interrupt priority level Interrupt priority level Level (lowest priority) Level Level Level Priority bits
There four SFRs associated with four interrupt levels: IP0, IP0H, IP1, IP1H. Every interrupt bits IPxH 0,1) therefore assigned four levels, shown Table P89LPC924/925 external interrupt inputs addition Keypad Interrupt function. interrupt inputs identical those present standard 80C51 microcontrollers. These external interrupts programmed level-triggered edge-triggered clearing setting Register TCON. external interrupt triggered level detected INTn pin. external interrupt edge triggered. this mode consecutive samples INTn show HIGH level cycle level next cycle, interrupt request flag TCON set, causing interrupt request. Since external interrupt pins sampled once each machine cycle, input HIGH level should held least machine cycle ensure proper sampling. external interrupt edge-triggered, external source hold request HIGH
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least machine cycle, then hold least machine cycle. This ensure that transition detected that interrupt request flag set. automatically cleared when service routine called. external interrupt level-triggered, external source must hold request active until requested interrupt generated. external interrupt still asserted when interrupt service routine completed, another interrupt will generated. necessary clear interrupt flag when interrupt level sensitive, simply tracks input level. external interrupt been programmed level-triggered enabled when P89LPC924/925 into Power-down Idle mode, interrupt occurrence will cause processor wake resume operation. Refer Section "Power reduction modes" page details.
External Interrupt glitch suppression
Most P89LPC924/925 pins have glitch suppression circuits reject short glitches (please refer P89LPC924/925 data sheet, Dynamic characteristics glitch filter specifications). However, pins SDA/INT0/P1.3 SCL/T0/P1.2 have glitch suppression circuits. Therefore, INT1 glitch suppression while INT0 does not.
Table Summary interrupts Interrupt flag bit(s) KBIF ADCI1,BNDI1 002Bh 0053h 0033h 003Bh 0043h 006Bh 0073h (IEN0.5) EWDRT (IEN0.6) EI2C (IEN1.0) EKBI (IEN1.1) (IEN1.2) (IEN1.6) (IEN1.7) IP0H.5,IP0.5 IP0H.6,IP0.6 IP0H.0,IP0.0 IP0H.0,IP0.0 IP0H.0,IP0.0 IP0H.0,IP0.0 IP1H.7,IP1.7 (lowest) Vector address 0003h 000Bh 0013h 001Bh 0023h Interrupt enable bit(s) (IEN0.0) (IEN0.1) (IEN0.2) (IEN0.3) ES/ESR (IEN0.4) Interrupt priority IP0H.0,IP0.0 IP0H.1,IP0.1 IP0H.2,IP0.2 IP0H.3,IP0.3 IP0H.4,IP0.4 Arbitration Powerranking down wake-up (highest)
Description
External interrupt Timer interrupt External interrupt Timer interrupt Serial port Serial port Brownout detect interrupt
Watchdog timer/Real-time clock WDOVF/RTCF interrupt Serial port
Comparators interrupts CMF1/CMF2
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BOPD RTCF ERTC (RTCCON.1) WDOVF KBIF EKBI EWDRT CMF2 CMF1 (IE0.7) RI/RI ES/ESR EI2C ENADCI1 ADCI1 ENBI1 BNDI1
002aaa792
WAKE-UP POWER-DOWN)
INTERRUPT
Interrupt sources, interrupt enables, power-down wake sources.
ports
P89LPC924/925 three ports: Port Port Port Ports 8-bit ports Port 2-bit port. exact number pins available depends upon clock reset options chosen (see Table 20).
Table Number pins available Reset option Number pins
Clock source On-chip oscillator Watchdog oscillator External clock input
external reset (except during power External supported External supported[1] external reset (except during power
Low/medium/high speed oscillator external reset (except during power (external crystal resonator) External supported[1]
Required operation above MHz.
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Port configurations
three port pins P89LPC924/925 configured software four types pin-by-pin basis, shown Table These are: quasi-bidirectional (standard 80C51 port outputs), push-pull, open drain, input-only. configuration registers each port select output type each port pin. P1.5 (RST) only input cannot configured. P1.2 (SCL/T0) P1.3 (SDA/INT0) only configured either input-only open drain.
Table PxM1.y Port output configuration settings PxM2.y Port output mode Quasi-bidirectional Push-pull Input only (high-impedance) Open drain
Quasi-bidirectional output configuration
Quasi-bidirectional outputs used both input output without need reconfigure port. This possible because when port outputs logic HIGH, weakly driven, allowing external device pull LOW. When driven LOW, driven strongly able sink large current. There three pull-up transistors quasi-bidirectional output that serve different purposes. these pull-ups, called `very weak' pull-up, turned whenever port latch contains logic This very weak pull-up sources very small current that will pull HIGH left floating. second pull-up, called `weak' pull-up, turned when port latch contains logic itself also logic level. This pull-up provides primary source current quasi-bidirectional that outputting this pulled external device, weak pull-up turns off, only very weak pull-up remains order pull under these conditions, external device sink enough current overpower weak pull-up pull port below input threshold voltage. third pull-up referred `strong' pull-up. This pull-up used speed LOW-to-HIGH transitions quasi-bidirectional port when port latch changes from logic logic When this occurs, strong pull-up turns clocks quickly pulling port HIGH. quasi-bidirectional port configuration shown Figure Although P89LPC924/925 device most pins V-tolerant. applied configured quasi-bidirectional mode, there will current flowing from causing extra power consumption. Therefore, applying pins configured quasi-bidirectional mode discouraged. quasi-bidirectional port Schmitt triggered input that also glitch suppression circuit.
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(Please refer P89LPC924/925 data sheet, Dynamic characteristics glitch filter specifications).
CLOCK DELAY strong very weak
weak
port latch data
port
input data glitch rejection
002aaa914
Quasi-bidirectional output.
Open drain output configuration
open drain output configuration turns pull-ups only drives pull-down transistor port when port latch contains logic used logic output, port configured this manner must have external pull-up, typically resistor tied VDD. pull-down this mode same quasi-bidirectional mode. open drain port configuration shown Figure open drain port Schmitt triggered input that also glitch suppression circuit. Please refer P89LPC924/925 data sheet, Dynamic characteristics glitch filter specifications.
port latch data
port
input data glitch rejection
002aaa915
Open drain output.
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Input-only configuration
input port configuration shown Figure Schmitt triggered input that also glitch suppression circuit. (Please refer P89LPC924/925 data sheet, Dynamic characteristics glitch filter specifications).
input data glitch rejection
port
002aaa916
Input only.
Push-pull output configuration
push-pull output configuration same pull-down structure both open drain quasi-bidirectional output modes, provides continuous strong pull-up when port latch contains logic push-pull mode used when more source current needed from port output. push-pull port configuration shown Figure push-pull port Schmitt triggered input that also glitch suppression circuit. (Please refer P89LPC924/925 data sheet, Dynamic characteristics glitch filter specifications).
strong
port latch data
port
input data
glitch rejection
002aaa917
Push-pull output.
Port analog functions
P89LPC924/925 incorporates Analog Comparators. order give best analog performance minimize power consumption, pins that being used analog functions must have both digital outputs digital inputs disabled.
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Digital outputs disabled putting port pins into input-only mode described Port Configurations section (see Figure 10). Digital inputs Port disabled through PT0AD register. Bits through this register correspond pins P0.1 through P0.5 Port respectively. Setting corresponding PT0AD disables that pin's digital input. Port bits that have their digital inputs disabled will read logic instruction that accesses port. reset, PT0AD bits through default logic enable digital functions.
Additional port features
After power-up, pins Input-Only mode. Please note that this different from LPC76x series devices.
After power-up, pins except P1.5, configured software. P1.5 input only. Pins P1.2 P1.3 configurable either input-only
open drain. Every output P89LPC924/925 been designed sink typical drive current. However, there maximum total output current ports which must exceeded. Please refer P89LPC924/925 data sheet detailed specifications. ports pins that function output have slew rate controlled outputs limit noise generated quickly switching output signals. slew rate factory-set approximately rise fall times.
Table Port P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 Port output configuration Configuration bits PxM1.y P0M1.0 P0M1.1 P0M1.2 P0M1.3 P0M1.4 P0M1.5 P0M1.6 P0M1.7 P1M1.0 P1M1.1 P1M1.2 P1M1.3 P1M1.4 P1M1.5 P1M1.6 PxM2.y P0M2.0 P0M2.1 P0M2.2 P0M2.3 P0M2.4 P0M2.5 P0M2.6 P0M2.7 P1M2.0 P1M2.1 P1M2.2 P1M2.3 P1M2.4 P1M2.5 P1M2.6 Alternate usage KBIO, CMP2 KBI1, CIN2B, AD10 Refer Section "Port KBI2, CIN2A, AD11 analog functions" usage analog inputs. KBI3, CIN1B, AD12 KBI4, CIN1A, AD13, DAC1 KBI5, CMPREF KBI6, CMP1 KBI7, INTO, INT1 Input-only open-drain input-only open-drain Notes
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Port output configuration Configuration bits PxM1.y PxM2.y P1M2.7 P3M2.0 P3M2.1 CLKOUT, XTAL2 XTAL1 Alternate usage Notes P1M1.7 P3M1.0 P3M1.1
Table Port P1.7 P3.0 P3.1
Power monitoring functions
P89LPC924/925 incorporates power monitoring functions designed prevent incorrect operation during initial power-on power loss reduction during operation. This accomplished with hardware functions: Power-on Detect Brownout Detect.
Brownout detection
Brownout Detect function determines power supply voltage drops below certain level. default operation Brownout Detection cause processor reset. However, alternatively configured generate interrupt setting (PCON.4) (IEN0.5) bit. Enabling disabling Brownout Detection done BOPD (PCON.5) bit, field PMOD1-0 (PCON.1-0) user configuration (UCFG1.5). unprogrammed state, brownout disabled regardless PMOD1-0 BOPD. programmed state, PMOD1-0 BOPD will used determine whether Brownout Detect will disabled enabled. PMOD1-0 used select power reduction mode. PMOD1-0 `11', circuitry Brownout Detection disabled lowest power consumption. BOPD defaults logic indicating brownout detection enabled power-on programmed. Brownout Detection enabled, brownout condition occurs when falls below Brownout trip voltage, (see P89LPC924/925 Static Characteristics), negated when rises above VBO. P89LPC924/925 device operate with power supply that below should left unprogrammed state that device operate otherwise continuous brownout reset prevent device from operating. Brownout Detect enabled (BOE programmed, PMOD1-0 `11', BOPD (RSTSRC.5) will when brownout detected, regardless whether reset interrupt enabled. will stay until cleared software writing logic bit. Note that unprogrammed, meaningless. programmed, initial power-on occurs, will addition power-on flag (POF RSTSRC.4). correct activation Brownout Detect, certain rise fall times must observed. Please data sheet specifications.
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Table (UCFG1.5) (erased) 1(program med)
Brownout options[1] PMOD1-0 (PCON.1-0) (total power-down) (any mode other than total power-down BOPD (PCON.5) 1(brownout detect powered down) (brownout detect active) (PCON.4) (IEN0.5) (IEN0.7) Description Brownout disabled. operating range Brownout disabled. operating range However, BOPD default logic upon power-up. Brownout reset enabled. operating range Upon brownout reset, (RSTSRC.5) will indicate reset source. cleared writing logic bit. Brownout interrupt enabled. operating range Upon brownout interrupt, (RSTSRC.5) will set. cleared writing logic bit. Both brownout reset interrupt disabled. operating range However, (RSTSRC.5) will when falls Brownout Detection trip point. cleared writing logic bit.
(brownout detect generates reset)
(brownout detect generates interrupt)
(enable brownout interrupt)
(global interrupt enable)
Cannot used with operation above this requires above.
Power-on detection
Power-On Detect function similar Brownout Detect, designed work power initially comes before power supply voltage reaches level where Brownout Detect function. flag (RSTSRC.4) indicate initial power-on condition. flag will remain until cleared software writing logic bit. Note that (UCFG1.5) programmed, (RSTSRC.5) will when set. unprogrammed, meaningless.
Power reduction modes
P89LPC924/925 supports three different power reduction modes determined bits PCON.1-0 (see Table 24).
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Table
Power reduction modes
PMOD1 PMOD0 Description (PCON.1) (PCON.0) Normal mode (default) power reduction. Idle mode. Idle mode leaves peripherals running order allow them activate processor when interrupt generated. enabled interrupt source reset terminate Idle mode. Power-down mode: Power-down mode stops oscillator order minimize power consumption. P89LPC924/925 exits Power-down mode reset, certain interrupts external pins INT0/INT1, brownout Interrupt, keyboard, Real-time Clock/System Timer), Watchdog, comparator trips. Waking reset only enabled corresponding reset enabled, waking interrupt only enabled corresponding interrupt enabled (IEN0.7) set. External interrupts should programmed level-triggered mode used exit Power-down mode. Power-down mode internal oscillator disabled unless both oscillator been selected system clock enabled. Power-down mode, power supply voltage reduced keep-alive voltage VRAM. This retains contents point where Power-down mode entered. contents guaranteed after been lowered VRAM, therefore recommended wake processor Reset this situation. must raised within operating range before Power-down mode exited. When processor wakes from Power-down mode, will start oscillator immediately begin execution when oscillator stable. Oscillator stability determined counting 1024 clocks after start-up when crystal oscillator configurations used, clocks after start-up internal external clock input configurations. Some chip functions continue operate draw power during Power-down mode, increasing total power used during power-down. These include:
Brownout Detect Watchdog timer WDCLK (WDCON.0) logic Comparators (Note: Comparators powered down separately with PCONA.5 logic comparators disabled) Real-time Clock/System Timer (and crystal oscillator circuitry this block using unless RTCPD, i.e., PCONA.7 logic
Total Power-down mode: This same Power-down mode except that Brownout Detection circuitry voltage comparators also disabled conserve additional power. Note that brownout reset interrupt will occur. Voltage comparator interrupts Brownout interrupt cannot used wake-up source. internal oscillator disabled unless both oscillator been selected system clock enabled. following wake-up options supported:
Watchdog timer WDCLK (WDCON.0) logic Could generate Interrupt Reset, either wake device External interrupts INTO/INT1 (when programmed level-triggered mode) Keyboard Interrupt Real-time Clock/System Timer (and crystal oscillator circuitry this block using unless RTCPD, i.e., PCONA.7 logic
Note: Using internal RC-oscillator clock during power-down result relatively high power consumption. Lower power consumption achieved using external frequency clock when Real-time Clock running during power-down.
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Table Symbol Reset Table
Power Control register (PCON address 87h) allocation SMOD1 SMOD0 BOPD PMOD1 PMOD0
Power Control register (PCON address 87h) description Symbol PMOD0 PMOD1 BOPD General Purpose Flag read written user software, effect operation General Purpose Flag read written user software, effect operation Brownout Detect Interrupt Enable. When logic Brownout Detection will generate interrupt. When logic Brownout Detection will cause reset Brownout Detect power-down. When logic Brownout Detect powered down therefore disabled. When logic Brownout Detect enabled. (Note: BOPD must logic before programming erasing commands issued. Otherwise these commands will aborted.) Framing Error Location: Description Power Reduction Mode (see Section 6.3)
SMOD0
SMOD1
When logic SCON accessed UART When logic SCON accessed framing error status (FE) UART
Double Baud Rate serial port (UART) when Timer used baud rate source. When logic Timer overflow rate supplied UART. When logic Timer overflow rate divided before being supplied UART. (See Section
Table Symbol Reset Table
Power Control register (PCONA address B5h) allocation RTCPD VCPD I2PD
Power Control register (PCONA address B5h) description Symbol Description reserved Serial Port (UART) power-down: When logic internal clock UART disabled. Note that either Power-down mode Total Power-down mode, UART clock will disabled regardless this bit. reserved power-down: When logic internal clock I2C-bus disabled. Note that either Power-down mode Total Power-down mode, clock will disabled regardless this bit. reserved
I2PD
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Table
Power Control register (PCONA address B5h) description Symbol VCPD Description Analog Voltage Comparators power-down: When logic voltage comparators powered down. User must disable voltage comparators prior setting this bit. reserved Real-time Clock power-down: When logic internal clock Real-time Clock disabled.
RTCPD
Reset
P1.5/RST function either active reset input digital input, P1.5. (Reset Enable) UCFG1, when enables external reset input function P1.5. When cleared, P1.5 used input pin. When using oscillator frequency above MHz, reset input function P1.5 must enabled. external circuit required hold device reset powerup until reached specified level. When system power removed will fall below minimum specified operating voltage. When using oscillator frequency above MHz, some applications, external brownout detect circuit required hold device reset when falls below minimum specified operating voltage. NOTE: During power-on sequence, selection overridden this will always functions reset input. external circuit connected this should hold this during Power-on sequence this will keep device reset. After power-on this input will function either external reset input digital input defined bit. Only power-on reset will temporarily override selection defined bit. Other sources reset will override bit. NOTE: During power cycle, must fall below VPOR (see P89LPC924/925 data sheet, Static characteristics) before power reapplied, order ensure power-on reset. Reset triggered from following sources (see Figure 12):
External reset (during power-on user configured UCFG1) Power-on Detect Brownout Detect Watchdog timer Software reset UART break detect reset
every reset source, there flag Reset Register, RSTSRC. user read this register determine most recent reset source. These flag bits cleared software writing logic corresponding bit. More than flag set:
During power-on reset, both other flag bits
cleared.
other reset, previously flag bits that have been cleared will remain
set.
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(UCFG1.6) WDTE (UCFG1.7) Watchdog timer reset Software reset SRST (AUXR1.3) chip reset Power-on detect UART break detect EBRR (AUXR1.6) Brownout detect reset BOPD (PCON.5)
002aaa918
Block diagram reset. Table Symbol Reset[1]
Reset Sources register (RSTSRC address DFh) allocation R_BK R_WD R_SF R_EX
value shown power-on reset. Other reset sources will their corresponding bits.
Table R_EX
Reset Sources register (RSTSRC address DFh) description Description external reset Flag. When this logic indicates external reset. Cleared software writing logic Power-on reset. still asserted after Power-on reset over, R_EX will set. software reset Flag. Cleared software writing logic Power-on reset Watchdog timer reset flag. Cleared software writing logic Power-on reset.(NOTE: UCFG1.7 must break detect reset. break detect occurs EBRR (AUXR1.6) logic system reset will occur. This indicate that system reset caused break detect. Cleared software writing logic Power-on reset. Power-on Detect Flag. When Power-on Detect activated, flag indicate initial power-up condition. flag will remain until cleared software writing logic bit. (Note: Power-on reset, both this will while other flag bits cleared.) Brownout Detect Flag. When Brownout Detect activated, this set. will remain until cleared software writing logic bit. (Note: Power-on reset, both this will while other flag bits cleared.) reserved
Symbol
R_SF R_WD R_BK
Reset vector
Following reset, P89LPC924/925 will fetch instructions from either address 0000h Boot address. Boot address formed using Boot Vector HIGH byte address byte address 00h. Boot address will used
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UART break reset occurs non-volatile Boot Status (BOOTSTAT.0) device been forced into mode. Otherwise, instructions will fetched from address 0000H.
Timers
P89LPC924/925 general-purpose counter/timers which upward compatible with 80C51 Timer Timer Both configured operate either timers event counters (see Table 32). option automatically toggle upon timer overflow been added. `Timer' function, timer incremented every PCLK. `Counter' function, register incremented response 1-to-0 transition corresponding external input T1). external input sampled once during every machine cycle. When HIGH during cycle next cycle, count incremented. count value appears register during cycle following which transition detected. Since takes machine cycles clocks) recognize 1-to-0 transition, maximum count rate clock frequency. There restrictions duty cycle external input signal, ensure that given level sampled least once before changes, should held least full machine cycle. `Timer' `Counter' function selected control bits TnC/T Timers respectively) Special Function Register TMOD. Timer Timer have five operating modes (modes which selected bit-pairs (TnM1, TnM0) TMOD TnM2 TAMOD. Modes same both Timers/Counters. Mode different. operating modes described later this section.
Table Symbol Reset Table T0M0 T0M1 T0C/T Timer/Counter Mode register (TMOD address 89h) allocation T1GATE T1C/T T1M1 T1M0 T0GATE T0C/T T0M1 T0M0
Timer/Counter Mode register (TMOD address 89h) description Description Mode Select Timer These bits used with T0M2 TAMOD register determine Timer mode (see Table 34). Timer Counter selector Timer Cleared Timer operation (input from CCLK). Counter operation (input from input pin).
Symbol
T0GATE Gating control Timer When set, Timer/Counter enabled only while INT0 HIGH control set. When cleared, Timer enabled when control set. T1M0 T1M1 T1C/T Mode Select Timer These bits used with T1M2 TAMOD register determine Timer mode (see Table 34). Timer Counter Selector Timer Cleared Timer operation (input from CCLK). Counter operation (input from input pin).
T1GATE Gating control Timer When set, Timer/Counter enabled only while INT1 HIGH control set. When cleared, Timer enabled when control set.
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Table Symbol Reset Table T0M2
Timer/Counter Auxiliary Mode register (TAMOD address 8Fh) allocation T1M2 T0M2
Timer/Counter Auxiliary Mode register (TAMOD address 8Fh) description Description Mode Select Timer These bits used with T0M2 TAMOD register determine Timer mode (see Table 34). reserved Mode Select Timer These bits used with T1M2 TAMOD register determine Timer mode (see Table 34). following timer modes selected timer mode bits TnM[2:0]: 8048 Timer `TLn' serves 5-bit prescaler. (Mode 16-bit Timer/Counter `THn' `TLn' cascaded; there prescaler.(Mode 8-bit auto-reload Timer/Counter. holds value which loaded into when overflows. (Mode Timer dual 8-bit Timer/Counter this mode. 8-bit Timer/Counter controlled standard Timer control bits. 8-bit timer only, controlled Timer control bits (see text). Timer this mode stopped. (Mode Reserved. User must configure this mode. Reserved. User must configure this mode. mode (see Section 8.5). Reserved. User must configure this mode.
Symbol
T1M2
reserved
Mode
Putting either Timer into Mode makes look like 8048 Timer, which 8-bit Counter with divide-by-32 prescaler. Figure shows Mode operation. this mode, Timer register configured 13-bit register. count rolls over from logic logic sets Timer interrupt flag TFn. count input enabled Timer when either TnGATE INTn (Setting TnGATE allows Timer controlled external input INTn, facilitate pulse width measurements). control Special Function Register TCON (Table 36). TnGATE TMOD register. 13-bit register consists bits lower bits TLn. upper bits indeterminate should ignored. Setting flag (TRn) does clear registers. Mode operation same Timer Timer Figure There different GATE bits, Timer (TMOD.7) Timer (TMOD.3).
Mode
Mode same Mode except that bits timer register (THn TLn) used. Figure
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Mode
Mode configures Timer register 8-bit Counter (TLn) with automatic reload, shown Figure Overflow from only sets TFn, also reloads with contents THn, which must preset software. reload leaves unchanged. Mode operation same Timer Timer
Mode
When Timer Mode stopped. effect same setting Timer Mode establishes separate 8-bit counters. logic Mode Timer shown Figure uses Timer control bits: T0C/T, T0GATE, TR0, INT0, TF0. locked into timer function (counting machine cycles) takes over from Timer Thus, controls `Timer interrupt. Mode provided applications that require extra 8-bit timer. With Timer Mode P89LPC924/925 device look like three Timer/Counters. Note: When Timer Mode Timer turned switching into Mode still used serial port baud rate generator, application requiring interrupt.
Mode
this mode, corresponding timer changed with full period timer clocks (see Figure 17). structure similar mode except that:
Timers respectively) cleared hardware period THn, should between 254, HIGH period always Loading with will force HIGH, loading with will force
Note that interrupt still enabled HIGH transition TFn, that still cleared software like other modes.
Table Symbol Reset Table Timer/Counter Control register (TCON) address 88h) allocation
Timer/Counter Control register (TCON address 88h) description Description Interrupt Type control bit. Set/cleared software specify falling edge/LOW level triggered external interrupts. Interrupt Edge flag. hardware when external interrupt edge detected. Cleared hardware when interrupt processed, software. Interrupt Type control bit. Set/cleared software specify falling edge/LOW level triggered external interrupts.
Symbol
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Table
Timer/Counter Control register (TCON address 88h) description Description Interrupt Edge flag. hardware when external interrupt edge detected. Cleared hardware when interrupt processed, software. Timer control bit. Set/cleared software turn Timer/Counter on/off. Timer overflow flag. hardware Timer/Counter overflow. Cleared hardware when processor vectors interrupt routine, software. (except mode where cleared hardware) Timer control bit. Set/cleared software turn Timer/Counter on/off Timer overflow flag. hardware Timer/Counter overflow. Cleared hardware when interrupt processed, software (except mode above, when cleared hardware).
Symbol
PCLK
control (5-bits) (8-bits)
overflow interrupt
toggle Gate INTn ENTn
002aaa919
Timer/counter Mode (13-bit counter).
PCLK
control (8-bits) (8-bits)
overflow interrupt
toggle Gate INTn ENTn
002aaa920
Timer/counter mode (16-bit counter).
PCLK
control (8-bits) reload
overflow interrupt
toggle
Gate INTn (8-bits)
ENTn
002aaa921
Timer/counter Mode (8-bit auto-reload).
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PCLK
control (8-bits)
overflow toggle interrupt
Gate INT0 ENT0 (AUXR1.4) overflow interrupt (P1.2 open drain)
Osc/2 control
(8-bits)
toggle (P0.7) ENT1 (AUXR1.5)
002aaa922
Timer/counter Mode (two 8-bit counters).
PCLK control (8-bits)
overflow interrupt
reload falling transition (256-THn) rising transition
toggle
Gate INTn (8-bits) ENTn
002aaa923
Timer/counter mode (PWM auto-reload).
Timer overflow toggle output
Timers configured automatically toggle port output whenever timer overflow occurs. same device pins that used count inputs outputs also used timer toggle outputs. This function enabled control bits ENT0 ENT1 AUXR1 register, apply Timer Timer respectively. port outputs will logic prior first timer overflow when this mode turned order this mode function, must cleared selecting PCLK clock source timer.
Real-time clock system timer
P89LPC924/925 simple Real-time Clock/System Timer that allows user continue running accurate timer while rest device powered down. Real-time Clock interrupt wake-up source (see Figure 18).
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Real-time Clock 23-bit down counter. clock source this counter either clock (CCLK) XTAL1-2 oscillator, provided that XTAL1-2 oscillator being used clock. XTAL1-2 oscillator used clock, then will CCLK clock source regardless state RTCS1:0 RTCCON register. There three SFRs used RTC: RTCCON Real-time Clock control. RTCH Real-time Clock counter reload HIGH (bits [22:15]). RTCL Real-time Clock counter reload (bits [14:7]). Real-time clock system timer enabled setting RTCEN (RTCCON.0) bit. Real-time Clock 23-bit down counter (initialized when RTCEN that comprised 7-bit prescaler 16-bit loadable down counter. When RTCEN written with logic counter first loaded with (RTCH, RTCL, `1111111') will count down. When reaches 0's, counter will reloaded again with (RTCH, RTCL, `1111111') flag RTCF (RTCCON.7) will set.
Power-on reset
RTCH
RTCL
Reset
XTAL2
XTAL1
Reload underflow FREQ. MED. FREQ. HIGH FREQ. CCLK internal oscillators RTCS1 RTCS2 select
002aaa924
23-bit down counter
7-bit prescaler
÷128
Wake-up from power-down RTCF Interrupt enabled (shared with WDT) underflow flag ERTC RTCEN enable
Real-time clock/system timer block diagram.
Real-time clock source
RTCS1-0 (RTCCON[6:5]) used select clock source either Internal oscillator internal oscillator used clock. internal crystal oscillator external clock input XTAL1 used clock, then will CCLK clock source.
Changing RTCS1-0
RTCS1-0 cannot changed currently enabled (RTCCON.0 Setting RTCEN updating RTCS1-0 done single write RTCCON. However, RTCEN this must first cleared before updating RTCS1-0.
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Real-time clock interrupt/wake-up
ERTC (RTCCON.1), EWDRT (IEN1[6:0]) (IEN0.7) logic RTCF used interrupt source. This interrupt vector shared with Watchdog timer. also source wake device.
Reset sources affecting Real-time clock
Only power-on reset will reset Real-time Clock associated SFRs their default state.
Table Real-time Clock/System Timer clock sources RTCS0 (RTCCON.5) FOSC2 (UCFG1.2) FOSC1 (UCFG1.1) FOSC0 (UCFG1.0) CCLK RTCS1 (RTCCON.6) CCLK clock source High frequency crystal Medium frequency crystal
RTCS1 (RTCCON.6)
frequency CCLK crystal High frequency crystal Medium frequency crystal frequency crystal CCLK Internal oscillator
High frequency crystal Medium frequency crystal frequency crystal CCLK
Watchdog oscillator
Table Symbol Reset
undefined undefined CCLK
undefined undefined External clock input
Real-time Clock Control register (RTCCON address D1h) allocation RTCF RTCS1 RTCS0 ERTC RTCEN
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Table
Real-time Clock Control register (RTCCON address D1h) description Description Real-time Clock enable. Real-time Clock will enabled this logic Note that this will power-down Real-time Clock. RTCPD (PCONA.7) set, will power-down disable this block regardless RTCEN. Real-time Clock interrupt enable. Real-time Clock shares same interrupt Watchdog timer. Note that user configuration WDTE (UCFG1.7) logic Watchdog timer enabled generate interrupt. Users read RTCF (RTCCON.7) determine whether Real-time Clock caused interrupt. reserved Real-time Clock source select (see Table 37). Real-time Clock Flag. This logic when 23-bit Real-time Clock reaches count logic cleared software.
Symbol RTCEN
ERTC
RTCS0 RTCS1 RTCF
UART
P89LPC924/925 enhanced UART that compatible with conventional 80C51 UART except that Timer overflow cannot used baud rate source. P89LPC924/925 does include independent Baud Rate Generator. baud rate selected from oscillator (divided constant), Timer overflow, independent Baud Rate Generator. addition baud rate generation, enhancements over standard 80C51 UART include Framing Error detection, break detect, automatic address recognition, selectable double buffering several interrupt options. UART operated four modes, described following sections.
10.1 Mode
Serial data enters exits through RXD. outputs shift clock. bits transmitted received, first. baud rate fixed 1/16 clock frequency.
10.2 Mode
bits transmitted (through TXD) received (through RXD): start (logic data bits (LSB first), stop (logic When data received, stop stored Special Function Register SCON. baud rate variable determined Timer overflow rate Baud Rate Generator (see Section 10.6 "Baud Rate generator selection").
10.3 Mode
bits transmitted (through TXD) received (through RXD): start (logic data bits (LSB first), programmable data bit, stop (logic When data transmitted, data (TB8 SCON) assigned value example, parity PSW) could moved into TB8. When data received, data goes into Special Function Register SCON stop saved. baud rate programmable either 1/16 1/32 CCLK frequency, determined SMOD1 PCON.
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10.4 Mode
bits transmitted (through TXD) received (through RXD): start (logic data bits (LSB first), programmable data bit, stop (logic Mode same Mode respects except baud rate. baud rate Mode variable determined Timer overflow rate Baud Rate Generator (see Section 10.6 "Baud Rate generator selection" page 45). four modes, transmission initiated instruction that uses SBUF destination register. Reception initiated Mode condition Reception initiated other modes incoming start
10.5 space
UART SFRs following locations shown Table
Table Register PCON SCON SBUF SADDR SADEN SSTAT BRGR1 BRGR0 BRGCON UART addresses Description Power Control Serial Port (UART) Control Serial Port (UART) Data Buffer Serial Port (UART) Address Serial Port (UART) Address Enable Serial Port (UART) Status Baud Rate Generator Rate HIGH Byte Baud Rate Generator Rate Byte Baud Rate Generator Control location
10.6 Baud Rate generator selection
P89LPC924/925 enhanced UART independent Baud Rate Generator. baud rate determined value programmed into BRGR1 BRGR0 SFRs. UART either Timer baud rate generator output determined BRGCON.2-1 (see Figure 19). Note that Timer further divided SMOD1 (PCON.7) set. independent Baud Rate Generator uses CCLK.
10.7 Updating BRGR1 BRGR0 SFRs
baud rate SFRs, BRGR1 BRGR0 must only loaded when Baud Rate Generator disabled (the BRGEN BRGCON register logic This avoids loading interim value baud rate generator. (CAUTION: either BRGR0 BRGR1 written when BRGEN result unpredictable.)
Table SCON.7 (SM0) UART baud rate generation. SCON.6 (SM1) PCON.7 (SMOD1) BRGCON.1 (SBRGS) Receive/transmit baud rate UART CCLK/16 CCLK/(256 TH1)64 CCLK/(256 TH1)32 CCLK/((BRGR1,BRGR0)
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Table SCON.7 (SM0)
UART baud rate generation. SCON.6 (SM1) PCON.7 (SMOD1) BRGCON.1 (SBRGS) Receive/transmit baud rate UART CCLK/32 CCLK/16 CCLK/(256 TH1)64 CCLK/(256 TH1)32 CCLK/((BRGR1,BRGR0)
Table Symbol Reset Table
Baud Rate Generator Control register (BRGCON address BDh) allocation SBRGS BRGEN
Baud Rate Generator Control register (BRGCON address BDh) description Description Baud Rate Generator Enable. Enables baud rate generator. BRGR1 BRGR0 only written when BRGEN Select Baud Rate Generator source baud rates UART modes (see Table details) reserved
Symbol BRGEN SBRGS
Timer Overflow (PCLK-based) Baud Rate Generator (CCLK-based)
SMOD1
SBRGS Baud Rate Modes SBRGS
002aaa419
SMOD1
Baud rate generation UART (Modes
10.8 Framing error
Framing error occurs when stop sensed logic Framing error reported status register (SSTAT). addition, SMOD0 (PCON.6) framing errors made available SCON.7. SMOD0 SCON.7 SM0. recommended that (SCON.7-6) programmed when SMOD0 logic
10.9 Break detect
break detect reported status register (SSTAT). break detected when consecutive bits sensed LOW. Since break condition also satisfies requirements framing error, break condition will also result reporting framing error. Once break condition been detected, UART will into idle state remain this idle state until stop been received. break detect used reset device force device into mode setting EBRR (AUXR1.6).
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Table Symbol Reset Table
Serial Port Control register (SCON address 98h) allocation SM0/FE
Serial Port Control register (SCON address 98h) description Description Receive interrupt flag. hardware time Mode approximately halfway through stop time Mode Mode Mode SMOD0, near middle data (bit SMOD0 near middle stop (see SCON.5 exceptions). Must cleared software. Transmit interrupt flag. hardware time Mode stop (see description INTLO SSTAT register) other modes. Must cleared software. data that received Modes Mode (SM2 must stop that received. Mode undefined. data that will transmitted Modes clear software desired. Enables serial reception. software enable reception. Clear software disable reception. Enables multiprocessor communication feature Modes Mode then will activated received data (RB8) Mode should Mode must With defines serial port mode, Table this determined SMOD0 PCON register. SMOD0 this read written SM0, which with SM1, defines serial port mode. SMOD0 this read written (Framing Error). receiver when invalid stop detected. Once set, this cannot cleared valid frames cleared software. (Note: UART mode bits should programmed when SMOD0 logic default mode reset.)
Symbol
SM0/FE
Table SM0,SM1 Table Symbol Reset
Serial Port modes UART mode Mode shift register Mode 8-bit UART Mode 9-bit UART Mode 9-bit UART UART baud rate CCLK/16 (default mode reset) Variable (see Table CCLK/32 CCLK/16 Variable (see Table
Serial Port Status register (SSTAT address BAh) allocation DBMOD INTLO CIDIS DBISEL STINT
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Table
Serial Port Status register (SSTAT address BAh) description Description Status Interrupt Enable. When cause interrupt. interrupt used (vector address 0023h) shared with (CIDIS combined TI/RI (CIDIS When cleared cannot cause interrupt. (Note: often accompanied which will generate interrupt regardless state STINT). Note that cause break detect reset EBRR (AUXR1.6) logic Overrun Error flag character received receiver buffer while still full (before software read previous character from buffer), i.e., when byte received while SCON still set. Cleared software. Break Detect flag. break detected when consecutive bits sensed LOW. Cleared software. Framing error flag when receiver fails valid STOP frame. Cleared software. Double buffering transmit interrupt select. Used only double buffering enabled. This controls number interrupts that occur when double buffering enabled. When set, transmit interrupt generated after each character written SBUF, there also more transmit interrupt generated beginning (INTLO (INTLO STOP last character sent (i.e., more data buffer). This last interrupt used indicate that transmit operations over. When cleared only transmit interrupt generated character written SBUF. Must logic when double buffering disabled. Note that except first character written (when buffer empty), location transmit interrupt determined INTLO. When first character written, transmit interrupt generated immediately after SBUF written. Combined Interrupt Disable. When interrupts separate. When cleared UART uses combined TX/RX interrupt (like conventional 80C51 UART). This reset logic select combined interrupts. Transmit interrupt position. When cleared interrupt issued beginning stop bit. When interrupt issued stop bit. Must logic mode Note that case single buffering, interrupt occurs STOP bit, exist before next start bit.
Symbol STINT
DBISEL
CIDIS
INTLO
DBMOD Double buffering mode. When enables double buffering. Must logic UART mode order compatible with existing 80C51 devices, this reset logic disable double buffering.
10.10 More about UART Mode
Mode write SBUF will initiate transmission. transmission, (SCON.1) set, which must cleared software. Double buffering must disabled this mode. Reception initiated clearing (SCON.0). Synchronous serial transfer occurs will again transfer. When cleared, reception next character will begin. Refer Figure
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write SBUF shift (data out) (shift clock) transmit
WRITE SCON (clear receive shift (data (shift clock)
002aaa925
Serial Port Mode (double buffering must disabled).
10.11 More about UART Mode
Reception initiated detecting 1-to-0 transition RXD. sampled rate times programmed baud rate. When transition detected, divide-by-16 counter immediately reset. Each time thus divided into counter states. 7th, 8th, counter states, detector samples value RXD. value accepted value that seen least samples. This done noise rejection. value accepted during first time receive circuits reset receiver goes back looking another 1-to-0 transition. This provides rejection false start bits. start proves valid, shifted into input shift register, reception rest frame will proceed. signal load SBUF RB8, will generated only following conditions time final shift pulse generated: either received stop either these conditions met, received frame lost. both conditions met, stop goes into RB8, data bits into SBUF, activated.
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clock write SBUF shift INTLO INTLO start stop transmit
clock shift
002aaa926 reset
start
stop receive
Serial Port Mode (only single transmit buffering case shown).
10.12 More about UART Modes
Reception same Mode signal load SBUF RB8, will generated only following conditions time final shift pulse generated. Either received data either these conditions met, received frame lost, set. both conditions met, received data goes into RB8, first data bits into SBUF.
clock write SBUF shift INTLO clock shift SMOD0 SMOD0
002aaa927 reset
transmit start stop
INTLO
start
stop
receive
Serial Port Mode (only single transmit buffering case shown).
10.13 Framing error Modes with
modes behaves following table.
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Table Mode
when SM2= Modes when Similar Figure with SMOD0 occurs during RB8, before when Similar Figure with SMOD0 occurs during STOP Occurs during STOP Occurs during STOP Will occur Occurs during STOP
PCON.6 (SMOD0)
10.14 Break detect
break detected when consecutive bits sensed reported status register (SSTAT). Mode this consists start bit, data bits, stop times. Modes this consists start bit, data bits, stop bit. break detect cleared software reset. break detect used reset device force device into mode. This occurs UART enabled EBRR (AUXR1.6) break occurs.
10.15 Double buffering
UART transmit double buffer that allows buffering next character written SBUF while first character being transmitted. Double buffering allows transmission string characters with only stop between characters, provided next character written between start stop previous character. Double buffering disabled. disabled (DBMOD, i.e. SSTAT.7 UART compatible with conventional 80C51 UART. enabled, UART allows writing SnBUF while previous data being shifted out.
10.16 Double buffering different modes
Double buffering only allowed Modes When operated Mode double buffering must disabled (DBMOD
10.17 Transmit interrupts with double buffering enabled (Modes 1,2,
Unlike conventional UART, when double buffering enabled, interrupt generated when double buffer ready receive data. following occurs during transmission (assuming eight data bits): double buffer empty initially. writes SBUF. SBUF data loaded shift register interrupt generated immediately. there more data, else continue. there more data, then: DBISEL logic more interrupts will occur.
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DBISEL logic INTLO logic interrupt will occur beginning STOP data currently shifter (which also last data). DBISEL logic INTLO logic interrupt will occur STOP data currently shifter (which also last data). Note that DBISEL logic writing SBUF when STOP last data shifted out, there uncertainty whether interrupt generated already with UART knowing whether there more data following. there more data, writes SBUF again. Then: INTLO logic data will loaded interrupt will occur beginning STOP data currently shifter. INTLO logic data will loaded interrupt will occur STOP data currently shifter.
write SBUF interrupt Single buffering (DBMOD/SSTAT.7 early interrupt (INTLO/SSTAT.6 shown
write SBUF interrupt Double buffering (DBMOD/SSTAT.7 early interrupt (INTLO/SSTAT.6 shown, ending interrupt (DBISEL/SSTAT.4
write SBUF interrupt Double buffering (DBMOD/SSTAT.7 early interrupt (INTLO/SSTAT.6 shown, with ending interrupt (DBISEL/SSTAT.4
002aaa928
Transmission with without double buffering.
10.18 (bit double buffering (Modes
double buffering disabled (DBMOD, i.e. SSTAT.7 written before after SBUF written, provided updated before that shifted out. must changed again until after shifting been completed, indicated interrupt.
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double buffering enabled, MUST updated before SBUF written, will double-buffered together with SBUF data. operation described Section 10.17 becomes follows: double buffer empty initially. writes TB8. writes SBUF. SBUF/TB8 data loaded shift register interrupt generated immediately. there more data, else continue there more data, then: DBISEL logic more interrupt will occur. DBISEL logic INTLO logic interrupt will occur beginning STOP data currently shifter (which also last data). DBISEL logic INTLO logic interrupt will occur STOP data currently shifter (which also last data). there more data, writes again. writes SBUF again. Then: INTLO logic data will loaded interrupt will occur beginning STOP data currently shifter. INTLO logic data will loaded interrupt will occur STOP data currently shifter. 10.Note that DBISEL logic writing SBUF when STOP last data shifted out, there uncertainty whether interrupt generated already with UART knowing whether there more data following.
10.19 Multiprocessor communications
UART modes have special provision multiprocessor communications. these modes, data bits received transmitted. When data received, stored RB8. UART programmed such that when stop received, serial port interrupt will activated only This feature enabled setting SCON. this feature multiprocessor systems follows: When master processor wants transmit block data several slaves, first sends address byte which identifies target slave. address byte differs from data byte that address byte data byte. With slave will interrupted data byte. address byte, however, will interrupt slaves, that each slave examine received byte being addressed. addressed slave will clear prepare receive data bytes that follow. slaves that weren't being addressed leave their bits about their business, ignoring subsequent data bytes. Note that effect Mode must logic Mode
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10.20 Automatic address recognition
Automatic address recognition feature which allows UART recognize certain addresses serial stream using hardware make comparisons. This feature saves great deal software overhead eliminating need software examine every serial address which passes serial port. This feature enabled setting SCON. UART modes (mode mode Receive Interrupt flag (RI) will automatically when received byte contains either `Given' address `Broadcast' address. mode requires that information indicate that received information address data. Using Automatic Address Recognition feature allows master selectively communicate with more slaves invoking Given slave address addresses. slaves contacted using Broadcast address. special Function Registers used define slave's address, SADDR, address mask, SADEN. SADEN used define which bits SADDR used which bits `don't care'. SADEN mask logically ANDed with SADDR create `Given' address which master will addressing each slaves. Given address allows multiple slaves recognized while excluding others. following examples will help show versatility this scheme:
Table Example Slave SADDR SADEN Given 1100 0000 1111 1101 1100 00X0 Slave examples Example Slave SADDR SADEN Given 1100 0000 1111 1110 1100 000X
above example SADDR same SADEN data used differentiate between slaves. Slave requires ignores Slave requires ignored. unique address Slave would 1100 0010 since slave requires unique address slave would 1100 0001 since will exclude slave Both slaves selected same time address which (for slave (for slave Thus, both could addressed with 1100 0000. more complex system following could used select slaves while excluding slave
Table Example Slave SADDR 1100 0000 SADEN 1111 1001 Given 1100 0XX0 Slave 0/1/2 examples Example Slave SADDR 1110 0000 SADEN 1111 1010 Given 1110 0X0X Example Slave SADDR SADEN Given 1100 0000 1111 1100 1110 00XX
above example differentiation among slaves lower address bits. Slave requires that uniquely addressed 1110 0110. Slave requires that uniquely addressed 1110 0101. Slave requires that unique address 1110 0011. select Slaves exclude Slave address 1110 0100, since necessary make exclude slave Broadcast Address each slave created taking logical SADDR SADEN. Zeros this result treated don't-cares. most cases,
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interpreting don't-cares ones, broadcast address will hexadecimal. Upon reset SADDR SADEN loaded with This produces given address `don't cares' well Broadcast address `don't cares'. This effectively disables Automatic Addressing mode allows microcontroller standard UART drivers which make this feature.
interface
I2C-bus uses wires, serial clock (SCL) serial data (SDA) transfer information between devices connected bus, following features:
Bidirectional data transfer between masters slaves. Multimaster central master). Arbitration between simultaneously transmitting masters without corruption serial
data bus.
Serial clock synchronization allows devices with different rates communicate
serial bus.
Serial clock synchronization used handshake mechanism suspend
resume serial transfer.
I2C-bus used test diagnostic purposes.
typical I2C-bus configuration shown Figure Depending state direction (R/W), types data transfers possible I2C-bus:
Data transfer from master transmitter slave receiver. first byte transmitted
master slave address. Next follows number data bytes. slave returns acknowledge after each received byte.
Data transfer from slave transmitter master receiver. first byte (the slave
address) transmitted master. slave then returns acknowledge bit. Next follows data bytes transmitted slave master. master returns acknowledge after received bytes other than last byte. last received byte, `not acknowledge' returned. master device generates serial clock pulses START STOP conditions. transfer ended with STOP condition with repeated START condition. Since repeated START condition also beginning next serial transfer, I2C-bus will released. P89LPC924/925 device provides byte-oriented interface. four operation modes: Master Transmitter Mode, Master Receiver Mode, Slave Transmitter Mode Slave Receiver Mode. P89LPC924/925 interfaces with I2C-bus through Special Function Registers (SFRs): I2CON (I2C Control Register), I2DAT (I2C Data Register), I2STAT (I2C Status Register), I2ADR (I2C Slave Address Register), I2SCLH (SCL Duty Cycle Register HIGH Byte), I2SCLL (SCL Duty Cycle Register Byte).
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I2C-BUS P1.3/SDA P1.2/SCL OTHER DEVICE WITH I2C-BUS INTERFACE OTHER DEVICE WITH I2C-BUS INTERFACE
002aaa952
P89LPC924/925
I2C-bus configuration.
11.1 Data register
I2DAT register contains data transmitted data received. read write this 8-bit register while process shifting byte. Thus this register should only accessed when set. Data I2DAT remains stable long set. Data I2DAT always shifted from right left: first transmitted (bit after byte been received, first received data located I2DAT.
Table Symbol Reset Data register (I2DAT address DAh) allocation I2DAT.7 I2DAT.6 I2DAT.5 I2DAT.4 I2DAT.3 I2DAT.2 I2DAT.1 I2DAT.0
11.2 Slave Address register
I2ADR register readable writable, only used when interface slave mode. master mode, this register effect. I2ADR general call bit. When this set, general call address (00h) recognized.
Table Symbol Reset Table Slave Address register (I2ADR address DBh) allocation I2ADR.6 I2ADR.5 I2ADR.4 I2ADR.3 I2ADR.2 I2ADR.1 I2ADR.0
Slave Address register (I2ADR address DBh) description Description General call bit. When set, general call address (00H) recognized, otherwise ignored.
Symbol
I2ADR1:7 slave address. When master mode, contents this register effect.
11.3 Control register
read write this register. There bits affected hardware: bit. hardware cleared hardware.
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CRSEL determines source when I2C-bus master mode. slave mode this ignored will automatically synchronize with clock frequency from master device. When CRSEL interface uses Timer overflow rate divided clock rate. Timer should programmed user auto-reload mode (Mode Data rate I2C-bus Timer overflow rate PCLK (2*(256 reload value)), fosc MHz, reload value 255, I2C-bus data rate range 11.72 Kbit/sec 3000 Kbit/sec. When CRSEL interface uses internal clock generator based value I2SCLL I2CSCLH register. duty cycle does need START flag. Setting this causes interface enter master mode attempt transmitting START condition transmitting repeated START condition when already master mode. STOP flag. Setting this causes interface transmit STOP condition master mode, recovering from error condition slave mode. both set, then STOP condition transmitted I2C-bus master mode, transmits START condition afterwards. slave mode, internal STOP condition will generated, transmitted bus.
Table Symbol Reset Table Control register (I2CON address D8h) allocation I2EN CRSEL
Control register (I2CON address D8h) description Description clock selection. When Timer overflow generates SCL, when cleared internal generator used base values I2SCLH I2SCLL. reserved Assert Acknowledge Flag. When acknowledge (LOW level SDA) will returned during acknowledge clock pulse line following situations: (1)The `own slave address' been received. (2)The general call address been received while general call (GC) I2ADR set. data byte been received while interface Master Receiver Mode. (4)A data byte been received while interface addressed Slave Receiver Mode. When cleared logic acknowledge (HIGH level SDA) will returned during acknowledge clock pulse line following situations: data byte been received while interface Master Receiver Mode. data byte been received while interface addressed Slave Receiver Mode.
Symbol CRSEL
Interrupt Flag. This when possible I2C-bus states entered. When EI2C (IEN1.0) both set, interrupt requested when set. Must cleared software writing this bit. STOP Flag. master mode, STOP condition transmitted I2C-bus. When detects STOP condition, will clear automatically. slave mode, setting this recover from error condition. this case, STOP condition transmitted bus. hardware behaves STOP condition been received switches `not addressed' Slave Receiver Mode. flag cleared hardware automatically.
Koninklijke Philips Electronics N.V. 2004. rights reserved.
User manual
Rev. March 2005
Philips Semiconductors
UM10108
P89LPC924/925 User manual
Table
Control register (I2CON address D8h) description Description Start Flag. I2C-bus enters master mode, checks generates START condition free. free, waits STOP condition (which will free bus) generates START condition after delay half clock period internal clock generator. When interface already master mode some data transmitted received, transmits repeated START condition. time, also when interface addressed slave mode. START condition repeated START condition will generated. Interface Enable. When set, enables interface. When clear, function disabled. reserved
Symbol
I2EN
11.4 status register
This read-only register. contains status code interface. lower three bits always There possible status codes. When code F8H, there relevant information available set. other status codes correspond defined states. When these states entered, will set. Refer Table Table details.
Table Symbol Reset Table STA.0:4 status register (I2STAT address D9h) allocation STA.4 STA.3 STA.2 STA.1 STA.0
Status register (I2STAT address D9h) description Description Reserved, always Status code.
Symbol
11.5 duty cycle registers I2SCLH I2SCLL
When internal generator selected interface setting CRSEL I2CON register, user must values registers I2SCLL I2SCLH select data rate. I2SCLH defines number PCLK cycles HIGH, I2SCLL defines number PCLK cycles LOW. frequency determined following formula: Frequency fPCLK (2*(I2SCLH I2SCLL)) Where fPCLK frequency PCLK. values I2SCLL I2SCLH have same; user give different duty cycle's setting these registers. However, value register must ensure that data rate data rate range kHz. Thus values I2SCLL I2SCLH have some restrictions values both registers greater than PCLKs recommended.
Koninklijke Philips Electronics N.V. 2004. rights reserved.
User manual
Rev. March 2005
Philips Semiconductors
UM10108
P89LPC924/925 User manual
Table
clock rates selection data rate (Kbit/sec) fosc 3.6865 Kbps Timer mode 1.8433 Kbps Timer mode 5.86 1500 Kbps Timer mode 2.93 Kbps Timer mode
I2SCLL+ CRSEL 7.373 I2SCLH Kbps Timer mode
11.6 operation modes
11.6.1 Master Transmitter mode
this mode data transmitted from master slave. Before Master Transmitter Mode entered, I2CON must initialized follows:
Table value Control register (I2CON address D8h) I2EN CRSEL rate
CRSEL defines rate. I2EN must enable function. logic will acknowledge slave address general call address event another device becoming master enter slave mode. STA, STO, bits must cleared logic first byte transmitted contains slave address receiving device bits) data direction bit. this case, data direction (R/W) will logic indicating write. Data transmitted bits time. After each byte transmitted, acknowledge received. START STOP conditions output indicate beginning serial transfer. I2C-bus will enter Master Transmitter Mode setting bit. logic will send START condition soon free. After START condition transmitted, set, status code I2STAT should 08h. This status code must used vector interrupt service routine where user should load slave address I2DAT (Data Register) data direction (SLA+W). must cleared before data transfer continue.
Koninklijke Philips Electronics N.V. 2004. rights reserved.
User manual
Rev. March 2005
Philips Semiconductors
UM10108
P89LPC924/925 User manual
When slave address have been transmitted acknowledgment been received, again, possible status codes 18h, 20h, master mode 68h, 78h, 0B0h slave mode enabled (setting logic appropriate action taken each these status codes shown Table
slave address
DATA
DATA
logic write logic read from Master Slave from Slave Master
data transferred Bytes acknowledge) acknowledge (SDA LOW) acknowledge (SDA HIGH) START condition STOP condition
002aaa929
Format Master Transmitter mode.
11.6.2 Master Receiver mode
Master Receiver Mode, data received from slave transmitter. transfer started same manner Master Transmitter Mode. When START condition been transmitted, interrupt service routine must load slave address data direction Data Register (I2DAT). must cleared before data transfer continue. When slave address data direction have been transmitted acknowledge been received, set, Status Register will show status code. master mode, possible status codes 40H, 48H, 38H. slave mode, possible status codes 68H, 78H, B0H. Refer Table details.
slave address
DATA
DATA
logic write logic read from Master Slave from Slave Master
data transferred Bytes acknowledge) acknowledge (SDA LOW) acknowledge (SDA HIGH) START condition
002aaa930
Format Master Receiver mode.
After repeated START condition, I2C-bus switch Master Transmitter Mode.
Koninklijke Philips Electronics N.V. 2004. rights reserved.
User manual
Rev. March 2005
Philips Semiconductors
UM10108
P89LPC924/925 User manual
DATA
DATA
DATA
logic write logic read from Master Slave from Slave Master
data transferred Bytes acknowledge) acknowledge (SDA LOW) acknowledge (SDA HIGH) START condition STOP condition slave address repeat START condition
002aaa931
Master Receiver switches Master Transmitter after sending Repeated Start.
11.6.3 Slave Receiver mode
Slave Receiver Mode, data bytes received from master transmitter. initialize Slave Receiver Mode, user should write slave address Slave Address Register (I2ADR) Control Register (I2CON) should configured follows:
Table value Control register (I2CON address D8h) I2EN CRSEL
CRSEL used slave mode. I2EN must enable function. must acknowledge slave address general call address. STA, cleared After I2ADR I2CON initialized, interface waits until addressed address general address followed data direction which 0(W). direction 1(R), will enter Slave Transmitter Mode. After address direction have been received, valid status code read from Status Register (I2STAT). Refer Table status codes actions.
slave address
DATA
DATA
P/RS
logic write logic read from Master Slave from Slave Master
data transferred Bytes acknowledge) acknowledge (SDA LOW) acknowledge (SDA HIGH) START condition STOP condition repeated START condition
002aaa932
Format Slave Receiver mode.
11.6.4 Slave Transmitter mode
first byte received handled Slave Receiver Mode. However, this mode, direction will indicate that transfer direction reversed. Serial data transmitted P1.3/SDA while serial clock input through P1.2/SCL. START
Koninklijke Philips Electronics N.V. 2004. rights reserved.
User manual
Rev. March 2005
Philips Semiconductors
UM10108
P89LPC924/925 User manual
STOP conditions recognized beginning serial transfer. given application, I2C-bus operate master slave. slave mode, I2C-bus hardware looks slave address general call address. these addresses detected, interrupt requested. When microcontrollers wishes become master, hardware waits until free before master mode entered that possible slave action interrupted. arbitration lost master mode, I2C-bus switches slave mode immediately detect slave address same serial transfer.
slave address
DATA
DATA
logic write logic read from Master Slave from Slave Master
data transferred Bytes acknowledge) acknowledge (SDA LOW) acknowledge (SDA HIGH) START condition STOP condition
002aaa933
Format Slave Transmitter mode.
Koninklijke Philips Electronics N.V. 2004. rights reserved.
User manual
Rev. March 2005
Philips Semiconductors
UM10108
P89LPC924/925 User manual
ADDRESS REGISTER P1.3
I2ADR INTERNAL I2DAT
COMPARATOR INPUT FILTER P1.3/SDA OUTPUT STAGE SHIFT REGISTER
INPUT FILTER P1.2/SCL OUTPUT STAGE TIMER OVERFLOW P1.2 I2CON I2SCLH I2SCLL
COUNTER ARBITRATION SYNC LOGIC
CCLK TIMING CONTROL LOGIC INTERRUPT
SERIAL CLOCK GENERATOR
CONTROL REGISTERS DUTY CYCLE REGISTERS
STATUS
STATUS DECODER
I2STAT
STATUS REGISTER
002aaa421
serial interface block diagram.
Koninklijke Philips Electronics N.V. 2004. rights reserved.
User manual
Rev. March 2005
Philips Semiconductors
UM10108
P89LPC924/925 User manual
Table
Master Transmitter mode Status hardware Application software response to/from I2DAT Load SLA+W I2CON SLA+W will transmitted; will received above; SLA+W will transmitted; I2C-bus switches Master Receiver Mode Data byte will transmitted; will received Repeated START will transmitted; STOP condition will transmitted; flag will reset I2DAT action STOP condition followed START condition will transmitted; flag will reset. Data byte will transmitted; will received Repeated START will transmitted; STOP condition will transmitted; flag will reset STOP condition followed START condition will transmitted; flag will reset Data byte will transmitted; will received Repeated START will transmitted; STOP condition will transmitted; flag will reset STOP condition followed START condition will transmitted; flag will reset Next action taken hardware
Status code (I2STAT)
START condition been transmitted repeat START condition been transmitted
Load SLA+W Load SLA+R
SLA+W been Load data byte transmitted; been received I2DAT action I2DAT action
SLA+W been transmitted; NOT-ACK been received
Load data byte
I2DAT action I2DAT action
I2DAT action
Data byte I2DAT Load data byte been transmitted; been received I2DAT action I2DAT action
I2DAT action
Koninklijke Philips Electronics N.V. 2004. rights reserved.
User manual
Rev. March 2005
Philips Semiconductors
UM10108
P89LPC924/925 User manual
Table
Master Transmitter mode Status hardware Application software response to/from I2DAT I2CON Data byte will transmitted; will received Repeated START will transmitted; STOP condition will transmitted; flag will reset STOP condition followed START condition will transmitted. flag will reset. I2C-bus will released; addressed slave will entered START condition will transmitted when becomes free. Next action taken hardware
Status code (I2STAT)
Data byte I2DAT Load data byte been transmitted, I2DAT action been received I2DAT action
I2DAT action
Arbitration lost SLA+R/W data bytes
I2DAT action I2DAT action
Table
Master Receiver mode Status hardware Application software response to/from I2DAT Load SLA+R I2CON SLA+R will transmitted; will received above SLA+W will tra
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