STD90/MDL90 0.35µm 3.3V CMOS Standard Cell Library Pure Logic/MDL Prod
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STD90/MDL90 0.35µm 3.3V CMOS Standard Cell Library Pure Logic/MDL Products
STD90/MDL90 0.35µm 3.3V CMOS Standard Cell Library Pure Logic/MDL Products Data Book 2000 Samsung Electronics Co., Ltd. rights reserved. part this document reproduced, form means, without prior written consent publisher. Samsung assumes responsibility errors resulting from information contained herein, does convey license under patent rights Samsung others. Samsung reserves right make changes products product specification improve function design time, without notice. STD90/MDL90 trademarks Samsung Electronics Co., Ltd. Verilog registered trademark Cadence Design Systems, Inc. Viewlogic registered trademark Viewlogic Systems, Inc. Mentor registered trademark Mentor Graphics Synopsys registered trademark Synopsys, Inc.
Head Office Samsung Electronics Co., System Business, ASIC Division, Design Technology #24, Nongseo-Ri, Kiheung-Eup, Yongin-City, Kyunggi-Do, Korea 82-2-760-6500, 6501(Hot Line) 82-331-209-4920 http://www.intl.samsungsemi.com Printed Republic Korea
Marketing Team Samsung Electronics Co., System Business, ASIC Division, ASIC Marketing Team #24, Nongseo-Ri, Kiheung-Eup, Yongin-City, Kyunggi-Do, Korea 82-22-331-209-1930 82-2-331-209-1919
Introduction
This databook contains information about STD90/MDL90 0.35µm 3.3V TLM/QLM standard cell library pure logic products developed (Samsung Electronics Corporation). "library" basically contains various kinds internal cells soft-macros which used developing ASIC (Application Specific Integrated Circuit). also includes design helping designers work workstation platform, sorts design environments needed automatic chip design. There seven chapters this databook: Chapter Chapter Chapter Chapter Chapter Chapter Introduction Electrical Characteristics Internal Macrocells Input/Output Cells Compiled Macrocells
this databook each cell followed electrical characteristics, these characteristic values almost equal when corresponding cell operated real chip. purpose this databook prevent misuse misapplication STD90/MDL90 cell library providing precise information about cell list, electrical data, directions use, matters demanding special attention.
Samsung ASIC
STD90/MDL90
Contents
Introduction
Library Description .1-1 Features .1-2 Support .1-3 Product Family .1-3 1.4.1 Internal Macrocells .1-3 1.4.2 Compiled Macrocells .1-3 1.4.3 Input/Output Cells.1-4 Propagation Delays .1-6 Delay Model .1-12 Testability Design Methodology.1-15 Maximum Fanouts .1-18 Product Line-Up .1-24 1.10 Packages Capability Lead Count .1-25 1.11 Power Dissipation.1-27 1.12 VDD/VSS Rules Guidelines.1-30 1.13 Crystal Oscillator Considerations .1-35
Electrical Characteristics
Electrical Characteristics.2-1 Input Buffer Curves .2-5 Output Drive Capabilities.2-7
Internal Macrocells
Overview .3-1 Summary Tables .3-2 Logic Cells AD2DH/AD2/AD2D2/AD2D4 .3-15 AD3DH/AD3/AD3D2/AD3D4 .3-17 AD4DH/AD4/AD4D2/AD4D4 .3-19 AD5/AD5D2/AD5D4 .3-22 ND2DH/ND2/ND2D2/ND2D4 .3-25 ND3DH/ND3/ND3D2/ND3D4 .3-27 ND4DH/ND4/ND4D2/ND4D2B/ND4D4 .3-30
Samsung ASIC
STD90/MDL90
Contents ND5/ND5D2/ND5D4.3-33 ND6/ND6D2/ND6D4.3-36 ND8/ND8D2/ND8D4.3-40 NR2DH/NR2/NR2D2/NR2D2B/NR2D4 .3-44 NR3DH/NR3/NR3D2/NR3D2B/NR3D4 .3-46 NR4DH/NR4/NR4D2/NR4D2B/NR4D4 .3-49 NR5/NR5D2/NR5D4.3-52 NR6/NR6D2/NR6D4.3-56 NR8/NR8D2/NR8D4.3-60 OR2DH/OR2/OR2D2/OR2D4 .3-64 OR3DH/OR3/OR3D3/OR3D4 .3-66 OR4DH/OR4/OR4D2/OR4D4 .3-69 OR5/OR5D2/OR5D4 .3-72 XN2/XN2D2/XN2D4 .3-76 XN3/XN3D2/XN3D4 .3-78 XO2/XO2D2/XO2D4 .3-80 XO3/XO3D2/XO3D4 .3-82 AO21/AO21D2/AO21D2B/AO21D4.3-84 AO2111/AO2111D2.3-90 AO22/AO22D2/AO22D2B/AO22D4.3-93 AO22A/AO22D2A/AO22D4A.3-96 AO221/AO221D2/AO221D4.3-98 AO222A/AO222D2A/AO222D4A.3-107 AO2222/AO2222D2/AO2222D4.3-109 AO31/AO31D2/AO31D4.3-113 AO311/AO311D2/AO311D4.3-115 AO3111/AO3111D2.3-119 AO32/AO32D2/AO32D4.3-122 AO321/AO321D2/AO321D4.3-126 AO322/AO322D2/AO322D4.3-130 AO33/AO33D2/AO33D4.3-134 AO331/AO331D2/AO331D4.3-138 AO332/AO332D2/AO332D4.3-142 AO4111/AO4111D2.3-146 OA2111/OA2111D2 .3-155 OA22A/OA22D2A/OA22D4A.3-161 OA221/OA221D2/OA221D4.3-163
Samsung ASIC
STD90/MDL90
Contents OA2222/OA2222D2/OA2222D4.3-172 OA31/OA31D2/OA31D4.3-176 OA311/OA311D2/OA311D4.3-178 OA3111/OA3111D2 .3-182 OA32/OA32D2/OA32D4.3-185 OA321/OA321D2/OA321D.3-189 OA322/OA322D2/OA322D4.3-193 OA33/OA33D2/OA33D4.3-197 OA331/OA331D2/OA331D4.3-201 OA332/OA332D2/OA332D4.3-205 OA4111/OA4111D2 .3-209 SCG1 .3-212 SCG2 .3-214 SCG3 .3-215 SCG4 .3-216 SCG5 .3-218 SCG6 .3-219 SCG7 .3-220 SCG8 .3-221 SCG9 .3-222 SCG10 .3-223 SCG11 .3-224 SCG12 .3-225 SCG13 .3-226 SCG14 .3-227 SCG15 .3-228 SCG16 .3-229 SCG17 .3-230 SCG18 .3-231 SCG19 .3-232 SCG20 .3-233 SCG21 .3-234 SCG22 .3-235 DL1D2/DL1D4 .3-236 DL2D2/DL2D4 .3-237 DL3D2/DL3D4 .3-238 DL4D2/DL4D4 .3-239 DL5D2/DL5D4 .3-240 DL10D2/DL10D4 .3-241 .3-242 IVT/IVTD2/IVTD4/IVTD8/IVTD16 .3-247 .3-249
STD90/MDL90
Samsung ASIC
Contents .3-251 NIT/NITD2/NITD4/NITD8/NITD16 .3-254 .3-257 Flip-Flops FD1/FD1D2 .3-263 FD1CS/FD1CSD2 .3-265 FD1S/FD1SD2 .3-268 FD1SQ/FD1SQD2.3-270 FD1Q/FD1QD2.3-272 FD2/FD2D2 .3-274 FD2CS/FD2CSD2 .3-276 FD2S/FD2SD2 .3-280 FD2SQ/FD2SQD2.3-283 FD2Q/FD2QD2.3-286 FD3/FD3D2 .3-288 FD3CS/FD3CSD2 .3-290 FD3S/FD3SD2 .3-293 FD3SQ/FD3SQD2.3-296 FD3Q/FD3QD2.3-299 FD4/FD4D2 .3-301 FD4CS/FD4CSD2 .3-305 FD4S/FD4SD2 .3-309 FD4SQ/FD4SQD2.3-313 FD4Q/FD4QD2.3-316 FD5/FD5D2 .3-318 FD5S/FD5SD2 .3-320 FD6/FD6D2 .3-322 FD6S/FD6SD2 .3-324 FD7/FD7D2 .3-327 FD7S/FD7SD2 .3-329 FD8/FD8D2 .3-332 FD8S/FD8SD2 .3-336 FDS2/FDS2D2 .3-340 FDS2CS/FDS2CSD2 .3-342 FDS2S/FDS2SD2.3-345 FDS3/FDS3D2 .3-347 FDS3CS/FDS3CSD2 .3-349 FDS3S/FDS3SD2.3-352 FJ1/FJ1D2.3-355 FJ1S/FJ1SD2 .3-357 FJ2/FJ2D2.3-359 FJ2S/FJ2SD2 .3-361
Samsung ASIC
STD90/MDL90
Contents FJ4/FJ4D2.3-364 FJ4S/FJ4SD2 .3-367 FT2/FT2D2 .3-370 Latches LD1/LD1D2 .3-373 LD1A/LD1D2A.3-375 LD1Q/LD1QD2 .3-377 LD2/LD2D2 .3-379 LD2Q/LD2QD2 .3-382 LD3/LD3D2 .3-384 LD4/LD4D2 .3-387 LD5/LD5D2 .3-390 LD5Q/LD5QD2 .3-392 LD5S/LD5SD2.3-394 LD6/LD6D2 .3-397 LD6Q/LD6QD2 .3-400 LD7/LD7D2 .3-402 LD8/LD8D2 .3-405 LS0/LS0D2 .3-408 LS1/LS1D2 .3-410 Holder BUSHOLDER .3-414 Internal Clock Drivers CK2/CK4/CK6/CK8/CK12/CK16/CK20 .3-416 Decoders .3-419 DC4I .3-421 DC8I .3-423 Adders FADH/FA/FAD2.3-427 HADH/HA/HAD2 .3-431 SCG23 .3-434 Multiplexers MX2DH/MX2/MX2D2/MX2D4 .3-436 MX2X4 .3-439 MX2IDH/MX2I/MX2ID2/MX2ID4 .3-441 MX2IX4 .3-447 MX3I/MX3ID2/MX3ID4 .3-449
STD90/MDL90
viii
Samsung ASIC
Contents MX4/MX4D2/MX4D4 .3-453 MX8/MX8D2/MX8D4 .3-457
Input/Output Cells
Overview .4-1 Summary Tables .4-2 Input Buffers PvIC/PvICD/PvICU.4-8 PvIS/PvISD/PvISU .4-11 Output Buffers PvOByz .4-15 PvODyz .4-21 PvOTyz .4-30 Bi-Directional Buffers PvBaDyz/PvBaUDyz .4-44 PvBaTyz/PvBaDTyz/PvBaUTyz .4-44 Input Clock Drivers PSCKDCaby.4-46 PSCKDSaby.4-51 Oscillators PSOSCK(1/2) .4-57 PSOSCK(17/27) .4-60 PSOSCM(1/2/3) .4-63 PSOSCM(16/26/36) .4-67 Buffers PIPCI .4-73 POPCI .4-74 PBPCI .4-75 PTIPCI.4-76 PTOPCI .4-77 PTBPCI .4-78 Buffers PBUSB/PBUSB1 .4-81 Power Pads VDD3(I/P/O/IP/OP/T) .4-88 VSS(I/P/O/IP/OP/T).4-88
Samsung ASIC
STD90/MDL90
Contents Analog Interface VDDA/VDDD .4-89 VSSD/VSSA/VBBA .4-89 .4-89 .4-89
Compiled Macrocells
Overview Compiled Macrocells .5-1 Characteristics Timing Power.5-2 Built-In Self Test Compiled Memory .5-3 Selection Guide Compiled Memory.5-4 SPSRAM_HD .5-5 SPSRAMBW_HD .5-15 DPSRAM_HD.5-25 SPARAM_HD .5-35 DROM_HD .5-45 MROM_HD.5-53 Compiled Datapath Macrocells .5-59 Datapath Module Design Flow .5-59 Selection Guide Compiled Datapath Macrocells.5-60 ADDER.5-61 .5-66 .5-70 CSADDER.5-75 BMPY .5-79 REGF .5-86
AL2007LX .6-1 AL2007LA .6-9
STD90/MDL90
Samsung ASIC
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