LC75385NE-R Electronic Volume Tone Control Stereo Systems Ov
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Ordering number EN6143
LC75385NE-R
Electronic Volume Tone Control Stereo Systems
Overview
LC75385NE-R electronic volume tone control that implement volume, balance, fader, bass/treble, loudness, input switching, input gain control functions with minimum number external components.
Features
Volume: positions: from 1-dB steps balance function implemented controlling left right volume settings independently. Fader: Either rear front outputs attenuated over positions. positions: From 1-dB steps, from 2-dB steps, from 10-dB step, Bass/treble: Control over 2-dB steps each band. Input gain: input signal amplified from +18.75 1.25 steps. Input switching: four signals selected each left right channels. Loudness: Taps output from 2-dB step volume control ladder resistor starting -32-dB position. loudness function implemented attaching external capacitors resistors. On-chip buffer amplifiers minimize number required external components.
Minimal switching noise when input signals present fabrication silicon gate CMOS process that minimizes noise generated internal switches. zero-cross switching circuits internal switches minimizes switching noise when signals present. Built-in VDD/2 reference voltage generator circuit controls from serial input data transferred over interface.
Package Dimensions
unit: 3148-QFP44MA
[LC75385NE-R]
13.2 10.0 0.35
13.2 10.0
2.8max
11.6
SANYO: QFP44MA (QIP44MA)
trademark SANYO ELECTRIC CO., LTD. SANYO's original format addresses controlled SANYO.
SANYO products described contained herein have specifications that handle applications that require extremely high levels reliability, such life-support systems, aircraft's control systems, other applications whose failure reasonably expected result serious physical and/or material damage. Consult with your SANYO representative nearest before using SANYO products described contained herein such applications. SANYO assumes responsibility equipment failures that result from using products values that exceed, even momentarily, rated values (such maximum ratings, operating condition ranges, other parameters) listed products specifications SANYO products described contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
41399RM (OT) No.6143-1/22
LC75385NE-R
Specifications
Absolute Maximum Ratings 25°C,
Parameter Maximum supply voltage Maximum input voltage Allowable power dissipation Operating temperature Storage temperature Symbol Topr Tstg input pins 85°C, when mounted printed circuit board Conditions Ratings +125 Unit
Allowable Operating Ranges 25°C,
Parameter Supply voltage High-level input voltage Low-level input voltage Input voltage amplitude Input pulse width Setup time Hold time Operating frequency Symbol tsetup thold fopg Conditions Ratings 10.5 Unit Vp-p
Electrical Characteristics 25°C,
Parameter [Input Block] Input resistance Minimum input gain Maximum input gain Inter-step setting error Left/right balance [Volume Block] Input resistance Inter-step setting error Left/right balance [Tone Control Block] Inter-step setting error Bass control range Treble control range Left/right balance [Fader Block] Input resistance Rfed LFIN, RFIN Inter-step setting error ATerr Left/right balance ±0.5 ±0.5 ATerr Gbass Gtre max. boost/cut max. boost/cut ±1.0 ±0.5 ATerr LVRIN, RVRIN, loudness ±0.5 ±0.5 Ginmin Ginmax ATerr +16.5 +18.75 ±0.6 ±0.5 Symbol Pins Conditions Ratings Unit
No.6143-2/22
LC75385NE-R
Allowable power dissipation, Pdmax
Mounted stipulated printed circuit board
Printed circuit board size: 76.1 Printed circuit board material: Fiberglass/epoxy
Independent device
Ambient temperature, (°C)
Overall Characteristics
Parameter Symbol controls flat, Conditions dBV, dBV, Vrms, Vrms, Vrms, Vrms, kHz, INMUTE, with fader controls flat, with IHF-A filter controls flat, with bandpass filter Ratings 0.004 0.006 Unit Vrms
Total harmonic distortion Inter-input crosstalk Left/right channel crosstalk Maximum attenuation
Output noise voltage Current drain High-level input current Low-level input current Maximum input voltage
Arrangement
LVROUT LTOUT LF1C1 LF1C2 LF1C3 LF3C1 LVRIN LCOM LTIN LFIN LFOUT LROUT DVSS AVSS RROUT RFOUT RFIN RSELO RVRIN RCOM RVROUT RTIN RF1C1 RF1C2 RF1C3 RF3C1 RTOUT
LSELO Vref
LC75385NE-R
view
A12263
No.6143-3/22
LC75385NE-R Equivalent Circuit Sample Application Circuit Diagram
Multiplexer
Multiplexer
No.6143-4/22
LC75385NE-R Functions
Single inputs Function Notes
LSEL0 RSEL0
Input selector outputs
LVRIN RVRIN
Inputs 2-dB step volume control These inputs must driven from low-impedance circuits.
Loudness function pins. Connect high-band compensation circuits between (RCT) LVRIN (RVRIN) pins connect low-band compensation circuits between (RCT) Vref.
LCOM RCOM
2-dB step volume control outputs reduce switching noise, each these pins should connected Vref through capacitor.
LVROUT RVROUT
Output from 1-dB step volume control
LTIN RTIN
Tone control circuit inputs
Continued next page.
No.6143-5/22
LC75385NE-R
Continued from preceding page.
Function Equivalent circuit
LF1C1 LF1C2 LF1C3 RF1C1 RF1C2 RF1C3 Tone control circuit band filter capacitor connections band compensation capacitors must connected between following pins: LF1C1 (RF1C1) LF1C2 (RF1C2) LF1C2 (RF1C2) LF1C3 (RF1C3)
LF3C1 RF3C1
Tone control circuit high band filter capacitor connections high band compensation capacitors must connected between LF3C1 (RF3C1) Vref.
LTOUT RTOUT
Tone control circuit outputs
LFIN RFIN
Fader block inputs These inputs must driven from low-impedance circuits.
LFOUT LROUT RFOUT RROUT Fader block outputs. front rear outputs attenuated independently. attenuation same left right channels.
Vref
VDD/2 voltage generator block. capacitor with value about must inserted between Vref AVSS (VSS) reduce power supply ripple.
Power supply
DVSS
Logic system ground
AVSS
Analog system ground
Continued next page. No.6143-6/22
LC75385NE-R
Continued from preceding page.
Function Equivalent circuit
Used zero cross circuit no-signal timer function. zero cross signal does occur between point when data loaded point when timer times out, data will stored forcibly when timer times out.
Serial data clock inputs used device control
Chip enable input. Data written internal latch when this goes from high low. analog switches then operate. Data transfers enabled when this high.
Internal Equivalent Circuits Selector Block Equivalent Circuit
Total resistance:
right channel identical. Unit (Resistance:
No.6143-7/22
LC75385NE-R 2-dB Step Volume Control Block Equivalent Circuit
left channel 1-dB step block
total resistance above
Switch used initial setup
right channel identical. Unit (Resistance:
total resistance below 30.847
No.6143-8/22
LC75385NE-R 1-dB Step Volume Control Block Equivalent Circuit
From left channel 2-dB volume control block
Switch used initial setup Unit: (Resistance Total resistance: right channel identical.
Switch used initial setup
Tone Control Block Equivalent Circuit
Unit: (Resistance
No.6143-9/22
LC75385NE-R Fader Volume Control Block Equivalent Circuit
When FADER will turned When FADER will turned
Unit: (Resistance Total resistance:
data that sets main volume control 1-dB step circuit sent device, switches will opened (off) switches will closed (on).
No.6143-10/22
LC75385NE-R Control System Timing Data Format LC75385NE-R controlled applying stipulated data pins. data consists total bits, which bits device address bits actual control data.
TDEST
Address code LC75385NE-R 8-bit address code, used along with other that support Sanyo serial bus. Address code
(LSB) (81HEX)
Control code allocation Input switching control
(R1) (R2) (R3) (R4)
test values. These values must used during normal operation.
test bit. This must during normal operation.
No.6143-11/22
LC75385NE-R Input gain control
+1.25 +2.50 +3.75 +5.00 +6.25 +7.50 +8.75 +10.0 +11.25 +12.5 +13.75 +15.0 +16.25 +17.5 +18.75
No.6143-12/22
LC75385NE-R Volume Control
STEP STEP MUTE INMUTE
No.6143-13/22
LC75385NE-R Tone Control
Bass Treble
These bits must
Fader Volume Control
Channel Selection Control
Left right together. This mode initially Left right together
Fader Rear/Front Control
Rear Front
No.6143-14/22
LC75385NE-R Loudness Control
Zero Cross Control
Data written when zero cross detected zero cross detection operation disabled data written falling edge signal
Zero Cross Signal Detection Block Control
Selector Volume Tone Feder
Test Mode Control
These test mode control bits must
No.6143-15/22
LC75385NE-R Usage Notes Data Transmission after Power First Applied When power first applied, state internal analog switches will undefined. Applications that this must include external circuits provide muting until control data been transferred After power first applied, applications should send initial setup data stabilize bias levels each circuit blocks short time. time between initial setup mode first actual data settings Applications should send initial setup data soon rises above After LCOM RCOM pins have stabilized Vref level, applications should send first data settings.
time required capacitors connected LCOM RCOM pins charged Vref level
level
(TYP)
Data First data left channel First data right channel
Initial setup mode
These operations clear initial setup mode
Procedure setting initial setup mode When IC's internal initial setup switch turned goes quick charge mode. this time other data D43) will also left right channels same time. This means that applications states various blocks same time specifying initial setup mode. Procedure clearing initial setup mode Initial setup mode cleared setting value other than other words, normal left right channel specification will turn internal initial setup switch clear quick charge mode.
No.6143-16/22
LC75385NE-R Zero Cross Switching Circuit Operating Principles LC75385NE-R includes function switching place where zero cross comparator operates thus allows applications select optimal detection location block which control data updated. Basically, switching noise will minimized signal immediately following block which control data updated input zero cross comparator. Thus detection location must changed each data update operation. Another issue point that signal amplitude lower than detection sensitivity rms) zero cross comparator (for example volume level), switching noise minimized further selecting point before volume control block, namely selector block output, zero cross detection point than simply waiting data write occur overflow zero cross timer. example, volume block input rms, volume lower, output will under rms. this case, detecting selector output block will result lower switching noise.
Selector
Volume
Tone
Fader
Switch Zero cross comparator
Zero Cross Detection Circuit Zero Cross Switching Control Procedure zero cross switching control procedure consists first setting zero cross detection mode with zero cross control bits (D36 then, after specifying detection block (with bits D38, D39, D40, D41), sending control data. Since these control bits latched first immediately after data sent, i.e. falling edge signal, possible both mode well specify zero cross switching operation single data transfer, even when updating volume other data. following presents example control operation when updating volume block data.
Zero cross detection mode specification
Volume block setting
Zero Cross Timer Setting When input signal level lower than sensitivity zero cross comparator, consists only extremely frequencies, zero cross detection circuit will remain state which cannot detect zero cross data will latched during that period. zero cross timer specifies time after which data will latched forcibly states where zero crossing cannot detected. time determined lowest frequency which zero cross detected reliably. example, timer 0.69 taken 0.033 then will 0.69
No.6143-17/22
LC75385NE-R Notes Serial Data Transfer signal lines must covered (and thus shielded) ground pattern formed from shielded cable prevent high-frequency digital signals those lines from entering analog system. LC75385NE-R data format consists bits address bits data. When data sent units bits each (i.e. bits actually sent), data transfer technique shown figure LC75385NE-R data reception 8-bit units
Dummy data
Input switching control
Test mode control
During transfers, this detects address matches rising edge signal. Therefore, applications must signal then high this time.
No.6143-18/22
Fader volume attenuation Attenuation
Input gain block Input gain block
Main volume block Main volume block
Step Step
Graphic equalizer block Graphic equalizer block
Main Volume Step Characteristics
Fader Volume Step Characteristics
Fader block Fader block
LC75385NE-R
Total harmonic distortion,
Output level
Input gain block
Input gain block
Main volume block
Main volume block
Step
80-kHz pass weighting
Graphic equalizer block
Frequency,
Graphic equalizer block
Fader block
Gain Step Characteristics
Frequency Characteristics
Fader block
No.6143-19/22
LC75385NE-R Output Level Characteristics
Flat overall Input Output LFOUT Settings: positions steps)
Level
Frequency,
Loudness Characteristics
Flat overall Input Output LFOUT Settings: positions steps)
Output level
Frequency,
No.6143-20/22
LC75385NE-R
Input Level Characteristics
Total harmonic distortion, 80-kHz pass weighting With position Total harmonic distortion,
Supply Voltage Characteristics
80-kHz pass weighting
Input level,
Graphic equalizer block
Supply voltage
Graphic equalizer block
Main volume block
Main volume block
Input gain block
Input gain block
Fader block
Bass Control Characteristics Input Output LFOUT
Treble Control Characteristics Input Output LFOUT, 10000
Level
Level
Frequency,
Frequency,
Fader block
No.6143-21/22
LC75385NE-R
Specifications SANYO products described contained herein stipulate performance, characteristics, functions described products independent state, guarantees performance, characteristics, functions described products mounted customer's products equipment. verify symptoms states that cannot evaluated independent device, customer should always evaluate test devices mounted customer's products equipment. SANYO Electric Co., Ltd. strives supply high-quality high-reliability products. However, semiconductor products fail with some probability. possible that these probabilistic failures could give rise accidents events that could endanger human lives, that could give rise smoke fire, that could cause damage other property. When designing equipment, adopt safety measures that these kinds accidents events cannot occur. Such measures include limited protective circuits error prevention circuits safe design, redundant design, structural design. event that SANYO products (including technical data, services) described contained herein controlled under applicable local export control laws regulations, such products must exported without obtaining export license from authorities concerned accordance with above law. part this publication reproduced transmitted form means, electronic mechanical, including photocopying recording, information storage retrieval system, otherwise, without prior written permission SANYO Electric Co., Ltd. information described contained herein subject change without notice product/technology improvement, etc. When designing equipment, refer "Delivery Specification" SANYO product that intend use. Information (including circuit diagrams circuit parameters) herein example only; guaranteed volume production. SANYO believes information herein accurate reliable, guarantees made implied regarding infringements intellectual property rights other rights third parties.
This catalog provides information April, 1999. Specifications information herein subject change without notice. No.6143-22/22
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