CMOS Analog Multiplexers/Demultiplexers* CD4051BMS, CD4052BMS CD4
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CD4051BMS, CD4052BMS CD4053BMS
CMOS Analog Multiplexers/Demultiplexers*
CD4051BMS, CD4052BMS CD4053BMS analog multiplexers/demultiplexers digitally controlled analog switches having impedance very leakage current. Control analog signals peak-topeak achieved digital signal amplitudes 4.5V VDD-VSS VDD-VEE controlled; VDD-VEE level differences above 13V, VDDVSS least 4.5V required). example, +4.5V, -13.5V, analog signals from 13.5V +4.5V controlled digital inputs These multiplexer circuits dissipate extremely quiescent power over full VDD-VSS VDD-VEE supply voltage ranges, independent logic state control signals. When logic present inhibit input terminal channels off. CD4051BMS single channel multiplexer having three binary control inputs, inhibit input. three binary signals select channels turned connect inputs output. CD4052BMS differential channel multiplexer having binary control inputs, inhibit input. binary input signals select pairs channels turned connect analog inputs outputs. CD4053BMS triple channel multiplexer having three separate digital control inputs, inhibit input. Each control input selects pair channels which connected single pole double-throw configuration. CD4051BMS, CD4052BMS CD4053BMS supplied these lead outline packages: Braze Seal Frit Seal Ceramic Flatpack *CD4051B Only *H4X CD4052B, CD4053 Only
December 1992 January 1995
Features
Logic Level Conversion High-Voltage Types (20V Rating) CD4051BMS Signal 8-Channel CD4052BMS Differential 4-Channel CD4053BMS Triple 2-Channel Wide Range Digital Analog Signal Levels: Digital Analog 20Vp-p Resistance: (typ) Over 15Vp-p Signal Input Range High Resistance: Channel Leakage ±100pA (typ) Logic Level Conversion: Digital Addressing Signals (VDD 20V) Switch Analog Signals 20Vp-p (VDD 20V); Introductory Text Matched Switch Characteristics: (typ) Very Quiescent Power Dissipation Under Digital Control Input Supply Conditions: 0.2µW (typ) Binary Address Decoding Chip Parametric Ratings 100% Tested Quiescent Current Maximum Input Current Over Full Package Temperature Range; 100nA +25oC Break-Before-Making Switching Eliminates Channel Overlap
Applications
Analog Digital Multiplexing Demultiplexing Conversion Signal Gating
When these devices used demultiplexers "CHANNEL IN/OUT" terminals outputs "COMMON OUT/IN" terminals inputs.
CAUTION: These devices sensitive electrostatic discharge. Users should follow proper I.C. Handling Procedures. Copyright
Harris Corporation 1992
File Number
3316
7-937
CD4051BMS, CD4052BMS, CD4053BMS Pinouts
CD4051BM VIEW
CHANNELS IN/OUT CHANNELS IN/OUT CHANNELS IN/OUT
CD4052BMS VIEW
CHANNELS IN/OUT
OUT/IN CHANNELS IN/OUT
COMMON OUT/IN CHANNELS IN/OUT
COMMON OUT/IN CHANNELS IN/OUT
CD4053BMS VIEW
IN/OUT OUT/IN IN/OUT OUT/IN OUT/IN IN/OUT
Functional Diagrams
CHANNEL IN/OUT
LOGIC LEVEL CONVERSION
BINARY DECODER WITH INHIBIT
COMMON OUT/IN
INPUTS PROTECTED STANDARD CMOS PROTECTION NETWORK
CD4051BMS
7-938
CD4051BMS, CD4052BMS, CD4053BMS Functional Diagrams
(Continued)
CHANNELS IN/OUT
COMMON OUT/IN
LOGIC LEVEL CONVERSION BINARY DECODER WITH INHIBIT
COMMON OUT/IN
CHANNELS IN/OUT
CD4052BMS
INPUTS PROTECTED STANDARD CMOS PROTECTION NETWORK BINARY DECODERS WITH INHIBIT IN/OUT OUT/IN OUT/IN
LOGIC LEVEL CONVERSION
OUT/IN
CD4053BMS
7-939
Specifications CD4051BMS, CD4052BMS, CD4053BMS
Absolute Maximum Ratings
Supply Voltage Range, (VDD) -0.5V +20V (Voltage Referenced Terminals) Input Voltage Range, Inputs .-0.5V +0.5V Input Current, Input .±10mA Operating Temperature Range -55oC +125oC Package Types Storage Temperature Range (TSTG) -65oC +150oC Lead Temperature (During Soldering) +265oC Distance 1/16 1/32 Inch (1.59mm 0.79mm) from case Maximum
Reliability Information
Thermal Resistance Ceramic FRIT Package 80oC/W 20oC/W Flatpack Package 70oC/W 20oC/W Maximum Package Power Dissipation (PD) +125 -55oC +100oC (Package Type 500mW +100oC +125oC (Package Type Derate Linearity 12mW/oC 200mW Device Dissipation Output Transistor 100mW Full Package Temperature Range (All Package Types) Junction Temperature +175oC
TABLE ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP SUBGROUPS 18V, Input Leakage Current Input Leakage Current On-State Resistance Returned VSS/2 Threshold Voltage Threshold Voltage Functional (Note VNTH VPTH 10V, -10µA 10µA 2.8V, 20V, 18V, Input Voltage (Note Input Voltage High (Note Input Voltage (Note Input Voltage High (Note Channel Leakage Channel Channels (Common Out/In) IOZL thru VSS, |IIS| Channels thru VSS, |ISS|, <2µA Channels VOUT IOZH VOUT NOTES: voltages referenced device GND, 100% testing being implemented. Go/No test with limits applied inputs. LIMITS TEMPERATURE +25oC +125 -55oC +25oC +125oC -55oC +25oC +125oC -55oC +25oC +125oC -55oC +25oC +125oC -55oC +25oC +125oC -55oC +25oC +25oC +25oC +25oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC +125oC -55oC +25oC +125oC -55oC -0.1 -1.0 -0.1
PARAMETER Supply Current
SYMBOL
CONDITIONS (NOTE 20V,
-100 -1000 -100 -2.8
1000 1000 1050 1300 -0.7
UNITS
VDD/2 VDD/2
accuracy, voltage measured differentially VDD. Limit 0.050V max. 2.8V/3.0V, 200k 20V/18V,
7-940
Specifications CD4051BMS, CD4052BMS, CD4053BMS
TABLE ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP SUBGROUPS TEMPERATURE +25oC +125oC, -55oC LIMITS UNITS
PARAMETER Propagation Delay (Note Address Signal Channels Propagation Delay (Note Inhibit Signal (Channel Turning Propagation Delay (Note Inhibit Signal (Channel Turning Off) NOTES:
SYMBOL TPHL TPLH
CONDITIONS (Notes
TPZH TPZL
+25oC +125oC, -55oC
TPHZ TPLZ
+25oC +125oC, -55oC
-55oC +125oC limits guaranteed, 100% testing being implemented. 50pF, 10K, Input 20ns. TABLE ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL CONDITIONS NOTES TEMPERATURE -55oC, +25oC +125oC 10V, +125oC 15V, -55oC, +25oC +125oC Input Voltage Input Voltage High Propagation Delay Address Signal (Channels Off) TPHL TPLH 10V, |IIS|, On/Off Channel +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC +25oC
UNITS
Propagation Delay Inhibit Signal (Channel Turning
TPZH TPZL
-10V
+25oC +25oC +25oC +25oC +25oC +25oC +25oC
Propagation Delay Inhibit Signal (Channel Turning Off)
TPHZ TPLZ
-15V
Input Capacitance NOTES:
Address Inhibit Input
voltages referenced device GND. parameters listed Table controlled design process directly tested. These parameters characterized initial design release upon design changes which would affect these characteristics. 50pF, 10K, Input 20ns.
7-941
Specifications CD4051BMS, CD4052BMS, CD4053BMS
TABLE POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current Threshold Voltage Threshold Voltage Delta Threshold Voltage Threshold Voltage Delta Functional SYMBOL VNTH CONDITIONS 20V, 10V, -10µA 10V, -10µA 10µA 10µA 18V, Propagation Delay Time TPHL TPLH +25oC NOTES TEMPERATURE +25oC +25oC +25oC +25oC +25oC +25oC -2.8 VDD/2 -0.2 VDD/2 1.35 +25oC Limit UNITS
NOTES: voltages referenced device GND. 50pF, 200K, Input 20ns.
Table +25oC limit. Read Record
TABLE BURN-IN LIFE TEST DELTA PARAMETERS +25OC PARAMETER Supply Current MSI-2 Resistance SYMBOL RONDEL10 1.0µA Pre-Test Reading DELTA LIMIT
TABLE APPLICABLE SUBGROUPS CONFORMANCE GROUP Initial Test (Pre Burn-In) Interim Test (Post Burn-In) Interim Test (Post Burn-In) (Note Interim Test (Post Burn-In) (Note Final Test Group Group Subgroup Subgroup Group MIL-STD-883 METHOD 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 Sample 5005 Sample 5005 Sample 5005 Sample 5005 GROUP SUBGROUPS Deltas Deltas Deltas Subgroups Subgroups IDD, IOL5, IOH5A, RONDEL10 READ RECORD IDD, IOL5, IOH5A, RONDEL10 IDD, IOL5, IOH5A, RONDEL10 IDD, IOL5, IOH5A, RONDEL10
NOTE: Parameteric, Functional; Cumulative Static
TABLE TOTAL DOSE IRRADIATION MIL-STD-883 METHOD 5005 TEST PRE-IRRAD POST-IRRAD Table READ RECORD PRE-IRRAD POST-IRRAD Table
CONFORMANCE GROUPS Group Subgroup
TABLE BURN-IN IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND -0.5V 50kHz 25kHz
PART NUMBER CD4051BMS
7-942
Specifications CD4051BMS, CD4052BMS, CD4053BMS
TABLE BURN-IN IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION Static Burn-In Note Static Burn-In Note Dynamic BurnIn Note Irradiation Note OPEN GROUND -0.5V 50kHz 25kHz
PART NUMBER CD4052BMS Static Burn-In Note Static Burn-In Note Dynamic BurnIn Note Irradiation Note
PART NUMBER CD4053BMS Static Burn-In Note Static Burn-In Note Dynamic BurnIn Note Irradiation Note NOTE: Each except will have series resistor 0.5V Each except will have series resistor 47K± Group Subgroup sample size dice/wafer, failures, 0.5V
Typical Performance Characteristics
SUPPLY VOLTAGE (VDD VEE) CHANNEL RESISTANCE (RON) CHANNEL RESISTANCE (RON) INPUT SIGNAL VOLTAGE (VIS) +25oC -55oC AMBIENT TEMPERATURE (TA) +125oC -10.0 -7.5 +25oC -55oC AMBIENT TEMPERATURE (TA) +125oC SUPPLY VOLTAGE (VDD VEE)
-5.0
-2.5
10.0
INPUT SIGNAL VOLTAGE (VIS)
FIGURE TYPICAL CHANNEL RESISTANCE INPUT SIGNAL VOLTAGE (ALL TYPES)
FIGURE TYPICAL CHANNEL RESISTANCE INPUT SIGNAL VOLTAGE (ALL TYPES)
7-943
CD4051BMS, CD4052BMS, CD4053BMS Typical Performance Characteristics
AMBIENT TEMPERATURE (TA) +25oC SUPPLY VOLTAGE (VDD VEE)
(Continued)
CHANNEL RESISTANCE (RON)
CHANNEL RESISTANCE (RON)
SUPPLY VOLTAGE (VDD VEE)
AMBIENT TEMPERATURE (TA) +125oC
+25oC -55oC
-10.0 -7.5 -5.0 -2.5 10.0 INPUT SIGNAL VOLTAGE (VIS)
-10.0 -7.5
-5.0
-2.5
10.0
INPUT SIGNAL VOLTAGE (VIS)
FIGURE TYPICAL CHANNEL RESISTANCE INPUT SIGNAL VOLATGE (ALL TYPES)
OUTPUT SIGNAL VOLTAGE (VOS) SUPPLY VOLTAGE (VDD) AMBIENT TEMPERATURE (TA)
FIGURE TYPICAL CHANNEL RESISTANCE INPUT SIGNAL VOLTAGE (ALL TYPES)
POWER DISSIPATION/PACKAGE (PD) (µW) AMBIENT TEMPERATURE (TA) +25oC ALTERNATING PATTERN LOAD CAPICATANCE (CL) 50pF SUPPLY VOLTAGE (VDD) (15V) TEST CIRCUIT CD4029
LOAD RESISTANCE (RL) 100k, 1500
15pF
CD4051
INPUT SIGNAL VOLTAGE (VIS)
SWITCHING FREQUENCY (kHz)
FIGURE TYPICAL CHARACTERISTICS CHANNELS (CD4051BMS)
POWER DISSIPATION/PACKAGE (PD) (µW) AMBIENT TEMPERATURE (TA) +25oC ALTERNATING PATTERN LOAD CAPICATANCE (CL) 50pF SUPPLY VOLTAGE (VDD) (15V) TEST CIRCUIT CD4029
FIGURE TYPICAL DYNAMIC POWER DISSIPATION SWITCHING FREQUENCY (CD4051BMS)
POWER DISSIPATION/PACKAGE (PD) (µW) AMBIENT TEMPERATURE (TA) +25oC ALTERNATING PATTERN LOAD CAPICATANCE (CL) 50pF SUPPLY VOLTAGE (VDD) (15V)
TEST CIRCUIT CD4051
15pF
CD4051
15pF
SWITCHING FREQUENCY (kHz)
SWITCHING FREQUENCY (kHz)
FIGURE TYPICAL DYNAMIC POWER DISSIPATION SWITCHING FREQUENCY (CD4052BMS)
FIGURE TYPICAL DYNAMIC POWER DISSIPATION SWITCHING FREQUENCY (CD4053BMS)
7-944
CD4051BMS, CD4052BMS, CD4053BMS
+15V
+7.5V
7.5V
-7.5V -10V
ADDRESS (digital-control inputs) INHIBIT logic levels are: VDD. analog signal (through swing from
FIGURE TYPICAL BIAS VOLTAGES
7-945
CD4051BMS, CD4052BMS, CD4053BMS
TRUTH TABLE INPUT STATES CD4051BMS INHIBIT CD4052BMS INHIBIT CD4053BMS INHIBIT Don't Care
OUTPUT CLOCK
"ON" CHANNEL(S) NONE
20ns
20ns
TURN-ON TIME
NONE
tPZL
TURN-OFF TIME
tPLZ
FIGURE WAVEFORM, CHANNEL BEING TURNED
20ns 20ns
TURN-OFF TIME TURN-ON TIME tPZH
NONE
tPHZ
FIGURE WAVEFORM, CHANNEL BEING TURNED OFF,
OUTPUT CLOCK
CD4051
OUTPUT CLOCK
CD4052
CD4053 FIGURE PROPAGATION DELAY ADDRESS INPUT SIGNAL OUTPUT
7-946
CD4051BMS, CD4052BMS, CD4053BMS
OUTPUT 50pF CLOCK tPHL tPLH tPHL tPLH CLOCK 50pF OUTPUT
CD4051
CD4052
OUTPUT 50pF CLOCK tPHL tPLH
CD4053 FIGURE PROPAGATION DELAY INHIBIT INPUT SIGNAL OUTPUT
DIFFERENTIAL SIGNALS CD4052 CD4052
COMMUNICATIONS LINK
DIFF AMPLIFIER/ LINE DRIVER
DIFF RECEIVER
DIFF MULTIPLEXING
DEMULTIPLEXING
FIGURE TYPICAL TIME-DIVISION APPLICATION CD4052BMS
7-947
CD4051BMS, CD4052BMS, CD4053BMS Chip Dimensions Layouts
CD4051BMSH
CD4052BMSH
CD4053BMSH Dimensions parentheses millimeters derived from basic inch dimensions indicated. Grid graduations mils (10-3 inch)
METALLIZATION: Thickness: PASSIVATION: Silane
BOND PADS: 0.004 inches 0.004 inches THICKNESS: 0.0198 inches 0.0218 inches
7-948
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