Dual Filter HSP43168/883 Dual Filter consists independent 8-tap f

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Dual Filter HSP43168/883 Dual Filter consists independent 8-tap f

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HSP43168/883
Dual Filter
HSP43168/883 Dual Filter consists independent 8-tap filters. Each filter supports decimation from provides on-board storage sets coefficients. Block Diagram shows cells each separate coefficient bank separate inputs. outputs cells either summed multiplexed MUX/Adder. compute power Cells configured provide quadrature filtering, complex filtering, convolution, 1-D/2-D correlations, interpolating/decimating filters. cells take advantage symmetry coefficients pre-adding data samples prior multiplication. This allows 8-tap implemented using only multipliers filter cell. These cells configured either single 16-tap filter dual 8-tap filters. Asymmetric filtering also supported. Decimation provided boost effective number filter taps from times. Further, decimation registers provide delay necessary fractional data conversion filtering with kernels 16x16. flexibility Dual further enhanced sets user programmable coefficients. Coefficient selection changed asynchronously from clock clock. ability toggle between coefficient sets further simplifies applications such polyphase adaptive filtering. HSP43168 power fully static design implemented advanced CMOS process. configuration device controlled through standard microprocessor interface.
January 1994
Features
This Circuit Processed Accordance MIL-STD883 Fully Conformant Under Provisions Paragraph 1.2.1. Independent 8-Tap Filters Configurable Single 16-Tap 10-Bit Data Coefficients On-Board Storage Programmable Coefficient Sets Taps, Kernels, 20-Bit Data Coefficients Programmable Decimation Programmable Rounding Output Standard Microprocessor Interface 33MHz, 25.6MHz Versions
Applications
Quadrature, Complex Filtering Correlation Image Processing PolyPhase Filtering Adaptive Filtering
Ordering Information
PART NUMBER HSP43168GM-25/883 HSP43168GM-33/883 TEMPERATURE RANGE +125 -55oC +125oC
PACKAGE Lead Lead
Block Diagram
CIN0 CSEL0 CONTROL/ CONFIGURATION
COEFFICIENT BANK INA0 CELL
COEFFICIENT BANK
CELL
INB0 OUT0
ADDER OEL# OEH# CAUTION: These devices sensitive electrostatic discharge. Users should follow proper I.C. Handling Procedures. Copyright OUT9
Harris Corporation 1994
File Number
3177.2
3-169
HSP43168/883 Pinouts
VIEW
INB4 INB5 INB7 INB6 INB8 INB9 INA1
OUT15 OUT14 OUT12 OUT10 OUT11 INB1 OUT18 OUT16 OUT13 OUT9 INB0 INB2
OUT19 OUT17 OUT21 OUT20
OEL#
INB3
INA0 INA3
INA2 INA4
OUT24 OUT23 OUT25 OUT27 OUT22 OUT26
INA7 INA8
INA5 INA9
INA6
OEH#
CIN2
CIN1
CIN0
TXFR#
ACCEN FWRD CSEL0
CIN6
CIN3 CIN4
'A1'
SHFT MUX0 MUX1 RVRS#
CSEL2 CIN9
CIN7
CIN5
CSEL1 CSEL3 CSEL4 CIN8
BOTTOM VIEW
RVRS SHFT CSEL0 CIN8 CIN5 CIN4 'A1'
CSEL1 CSEL3 CSEL4 CSEL2 CIN9 CIN7 CIN6
MUX0 MUX1 FWRD ACCEN
TXFR# OEH#
CIN3
CIN2 INA8
CIN1 INA9
CIN0
OUT27 OUT22 OUT26
OUT24 OUT23 OUT25 OUT21 OUT20
INA7
INA5
INA6
INA3
INA4
OUT19 OUT17
OUT9
OEL# INB3
INA0
INA2
OUT18
OUT16 OUT13
INB0
INB2
INB4
INB7 INB5
INB8 INB6
INA1 INB9
OUT15 OUT14 OUT12 OUT10 OUT11 INB1
3-170
HSP43168/883 NAME NUMBER D11, K10, E10, L11, E1-3, C1-2, B1-3, A5-8, B6-8, C6-7 TYPE VCC: power supply pin. DESCRIPTION
Ground.
CIN0-9
Control/Coefficient Data Bus. Processor interface loading control data coefficients. CIN0 LSB. Control/Coefficient Address Bus. Processor interface addressing control coefficient registers. LSB. Control/Coefficient Write Clock. Data latched into control coefficient registers rising edge WR#. Coefficient Select. This input determines which coefficient sets used This input registered CSEL0 LSB. Input INA0
A0-8
CSEL0-4
A2-4,
INA0-9
J1-2, H1-2, G1-3, F2-3 L1-5, K2-3, K5-6, F9-11, G9-11, H10-11, J10-11, K11, K8-9, L6-10
INB0-9
Bidirectional Input INB0 input only.When used output, INB1-9 LSB's output bus. MSB's Output Bus. Data format either unsigned two's complement depending configuration. OUT27 MSB.
OUT9-27
SHFTEN#
Shift Enable. This active input enables shifting data through decimation registers. Forward Input Enable. When active low, data from forward decimation path input ALU's through input. When high, inputs ALUs zeroed. Reverse Input Enable. When active low, data from reverse decimation path input ALU's through input. When high, inputs ALUs zeroed. Data Transfer Control. This active input switches LIFO being read into reverse decimation path with LIFO being written from forward decimation path (see Figure Adder/Mux Control. This input controls data flow through output Adder/Mux. Table lists various configurations. Clock. inputs except those associated with processor interface (CIN0-9, A0-8, WR#) output enables (OEL#, OEH#) registered rising edge CLK. Output Enable Low. This tristate control enables LSB's output INB1-9 when OEL# low. Output Enable High. This tristate control enables OUT9-27 when OEH# low. Accumulate Enable. This active high input allows accumulation Cell Accumulator. this input latches Accumulator contents into Output Holding Registers while zeroing feedback path Accumulator.
FWRD#
RVRS#
TXFR#
MUX0-1
B9-10
OEL#
OEH# ACCEN
3-171
Specifications HSP43168/883
Absolute Maximum Ratings
Supply Voltage +8.0V Input, Output Voltage .GND-0.5V VCC+0.5V Storage Temperature Range -65oC +150oC Junction Temperature +175oC Lead Temperature (Soldering 10s) +300oC Classification Class
Reliability Information
Thermal Resistance Ceramic Package 33.5oC/W 7.5oC/W Maximum Package Power Dissipation +125oC Ceramic Packazge 1.49 Gate Count 32529 Gates
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
Operating Conditions
Operating Voltage Range +4.5V +5.5V Operating Temperature Range -55oC +125oC
TABLE ELECTRICAL PERFORMANCE CHARACTERISTICS Device Guaranteed 100% Tested GROUP SUBGROUPS LIMITS TEMPERATURE -55o 125oC -55o 125oC -55o 125oC -55o 125oC -55o 125oC -55o 125oC -55o 125oC -55o 125oC -55o 125oC UNITS
PARAMETER Logical Input Voltage Logical Zero Input Voltage Logical Input Voltage Clock Logical Zero Input Voltage Clock Output HIGH Voltage
SYMBOL
CONDITIONS 5.5V
4.5V
VIHC
5.5V
VILC
4.5V
-400µA VCC= 4.5V (Note +2.0mA VCC= 4.5V (Note 5.5V 5.5V 5.5V, Outputs Open 25.6MHz, GND, 5.5V (Note (Note
Output Voltage Input Leakage Current
Output Leakage Current
Standby Power Supply Current
ICCSB
Operating Power Supply Current
ICCOP
-55o 125oC
281.6
Functional Test NOTES:
-55o 125oC
Interchanging force sense conditions permitted. Operating Supply Current proportional frequency, typical rating 11mA/MHz. Tested follows: 1MHz, VIH(clock inputs) 3.4V, (all other inputs) 2.6V, 0.4V, 1.5V, 1.5V.
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Specifications HSP43168/883
TABLE ELECTRICAL PERFORMANCE CHARACTERISTICS Device Guaranteed 100% Tested GROUP SUBGROUPS (-33MHz) TEMPERATURE -55o +125oC -55o +125oC -55o +125oC -55o +125oC -55o +125oC -55o +125oC -55o +125oC -55o +125oC -55o +125oC -55o +125oC -55o +125oC -55o +125oC -55o +125oC (-25MHz) UNITS
PARAMETER Period High Period High Set-up Time; A0-8 Hold Time; A0-8 High Set-up Time; CIN0-9 High Hold Time; CIN0-9 High Set-up Time; Set-up Time; CIN0-9 Set-up Time; CSEL0-5, SHFTEN#, FWRD#, RVRS#, TXFR#, MUX0-1 High Hold Time; CSEL0-5, SHFTEN#, FWRD#, RVRS#, TXFR#, MUX0-1 High Output Delay OUT0-27 Output Enable Time NOTES:
SYMBOL TAWS
(NOTE CONDITIONS
TAWH
TCWS
TCWH
TWLCL
Note
TCVCL
Note
TECS
TECH
-55o +125oC
-55o +125oC -55o +125oC
Note
testing performed follows: Input levels (CLK Input) 4.0V Input levels (all other inputs) 3.0V Timing reference levels (CLK) 2.0V; others 1.5V. 4.5V 5.5V. Output load test load circuit with Output transition measured 1.5V 1.5V. Transition measured ±200mV from steady state voltage, Output loading test load circuit, 40pF. Set-up time requirements loading data CIN0-9 guarantee recognition following clock.
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Specifications HSP43168/883
TABLE ELECTRICAL PERFORMANCE CHARACTERISTICS (-33MHz) PARAMETER Input Capacitance Output Capacitance SYMBOL COUT CONDITIONS Open, measurements referenced device GND. NOTES TEMPERATURE +25oC +25oC -55o +125oC -55o +125oC -55o +125oC (-25MHz) UNITS
Output Disable Time Output Rise Time Output Fall Time NOTE:
From 0.8V 2.0V From 2.0V 0.8V
parameters Table controlled design process parameters directly tested. Characterized upon initial design after major process and/or design changes. Loading specified test load circuit with 40pF.
TABLE APPLICABLE SUBGROUPS CONFORMANCE GROUPS Initial Test Interim Test Final Test Group Groups METHOD 100%/5004 100%/5004 100% 100% Samples/5005 SUBGROUPS
Test Load Circuit
INCLUDES STRAY CAPACITANCE
1.5V
EQUIVALENT CIRCUIT
SWITCH OPEN ICCSB ICCOP TEST
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HSP43168/883 Waveforms
TECS CSEL0-4, MUX0-1 SHFTEN#, FWRD#, RVRS#, TXFR#, INA0-9, INB0-9 OUT0-27
TECH
TWLCL
TAWS A0-8
TAWH
TCWS CIN0-15
TCWH
TCVCL 1.5V 1.5V
OEL#, OEH#
1.7V OUT0-27 HIGH IMPEDANCE 1.3V
HIGH IMPEDANCE
OUTPUT ENABLE, DISABLE TIMING
2.0V 0.8V
2.0V 0.8V
OUTPUT RISE FALL TIMES
3-175
HSP43168/883 Burn-In Circuit
BOTTOM VIEW
RVRS CSEL0 'A1'
CSEL1 CSEL3 CSEL4 CIN8 CSEL2 CIN9 CIN7 CIN6 CIN5 CIN4 CIN3 CIN0 INA6 INA4
SHFT MUX0 MUX1 TXFR# FWRD OEH# ACCEN
CIN2 INA8
CIN1 INA9
OUT27 OUT22 OUT26
OUT24 OUT23 OUT25 OUT21 OUT20
INA7
INA5 INA3
OUT19 OUT17 OUT18 OUT16 OUT13
OUT9
OEL# INB3 INB0 INB2 INB4 INB7 INB5
INA0 INB8 INB6
INA2 INA1 INB9
OUT15 OUT14 OUT12 OUT10 OUT11 INB1
NOTES: VCC/2 (2.7V ±10%) used outputs only. (±20%) resistor connected pins except ±0.5V. 0.1µf (Min) capacitor between position. NAME CIN8 CSEL4 CSEL3 CSEL1 RVRS CIN5 CIN7 CIN9 CSEL2 MUX1 MUX0 BURN-IN SIGNAL NAME SHFTEN CIN4 CIN6 CSEL0 FWRD TXFR CIN3 ACCEN CIN0 CIN1 CIN2 OEHB INA9 INA8 BURN-IN SIGNAL
100KHz ±10%, F0/2, F1/2. F15/2, duty cycle. Input voltage limits: 0.8V Max, ±10%
NAME SUM26 SUM22 SUM27 INA6 INA5 INA7 SUM25 SUM23 SUM24 INA4 INA3 SUM20 SUM21 INA2 INA0 INB3 OELB SUM9 SUM17 SUM19 INA1
BURN-IN SIGNAL VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2
NAME INB8 INB7 INB2 INB0 SUM13 SUM16 SUM18 INB9 INB6 INB5 INB4 INB1 SUM11 SUM10 SUM12 SUM14 SUM15
BURN-IN SIGNAL VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2
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HSP43168/883 Metallization Topology
DIMENSIONS: 1mils METALLIZATION: Type: Si-Al Si-Al-Cu Thickness: GLASSIVATION: Type: Nitrox Thickness: WORST CASE CURRENT DENSITY: 1.93 A/cm2
Metallization Mask Layout
HSP43168/883
CSEL4 CSEL3 CSEL2 CSEL1 CSEL0 MUX1 CIN9 MUX0 CIN8
CIN7 CIN6 CIN5 CIN4 CIN3 CIN2 CIN1 CIN0 INA9 INA8
RVRS# FWD# SHIFTEN# TXFR# ACCEN
OEH# OUT27
INA7 OUT26 INA6 INA5 INA4 INA3 INA2 INA1 INA0 INB9 OUT25 OUT24 OUT23 OUT22 OUT21 OUT20 OUT19 OUT18 OUT17
OUT9
OUT10
OUT12
OUT13
OUT14
OUT15
OUT16
INB8
INB7
INB6
INB5
INB4
INB3
INB2
INB1
INB0
OEL#
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OUT11
HSP43168/883 Packaging
GRID ARRAY (PGA)
LEAD MATERIAL: Type LEAD FINISH: Type PACKAGE MATERIAL: Ceramic, AI2O3 PACKAGE SEAL: Material: Gold/Tin Temperature: 320oC 10oC Method: Furnace Braze
INTERNAL LEAD WIRE: Material: Aluminum Diameter: 1.25 Bonding Method: Ultrasonic Wedge COMPLIANT OUTLINE: 38510-P-AC
NOTE:
Dimensions
Dimensions inches.
Mil-M-38510 Compliant Materials, Finishes Dimensions
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HSP43168/883
Dual Filter
DESIGN INFORMATION
April 1995
information contained this section been developed through characterization Harris Semiconductor application design informiation only. guarantee implied.
Functional shown Figure 1.0, HSP43168 consists 4-multiplier filter cells which process data coefficients. cells operate independent 8-tap filters 4-tap asymmetric filters maximum rates. single filter mode provided which allows cells operate 16-tap filter 8-tap asymmetric filter. board coefficient storage sets coefficients provided. coefficient sets user selectable programmed through microprocessor interface. Programmable decimation also provided. utilizing decimation registers together with coefficient sets, polyphase filters realizable which allow user trade data rate filter taps. MUX/ Adder configured either multiplex outputs filter cells depending upon whether cells operating single dual filter mode. addition, shifter MUX/Adder provided implementation filters with data coefficients vice versa. LSB's control word loaded address 001H used configure format cell's data coefficients. programmed enable disable reversal data sample order prior entering backward shifting decimation registers. Bits used support programmable rounding output.
TABLE CONTROL ADDRESS 000H BITS FUNCTION Decimation Factor Mode Select Odd/Even Symmetry odd/even taps odd/even taps Input Source Used DESCRIPTION 0000=No Decimation 1111=Decimation Single FIlter Mode Dual FIlter Mode Even symmetric coefficients symmetric coefficients number taps filter Even number taps filter (Defined same above) Input from INA0-91 Input from INB0-9 proper operation
Microprocessor Interface
Dual write only microprocessor interface loading data into Control Block Coefficient Bank. interface consists 10-bit data (CIN0-9), address (A0-8), write input (WR#) latch data into on-board registers. control coefficient data loaded asynchronously CLK.
Control Block
Dual configured writing registers within Control Block. These registers memory mapped address 000H Hexadecimal) 001H A0-8. format these registers shown Table Table Writing Control/Configuration registers causes reset which lasts cycles following assertion WR#. reset caused writing registers Control Block will clear contents Coefficient Bank. LSBs control word loaded address 000H used select decimation factor. example, LSBs programmed with value 0010, forward reverse shifting decimation registers each configured with delay used select whether cells operate independent filters extended length filter. Coefficient symmetry selected Bits programmed configure cells even filter lengths. selects input source when cells configured independent operation. must programmed
BITS FUNCTION
TABLE CONTROL ADDRESS 001H DESCRIPTION Unsigned Two's Complement (Defined same input) (Defined same input) (Defined same input) Enabled Disabled 0000 2-10 1011 Enabled Disabled
Input Format Coefficient Format Input Format Coefficient Data Reversal Enable Round Position Round Enable
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HSP43168
FIGURE DUAL FILTER
3-180
HSP43168
DESIGN INFORMATION (Continued)
information contained this section been developed through characterization Harris Semiconductor application design informiation only. guarantee implied.
Filter Cells
Each filter cell based array four 11x10 two's complement multipliers. multipliers input from ALUs which combine data shifting through forward backward decimation registers. second input comes from user programmable coefficient bank. multiplier outputs feed accumulator whose result passed output section where multiplexed added.
applications which require sample order reversal, cells must configured with data reversal disabled (see Table addition, TXFR# must asserted ensure proper data flow. this configuration, data backward shifting decimation path routed though delay stage instead ping-pong LIFO's. number registers delay stage based programmed decimation factor. Note: data reversal must disabled TXFR# must asserted filtering applications which decimation. shifting data through forward reverse decimation registers enabled asserting SHFTEN# input. When SHFTEN# transitions high, data shifting disabled, data sample latched into part previous clock last input forward decimation path. When SHFTEN# asserted, shifting data through decimation paths enabled. data sample part input when SHFTEN# asserted will next data sample into forward decimation path. When operating cells independent filters, receives input data INA0-9 receives data from either INA0-9 INB0-9 depending configuration (Table When cells configured single extended length filter, forward backward decimation paths cascaded. this mode, data transferred from forward decimation path back- ward decimation path Data Feedback Circuitry Thus, manner which data read into backward shifting decimation path determined configuration. When decimation paths cascaded, data routed through delay stage Data Feedback Circuitry. configuration cells even length filters determines point forward decimation path from which data multiplexed Data Feedback Circuitry. example, cell configured length filter, data prior last register third forward decimation stage routed Feedback Circuitry. cell configured even length filter, data output from third forward decimation stage multiplexed Feedback Circuitry. This required insure proper data alignment with symmetric filter coefficients (See Application Examples).
Decimation Registers
forward backward shifting registers configurable decimation (see Table backward shifting registers used take advantage symmetry linear phase filters aligning data ALU's preaddition prior multiplication common coefficient. When cells configured single filter mode, decimation registers each cell cascaded. This lengthened delay path allows computation filter which twice size that capable single cell. decimation registers also provide data storage poly-phase filtering applications (See Applications Examples section). Data Feedback Circuitry each cell responsible transferring data from forward backward shifting decimation registers. This circuitry feeds blocks samples into backward shifting decimation path either reversed non-reversed sample order. MUX/DEMUX structure input Feedback Circuitry routes data LIFO's delay stage depending configuration. Feedback Circuitry Output selects storage element which feeds backward shifting decimation registers. applications requiring reversal sample order, such filtering with decimation, cells configured with data reversal enabled (see Table this mode, data transferred from forward backward shifting registers through ping-ponged LIFO structure. While LIFO being read into backward shifting path, other written with data samples. MUX/DEMUX controls which LIFO being written, Feedback Circuitry output controls which LIFO being read. TXFR# SHIFTEN#, switches LIFO's being read written, which causes block data read from structure reversed sample order (See Example Application Examples section). frequency with which TXFR# asserted determines size data blocks which sample order reversed. example, TXFR# asserted once every three CLK's, blocks data samples with order reversed, would into backward decimation registers. Note: altering frequency phase TXFR# assertion once filtering operation been started will cause unknown results.
ALUs
Data shifting through forward reverse decimation path feeds inputs ALUs respectively. ALU's perform "b+a" operation cell configured even symmetric coefficients "b-a" operation configured symmetric coefficients. applications which pre-add subtract required, input zeroed disabling FWRD# RVRS# respectively. This effect pro-
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HSP43168
DESIGN INFORMATION (Continued)
information contained this section been developed through characterization Harris Semiconductor application design informiation only. guarantee implied.
ducing output which either "a", "-a", depending filter symmetry chosen. example, cell configured even symmetric filter with FWRD# RVRS# high, data shifting through forward decimation registers would appear output. Coefficient Bank output multiplied coefficient from user programmable coefficient sets. Each consists coefficients coefficients active coefficient selected using CSEL0-4. coefficient switched every clock support polyphase filtering operations. coefficients loaded into on-board registers using microprocessor interface, CIN0-9, A0-8, WR#. Each multiplier within Cells driven coefficient bank with coefficients. These coefficients addressed shown Table inputs A0-1 specify Coefficient Bank four multipliers each Cell; specifies Cell Bits A7-3 specify sets which coefficient stored. example, address 10dH would access coefficient second multiplier second coefficient set.
TABLE A7-3 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx A0-1 BANK
Mux/Adder controlled MUX0-1 inputs shown Table Applications requiring data coefficients data coefficients made possible configuring MUX/Adder scale output 2-10 prior summing with When Dual configured independent filters, MUX0-1 inputs would used multiplex filter outputs each cell. applications which configured single filter, MUX/Adder configured output each cell.
TABLE MUX0-1 DECODING MUX0-1 OUT0-27 FIRA FIRB (FIR Scaled 2-10) FIRA FIRB FIRA FIRB
Input/Output Formats
Dual supports mixed mode arithmetic with both unsigned two's complement data coefficients. input output formats both data types shown low. Dual configured even symmetric filter with unsigned data coefficients, output will unsigned. Otherwise, output will two's complement.
INPUT DATA FORMAT INA0-9, INB0-9 FRACTIONAL TWO'S COMPLEMENT .2-1
OUTPUT DATA FORMAT OUT9-27 FRACTIONAL TWO'S COMPLEMENT
Cell Accumulator
registered outputs from multipliers each cell feed cell's accumulator. ACCEN input controls each accumulator's running latching data from accumulator into Output Holding Registers. When ACCEN low, feedback from accumulator adder zeroed which disables accumulation. Also, output from accumulator latched into Output Holding Registers. When ACCEN asserted, accumulation enabled contents Output Holding Registers remain unchanged.
.2-1
OUTPUT DATA FORMAT OUT0-8 FRACTIONAL TWO'S COMPLEMENT 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18
Output MUX/Adder
contents each Cell's Output Holding Register summed multiplexed Mux/Adder. operation
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HSP43168
DESIGN INFORMATION (Continued)
information contained this section been developed through characterization Harris Semiconductor application design informiation only. guarantee implied.
INPUT DATA FORMAT INA0-9, INB0-9 FRACTIONAL UNSIGNED
HSP43168
.2-1
INA0-9
OUT9-27
INB0-9
OUTPUT DATA FORMAT OUT9-27 FRACTIONAL UNSIGNED
FIGURE USING HSP43168 INDEPENDENT FILTERS
OUTPUT DATA FORMAT OUT0-8 FRACTIONAL UNSIGNED 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18
Figure order data samples within filter cell shown numbers forward backward shifting decimation paths. output filter cell given equation bottom each block diagram. Figure shows data sample alignment pre-adders data/coefficient alignment shown Figure
h(n)
MUX/Adder configured implement programmable rounding locations 2-10 through round implemented adding specified location (see Table 2.0). example, configure part such that output rounded MSBs, OUT18-27, round position would chosen 2-1.
x(n)
Application Examples
this section number examples which show even, odd, symmetric, asymmetric decimating filters presented. These examples intended show different operational modes HSP43168. examples based dual filter configuration. However, same principles apply when part configured with both cells operating single filter. Example Even-Tap Symmetric Filter Example HSP43168 configured independent 8-tap symmetric filters shown block diagram Figure Each cells takes advantage symmetric filter coefficients pre-adding data samples common given coefficient. result, each cell implement 8-tap symmetric filter using only four multipliers. Similarly, when HSP43168 configured single filter mode 16-tap symmetric filter possible using multipliers both cells. operation cell better understood comparing data coefficient alignment given filter output, Figure with data flow through cell, shown Figure block diagrams Figure simplification cell shown Figure simplicity, ALU's Cell Accumulators were replaced adders, pipeline delay registers were omitted.
FIGURE DATA/COEFFICIENT ALIGNMENT 8-TAP EVEN SYMMETRIC FILTER
dual filter application configured writing 1d0H address 000H microprocessor interface, CIN0-9, A08, WR#. Since this application does decimation, control register address 001H must disable data reversal (see Table Failure disable data reversal will produce erroneous results.
DATA FLOW DATA SAMPLE CLOCKED INTO FEED FORWARD STAGE.
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HSP43168
DESIGN INFORMATION (Continued)
information contained this section been developed through characterization Harris Semiconductor application design informiation only. guarantee implied.
DATA FLOW DATA SAMPLE CLOCKED INTO FEED FORWARD STAGE.
Example Odd-Tap Symmetric Filter Example HSP43168 configured independent 7-tap symmetric filters with functional block diagram resembling Figure 8-tap filter example, HSP43168 implements filtering operation summing data samples sharing common coefficient prior multiplication that coefficient. However, length filters pre-addition requires that center coefficient scaled 1/2. operation cell length filters better understood comparing data/coefficient alignment Figure with data flow diagrams Figure block diagrams Figure simplification cell shown Figure
h(n)
DATA FLOW DATA SAMPLE CLOCKED INTO FEED FORWARD STAGE.
x(n)
FIGURE DATA/COEFFICIENT ALIGNMENT 7-TAP SYMMETRIC FILTER
FIGURE DATA FLOW DIAGRAMS 8-TAP SYMMETRIC FILTER
length filters, proper data/coefficient alignment ensured routing data entering last register third forward decimation stage backward shifting registers. this configuration, center coefficient must scaled compensate summation same data sample from both forward backward shifting registers.
DATA FLOW DATA SAMPLE CLOCKED INTO FEED FORWARD STAGE.
Using this architecture, only unique coefficients need stored Coefficient Bank. example, above filter would stored first coefficient writing address 100H, 101H, 102H, 103H respectively. write same filter first coefficient address sequence would change 104H, 105H, 106H, 107H. operate HSP43168 this mode, TXFR# tied ensure proper data flow; both FWRD# RVRS# tied enable data samples from forward reverse data paths ALU's pre-adding; ACCEN tied prevent accumulation over multiple CLK's; SHFTEN# tied allow shifting data through decimation registers; MUX0-1 programmed multiplex output either CSEL0-4 pro- grammable access stored coefficient set, this ample CSEL 0000.
C3/2
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HSP43168
DESIGN INFORMATION (Continued)
information contained this section been developed through characterization Harris Semiconductor application design informiation only. guarantee implied.
DATA FLOW DATA SAMPLE CLOCKED INTO FEED FORWARD STAGE.
example, only unique coefficients need stored Coefficient Bank. These coefficients stored first coefficient writing address 100H, 101H, 102H, 103H respectively. write same filter first coefficient address sequence would change 104H, 105H, 106H, 107H. control signals TXFR#, FWRD#, RVRS#, ACCEN, SHFTEN#, CSEL0-4 controlled described Example Example Asymmetric Filter Example
C3/2
cells within HSP43168 each calculate asymmetric taps each clock. Thus, single cell implement 8-tap asymmetric filter HSP43168 clocked twice input data rate. Similarly, Dual configured single filter, asymmetric filter realizable. this example, cells configured 8-tap asymmetric filters which clocked twice input data rate. data shifted into forward backward decimation paths every other assertion SHFTEN#. filter output computed passing data from each decimation path multipliers alternating clocks. sets coefficients required, data forward decimation path, data reverse path. filter output generated accumulating multiplier outputs CLKs. operation this configuration better understood comparing data/coefficient alignment Figure with data flow diagrams Figure ALU's have been omitted from cell diagrams because data multipliers directly from forward reverse decimation paths. data samples within cell shown numbers decimation paths.
h(n)
DATA FLOW DATA SAMPLE CLOCKED INTO FEED FORWARD STAGE.
C3/2
FIGURE DATA FLOW DIAGRAMS 7-TAP SYMMETRIC FILTER.
data flow diagrams Figure order data samples input filter cell shown numbers forward backward shifting decimation paths. output filter cell given equation bottom block. diagram Figure shows data sample alignment pre-adders data/coefficient alignment shown Figure This dual filter application configured writing 110H address 000H microprocessor interface, CIN0-9, A08, WR#. Also, data reversal must disabled setting control register address 0001H. 8-tap
x(n)
FIGURE DATA/COEFFICIENT ALIGNMENT 8-TAP ASYMMETRIC FILTER
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HSP43168
DESIGN INFORMATION (Continued)
information contained this section been developed through characterization Harris Semiconductor application design informiation only. guarantee implied.
DATA SHIFTING DISABLED, BACKWARD SHIFTING DECIMATION REGISTERS FEEDING MULTIPLIERS.
SHIFTING DATA SAMPLE INTO CELL ENABLED, FORWARD SHIFTING REGISTERS FEEDING MULTIPLIERS
ACCUMULATOR
ACCUMULATOR
(X0)C0+(X1)C1+(X2)C2+(X3)C3
(X1)C0+(X2)C1+(X3)C2+(X4)C3 +(X8)C7+(X7)C6+(X6)C5+(X5)C4
SHIFTING DATA SAMPLE INTO CELL ENABLED, FORWARD SHIFTING REGISTERS FEEDING MULTIPLIERS.
FIGURE DATA FLOW DIAGRAMS 8-TAP ASYMMETRIC FILTER CONTINUED
ACCUMULATOR
this application, each filter cell configured length filter writing 110H control register address 000H. Even though even filter being implemented, filter cells must configured length ensure proper data flow. Also, control address 001H must disable data reversal, TXFR# must tied low. Since 8-tap asymmetric filter being implemented, sets coefficients must stored. These eight coefficients could loaded into first coefficient sets writing address 100H, 101H, 102H, 103H, 108H, 109H, 10aH, 10bH respectively. products required this 8-tap filter require dynamic control over FWRD#, RVRS#, ACCEN, CSEL0- relative timing these signals shown Figure
INA0-9
(X0)C0+(X1)C1+(X2)C2+(X3)C3 +(X7)C7+(X6)C6+(X5)C5+(X4)C4
DATA SHIFTING DISABLED, BACKWARD SHIFTING DECIMATION REGISTERS FEEDING MULTIPLIERS.
CSEL0-4
ACCEN FWRD#
RVRS# ACCUMULATOR SHFTEN#
(X1)C0+(X2)C1+(X3)C2+(X4)C3
FIGURE CONTROL TIMING 8-TAP ASYMMETRIC FILTER
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HSP43168
DESIGN INFORMATION (Continued)
information contained this section been developed through characterization Harris Semiconductor application design informiation only. guarantee implied.
Example Even-Tap Decimating Filter Example HSP43168 supports filtering applications requiring decimation these applications output data rate reduced factor result, clock cycles used computation filter output. example, each cell calculate symmetric asymmetric taps clock. application requires decimation two, filter output calculated over clocks thus boosting number taps cell symmetric asymmetric. this example, each cell configured independent 24-tap decimate filter. alignment data relative filter coefficients particular output depicted graphically Figure previous examples, HSP43168 implements filtering operation summing data samples prior multiplication common coefficient. this example output required every third which allows CLK's computation. each CLK, three sets coefficients used calculate filter taps. block diagrams Figure show data flow accumulator output data/ coefficient alignment Figure
COMPUTATIONAL FLOW DATA SAMPLE CLOCKED INTO FEED FORWARD STAGE
ACCUMULATOR
COMPUTATIONAL FLOW DATA SAMPLE CLOCKED INTO FEED FORWARD STAGE
h(n)
ACCUMULATOR
x(n)
COMPUTATIONAL FLOW DATA SAMPLE CLOCKED INTO FEED FORWARD STAGE
FIGURE DATA/COEFFICIENT ALIGNMENT 24-TAP DECIMATE FILTER
Proper data coefficient alignment achieved asserting TXFR# once every three CLK's switch LIFO's which being read written. This effect feeding blocks three samples into backward shifting decimation path which reversed sample order. addition, ACCEN de-asserted once every three clocks allow accumulation over three CLK's. three sets coefficients required calculation 24-tap symmetric filter cycled through using CSEL0-4. timing relationship between CSEL0-4, ACCEN, TXFR# shown Figure
ACCUMULATOR
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HSP43168
DESIGN INFORMATION (Continued)
information contained this section been developed through characterization Harris Semiconductor application design informiation only. guarantee implied.
operate this mode Dual configured writing address 000H microprocessor interface, CIN0-9, A0-8, WR#. Data reversal must enabled (Table 2.0). unique coefficients this example stored three sets coefficients either cell. coefficients loaded into Coefficient Bank writing C11, C10, address 100H, 101H, 102H, 103H, 108H, 109H, 10aH, 10bH, 110H, 111H, 112H, 113H respectively.
COMPUTATIONAL FLOW DATA SAMPLE CLOCKED INTO FEED FORWARD STAGE
24-tap example, output required every third which allows CLK's computation. each CLK, three sets coefficients used calculate filter taps. Since this length filter, center coefficient must scaled compensate summation same data sample from forward backward shifting decimation paths.The block diagrams Figure show data flow accumulator output data coefficient alignment Figure Proper data coefficient alignment achieved asserting TXFR# once every three CLK's switch LIFO's which being read written. length filters, data prior last register forward decimation path routed Feedback Circuitry. result, TXFR# should asserted cycle prior input data samples which align with center tap. timing relationship between CSEL0-5, ACCEN, TXFR# shown Figure
h(n)
ACCUMULATOR
x(n)
FIGURE DATA FLOW DIAGRAMS 24-TAP DECIMATE FILTER
FIGURE DATA/COEFFICIENT ALIGNMENT 23-TAP DECIMATE SYMMETRIC FILTER
CSEL0-4 ACCEN TXFR# C11/2
COMPUTATIONAL FLOW DATA SAMPLE CLOCKED INTO FEED FORWARD STAGE
INA0-9
FIGURE CONTROL SIGNAL TIMING 24-TAP DECIMATE FILTER
Example Odd-Tap Decimating Symmetric Filter This example highlights HSP43168 dependent, 23-tap, symmetric, decimate filters. this example, operational differences control signals data reversal structure compared previously discussed even-tap decimating filter.
ACCUMULATOR
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HSP43168
DESIGN INFORMATION (Continued)
information contained this section been developed through characterization Harris Semiconductor application design informiation only. guarantee implied.
COMPUTATIONAL FLOW DATA SAMPLE CLOCKED INTO FEED FORWARD STAGE
COMPUTATIONAL FLOW DATA SAMPLE CLOCKED INTO FEED FORWARD STAGE
C11/2
ACCUMULATOR
ACCUMULATOR
FIGURE DATA FLOW DIAGRAMS 23-TAP DECIMATE SYMMETRIC FILTER
COMPUTATIONAL FLOW DATA SAMPLE CLOCKED INTO FEED FORWARD STAGE
INA0-9 CSEL0-5
ACCEN TXFR#
ACCUMULATOR
FIGURE CONTROL SIGNAL TIMING 23-TAP SYMMETRIC FILTER
operate this mode, Dual configured writing 132H address 000H microprocessor interface, CIN0-9, A0-8, WR#. Data reversal must enabled (see Table 2.0). unique coefficients this example stored three sets coefficients either cell. coefficients loaded into Coefficient Bank writing (C11)/ C10, address 100H, 101H, 102H, 103H, 108H, 109H, 10aH, 10bH, 110H, 111H, 112H, 113H respectively.
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Dual Filter HSP43168/883 Dual Filter consists independent 8-tap f

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