4096 CMOS HM-6504/883 4096 static CMOS fabricated using self-alig
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HM-6504/883
4096 CMOS
HM-6504/883 4096 static CMOS fabricated using self-aligned silicon gate technology. device utilizes synchronous circuitry achieve high performance power operation. On-chip latches provided addresses, data input data output allowing efficient interfacing with microprocessor systems. data output forced high impedance state expanded memory arrays. Gated inputs allow lower operating current also eliminate need pull pull down resistors. HM-6504/883 fully static maintained state indefinite period time. Data retention supply voltage supply current guaranteed over temperature.
March 1997
Features
This Circuit Processed Accordance MIL-STD883 Fully Conformant Under Provisions Paragraph 1.2.1. Power Standby 125µW Power Operation 35mW/MHz Data Retention 2.0V Compatible Input/Output Three-State Output Standard JEDEC Pinout Fast Access Time. 120/200ns Package High Density On-Chip Address Register Gated Inputs Pull Pull Down Resistors Required
Ordering Information
PACKAGE CERDIP TEMPERATURE RANGE -55oC +125oC 200ns HM1-6504B/883 300ns HM1-6504/883 PKG. F18.3
Pinout
HM-6504/883 (CERDIP) VIEW
DESCRIPTION Address Input Chip Enable Write Enable Data Input Data Output
CAUTION: These devices sensitive electrostatic discharge. Users should follow proper Handling Procedures. Copyright
Harris Corporation 1997
File Number
2993.1
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HM-6504/883 Functional Diagram
LATCHED ADDRESS REGISTER GATED DECODER GATED COLUMN DECODER DATA MATRIX
LATCH
LATCH
LATCH
LATCHED ADDRESS REGISTER
LATCH
NOTES: lines active high-positive logic. Three-state Buffers: high output active. Control Data Latches: latches rising edge Address Latches: Latch falling edge Gated Decoders: Gate rising edge
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HM-6504/883
Absolute Maximum Ratings
Supply Voltage +7.0V Input, Output Voltage -0.3V +0.3V Classification Class
Thermal Information
Thermal Resistance CERDIP Package 75oC/W 15oC/W Maximum Storage Temperature Range .-65oC +150oC Maximum Junction Temperature +175oC Maximum Lead Temperature (Soldering 10s) +300oC
Characteristics
Gate Count 6910 Gates
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
Operating Conditions
Operating Voltage Range +4.5V +5.5V Operating Temperature Range -55oC +125oC Input Voltage .-0.3V +0.8V Input High Voltage -2.0V +0.3V
TABLE HM-6504/883 ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed 100% Tested LIMITS PARAMETER Output Voltage SYMBOL (NOTE CONDITIONS 4.5V, 4.5V, -1.0mA 5.5V, 5.5V, 2.0V, VCC, 5.5V, (Note 1MHz, 5.0V, -0.3V, GROUP SUBGROUPS TEMPERATURE -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC UNITS
Output High Voltage
Input Leakage Current
-1.0
+1.0
Output Leakage Current
-1.0
+1.0
Data Retention Supply Current
ICCDR
Operating Supply Current
ICCOP
Standby Supply Current
ICCSB
-55oC +125oC
NOTES: voltage referenced device GND. Typical derating 1.5mA/MHz increase ICCOP.
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HM-6504/883
TABLE HM-6504/883 ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed 100% Tested LIMITS (NOTES CONDITIONS 5.5V 5.5V, Note 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V GROUP SUBGROUPS TEMPERATURE -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC HM-6504S/883 HM-6504B/883
HM-6504/883
UNITS
PARAMETER Chip Enable Access Time Address Access Time Chip Enable Pulse Negative Width Chip Enable Pulse Positive Width Address Setup Time Address Hold Time Write Enable Pulse Width Write Enable Pulse Setup Time Early Write Pulse Setup Time Early Write Pulse Hold Time Data Setup Time Early Write Data Setup Time Data Hold Time Early Write Data Hold Time Read Write Cycle Time
SYMBOL
TELQV TAVQV TELEH
TEHEL
TAVEL TELAX TWLWH (10) TWLEH
(11) TWLEL (13) TELWH (14) TDVWL (15) TDVEL (16) TWLDX (17) TELDX (18) TELEL
NOTES:
voltages referenced device GND. Input pulse levels: 0.8V VCC-2.0V; Input rise fall times: (max); Input output timing reference level: 1.5V; Output load: 1TTL gate equivalent, 50pF (min) greater than 50pF, access time derated 0.15ns TAVQV TELQV TAVEL.
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HM-6504/883
TABLE HM-6504/883 ELECTRICAL PERFORMANCE SPECIFICATIONS HM-6504S/883 LIMITS PARAMETER Input Capacitance SYMBOL CONDITIONS Open, 1MHz, Measurements Referenced Device Ground Open, 1MHz, Measurements Referenced Device Ground
5.5V
NOTE
TEMPERATURE +25oC
UNITS
Output Capacitance
+25oC
Chip Enable Output Disable Time Chip Enable Output Disable Time
TELQX
-55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC
TEHQZ
5.5V HM-6504S/883 5.5V HM-6504B/883 5.5V HM-6504/883
Write Enable Read Mode Setup Time
(12)
TWHEL
5.5V
High Level Output Voltage NOTE:
VOHL
4.5V, -100µA
-55oC +125oC
parameters listed Table controlled design, process parameters characterized upon initial design after major process and/or design changes.
TABLE APPLICABLE SUBGROUPS CONFORMANCE GROUPS Initial Test Interim Test Final Test Group Groups METHOD 100%/5004 100%/5004 100%/5004 100%/5004 Samples/5005 Samples/5005 SUBGROUPS
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HM-6504/883 Timing Waveforms
TAVEL TEHEL TELQV TELQX TELAX TAVEL NEXT TELEH TELEL (18) TEHEL
VALID
TEHQZ VALID DATA OUTPUT
HIGH HIGH TIME REFERENCE
HIGH
FIGURE READ CYCLE TRUTH TABLE INPUTS TIME REFERENCE OUTPUT Memory Disabled Cycle Begins, Addresses Latched Output Enabled Output Valid Read Accomplished Prepare Next Cycle (Same Cycle Ends, Next Cycle Begins (Same FUNCTION
address information latched on-chip registers falling edge Minimum address hold time requirements must met. After required hold time, addresses change state without affecting device operation. During time output becomes
enabled data valid until during time must remain high read cycle. After output data been read, return high This will disable output buffer input, ready next memory cycle
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HM-6504/883 Timing Waveforms (Continued)
TAVEL TEHEL (11) (13) TWLEL TELWH (15) TDVEL HIGH-Z TIME REFERENCE (17) TELDX (15) TDVEL NEXT DATA HIGH-Z (11) TWLEL TELAX TAVEL NEXT (18) TELEL TELEH
VALID
TEHEL
DATA VALID
FIGURE EARLY WRITE CYCLE TRUTH TABLE INPUTS TIME REFERENCE OUTPUT Memory Disabled Cycle Begins, Addresses Latched Write Progress Internally Write Completed Prepare Next Cycle (Same Cycle Ends, Next Cycle Begins (Same FUNCTION
early write cycle only cycle where output guaranteed become active. falling edge addresses, write signal, data input latched on-chip registers. logic value time falls determines state output buffer that cycle. Since when falls, output buffer latched into high impedance state will remain that
state until returns high this cycle, data input latched going low; therefore, data hold times should referenced When returns high state, output buffer inputs disabled signals unlatched. device ready next cycle.
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HM-6504/883 Timing Waveforms (Continued)
TAVEL TELAX TAVEL NEXT (18) TELEL TELEH TEHEL TWLWH (14) TDVWL TELQX HIGH DATA VALID TEHQZ HIGH (16) TWLDX (10) TWLEH TEHEL
VALID
TIME REFERENCE
FIGURE LATE WRITE CYCLE TRUTH TABLE INPUTS TIME REFERENCE OUTPUTS Memory Disabled Cycle Begins, Addresses Latched Write Begins, Data Latched Write Progress Internally Write Completed Prepare Next Cycle (Same Cycle Ends, Next Cycle Begins (Same FUNCTION
late write cycle cross between early write cycle read-modify-write cycle. Recall that early write, output guaranteed remain high impedance, read-modify-write, output guaranteed valid access time. late write
between these cases. With this cycle output become active, become valid data, remain active undefined. Valid data written into data setup, data hold, write setup write pulse widths observed.
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HM-6504/883 Test Load Circuit
(NOTE
1.5V
EQUIVALENT CIRCUIT
NOTE: Test head capacitance includes stray capacitance.
Burn-In Circuit
HM-6504/883 CERDIP
NOTES: resistors ±5%. 100kHz ±10%. 5.5V ±0.5V. 4.5V ±10%. -0.2V +0.4V. 0.01µF Min.
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HM-6504/883 Characteristics
DIMENSIONS: ±1mils METALLIZATION: Type: Thickness: GLASSIVATION: Type: SiO2 Thickness: WORST CASE CURRENT DENSITY: 1.79 A/cm2 LEAD TEMPERATURE (10s soldering): 300oC
Metallization Mask Layout
HM-6504/883
NOTE: numbers correspond Package only.
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