SFH67XX series high speed optocoupler capable transmitting data rates

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SFH67XX series high speed optocoupler capable transmitting data rates

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High Speed/Logic Gate Optocoupler (SFH67XX Series) (Appnote
SFH67XX series high speed optocoupler capable transmitting data rates Mb/s typically Mb/s over full temperature range (guaranteed).The combination input current (1.6 active logic level output fits nearly logic applications, where galvanic insulation necessary. SFH67XX series features positive logic with output levels. improved noise immunity detector incorporates Schmitt-Trigger stage. SFH6700/19 provides enable input, which allows switching output into high ohmic state applications.
SFH6700/19 Anode Cathode Three-State-Output SFH6705 Anode Cathode
17850
applications which need open collector output, SFH6705 offered.The SFH6731 SFH6732 dual versions. channels free crosstalk interference. ensure high common mode transient immunity guaranteed kV/µs SFH671X/6732 series feature internal shield, which consists additional layer. (Indium Oxide) layer optically transparent, electrically conductive layer detector. standard SFH670X series withstands kV/µs SFH67XX series also available version (option with creepage clearance distance).
SFH6702/12 Anode Cathode Totem-Pole-Output SFH6731/32
SFH6701/11 Anode Cathode Totem-Pole-Output
Anode Cathode Cathode Anode
Open-Collector-Output
Dual/Totem-Pole-Output
Figure Variations SFH67XX Family SFH6700/ Table Truth Table (Positive Logic) Logic High Level, Logic Level, High Ohmic State Enable Output
SFH6701/
Document Number: 83701 Rev. 1.2, 24-Nov-03
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Vishay Semiconductors Design Considerations
circuits shown below intended give design engineer guideline logic family interconnection. Input Circuitry Below stated most common interface circuits which work this coupler series. Totem Pole Drive Circuits Figures most common used circuits. designer chooses according equation: good compromise between power dissipation symmetrical propagation delays with respect some guard band IFN3 some applications speed-up capacitor (typical around across used achieve faster switching times (please refer this section details).
Figure Logic Gate (e.g.) 74LS04 74LS04 74HCT04 Value 1.10 1.10
Table Typical Values
Data LOGIC
TTL/
(valid Figure
(valid Figure
SFH6700/19
17851
Both circuits simple feature minimum component count with power dissipation. logic source drive, like Figure recommended current limitations (especially CMOS logic family), speed capability lower common mode transient immunity. coupler's typically input current threshold 0.50 negative temperature gradient input current threshold (see Figure output leakage current driver element high temperatures become issue certain applications where circuit operated upper temperature range. critical applications, where high leakage current expected, shunt drive circuit according Figure good solution.
Normalized Input Current Threshold
Temperature (°C)
Figure Series Drive
SFH6700/19
TTL/ CMOS LOGIC
Data
17852
17853
Figure Series drive
Figure Typical Input Current Threshold (Normalized) Temperature
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Document Number: 83701 Rev. 1.2, 24-Nov-03
SFH6700/19 Data CMOS LOGIC
TTL/
Data
TTL/ CMOS LOGIC
SFH6700/19
17854
17855
Figure Shunt Drive Circuit with leakage Current Protection
Figure Logic Gate Shunt Drive Circuit
resistor determines forward current, shunts LED. chosen between power dissipation considerations expected leakage current. good idea about resistor values given following equations:
Fmax(LEDoff) Leak@Temp Leakage
Value
Open Collector Drive Circuits simple circuit, which works also open collector drive circuits, been presented Figures Figure resistor represents leakage current protection path. more efficient, more power dissipating solution presented Figure This drive circuit provides good speed protection against leakage currents. resistor chosen accordance with
Value
Table Typical Input Circuit Values Shunt Around Away from (According Figure
Refer Table some typical resistor values. Note that leakage protection generally might only issue some special applications.
Data Open Collector Drain SFH6700/19
17856
better solution concerning leakage current presented Figure This circuit provides excellent speed properties leakage current protection. silicon diode ensures that current only sourced therefore required units driven open collector open drain. forward voltage ensures that stays logic low. equation choose
Figure Open Collector/Drain Shunt Drive Circuit
Value 1.10 2.80 4.42
Table Typical Input Circuit Values Circuit According Figure
Document Number: 83701 Rev. 1.2, 24-Nov-03
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Input Circuitry Improved Switching Speed switching speed concern, speed-up capacitor good solution. resistor limits peek transient current IFpeak, whereas determine current steady operation. equations reasonable resistor values printed below. reasonable value speed-up capacitor
SFH6700/19
loads loads) easily. general, bypass capacitor strongly recommended proper operation. SFH6700/19 with three state output fits best applications because possibility switch couplers output into high ohmic state (for typical setup please refer Figure 28). Interfacing Compatible Logic Interfacing SFH67XX coupler other compatible logic quite simple. active output this coupler eliminates external pull resistor, minimizes number parts saves board space. typical connection seen Figure Even logic interfaced this way.
SFH6701/11
TTL/ INPUT
Data
17857
TTL/ CMOS LOGIC
Data
Figure Series Drive with Speed-up Capacitor
equations resistor values are:
Fpeak
18014
Figure Interfacing Coupler TTL, LSTTL Compatible Logic
maximum IFpeak this transient SFH67XX series.
Value Value Value
Table Typical Input Circuit Values Circuit According Figure
Drive Circuits Dual Channel Devices SFH6731/32 driven simple single channel devices. drive circuits equations adapted drive dual channel devices. (The dual channel devices reduces number parts required board space.) Output Circuitry advantage SFH67XX series easy connection logic system, because active output stage (totem pole/three state output). Either direct pull-up resistor, couplers drive
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Interfacing CMOS Logic ensure reliable logic switching pull-up resistor between output recommended (see Figures 12). logic family, this pull resistor omitted, matching switching level couplers output input. There three simple ways connect CMOS logic SFH67XX coupler family: Using SFH67XX (totem pole) pull-up resistor (see Figure Using SFH6705 (open collector) pull-up resistor (see Figure Using logic device (see Figure Using device simplest most convenient solution eliminating external pull-up resistor (see Figure 10). designer doesn't have worry about power consumption, rise times system speed.
Document Number: 83701 Rev. 1.2, 24-Nov-03
SFH6701/11
17858
Input
Data CMOS Logic Level
times results higher power dissipation. Reasonable values shown Table have impression relationship between rise time pull-up resistor RP/load capacitance please refer Figure details.
SFH6705
CMOS Input
Figure Interfacing CMOS Logic Level Device
Data
Using open collector device, like Figure requires external pull-up resistor determine right value this pull-up resistor, necessary have look following equations:
17859
Figure Interfacing SFH6705 (Open Collector Output) CMOS Logic
CCmax OLmin Pmin OLmax
where represents total load current level VOL. ensure VOLmax over temperature IOLmax should higher than mA.) maximum value determined
using totem pole device, equations (10) also valid, pull-up resistor only bring voltage difference between -1.8 input switching limit, e.g. logic, which makes This allows higher which results lower power consumption.
SFH6701/11
CMOS Input
CCmin IHmin Pmin OHmax
(10)
CMOS applications however, where region, limiting factor also determined maximum allowable rise time (500 logic). equation leads
Data
(11)
17860
Pmax IHmin CCmin
(12)
Figure Interfacing SFH67XX (totem Pole Output) CMOS Logic (Open Collector) (Totem Pole) 1.10
which represents total capacitance load, including coupler (which around pF). resistor value compromise between requirements, power dissipation switching speed. produces symmetrical short switching
Table Typical Values Connecting CMOS Logic (According Figures
Note that generally value negligible influence delay time strongly determines rise time, especially open collector type.
Document Number: 83701 Rev. 1.2, 24-Nov-03
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Interfacing Level Interfacing logic families (e.g. quite easy, presented Figure totem pole/three-state coupler operated with then output "high" level coupler, which then typically matches perfectly with logic input levels. general, output "high" voltage determined -1.8 (Even with output voltage within limits, guaranteed higher than over temperature fulfill also logic requirement).
SFH6701/11
17861
1000 Rise Time, (ns)
18015
Time Constant (ns)
1000
Logic
Data
Figure Typical Rise Time Load (Test Circuit Figure
SFH6705 0.1µF VCC=5 Time
Figure Interfacing Logic with
17862
Interfacing other Levels shifting other level intended (e.g. logic, like ALVC ALVT series), SFH6705 with open collector output qualified. works pull-up resistor ensure proper logic high level. basic principals same they have been described section "interfacing CMOS logic" equations (12). Pull-Up Resistor Considerations Open Collector Type SFH6705 previously mentioned above, pull-up resistor chosen accordance with equations (9), (10) (12). Figure gives impression about expected rise time versus time constant Unlike rise time fall time mostly independent around
Figure Test Circuit Rise Time Time Constant
Common Mode Transient Immunity (CMTI)
SFH6711/12/19 feature guaranteed Common Mode Transient Immunity (CMTI) kV/µs This achieved using faraday shield which transparent infrared light, electrically conducting. This shield prevents photodiode from being turned common mode transients. general there some design rules achieve high CMTI. These recommendations especially important drive current devices, like SFH67XX series: Connect used pins virtually grounded input potential (either VDD) Minimize stray capacitance Avoid long distances between input circuit coupler Choose appropriate high forward current improve (common mode transient immunity logic "high" level)
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Document Number: 83701 Rev. 1.2, 24-Nov-03
layout which keeps these hints mind seen Figure Note that this layout reduces creepage clearance distance!
(top layer) SFH6719
17865
SFH6719
Data
*Transistor switching transistor (e.g. 2N2222)
Figure Input Circuitry High CMTI
17863
(bottom layer)
Figure Principle Board Layout Enhanced CMTI Fits Schematic Figure
circuit which brings additional safety concerning CMTI shown Figure diode intended sink parasitic current, which caused stray capacitance, away from prevent false turn-on.
SFH6719 Data
CMOS LOGIC
common achieve ultra high CMTI presented Figure balanced input impedance principle works with four resistors, used minimize noticeable current when transistor achieve maximum performance, stray capacitance from anode cathode output side coupler kept possible. Reasonable values with 2N2222 omitted. Note that omitted, depending transistor
SFH6719
Q1** Signal
17866
17864
Figure Input Circuitry Improved CMTI
Diode signaling diode Another input circuit high common mode transient immunity shown Figure transistor shunts off-state prevents false turn This circuit tolerates very high common mode transients off-state. improvement on-state reached choosing high current. typically around
Figure Balanced Input Impedance Circuitry
Resistor achieve balanced input impedance Transistor switching transistor
Dynamic Operation
SFH67XX series active pull-up outputs offer guaranteed maximum propagation delay time over temperature features also guaranteed Mb/s data rate over temperature.
Document Number: 83701 Rev. 1.2, 24-Nov-03
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Pulse Width Distortion Pulse width distortion (PWD) defined difference between tPHL tPLH (PWD |tPHL- tPLH|). This value important applications where symmetrical switching times required, e.g. systems which based pulse width modulation. transmission systems, should exceed minimum propagation delay time. forward current, SFH67xx typical around over temperature, which corresponds maximum Note that speed capacitor decreases tPLH might increase PWD.
Pulse Width Distor tion, (ns)
17867
Propagation Dela Skew, (ns)
17868
Temperature (°C)
Figure Typical Propagation delay Skew over Temperature (Test Circuit Figure
logic circuits must noticed that overall tPSK determined input output logic gates signal path. minimize overall PWD, identical couplers compensates their influence, like seen Figure Note that minimum achieved costs higher overall propagation delay.
Temperature, (°C)
SFH6702/12 1.1k
74LS04
Figure Typical Pulse Width Distortion over Temperature (Test Circuit Figure
SFH6702/12
1.1k 0.1µF
0.1µF
74LS04
Propagation Delay Skew Propagation delay skew (tPSK) defined difference between minimum propagation delay, either tPHL tPLH, maximum propagation delay, either tPLH tPHL, between SFH67XX coupler under same operation conditions. Propagation delay skew therefore important value parallel data transmission, where synchronized data needed.
17869
Figure
Pattern Diagram typical pattern diagram Mb/s data transmission presented Figure pattern testing done with pseudo random data sequence (NRZ coding).
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Document Number: 83701 Rev. 1.2, 24-Nov-03
Vishay Semiconductors Design Ideas
Optocouplers commonly used interface between circuits, where galvanic insulation required, either protect humans sensitive electronic equipment behind front Based this requirement, some designs presented below, which SFH67XX series. IGBT/IPM Driver SFH67XX series predestined fast driver Intelligent Power Modules (IPMs) resp. IGBT's/MOSFET's. SFH67XX optocoupler series provide level shifting galvanic insulation therefore ideal interface control logic. With guaranteed minimum kV/µs common mode transient immunity, SFH671X also fulfills enhanced switching requirements.
Output Monitoring
17870
Figure
SFH6701/11
74LS04
74LS04
17871
Input Monitoring
Figure
Switching Loads SFH67XX series easily handle currents mADC voltages desired handle loads which beyond these limits, circuits Figures considered. circuit, used pull-up resistor load current handled limited external transistor Unlike Figure schematic Figure qualified support both high voltages currents. power supply might raised achieve proper voltage turn transistor fully combination SFH67XX series with logic level power transistors provides fast part saving solution.
Galvanic Insulation SFH6711 Data
74HCT04
+VCC
Intelligent Power Module
IGBT/MOSFET Driver
IGBT Module
Protection/ Suppression Unit
Figure
17872
Document Number: 83701 Rev. 1.2, 24-Nov-03
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SFH6712 LOAD R1** BSP89 0.1µF BUZ104SL BUZ73L
17873
Time Multiplexed Line Access with Optical Insulation Barrier schematic Figure shows common data line with independent data lines time multiplexing mode. 2-line 4-line address decoder selects data lines enabling output, whereas other outputs remain high ohmic state. Opto-Insulated Interface When galvanic insulation digital-to-analog-conversion analog-to-digital-conversion systems required, SFH67XX series good choice interface. Setups like Figure provide fast part saving insulation barrier. propagation delay skew SFH67XX family makes them ideal parallel data transfer. SFH67XX series provide optimal interface solution C167/C165 micro controllers supporting Mb/s data rate clock.
Figure
Transistor n-channel enhancement transistor Resistor might omitted, depending necessary turn fully
SFH6711 0.1µF LOAD
17874
SP0610T
Figure
Transistor p-channel enhancement transistor
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Document Number: 83701 Rev. 1.2, 24-Nov-03
Galvanic Insulation Barrier SFH6700/19
Common Data
Data Line
74HCT04
SFH6700/19 Data Line
74HCT04
74HCT139 2-Line 4-Line Decoder Enable
Select Inputs
SFH6700/19
Data Line
74HCT04
Truth Tabl
Active Line none (all high ohmic) Data Line Data Line Data Line Data Line
SFH6700/19 Data Line
74HCT04
Common Data
17875
Figure Typical Setup Common Line with Different Lines Time Multiplex Mode
Document Number: 83701 Rev. 1.2, 24-Nov-03
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0.33 MAX845 Transformer Driver GND1 GND2
Galvanic Insulation Barrier 78L05 0.33
MAX873
0.33
BAW56 Diodes HALO TGM-030P3 Transformer SFH6731/32
80C167 Microcontroller** Synchronous Serial Channel (SSC)/SPI P3.13/SCLK P3.9/MTSR Data
74HCT04*
REFAB SCLK MAX525 Digital-to-Analog Converter OUTA OUTB DOUT GNDD OUTD AGND OUTC Channel Channel Channel REFCD Channel
74HCT04*
SFH6701/11
PX.Y
74HCT04*
17876
Figure Fully Galvanic Insulated Digital-to-Analog-Conversion System Channel DAC)
Inverter 74HCT04 used allow current C16X micro controller used
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Document Number: 83701 Rev. 1.2, 24-Nov-03

SFH67XX series high speed optocoupler capable transmitting data rates

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