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High Speed / Logic Gate Optocoupler SFH67XX Series Appnote 73

SFH6700 / 19 NC 1 Anode 2 Cathode 3 NC 4 8 VCC 7 Out 6 VE 5 GND Three-State-Output SFH6705 NC 1 Anode 2 Cathode 3 NC 4

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High Speed / Logic Gate Optocoupler (SFH67XX Series) (Appnote 73)
1. Introduction
The new SFH67XX series of high speed optocoupler is capable of transmitting data rates up to 5 Mb / s typically and 2.5 Mb / s over full temperature range (guaranteed).The combination of low input current (1.6 mA) and active logic level output fits for nearly all logic applications, where a galvanic insulation is necessary. The SFH67XX series features positive logic with TTL output levels. For improved noise immunity the detector incorporates a Schmitt-Trigger stage. The SFH6700 / 19 provides an enable input, which allows switching the output into the high ohmic state for bus applications.
SFH6700 / 19 NC 1 Anode 2 Cathode 3 NC 4 8 VCC 7 Out 6 VE 5 GND Three-State-Output SFH6705 NC 1 Anode 2 Cathode 3 NC 4
SFH6702 / 12 8 VCC 7 Out 6 NC 5 GND NC 1 Anode 2 Cathode 3 NC 4 Totem-Pole-Output SFH6731 / 32 8 VCC 7 NC 6 Out 5 GND
SFH6701 / 11 NC 1 Anode 2 Cathode 3 NC 4 Totem-Pole-Output
Anode 1 Cathode 2 Cathode 3 Anode 4
Open-Collector-Output
Dual / Totem-Pole-Output
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The circuits shown below are intended to give the design engineer a guideline for logic family interconnection. Input Circuitry Below are stated the most common interface circuits which work for this coupler series. Totem Pole Drive Circuits Figures 2 and 3 are two of the most common used circuits. The designer chooses R1 according to the equation: A good compromise between low power dissipation and symmetrical propagation delays with respect to some guard band is IFN3 mA. In some applications a speed-up capacitor (typical around 100 pF) across R1 may be used to achieve faster switching times (please refer to the end of this section for details).
Figure 2 3 Logic Gate (e.g.) 74LS04 74LS04 74HCT04 R1 Value 750 1.10 k 1.10 k
VDD Data LS TTL IN LOGIC
(valid for Figure 2) (1)
(valid for Figure 3) (2)
SFH6700 / 19 1 NC VCC 8 Out 7
50 40 30 20 10 0 -10 -20 -30 -60 -40 - 20 0 20 40 60 Temperature , TA (°C) 80 100
Figure 2. Series LED Drive
SFH6700 / 19 1 NC VDD
TTL / CMOS LOGIC
Data IN
Figure 3. Series LED drive
Figure 4. Typical Input Current Threshold (Normalized) vs. Temperature
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Document Number: 83701 Rev. 1.2, 24-Nov-03
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SFH6700 / 19 1 NC VDD Data CMOS IN LOGIC
VDD Data IN
TTL / CMOS LOGIC
SFH6700 / 19 1 NC R1 D1 3 GND 4 NC GND 5 2 VCC 8 Out 7
Figure 5. Shunt LED Drive Circuit with leakage Current Protection
Figure 6. Logic Gate Shunt Drive Circuit
The resistor R1 determines the forward LED current, and R2 shunts the LED. R2 has to be chosen between power dissipation considerations and expected leakage current. A good idea about the resistor values is given by the following equations:
VDD 5V IF 3 mA R1 Value 1.0 k
Open Collector Drive Circuits A simple circuit, which works also for open collector drive circuits, has been presented in Figures 3 and 5. In Figure 5, the resistor R2 represents a leakage current protection path. A more efficient, but more power dissipating solution is presented in Figure 7. This drive circuit provides good speed and protection against leakage currents. The resistor R1 is chosen in accordance with
R2 Value 4.7 k
Table 3: Typical Input Circuit Values to Shunt Around 250 µA Away from the LED (According to Figure 5)
Refer to Table 4 for some typical resistor values. Note that leakage protection generally might only be an issue in some special applications.
VDD Data Open Collector IN Drain R1 SFH6700 / 19 1 NC 2 3 GND 4 NC
A better solution concerning leakage current is presented in Figure 6. This circuit provides excellent speed properties and leakage current protection. The silicon diode D1 ensures that the current is only sourced by VDD and is therefore not required for units driven by open collector or open drain. The low forward voltage of D1 ensures that the LED stays off at logic low. The equation to choose R1 is:
Figure 7. Open Collector / Drain Shunt Drive Circuit
R1 Value 1.10 k 2.80 k 4.42 k
Table 4: Typical Input Circuit Values for a Circuit According to Figure 7
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Input Circuitry for Improved Switching Speed If switching speed is a concern, the use of a speed-up capacitor is a good solution. The resistor R2 limits the peek transient current IFpeak, whereas R1 and R2 determine the current at steady operation. The equations and reasonable resistor values are printed below. A reasonable value for the speed-up capacitor CS is 100 pF.
CS VDD R1 R2 SFH6700 / 19 1 NC 2 3 4 NC VCC 8 Out 7
16 LS TTL loads (4 TTL loads) easily. In general, a 0.1 µF bypass capacitor is strongly recommended for proper operation. The SFH6700 / 19 with its three state output fits best in bus applications because of the possibility to switch the couplers output into the high ohmic state (for a typical setup please refer to Figure 28). Interfacing to TTL / TTL Compatible Logic Interfacing the SFH67XX coupler to LS TTL or any other compatible logic is quite simple. The active output of this coupler eliminates the use of an external pull up resistor, and minimizes the number of parts and saves board space. The typical connection is seen in Figure 9. Even HCT logic can be interfaced this way.
TTL / LS TTL INPUT
Data IN
TTL / CMOS LOGIC
VCC Data Out
Figure 8. Series LED Drive with Speed-up Capacitor
0.1 µF GND
The equations for the resistor values are:
Figure 9. Interfacing the Coupler to TTL, LSTTL or Compatible Logic
The maximum IFpeak for this transient is 50 mA for the SFH67XX series.
VDD 5V CS Value 100 pF R1 Value 1.0 k R2 Value 75
Table 5: Typical Input Circuit Values for a Circuit According to Figure 8
Drive Circuits for the Dual Channel Devices The SFH6731 / 32 can be driven as simple as the single channel devices. All drive circuits and the equations (1) to (8) can be adapted to drive the dual channel devices. (The use of the dual channel devices reduces the number of parts and the required board space.) Output Circuitry The advantage of the SFH67XX series is its easy connection to any logic system, because of the active output stage (totem pole / three state output). Either direct or via a pull-up resistor, all couplers can drive up to
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Document Number: 83701 Rev. 1.2, 24-Nov-03
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HCT Input
VCC Data Out at CMOS Logic Level
times but results in a higher power dissipation. Reasonable values are shown in Table 6. To have an impression on the relationship between the rise time t r and the pull-up resistor RP / load capacitance CL, please refer to Figure 14 for details.
SFH6705 1 NC V CC 8 NC 7 Out 6 5 0.1 µF VCC
0.1 µF GND
CMOS Input
Figure 10. Interfacing to CMOS Logic Level via a HCT Device
Data Out GND
Using the open collector device, like in Figure 11, requires an external pull-up resistor RP . To determine the right value of this pull-up resistor, it is necessary to have a look at the following equations:
Figure 11. Interfacing SFH6705 (Open Collector Output) to CMOS Logic
By using a totem pole device, the equations (9) and (10) are also valid, but the pull-up resistor has only to bring up the voltage difference between VOH ( VCC -1.8 V) and the input switching limit, e.g. 3.5 V for HC logic, which makes a V of 0.3 V. This allows to use a higher RP which results in lower power consumption.
CMOS Input
-t -------- RP CL
VCC Data Out
0.1 µF GND
Figure 12. Interfacing SFH67XX (totem Pole Output) to CMOS Logic VCC 5V RP (Open Collector) 820 RP (Totem Pole) 1.10 k
in which CL represents the total capacitance of the load, including the coupler (which is around 6 pF). The resistor value is a compromise between the two requirements, power dissipation and switching speed. A low RP produces symmetrical and short switching
Table 6: Typical Values for Rp by Connecting to CMOS Logic (According to Figures 11 and 12)
Note that generally the RP value has a negligible influence on the delay time td, but it strongly determines the rise time, especially for the open collector type.
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1000 900 800 Rise Time, t r (ns) 700 600 500 400 300 200 100 0
100 RC Time Constant (ns)
3.3 V Logic
Data Out
0.1 µF GND
Figure 15. Test Circuit for Rise Time tr vs. Time Constant
3. Common Mode Transient Immunity (CMTI)
The SFH6711 / 12 / 19 feature a guaranteed Common Mode Transient Immunity (CMTI) of 2.5 kV / µs at 400 V. This is achieved by using a faraday shield which is transparent to infrared light, but electrically conducting. This shield prevents the photodiode from being turned on by common mode transients. In general there are some design rules to achieve a high CMTI. These recommendations are especially important for low LED drive current devices, like the SFH67XX series: · Connect the not used pins 1 and 4 to the virtually grounded input potential (either GND or VDD) · Minimize stray capacitance · Avoid long distances between LED input circuit and coupler · Choose an appropriate high LED forward current to improve CMH (common mode transient immunity at logic "high" level)
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Document Number: 83701 Rev. 1.2, 24-Nov-03
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VCC (top layer) SFH6719 VDD 1 NC R1 Q1 2 3 4 NC GND 0.1 µF
SFH6719
Data IN RS
Transistor Q1: Any switching transistor (e.g. 2N2222)
Figure 18. Input Circuitry for High CMTI
GND (bottom layer)
Figure 16. Principle Board Layout for Enhanced CMTI ( Fits to Schematic in Figure 18)
A circuit which brings additional safety concerning CMTI is shown in Figure 17. The diode D1 is intended to sink parasitic current, which is caused by stray capacitance, away from the LED to prevent a false turn-on.
SFH6719 D1 VDD R1 Data IN
CMOS LOGIC
SFH6719 VDD 1 NC R3 R1 3 R2 4 NC GND 5 VE 6 2 VCC 8 Out 7
Q1 Signal IN R4 GND
Figure 17. Input Circuitry for Improved CMTI
Figure 19. Balanced Input Impedance Circuitry
4. Dynamic Operation
The SFH67XX series of active pull-up outputs offer guaranteed maximum propagation delay time of 300 ns over temperature and features also guaranteed 2.5 Mb / s data rate over temperature.
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Pulse Width Distor tion, PWD (ns)
Propagation Dela y Skew, t PSK (ns)
0 20 40 60 Temperature , TA (°C)
In logic circuits it must be noticed that the overall PWD and tPSK are determined by all input and output logic gates in the signal path. To minimize the overall PWD, the use of two identical couplers compensates their influence, like seen on Figure 22. Note that the minimum PWD is achieved on costs of a higher overall propagation delay.
-20 0 20 40 60 Temperature, TA (°C) 80 100
SFH6702 / 12 VCC 8 1 NC 5V 1.1k
74LS04
1.1k 2 3 0.1µF 4 NC
0.1µF
74LS04
Propagation Delay Skew Propagation delay skew (tPSK) is defined as the difference between the minimum propagation delay, either tPHL or tPLH, and the maximum propagation delay, either tPLH or tPHL, between any SFH67XX coupler under the same operation conditions. Propagation delay skew is therefore an important value for parallel data transmission, where synchronized data is needed.
Figure 22.
Eye Pattern Diagram A typical eye pattern diagram for 5 Mb / s data transmission is presented in Figure 23. The eye pattern testing was done with a pseudo random data sequence (NRZ coding).
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Document Number: 83701 Rev. 1.2, 24-Nov-03
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Output Monitoring 5V
Figure 23.
SFH6701 / 11 1 NC
74LS04
0.1 µF
Input Monitoring
Figure 24.
Switching Loads The SFH67XX series can easily handle currents up to 25 mADC and voltages up to 15 V. If it is desired to handle loads which are beyond these limits, the circuits in Figures 26 and 27 may be considered. In the circuit, R1 is used as a pull-up resistor and the load current is handled and limited by the external transistor Q1. Unlike Figure 27, the schematic in Figure 26 is qualified to support both high voltages and currents. The 5 V power supply might be raised up to 15 V to achieve a proper VGS voltage to turn the transistor fully on. The combination of the SFH67XX series with logic level power transistors provides a fast and part saving solution.
+VS +HV
Galvanic Insulation SFH6711 1 NC BAR 74 5V 1.1 k Data IN
74HCT04
IPM - Intelligent Power Module
IGBT / MOSFET Driver
IGBT Module
Out 7 Protection / Suppression Unit
GND 5 GND
Figure 25.
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SFH6712 1 NC 2 3 4 NC V CC 8 NC 7 Out 6 G ND 5 5V LOAD R1 1k Q1 BSP89 0.1µF BUZ104SL BUZ73L G ND
Time Multiplexed Bus Line Access with Optical Insulation Barrier The schematic in Figure 28 shows the use of a common data bus line with 4 independent data lines in time multiplexing mode. The 2-line to 4-line address decoder selects one of the 4 data lines by enabling the output, whereas all the other outputs remain in the high ohmic state. Opto-Insulated DAC Interface When galvanic insulation in digital-to-analog-conversion or analog-to-digital-conversion systems is required, the SFH67XX series is a good choice for an interface. Setups like the one in Figure 29 provide a fast and part saving insulation barrier. The low propagation delay skew of the SFH67XX family makes them ideal for use in parallel data transfer. The SFH67XX series provide an optimal interface solution for the SAB 80 C167 / C165 micro controllers by supporting the 5 Mb / s data rate at a 20 MHz CPU clock.
Figure 26.
Transistor Q1: Any n-channel enhancement transistor Resistor R1: R1 might be omitted, depending on the necessary VGS of Q1 to turn Q1 fully on
V SS 1k Q1 SP0610T
Figure 27.
Transistor Q1: Any p-channel enhancement transistor
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Document Number: 83701 Rev. 1.2, 24-Nov-03
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Galvanic Insulation Barrier 5 SFH6700 / 19 1 NC 1.1 k 2 3 4 NC V CC 8 Out 7
Common Data Bus
0.1 µF Data Line 1
74HCT04
SFH6700 / 19 1 NC 1.1 k 2 3 4 NC V CC 8 Out 7 0.1 µF Data Line 2
74HCT04
VE 6 GND 5 Y0 B Y1 74HCT139 2-Line to 4-Line Y2 Decoder G Enable Y3 0.1 µF A
Select Inputs
Data Line 3
74HCT04
Truth Tabl e
Active on Bus Line none (all high ohmic) Data Line 1 Data Line 2 Data Line 3 Data Line 4
SFH6700 / 19 1 NC 1.1 k 2 3 4 NC V CC 8 Out 7 0.1 µF Data Line 4
74HCT04
Common Data Bus
Figure 28. Typical Setup for a Common Bus Line with 4 Different Lines in Time Multiplex Mode
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5V 0.33 µF V CC D1 MAX845 Transformer Driver SD D2 GND1 GND2 FS
Galvanic Insulation Barrier 78L05 + 0.33 µF
5V 2.2 µF
MAX873
0.33 µF
2 x BAW56 Diodes HALO TGM-030P3 Transformer V DD SFH6731 / 32
0.1 µF
SAB 80C167 Microcontroller Synchronous Serial Channel (SSC) / SPI P3.13 / SCLK CLK P3.9 / MTSR Data
74HCT04
REFAB CL SCLK 0.1 µF 6 DIN MAX525 Digital-to-Analog Converter OUTA FBB OUTB FBC CS 0.1 µF DOUT UPO PDL GNDD OUTD AGND OUTC FBD 10 k 10 k Channel D 0..5 V 10 k 10 k 7 Channel C 0..5 V 10 k 10 k Channel B 0..5 V REFCD FBA 10 k 10 k Channel A 0..5 V
74HCT04
GND 5 SFH6701 / 11
74HCT04
Figure 29. Fully Galvanic Insulated Digital-to-Analog-Conversion System (4 Channel DAC)
Inverter 74HCT04 is used to allow 3 mA LED current Any C16X micro controller can be used
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Document Number: 83701 Rev. 1.2, 24-Nov-03