N-Channel Synchronous MOSFETs FUNCTIONAL DESCRIPTION SI4724C
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SPICE Device Model Si4724CY
N-Channel Synchronous MOSFETs
FUNCTIONAL DESCRIPTION
SI4724CY high speed driver designed operate high frequency dc-dc switchmode power supplies. designed used with single output ASIC produce highly efficient synchronous rectifier converter. Under-voltage protection provided power supply. device includes bootstrap diode, integrated Schottky diode, fast switching times.
MODEL DESCRIPTION
driver circuit decomposed into elemental blocks, then modeled accordingly data sheet specific topological information provided Systems Vishay's engineers. IsSpice models output MOSFETs, bootstrap diode, Schottky diode were provided used modeling model includes following functionality features: Proper transient response including variations with external components. Proper connectivity real-life part Output rise fall times varying loads Under voltage lockout hysteresis Switching times (turn propagation delays) Schottky behavior Bootstrap voltage diode characteristics Logic input voltage thresholds Break-before-make reference SI4724CY. efforts were made improve models although they were reviewed comments shown below. Using ICAP/4, SPICE package from Systems, model driver then created using modules corresponding schematic netlist generated.
Note: variation Vref logic input voltage levels with modeled. schematic subcircuit topology, including several elements used test subcircuit (parts green), shown Figure corresponding IsSpice4 subcircuit netlist shown Table
SUBCIRCUIT SCHEMATIC
Figure
Document Number: 72365 23-Jan-04
Si4724CY subcircuit with additional test circuitry
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SPICE Device Model Si4724CY
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Document Number: 72365 23-Jan-04
SPICE Device Model Si4724CY
model operation described follows: under voltage lockout threshold modeled V10, VBBM/Vref, Sync, comparisons handled BIN, respectively. logic input threshold value used 2.3V. This value static could made function VIN. combinations, R2/C1, R8/C2 R7/C1 account majority propagation delays TON/TOFF delay matching. level shifting logic functions modeled output FETs have been modeled provide appropriate drive performance along with proper values rDSon (values used: N-Channel /P-Channel N-Channel /P-Channel
ASSUMPTIONS
Behavior based typical values given specification sheet operation Some thermal variations modeled including some related parameters propagation delay represented subcircuit. SPICE syntax used compatible with Intusoft ICAP/4. PSpice version subcircuit also provided.
SPICE NETLIST
Vishay SI4724CY This model developed Vishay Systems, 5777 Century Blvd. Suite Angeles, California 90045 Copyright 2003, rights reserved. This model subject change without notice. Users directly indirectly re-sell re-distribute this model. more information regarding modeling services, model libraries simulation products, please call Systems (310) 216-1144, contact email: info@aeng.com. http://www.AENG.com Revision: 6/3/02, version Revision: 1/28/04, version Updated driver voltages reduce current draw. Note, trust spice have accurate currents. ********** Mosfet;Synchronous *SYM=Si4724CY .SUBCKT Si4724CY Sync Boot Sync Boot #alias v(bbm) #alias v(g1) #alias v(vin) #alias syncin v(18) #alias v(in2) #alias v(in3) #alias vout v(5) #alias vswitch v(s1) #alias vboot v(boot) #alias vdduvlo v(vdduvlo) #alias v(g2) DC=5 V=V(Sync) Boot Boot SIDRVABSD .MODEL SIDRVABSD BF=1.2465499 BR=0.0743382 CJC=2.48725E-10 CJE=1.45909E-10 EG=1.32 FC=0.5 IKF=10.6793593 IKR=100 IRB=9.494516E-6 IS=5.828556E-18 ISC=5.929013E-14 ISE=3.690477E-15 MJC=0.3677641 MJE=0.3267463 NC=1.47 NE=1.0479867 NF=0.9018194 NR=1.0087761 RB=130.4148594 RBM=0.0957343 RC=80 RE=1.0245273 TR=7.68E-7 VAF=1E4 VAR=2E4 VJC=0.6097614 VJE=0.803 XTB=3.4 XTI=0.5 V=V(VDDUvlo) V(16) SIFETADY 100p V=V(16) 200p V=V(16) V=V(Vin) VDDUvlo _S2_mod .MODEL _S2_mod VT=3.8 VH=.2 ROFF=10meg DC=10 VDDUvlo V=V(S1) SISCHC2 .MODEL SISCHC2 BV=30.2 CJO=200p EG=0.9 FC=0.50 IS=1.5u RS=0 VJ=0.6 XTI=0.50 V=V(VDDUvlo) V(16) V(18) V(BBM) SIFETADY SIDRVAFETPh .MODEL SIDRVAFETPh PMOS Level=1 CBD=530p CBS=636p CGBO=1.07u CGDO=650n CGSO=780n GAMMA=0 IS=1.00p KP=75.0m LAMBDA=2.50m MJ=0.460 PB=0.800 PHI=.75 RD=0.210 RS=0.210 VTO=2 SIDRVAFETPL .MODEL SIDRVAFETPL PMOS Level=1 CBD=530p CBS=636p CGBO=1.07u CGDO=650n CGSO=780n GAMMA=0 IS=1.00p KP=75.0m LAMBDA=2.50m MJ=0.460 PB=0.800 PHI=.75 RD=0.140 RS=0.140 VTO=2 Boot SIDRVAFETNh .MODEL SIDRVAFETNh NMOS Level=1 CBD=530p CBS=636p CGBO=1.07u CGDO=650n CGSO=780n GAMMA=0 IS=1.00p KP=75.0m LAMBDA=2.50m MJ=0.460 PB=0.800 PHI=.75 RD=98.0m RS=98.0m VTO=2
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Document Number: 72365 23-Jan-04
SPICE Device Model Si4724CY
SIDRVAFETNL .MODEL SIDRVAFETNL NMOS Level=1 CBD=530p CBS=636p CGBO=1.07u CGDO=650n CGSO=780n GAMMA=0 IS=1.00p KP=75.0m LAMBDA=2.50m MJ=0.460 PB=0.800 PHI=.75 RD=84.0m RS=84.0m VTO=2 .SUBCKT SIFETADY NMOS W=1358279u L=0.50u PMOS W=1358279u L=0.40u 11E-3 RTEMP 450E-12 .MODEL NMOS NMOS (LEVEL 5E-8 4.3E-3 NSUB 1.77E17 2.1E-5
VMAX 5E-7 KAPPA 7E-2 1E-4 CGSO CGDO CGBO 0.8E12 DELTA 0.1) .MODEL PMOS PMOS (LEVEL 5E-8 +NSUB 2.1E16 .MODEL (CJO=210E-12 VJ=0.38 M=0.22 +RS=0.01 FC=0.1 IS=1E-12 TT=2.8E-8 BV=30.2) .MODEL RTEMP (TC1=6.5E-3 TC2=5.5E-6) .ENDS .ENDS ******
Table
IsSpice4 Subcircuit Netlist
MODEL VERIFICATION
test circuit described data sheet Figure created using ICAP/4, shown figure model tested manufacturer's datasheet using component values provided Vishay. results simulation performance various model aspects shown following figures.
Si4724CY Sync
Sync CBoot
.1uf
VOUT 4.7u
14.3m
ILoad
940u ESR@1K 100m RLEAK 1meg
Sync
Figure
SPICE schematic diagram SI4724CY switching test circuit
Note: configuration Figure this schematic were used propagation delay, delay matching, rise/fall time tests. Capacitor ESR/ESL leakage were estimated.
Document Number: 72365 23-Jan-04
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SPICE Device Model Si4724CY
vswitch
16.0
12.0 8.00 4.00
96.0U
96.2U
96.4U time secs
96.6U
96.8U
Figure
Single input pulse simulation results. Note Vswitch (green waveform)
vswitch
16.0
12.0 8.00 4.00
td(off) 27.7N secs
Delta t1-2 17.2N secs
96.49U
96.53U
96.57U time secs
96.61U
96.65U
Figure
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Delta t1-2 Propagation delay simulation results (falling edge
Document Number: 72365 23-Jan-04
SPICE Device Model Si4724CY
vswitch
16.0
8.00 4.00
12.0
Deltat2-1 38.5N secs
td(off) 18.8N secs
95.97U
96.01U
96.05U time secs
96.09U
96.13U
Figure
Delta t2-1 Propagation delay simulation results (rising edge
vout
vout
vswitch
1.60 1.20 800M 400M 50.0U 150U 250U time secs 350U 450U
500U secs, 1.37 volts
1.44 1.42 n1.40 1.38 1.36
14.0 10.0 6.00 2.00 -2.00 468U 470U 472U time secs 474U 476U
Delta 550N secs
Figure
Document Number: 72365 23-Jan-04
Startup simulation shows VOUT (top graph) Vout, Vswitch (S1/D1), (bottom graph)
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SPICE Device Model Si4724CY
syncin
4.00 44.0 16.0
24.0
12.0
n-4.00
4.00
8.00
-8.00 -16.0 4.00
-12.0
-36.0
380U
400U
420U time secs
440U
460U
Figure
Response signals Sync pulse
v(vdd)
vdduvlo
8.00
6.00 4.00 2.00
40.0U secs, 4.00 volts
74.0U secs, 3.60 volts
30.0U
70.0U
110U time secs
150U
190U
Figure
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Turn-on/Turn-off hysteresis
Document Number: 72365 23-Jan-04
SPICE Device Model Si4724CY
CONCLUSIONS
model SI4724CY driver correlates very well with manufacturer's datasheet meets items listed Statement Work (SOW). This data should verified against actual hardware further confirmation. output voltage (1.4 somewhat less than that should achieved with input pulse width 545us (0.545u/4u). reason this unknown. variation Vref logic input voltage levels with modeled could added. reader referred three references this topic. "Power Requirements Power MOSFET Models", Budihardjo, Peter Lauritzen, Mantooth, IEEE Transactions Power Electronics, 1997 Improved Mosfet Spice Model, Supports development Dropout Voltage Regulators", Steven Sandler, EDATools Internal White Paper, Papers/Mosfet_paper.htm "SPICE Model TMOS", C.E. Cordonnier, Motorola Application Note, AN1043, 1989.
Document Number: 72365 23-Jan-04
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