P-Channel 1.8-V (G-S) MOSFET CHARACTERISTICS P-Channel Verti
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SPICE Device Model Si1407DL
P-Channel 1.8-V (G-S) MOSFET
CHARACTERISTICS
P-Channel Vertical DMOS Macro Model (Subcircuit Model) Level Apply both Linear Switching Application Accurate over 125°C Temperature Range Model Gate Charge, Transient, Diode Reverse Recovery Characteristics
DESCRIPTION
attached spice model describes typical electrical characteristics p-channel vertical DMOS. subcircuit mode extracted optimized over 125°C temperature ranges under pulsed 0-to-5V gate drive. saturated output impedance best gate bias near threshold voltage. novel gate-to-drain feedback capacitance network used model gate charge characteristics while avoiding convergence difficulties switched model. model parameter values optimized provide best measured electrical data intended exact physical interpretation device.
SUBCIRCUIT MODEL SCHEMATIC
This document intended SPICE modeling guideline does constitute commercial product data sheet. Designers should refer appropriate data sheet same number guaranteed specification limits. Document Number: 71859 25-Mar-03 www.vishay.com
SPICE Device Model Si1407DL
SPECIFICATIONS 25°C UNLESS OTHERWISE NOTED) Parameter Static
Gate Threshold Voltage On-State Drain Current
Symbol
Test Conditions
Simulated Data
0.87 0.109 0.140 0.185 0.78
Measured Data
Unit
VGS(th) ID(on)
VGS, 250µA 4.5V 4.5V, -1.8A
0.105 0.140 0.185 0.77
Drain-Source On-State Resistancea
rDS(on)
2.5V, 1.8V, 0.80
Forward Transconductancea Diode Forward Voltage
10V, 1.8A 0.80A,
Dynamic
Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Source-Drain Reverse Recovery Time
td(on) td(off) 0.80A, di/dt A/µs VGEN 4.5V, 4.5V, 1.8A
0.95
0.95
Notes Pulse test; pulse width duty cycle Guaranteed design, subject production testing.
www.vishay.com
Document Number: 71859 25-Mar-03
SPICE Device Model Si1407DL
COMPARISON MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)
Document Number: 71859 25-Mar-03
www.vishay.com
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