P-Channel 1.8-V (G-S) MOSFET CHARACTERISTICS P-Channel Verti
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SPICE Device Model Si1405DL
P-Channel 1.8-V (G-S) MOSFET
CHARACTERISTICS
P-Channel Vertical DMOS Macro Model (Subcircuit Model) Level Apply both Linear Switching Application Accurate over 125°C Temperature Range Model Gate Charge, Transient, Diode Reverse Recovery Characteristics
DESCRIPTION
attached spice model describes typical electrical characteristics p-channel vertical DMOS. subcircuit model schematic extracted optimized over 125°C temperature ranges under pulsed 0-to-5V gate drive. saturated output impedance best gate bias near threshold voltage. novel gate-to-drain feedback capacitance network used model gate charge characteristics while avoiding convergence difficulties switched model. model parameter values optimized provide best measured electrical data intended exact physical interpretation device.
SUBCIRCUIT MODEL SCHEMATIC
This document intended SPICE modeling guideline does constitute commercial product data sheet. Designers should refer appropriate data sheet same number guaranteed specification limits. Document Number: 71500 14-Oct-99 www.vishay.com
SPICE Device Model Si1405DL
SPECIFICATIONS 25°C UNLESS OTHERWISE NOTED) Parameter Static
Gate Threshold Voltage On-State Drain Current
Symbol
VGS(th) ID(on)
Test Condition
VGS, -250 -4.5 -4.5 -1.8
Typical
0.72 0.105 0.136 0.177 -0.78
Unit
Drain-Source On-State Resistance
rDS(on)
-2.5 -1.6 -1.8 -0.8
Forward Transconductance Diode Forward Voltage
-1.8 -0.8
Dynamic
Total Gate Charge
td(on) td(off) -0.8 di/dt A/µs VGEN -4.5 -4.5 -1.8
Gate-Source Chargeb Gate-Drain Chargeb Turn-On Delay Timeb Rise Timeb Turn-Off Delay Timeb Fall Time
Source-Drain Reverse Recovery Time Notes Pulse test; pulse width duty cycle Guaranteed desing, subject production testing.
www.vishay.com
Document Number: 71500 14-Oct-99
SPICE Device Model Si1405DL
COMPARISON MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)
Document Number: 71500 14-Oct-99
www.vishay.com
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