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M5621 High-Speed USB2.0 Device Controller M5621 High-Speed USB2.0


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M5621 High-Speed USB2.0 Device Controller
M5621 High-Speed USB2.0 Device Controller
Section Introduction
Overview ALi's M5621 USB2.0 Device controller provides cost-effective solution high-speed USB2.0 based application, such USB-to-IDE bridge interface, scanner, printer, digital still camera multi-function peripheral /communication /networking systems. With built-in USB2.0 transceiver related high-speed circuitry, M5621 also integrates four user-configurable endpoints with bi-directional ping-pong buffers maximized USB2.0 throughput operation. With extended design flexibility, M5621 configured three different operation modes, including working USBto-IDE bridge interface, PIO/DMA based device controller, UTMI-compliant USB2.0 standalone transceiver device. Through these highly flexible features capabilities work with embedded controller, external microcontroller ISA-based Device CPU, M5621 fully capable achieving most compact cost-effective solution varieties high-speed-oriented peripheral system applications. Features Specification revision Compliant Support High-speed(HS) Full-speed(FS) Operation with on-chip transceiver, Supports User-Configurable Endpoints bulk, interrupt, control transfers allow bulk-transfer-based device operation device, scanner, printer, camera multi-function-peripheral application Endpoint 64-byte FIFO support Control transfer Endpoint 512-byte Ping-Pong buffers Bulk-In transfer Endpoint 512-byte Ping-Pong buffers Bulk-Out transfer Endpoint 8-byte FIFO support Interrupt transfer Supplementary Bulk-In Transfer Endpoint Built-in High-performance Micro-controller Engine interface, flow multi-functional control Built-in USB2.0-to-IDE Interface Controller with general interface bulk-only transport mass storage class support upto UDMA66 storage devices DVD/CD-ROM, CD-R/W, Harddisk Compact Flash device, etc. Built-in PIO/DMA-based Device Controller with industry-standard 8/16-bit PIO/DMA Multi-word supported standard MCU/DCPU operation Configurable Standalone UTMI-compliant USB2.0 Operation Supported Optional External EEPROM, External Program Interface GPIOs Control Supported Built-in Clock Synthesizer using low-cost 12Mhz crystal external 12Mhz clock sources 100-pin TQFP 64-pin TQFP package
DEC. 2001 Document 5621IDEda03.doc Acer Labs 246, NeiHu Rd., Taipei, 114, R.O.C. Tel: 886-2-8752-2000, Fax: 886-2-8751-1001 Homepage www.ali.com.tw
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Functional Block Diagram
M5621 High-Speed USB2.0 Device Controller
USB2.0 SIE/Txcvr Host System USB2.0 Interface Controller
Configurable EndPoint FIFOs
8/16-bit /DMA /IDE Interface
/PIO /DMA
Device Peripheral ASIC DCPU
Controller
Configuration Registers
Program
Optional Program
Clock Synthesizer
Embedded Engine
GPIOs Optional EEPROM
System Application Diagram USB2.0 /1.1
USB-to-IDE Operating Mode
USB2.0/1.1 Host System
M5621
Devices (ATA/ATAPI Interface)
Device Operating Mode
USB2.0/1.1 Host System
USB2.0 /1.1
8/16-bit PIO/DMA
M5621
UTMI
Peripheral Device ASIC System
Multi-functional Control Operating Mode
USB2.0/1.1 Host System
USB2.0 /1.1
M5621
(100-pin package only)
8/16-bit PIO/DMA GPIO Control
Peripheral Device ASIC System
External
Page DEC. 2001 Document 5621IDEda03.doc Acer Labs 246, NeiHu Rd., Taipei, 114, R.O.C. Tel: 886-2-8752-2000, Fax: 886-2-8751-1001 Homepage www.ali.com.tw
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M5621 High-Speed USB2.0 Device Controller
Section Description shown below configuration USB2.0-to-IDE interface operation. configuration USB2.0 PIO/DMA device operation, please refer supplementary technical documentation. Pinout Diagram TQFP100 description USB2.0-to-IDE Interface configuration
ROMD4 ROMD3 ROMD2 ROMD1 ROMD0 VBUS GPIO<0>/EEPROMCLK/IDSEL0 GPIO<1>/EEPROMDAT/IDSEL1 GPIO<2>/USBPNP MCUCLKSEL HWSEL0(L) HWSEL1(L) HWSEL2(L) M5621 (TQFP100) ROMOEJ ROMWRJ ROMA14 ROMA13 ROMA12 ROMA11 ROMA10 ROMA9 ROMA8
DEC. 2001 Document 5621IDEda03.doc Acer Labs 246, NeiHu Rd., Taipei, 114, R.O.C. Tel: 886-2-8752-2000, Fax: 886-2-8751-1001 Homepage www.ali.com.tw
ROMA7 ROMA6 ROMA5 ROMA4 ROMA3 ROMA2 ROMA1 ROMA0 IDERESETJ VDD5 IDED8 IDED9 IDED10 IDED11 IDED12 IDED13 IDED14 IDED15 IDEDRQ IDEIOWJ IDED7 IDED6 IDED5
GPIO<6> GPIO<7> ROMSEL CLKOUT USBAVDD USBAVSS USBAVSS USBAVDD USBAVSS USBAVDD USBRREF XTALI XTALO RESETJ ROMA15 ROMD7 ROMD6 ROMD5 GPIO<5> GPIO<4> IDEDASP IDECS3FXJ IDECS1FXJ IDEA2 IDEA1 IDEA0 IDEPDIAGJ IDEIRQ IDEDACKJ GPO/USBSPEED IDEIORDY IDEIORJ IDED0 IDED1 IDED2 IDED3 IDED4
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M5621 High-Speed USB2.0 Device Controller
TQFP64 description USB2.0-to-IDE Interface configuration USBAVDD USBAVSS USBAVSS USBAVDD USBAVSS USBAVDD USBRREF XTALI XTALO RESETJ
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DEC. 2001 Document 5621IDEda03.doc Acer Labs 246, NeiHu Rd., Taipei, 114, R.O.C. Tel: 886-2-8752-2000, Fax: 886-2-8751-1001 Homepage www.ali.com.tw
IDED6 IDED7 IDERESETJ VDD5 IDED8 IDED9 IDED10 IDED11 IDED12 IDED13 IDED14 IDED15 IDEDRQ IDEIOWJ
VBUS GPIO<0>/EEPROMCLK/IDSEL0 GPIO<1>/EEPROMDAT/IDSEL1 GPIO<2>/USBPNP MCUCLKSEL HWSEL0(L) HWSEL1(L) HWSEL2(L) M5621 (TQFP64) IDED0 IDED1 IDED2 IDED3 IDED4 IDED5
IDEDASP IDECS3FXJ IDECS1FXJ IDEA2 IDEA1 IDEA0 IDEPDIAGJ IDEIRQ IDEDACKJ GPO/USBSPEED IDEIORDY IDEIORJ
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M5621 High-Speed USB2.0 Device Controller
Description shown below configuration USB2.0-to-IDE interface operation. configuration USB2.0 PIO/DMA device operation, please refer supplementary technical documentation.
Number TQFP100 TQFP64 System Signal pins) XTALI XTALO RESETJ CLKOUT HWSEL2 HWSEL1 HWSEL0 Interface pins) IDED15 IDED14 IDED13 IDED12 IDED11 IDED10 IDED9 IDED8 IDED7 IDED6 IDED5 IDED4 IDED3 IDED2 IDED1 IDED0 IDEDRQ IDEDACKJ IDEIOWJ IDEIORJ IDEIRQ IDEA2 IDEA1 IDEA0 IDECS1FXJ IDECS3FXJ IDEPDIAGJ IDEDASP IDERESETJ IDEIORDY Interface Signal pins) Name
Description
ICLK OCLK IO10U IO10U IO10U IO10U IO10U IO10U IO10U IO10U IO10U IO10U IO10U IO10U IO10U IO10U IO10U IO10U
X'TAL/OSC X'TAL System Reset, active Programmable Clock Output Hardware Operation mode selection <2:0> 000: 001: data <15:0>
Request Acknowledge Write Read Interrupt address <2:0>
address chip select address chip select Pass Diagnostics: Cable assembly type identifier slave device define Device Reset Channel Ready High-speed High-speed DFull-speed Full-speed DPage
DEC. 2001 Document 5621IDEda03.doc Acer Labs 246, NeiHu Rd., Taipei, 114, R.O.C. Tel: 886-2-8752-2000, Fax: 886-2-8751-1001 Homepage www.ali.com.tw
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USBRREF VBUS Flash interface ROMD7 ROMD6 ROMD5 ROMD4 ROMD4 ROMD2 ROMD1 ROMD0 ROMA15 ROMA14 ROMA13 ROMA12 ROMA11 ROMA10 ROMA9 ROMA8 ROMA7 ROMA6 ROMA5 ROMA4 ROMA3 ROMA2 ROMA1 ROMA0 ROMSEL ROMOEJ ROMWRJ MISC GPIO0 EEPROMCLK IDSEL0 GPIO1 EEPROMDAT IDSEL1 GPIO2 USBPNP USBSPEED GPIO4 GPIO5 GPIO6 GPIO7 MCUCLKSEL Power VDD5
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M5621 High-Speed USB2.0 Device Controller
External Reference. Requires resistor connected ground. power detection. data
address
Select booting from External output enable Flash write strobe General purpose EEPROM Clock selection General purpose EEPROM Data selection General purpose Indicate Plug Play, active cable select Indicate operation speed, high speed, high full speed. General purpose General purpose General purpose General purpose General purpose Power input tolerance. there input signal, this could connected 3.3V. 3.3V Power 3.3V Power core
35,54,65 14,68
20,40 9,43
DEC. 2001 Document 5621IDEda03.doc Acer Labs 246, NeiHu Rd., Taipei, 114, R.O.C. Tel: 886-2-8752-2000, Fax: 886-2-8751-1001 Homepage www.ali.com.tw
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M5621 High-Speed USB2.0 Device Controller
USBAVDD USBAVSS 81,85,89 49,53,57 15,22,36,53 10,21,39,42 ,64,67,78 82,84,88 50,52,56
3.3V Power transceiver Ground core Ground transceiver
Type Descriptions: IO10U ICLK OCLK Input with Schmidt Trigger Input with Schmidt Trigger, internal pull-up. Output with sink source Output with sink source Input with Schmidt Trigger/Output with sink source Input with Schmidt Trigger, internal pull-up/Output with sink source input output transceiver
DEC. 2001 Document 5621IDEda03.doc Acer Labs 246, NeiHu Rd., Taipei, 114, R.O.C. Tel: 886-2-8752-2000, Fax: 886-2-8751-1001 Homepage www.ali.com.tw
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Section Functional Description General Interfaces Controller (IDEC)
M5621 High-Speed USB2.0 Device Controller
M5621 provides general interface connect with most devices with ATAPI compliant interface. M5621's interface unit supports 16-bit DMA, UltraDMA (support UltraDMA/66) transfer. controller designed transfer mass storage data through interface uses M5621's on-chip ping-pong FIFOs Endpoint Endpoint pass data bus. Embedded Micro-Controller Unit M5621 embeds high-performance enable exceptional data transfer performance through bus. embedded unit also provides flexible programmability capable performance horsepower ease operations systematic control, Plug-N-Play operation optimize data transfer operation device control/application. M5621 utilize external ROM/EEPROM interface provide future upgrade path improving performance interface compatibility necessary. Interface with Proven Low-Power CMOS Design M5621 builds USB2.0-compliant transceiver, Serial Interface Engine (SIE) Command Decoder (UBL) fully compliant with high-speed specifications revision operation rate 480Mb/s. compliance-proven USB2.0 transceiver design provides standard differential single-ended connection data transmission reception. With existed functional support suspend resume operation, M5621 also utilizes proven low-power CMOS technology further reduce actual operating suspend-mode power consumption USB-based peripheral system. Built-in On-Chip Clock Synthesizer With on-chip clock synthesizer, M5621 allowed nominal low-cost 12MHz crystal oscillator) connecting XTALI XTALO, generates standard internal high-frequency clock interface. external 12MHz clock source available, XTALI input used clock input provide more cost-saving clock circuitry. User-Configurable End-Point Control M5621 supports four user-configurable end-point control units with standard command decoder, automatic CRC-checking handshaking fully meet specification. associated command decoding operational descriptions described below. 3.5.1 Endpoint This Endpoint designed command transfer including standard, class, vendor commands. built-in decodes following standard commands, checks handshakes automatically. SET_FEATURE, CLEAR_FEATURE, SET_CONFIGURATION, GET_CONFIGURATION, SET_INTERFACE, GET_INTERFACE SET_ADDRESS, GET_STATUS Other un-decoding commands transferred micro-controller service. 3.5.2 Endpoint (BULK with DMA)
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DEC. 2001 Document 5621IDEda03.doc Acer Labs 246, NeiHu Rd., Taipei, 114, R.O.C. Tel: 886-2-8752-2000, Fax: 886-2-8751-1001 Homepage www.ali.com.tw
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M5621 High-Speed USB2.0 Device Controller
This Endpoint designed general data transfer with support link controller (IDEC). maximum data transfer rate Mbytes/Sec from IDEC Endpoint supported package size bytes transfer, bytes transfer. 3.5.3 Endpoint (BULK with DMA) This Endpoint designed general data transfer with support link controller (IDEC). maximum data transfer rate Mbytes/Sec from Endpoint ICEC. supported package size bytes transfer, bytes transfer 3.5.4 Endpoint (Interrupt BULK This endpoint designed interrupt transaction, used only (Control, Bulk, Interrupt) transport.
DEC. 2001 Document 5621IDEda03.doc Acer Labs 246, NeiHu Rd., Taipei, 114, R.O.C. Tel: 886-2-8752-2000, Fax: 886-2-8751-1001 Homepage www.ali.com.tw
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Section Application Description
M5621 High-Speed USB2.0 Device Controller
shown below application description USB2.0-to-IDE interface operation. applying USB2.0 PIO/DMA device operation, please refer supplementary technical documentation. Firmware support Through embedded control, M5621 operates with internal ROMSEL low. embedded firmware designed perform direct interface conversion between interface target device. This conversion operation includes handling commands, processing device descriptors, performing data transfer between bus. However, it's required modify commands revise different control behaviors interface conversion process, setting ROMSEL high will allow external programmed activated provide command/instruction access from external firmware. 100-pin package M5621, optional external firmware ROM, since internal should sufficient most USB2IDE application needs. However, M5621's 64-pin package only allow internal firmware used USB2.0-to-IDE operation, pincount limitation.
Programming External PROM M5621's modified adding external PROM. external PROM exists after system power-up, M5621 will access serial interface through EEPROMCLK EEPROMDAT pins. serial data (LSB first resource data) written read from PROM sequentially writing reading mapping registers further described M5621 register definition.
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DEC. 2001 Document 5621IDEda03.doc Acer Labs 246, NeiHu Rd., Taipei, 114, R.O.C. Tel: 886-2-8752-2000, Fax: 886-2-8751-1001 Homepage www.ali.com.tw
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M5621 High-Speed USB2.0 Device Controller
Section Configuration Registers Address FF60: EEPROM Control/Status Register Bit-Name Default Description NONE None EEPROM_RST Reset EEPROM hardware, Self clear after complete EEPROM_START Request EEPROM_START timing, Self clear after complete EEPROM_STOP Request EEPROM_STOP timing, Self clear after complete EEPROM_ACK Request EEPROM_ACK timing, Read check SLAVE_ACK EEPRON_NOACK Request EEPROM_NOACK timing, Self clear after complete EEPROM_READ Request EEPROM_READ timing, Self clear after complete, data will EEPROM_READ_DAT register EEPROM_WRITE Request EEPROM_WRITE timing, Self clear after complete, write data EEPROM_WRITE_DAT register Address FF61: EEPROM_WRITE_DAT register Bit-Name Default EEPROM_WRITE_DAT 00000000 Address FF62: EEPROM_READ_DAT register Bit-Name Default EEPROM_READ_DAT 00000000 Address FF63: EEPROM_TIMER register Bit-Name Default EEPROM_TIMER 00000010
Description Data write SDAT
Description Data read from SDAT
Description SCLK Divider, EEPROM_TIMER*132.8ns
Address FFC0: DEVICE SETTING REGISTER Bit-Name Default Description USBON pull-up resistor turn-off initially. Turn pull-up resistor RES_SPEED Check current speed mode EXP_SPEED Support Support USB2.0, modes. Support USB1.1, mode only. RMT_WKUP_FEAT This reflects host set/clear feature remote wakeup device currently disabled request remote wakeup device currently enabled request remote wakeup SUSPEND_STATUS This reflects suspend mode normal suspend RESUME_WAKEUP suspend mode, asserts this wake-up host system normal wake-up RMT_WKUP_SUPP This data Remote-Wake-up GET_STATUS command don't support remote wake-up support remote wake-up SELF_POWERED This data Self-Powered GET_STATUS command powered self powered
DEC. 2001 Document 5621IDEda03.doc Acer Labs 246, NeiHu Rd., Taipei, 114, R.O.C. Tel: 886-2-8752-2000, Fax: 886-2-8751-1001 Homepage www.ali.com.tw
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M5621 High-Speed USB2.0 Device Controller
Address FFC1: ENDPOINT FIFO CONTROL REGISTER (EP0FCTR) Bit-Name Default Description EP0EMP Endpoint FIFO empty empty EP0FUL Endpoint FIFO full full EP0FRC Force Endpoint current packet output host (available when EP0DIR this self-clear after sending packet) normal force sending EP0INI Clear Endpoint FIFO normal reset Endpoint FIFO EP0OVF EP0DIR=1, EP0FIFO over-written. (MCU write full FIFO) normal over-run EP0DIR=0, EP0FIFO over-read (MCU read from empty FIFO) EP0UNF normal under-run SETUP Indicate setup stage setup stage setup stage EP0DIR Select Endpoint transfer direction SETUP/OUT (MCU receive) (MCU transmit) EP0STALL STALL condition normal STALL (after receiving next setup token, resets this bit) Address FFC2: ENDPOINT FIFO REGISTER (EP0FIFO) Bit-Name Default EP0FIFO<7:0> Endpoint FIFO data port
Description
Address FFC3: ENDPOINT SETTING REGISTER (EPASETR) Bit-Name Default Description EPATYP Type endpoint Reserved Isochronous Bulk Interrupt EPANUM Logical endpoint number disable Endpoint Endpoint Endpoint Endpoint Endpoint Endpoint Reserved disable EPAINTF This indicates interface number which Endpoint belongs Interface Interface EPAFFTYP This bits used define Endpoint FIFO type ping-pong single extend ping-pong
Page DEC. 2001 Document 5621IDEda03.doc Acer Labs 246, NeiHu Rd., Taipei, 114, R.O.C. Tel: 886-2-8752-2000, Fax: 886-2-8751-1001 Homepage www.ali.com.tw
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M5621 High-Speed USB2.0 Device Controller
Reserved
Address FFC4: ENDPOINT FIFO CONTROL REGISTER2 (EPAFCTR) Bit-Name Default Description EPAEMP FIFO EPADS empty empty EPAFUL FIFO EPADS full full EPAFRC Force Endpoint current packet output host (The selfclear after sending packet) normal force sending This available only BULK_IN transfer,. EPAINI Initialize Endpoint FIFO (Both dataset FIFO) normal initialize FIFO EPAOVF EPAFIFO over-written. (MCU write full FIFO) normal over-run EPAALLEMP FIFO (dual dataset FIFO) empty empty, i.e. there data Endpoint FIFO transmission. EPADS interface points Endpoint dataset FIFO dataset FIFO EPASTALL STALL condition normal STALL Address FFC5: ENDPOINT FIFO REGISTER (EPAFIFO) Bit-Name Default EPAFIFO<7:0> Endpoint FIFO data port.
Description
Address FFC6: ENDPOINT SETTING REGISTER (EPBSETR) Bit-Name Default Description EPBTYP Type endpoint Reserved Isochronous Bulk Interrupt EPBNUM Logical endpoint number disable Endpoint Endpoint Endpoint Endpoint Endpoint Endpoint Reserved disable EPBINTF This indicates interface number which Endpoint belongs Interface Interface EPBFFTYP This bits used define Endpoint FIFO type
DEC. 2001 Document 5621IDEda03.doc Acer Labs 246, NeiHu Rd., Taipei, 114, R.O.C. Tel: 886-2-8752-2000, Fax: 886-2-8751-1001 Homepage www.ali.com.tw Page
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M5621 High-Speed USB2.0 Device Controller
ping-pong single extend ping-pong Reserved
Address FFC7: ENDPOINT FIFO CONTROL REGISTER (EPBFCTR) Bit-Name Default Description EPBEMP FIFO EPBDS empty empty EPBFUL FIFO EPBDS full full (Reserved) EPBINI Initialize Endpoint FIFO (Both dataset FIFO) normal initialize FIFO EPBOVF EPBFIFO over-read. (MCU read from empty FIFO) normal over-run EPBALLEMP FIFO (dual dataset FIFO) empty empty, i.e. there data Endpoint FIFO transmission. EPBDS interface points Endpoint dataset FIFO dataset FIFO EPBSTALL STALL condition normal STALL
Address FFC8: ENDPOINT FIFO REGISTER (EPBFIFO) Bit-Name Default EPBFIFO<7:0> Endpoint FIFO data port
Description
Address FFC9: ENDPOINT SETTING REGISTER (EPCSETR) Bit-Name Default Description EPCTYP Type endpoint Reserved Isochronous Bulk Interrupt EPCNUM Logical endpoint number disable Endpoint Endpoint Endpoint Endpoint Endpoint Endpoint Reserved disable EPCINTF This indicates interface number which Endpoint belongs Interface
Page DEC. 2001 Document 5621IDEda03.doc Acer Labs 246, NeiHu Rd., Taipei, 114, R.O.C. Tel: 886-2-8752-2000, Fax: 886-2-8751-1001 Homepage www.ali.com.tw
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M5621 High-Speed USB2.0 Device Controller
EPCFFTYP
Interface This bits used define Endpoint FIFO type ping-pong single Reserved
Address FFCA: ENDPOINT FIFO CONTROL REGISTER (EPCFCTR) Bit-Name Default Description EPCEMP FIFO EPCDS empty empty EPCFUL FIFO EPCDS full full EPCFRC Force Endpoint current packet output host (The selfclear after sending packet) normal force sending This available only BULK_IN transfer,. EPCINI Initialize Endpoint FIFO (Both dataset FIFO) normal initialize FIFO EPCOVF EPCFIFO over-written. (MCU write full FIFO) normal over-run EPCALLEMP FIFO (dual dataset FIFO) empty empty, i.e. there data Endpoint FIFO transmission. EPCDS interface points Endpoint dataset FIFO dataset FIFO EPCSTALL STALL condition normal STALL
Address FFCB: ENDPOINT FIFO REGISTER (EPCFIFO) Bit-Name Default EPCFIFO<7:0> Endpoint FIFO data port
Description
Address FFCC: CLKOUT SELECT REGISTER(CLKSELR) Bit-Name Default Description (Reserved) EOTPOL polarity high active active DMAVLDH_ENJ When read, force validh output dmavalidh enable output dmavalidh disable (Reserved) CLKSELR<2:0> Clkout frequency select 12MHz 24MHz 30MHz
DEC. 2001 Document 5621IDEda03.doc Acer Labs 246, NeiHu Rd., Taipei, 114, R.O.C. Tel: 886-2-8752-2000, Fax: 886-2-8751-1001 Homepage www.ali.com.tw Page
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M5621 High-Speed USB2.0 Device Controller
48MHz 60MHz force High force tri-state
Address FFCD: GPIO REGISTER (GPIOR) Bit-Name Default (Reserved) GPIO_DIR[2:0] GPIO direction input direction output direction (Reserved) GPIO_DATA[2:0] GPIO data
Description
Address FFD5: INTERRUPT ENABLE REGISTER (INTENR1) Bit-Name Default Description ResetIE Enable Reset signal interrupt disable enable SuspendIE/ Enable Suspend/Resume/VBUS signal interrupt ResumeIE/VBusIE disable enable EOTIE Enable EOTInt disable enable EPCTxIE Enable done interrupt Endpoint disable enable EPBRxIE Enable done interrupt Endpoint disable enable EPATxIE Enable done interrupt Endpoint disable enable EP0RxIE Enable done interrupt Endpoint disable enable EP0TxIE Enable done interrupt Endpoint disable enable Address FFD7: INTERRUPT FLAG REGISTER (INTFLR1) Bit-Name Default Description ResetInt receives reset signal SuspendInt/ receives suspend/ resume interrupt ResumeInt/VBUSInt EOTInt DMARInt Either "end-of-transfer active signal" "DMAR down-count from interrupt status asserted cycle stopped. EPCTxD done flag Endpoint EPBRxD done flag Endpoint EPATxD done flag Endpoint EP0RxD done flag Endpoint EP0TxD done flag Endpoint Note This Read-Cleared register, flag always reflect event even interrupt disabled.
Page
DEC. 2001 Document 5621IDEda03.doc Acer Labs 246, NeiHu Rd., Taipei, 114, R.O.C. Tel: 886-2-8752-2000, Fax: 886-2-8751-1001 Homepage www.ali.com.tw
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M5621 High-Speed USB2.0 Device Controller
Address FFD8: test Bit-Name Phy_thd
Default Description current source test mode normal o.w. test mode Phy_sync_len sync. length test mode bits bits bits bits Resvered 0000 Note This Read-Cleared register, flag always reflect event even interrupt disabled. Address FFD9: CONTROL REGISTER (DMACTR) Bit-Name Default Description DMA_INI disable. initial controller. DMA_SYNC async. sync. DMA_CLK DMA_BUS bits bits BURST_MODE Select operation mode burst mode non-burst mode DMA_DIR Select operation direction DMA_MODE Select operation mode quick mode compatible mode DMA_ENABLE uses this enable/disable operation disable enable transfer This auto-cleared when active counter down-count From Address FFDA: COUNTER BYTE REGISTER (DMACLR) Bit-Name Default Description DMAR<7:0> operation counter DMAR's byte register Address FFDB: COUNTER MIDDLE BYTE REGISTER (DMACMR) Bit-Name Default Description DMAR<15:8> operation counter DMAR's middle byte register Address FFDC: COUNTER HIGH BYTE REGISTER(DMACHR) Bit-Name Default Description DMAR<23:16> operation counter DMAR's high byte register Note: When DMAR countdown from terminate-count interrupt generated. Address FFDD: ENDPOINT SIZE REGISTER (EPSIZE) Bit-Name Default EPB_TEST Reserved EPB_SIZE Select package size Description
DEC. 2001 Document 5621IDEda03.doc Acer Labs 246, NeiHu Rd., Taipei, 114, R.O.C. Tel: 886-2-8752-2000, Fax: 886-2-8751-1001 Homepage www.ali.com.tw
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M5621 High-Speed USB2.0 Device Controller
byte byte byte byte byte byte byte 1024 byte (for Interrupt transfer only) Note that this registers designed Bulk Interrupt transfer Interrupt transfer It's fixed 512-byte maximum package Bulk transfer Reserved Select package size byte byte byte byte byte byte byte 1024 byte (for Interrupt transfer only) Note that this registers designed Bulk Interrupt transfer Interrupt transfer It's fixed 512-byte maximum package Bulk transfer
EPA_TEST EPA_SIZE
Address FFDE: TEST1 Bit-Name FFTEST TIMERTEST SETUPDATALOCKEN POWERDOWN EPAEOTFORCE
IRQ_OPENDRAIN DRQ_POL IRQ_POL
Default Description FIFO test timer test mode Setup data lock enable lock lock enable Power down DPLL normal operation power down Endpoint auto force enable when counter down form event. disable enable open drain enable force driving opendrain polarity active high active polarity active high active
Address FFDF: TEST2 Bit-Name DMAEOT ISODMYEN
Default Description test normal test pipe insert dummy bytes enable disable
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DEC. 2001 Document 5621IDEda03.doc Acer Labs 246, NeiHu Rd., Taipei, 114, R.O.C. Tel: 886-2-8752-2000, Fax: 886-2-8751-1001 Homepage www.ali.com.tw
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M5621 High-Speed USB2.0 Device Controller
ISOHBW
CHIPVERSION
0001
enable high bandwidth requirement transfer uSOF transfer uSOF transfer uSOF Chip version
Address FFE0: Mode Register Bit-Name NONE DMA_PIO DMA_MODE PIO_MODE
Default Description None BULK path mode BULK path mode 0~4: UDMA mode 0~4, 7~5: Multiword mode 0~4: mode
Address FFE1: Control/Status Register Bit-Name Default BULK_EN BULK_DIR HOST_STOP FIFO_CLRJ FRC_EOT BUF_EMPTY NONE
Description BULK access FIFO (BULK path enable) Bulk path disable BULK BULK UDMA PIO, self cleared, auto when UDMA, mode Clear FIFO, active, self cleared force EOT, will check buffer empty, self-clear sdram buffer fifos empty None
Address FFE2: Status Register Bit-Name Default Description NONE NONE SUCCESS When access ATA, this signal this command successed. Address FFE3: Control/Status Register Bit-Name Default ATA_RESETJ DASPJ PDIAGJ DMARQ IDE_CSEL ATA_CS_OEJ ATA_CTL_OEJ SOFT_RSTJ
Description Reset device DASPJ PDIAGJ request asserted IDE_CSEL output enable DIORJ/DIOWJ output enable state machine software reset
Address FFE4: counter high Register Bit-Name Default Description DMAR<23:16> 00000000 counter high Register, unit BYTE, decrease each time moving. Only UDMA needed write this register
Address FFE5: counter middle Register, (the unit BYTE, decrease each time moving.) Bit-Name Default Description DMAR<15:8> 00000000 counter middle Register, unit BYTE, decrease each time moving. Only UDMA needed write this register Address FFE6: mode counter Register, (the unit BYTE, decrease each time moving.) Bit-Name Default Description
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DMAR<7:0> Address FFE7: Interrupt MASK Bit-Name EOTINT_EN DEVTERM_EN ATAINT_EN NONE GPIO2INT_EN NONE
M5621 High-Speed USB2.0 Device Controller
00000000 counter Register, unit BYTE, decrease each time moving. Only UDMA needed write this register
Default
Description EOTINT enable DEVICE terminate interrupt enable ATAINT enable None GPIO interrupt enable NONE
Address FFE8: Interrupt FLAG register Bit-Name Default EOTINT DEV_TERMINT ATAINT NONE GPIO2_INT NONE Address FFE9: GPIO_DIR, bit-wise Bit-Name GPIO_DIR Address FFEA: GPIO_DAT Bit-Name GPIO_DAT
Description When counter count from trigger this interrupt DEVICE terminate interrupt When interrupt post edge/high level, trigger this interrupt None When GPIO2 transition, trigger this interrupt NONE
Default Description 00000000 GPIO direction, 0:input only 1:output enable
Default Description 00000000 GPIO Data, when write, output GPIO, when read, read GPIO(not register)
Address FFEB: Misc control register Specialized ASYNC Reset Bit-Name Default Description IFM_DRV_OE DRQ, DACKJ, EOT, DBWRJ, DBRDJ Output Enable IFM_COUNT 0000 master mode timng counter ATA_INT_TYPE interrupt type, edge level EEPROM_EN Enable EEPROM hardware GPIO[1:0] GPIO GPIO[1:0] EEPROM SDAT,SCLK IFM_MODE master/slave mode, Slave mode Master mode Address FFEC: Misc control register Bit-Name Default NONE 00000 IRQ_POL DRQ_POL EOT_POL
Description NONE EXT_IRQ high active, EXI_IRQ active(include mode) IFM_DRQ high active, IFM_DRQ active IFM_EOT high active, IFM_EOT active
Address FFED: Hardware Setting register Bit-Name Default HWSET xxxxxxxx Hardware Setting Register
Description
Address FFF0~FFFF: ports register. Note detailed description register their related operation details, please refer standard specifications.
Page DEC. 2001 Document 5621IDEda03.doc Acer Labs 246, NeiHu Rd., Taipei, 114, R.O.C. Tel: 886-2-8752-2000, Fax: 886-2-8751-1001 Homepage www.ali.com.tw
-Preliminary, Confidential, Proprietary-
M5621 High-Speed USB2.0 Device Controller
Section Electrical Characteristics Absolute Maximum Ratings
Absolute maximum ratings those values beyond which damage device occur. Continuous operation these limits intended should limited those conditions specified under electrical characteristics. Unless otherwise specified, voltages reference ground. Table Absolute Maximum Ratings Item Supply voltage Operating supply voltage (VDD5) Operating supply voltage (VCC, VDD, USBAVDD) input output voltages Storage temperature range (TSTG) Operating temperature (TA) Characteristics VDD5=5.5 3.15 Vss=0V, unless otherwise specified. These values measured under static conditions, under dynamic condition. Table Characteristics Symbol Parameter level input voltage High Level Input voltage level output voltage High level output voltage Input Current Output tri-state leakage Current Suspend Mode Current
Ratings -0.5V 4.5V 5.5V 3.15V 3.6V -0.5V VDD+0.5V
-0.5
VDD5+0.5 ±1.0 ±1.0
Units
Test Conditions
DEC. 2001 Document 5621IDEda03.doc Acer Labs 246, NeiHu Rd., Taipei, 114, R.O.C. Tel: 886-2-8752-2000, Fax: 886-2-8751-1001 Homepage www.ali.com.tw
Page
-Preliminary, Confidential, Proprietary-
Section Timing Diagram
M5621 High-Speed USB2.0 Device Controller
tras
trdw
trah
ADDR valid
IDEIORJ
IDED<15:0>
trdz
trds
trdh
read from device
twas
twrw
twah
ADDR valid
IDEIOWJ
IDED<15:0>
twds
twdh
write device
tras twas trdw twrw trah twah trds twds trdh twdh trdz
timing parameter ADDR setup IDEIORJ falling ADDR setup IDEIOWJ falling IDEIORJ pulse width IDEIOWJ pulse width ADDR hold from IDEIORJ rising ADDR hold from IDEIOWJ rising IDEIORJ data setup IDEIOWJ data setup IDEIORJ data hold IDEIOWJ data hold IDEIORJ data access IDEIORJ data disable
min.
typ.
max.
(ns.)
Page
DEC. 2001 Document 5621IDEda03.doc Acer Labs 246, NeiHu Rd., Taipei, 114, R.O.C. Tel: 886-2-8752-2000, Fax: 886-2-8751-1001 Homepage www.ali.com.tw
-Preliminary, Confidential, Proprietary-
M5621 High-Speed USB2.0 Device Controller
IDEDRQ
IDEDACKJ
IDEIORJ
IDED<15:0>
Multiword read data
IDEDRQ IDEDACKJ
IDEIORJ
IDED<15:0>
Multiword write data
timing parameter Read cycle time Write cycle time IDEIORJ pulse width IDEIOWJ pulse width IDEIORJ data setup IDEIOWJ data access IDEIORJ data hold IDEIOWJ data hold IDEDACKJ IDEIORJ/IDEIOWJ setup IDEDACKJ from IDEIORJ hold IDEDACKJ from IDEIOWJ hold
min.
typ.
max.
(ns.)
DEC. 2001 Document 5621IDEda03.doc Acer Labs 246, NeiHu Rd., Taipei, 114, R.O.C. Tel: 886-2-8752-2000, Fax: 886-2-8751-1001 Homepage www.ali.com.tw
Page
-Preliminary, Confidential, Proprietary-
Section Packaging Information 100-pin TQFP Packaging Dimension
M5621 High-Speed USB2.0 Device Controller
indicator
seating plane
1.50 0.05 (0.002) 1.35 (0.053) 15.85 (0.624) 13.90 (0.547) 15.85 (0.624) 13.90 (0.547) 0.45 (0.018) 0.17 (0.007)
NOM. 1.40 (0.055) 16.00 (0.630) 14.00 (0.551) 16.00 (0.630) 14.00 (0.551) 0.60 (0.024) 0.50 0.22 (0.009)
1.60 (0.063) 0.15 1.45 (0.057) 16.15 (0.636) 14.10 (0.555) 16.15 (0.636) 14.10 (0.555) 0.75 (0.030) (0.039) 0.27 (0.011)
Note Coplanarity 2.70 mils maximum from seating plane. Package body dimensions include mold protrusion. Maximum mold protrusion 0.25 side. Controlling dimension millimeter (inch).
Page
DEC. 2001 Document 5621IDEda03.doc Acer Labs 246, NeiHu Rd., Taipei, 114, R.O.C. Tel: 886-2-8752-2000, Fax: 886-2-8751-1001 Homepage www.ali.com.tw
-Preliminary, Confidential, Proprietary-
M5621 High-Speed USB2.0 Device Controller
64-pin TQFP Packaging Dimension
DEC. 2001 Document 5621IDEda03.doc Acer Labs 246, NeiHu Rd., Taipei, 114, R.O.C. Tel: 886-2-8752-2000, Fax: 886-2-8751-1001 Homepage www.ali.com.tw
Page
-Preliminary, Confidential, Proprietary-
Section Revision History listed brief history ASIC development. VERSION TAPEOUT DATE TAPEOUT LAYERS 2001, Full layer tapeout
M5621 High-Speed USB2.0 Device Controller
DESCRIPTION
Page
DEC. 2001 Document 5621IDEda03.doc Acer Labs 246, NeiHu Rd., Taipei, 114, R.O.C. Tel: 886-2-8752-2000, Fax: 886-2-8751-1001 Homepage www.ali.com.tw
Acer Laboratories Inc. -Preliminary, Confidential, Proprietary-M5621 High-Speed USB2.0 Device Controller Worldwide Distributors Sales Office
Taiwan Acer Laboratories Inc. NeiHu Road, Taipei 114, Taiwan, R.O.C. Tel: 8752 -2000 Fax: 8752 -1001 Acer Sertek 11-15F, 135, Sec. Chien North Road, Taipei 10479,Taiwan, R.O.C. Tel: 2501-0055 Fax: 2501- 2521 Arrow Ally, Inc. 11F, 678, Sec. Road, Taipei, Taiwan, R.O.C. Tel: 2768 6399 Fax: 2768 6390 Asec International Inc. Chung Yang Road, Kang, Taipei, Taiwan, R.O.C. Tel: 2786-6677 Fax: 2786 5257 Hong Kong Lestina International Ltd. 14/F, Park Tower Austin Road, Tsimshatsui, Hong Kong Tel: 852-2735 -1736 Fax: 852-2730 5260 Texny Glorytact (HK) Ltd. Unit 6/F, Kaiser Estate Phase Yuen Street, Hunghom, Kowloon, Hong Kong Tel: 2765 0118 Fax: 2765 0557 Singapore Electronic Resources Ltd. Kallang Bahru, 04-00, Singapore 339341 Tel: 0888 Fax: 1111 Japan ASCII Corporation 8-1, Inarimae, Tsukuba-shi Ibaraki, 305, Japan Tel: 4004 Fax: 1985 Kanematsu Electronic Comp. Corp. Shin-Ohsaki Kangyo Bldg., 6-4, Ohsaki 1-Chome, Shinagawa-Ku, Tokyo, Japan Tel: 3779 7850 Fax: 3779 7898 Macnica Inc. Hakusan High-Tech Park, 1-22-2 Hakusan, Midori-Ku, Yokohama City, Japan Tel: (45) 6116 Fax: (45) 6117 Technova Inc. Daiichi-Seimei Daini Bldg., 2-14-27, Shin-Yokohama, Kouhoku-ku, Yokohama-Shi, Kanagawa, Tel: (45) 472-7800 Fax: (45) 472-7830 Korea Microsystems Co., Ltd. 801, 8/F, Bethel Bldg., 324-1, Yangjae-Dong, Seocho-Ku, Seoul, Korea Tel: 9131 Fax: 9130 Italy EL.CO.MI. Cassanese, 20090 Segrate (MI), Italy Tel: 39-2-26927430 Fax: 39-2-26927410 Germany KaMa GmbH Haupstrasse Maxdorf 67133, Germany Tel: 49-62-37-60678 49-62-37-59336 Denmark C-88 Kokkedai Industripark Kokkedai, Denmark DK-2980 Tel: 45-49-14-48-88 Fax: 45-49-14-48-89
DEC. 2001 Document 5621IDEda03.doc Acer Labs 246, NeiHu Rd., Taipei, 114, R.O.C. Tel: 886-2-8752-2000, Fax: 886-2-8751-1001 Homepage www.ali.com.tw
Page27
-Preliminary, Confidential, Proprietary-
United Kingdom Sabre Advanced Microelectronics Sussex House, Unit Pines Trading Estate, Broad Street Guilford, Surrey 3BH, England Tel: 44-1-483-35444 Fax: 44-1-483-35888 France Microel Fjords- Inneuble OSLO Norvege Courtaboeuf -BP3 Ullis, Cedex 91941, France Tel: 33-1-69-07-08-24 Fax: 33-1-69-07-17-23 Office/European Operations 1830-B Bering Drive Jose, 95112 Tel: (408) 7456 Fax: (408) 7474
M5621 High-Speed USB2.0 Device Controller
This material recyclable.
Acer Labs products licensed medical applications, including, limited life support devices without proper authorization from medical officers. Buyers requested inform sales office when planning products medical applications. Product names used this publication identification purposes only registered trademarks their respective companies. Acer Laboratories Inc. makes warranty products assumes responsibility errors which appear this document does make commitment update information contained herein. Acer Laboratories Inc. retains right make changes these specifications time, without notice. Contact your local sales office obtain latest specifications before placing your order. registered trademark Acer Laboratories Incorporated only used identify products. ACER LABORATORIES INCORPORATED 2001
Page
DEC. 2001 Document 5621IDEda03.doc Acer Labs 246, NeiHu Rd., Taipei, 114, R.O.C. Tel: 886-2-8752-2000, Fax: 886-2-8751-1001 Homepage www.ali.com.tw

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