SMALL-OUTLINE SDRAM MODULE JEDEC-standard, PC100, PC133, 144-pin,
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256, 512MB (x64) SDRAM SODIMM
SMALL-OUTLINE SDRAM MODULE
JEDEC-standard, PC100, PC133, 144-pin, smalloutline, dual in-line memory module (SODIMM) Utilizes SDRAM components 256MB SDRAM) 512MB 64)(x8 SDRAM) Single +3.3V ±0.3V power supply Fully synchronous; signals registered positive edge system clock Internal pipelined operation; column address changed every clock cycle Internal banks hiding access/precharge Programmable burst lengths: full page Auto Precharge Auto Refresh Modes Self Refresh Mode: Standard Power 256MB module: 64ms, 4,096-cycle refresh; 512MB module: 64ms, 8,192-cycle refresh. LVTTL-compatible inputs outputs Serial Presence-Detect (SPD)
MT16LSDF3264(L)HG, MT16LSDF6464(L)HG
latest data sheet, please refer Micron site: www.micron.com/datasheets
ASSIGNMENT 144-Pin Small-Outline DIMM
OPTIONS
Package 144-pin SODIMM (gold) Frequency/CAS Latency MHz/CL MHz/CL MHz/CL Self Refresh Current Standard power
*Consult Micron availability
MARKING
-13E -133 -10E
None
TIMING PARAMETERS
MODULE MARKING -13E -133 -10E PC133 tRCD tRP) 2-2-2 3-3-3 PC100 tRCD tRP) 2-2-2 2-2-2 2-2-2
FRONT DQMB0 DQMB1 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 RAS#
BACK DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQMB4 DQMB5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 CKE0 CAS# CKE1 NC/A12
FRONT DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQMB2 DQMB3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
BACK DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQMB6 DQMB7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
NOTE: (READ) Latency
NOTE: conncected (NC) 256MB module. 512MB module, address input A12.
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256, 512MB (x64) SDRAM SODIMM
ADDRESS TABLE
Refresh Count Device Banks Base Device Configuration Addressing Column Addressing Module Banks 256MB Module (BA0, BA1) (A0-A11) (A0-A9) (S0#, S1#) 512MB Module (BA0, BA1) (A0-A12) (A0-A9) (S0#, S1#)
PART NUMBERS
PART NUMBER
MT16LSDF3264(L)HG-13E_ MT16LSDF3264(L)HG-133_ MT16LSDF3264(L)HG-10E_ MT16LSDF6464(L)HG-13E_ MT16LSDF6464(L)HG-133_ MT16LSDF6464(L)HG-10E_
CONFIGURATION
VERSION
MHz, MHz, MHz, MHz, MHz, MHz,
NOTE: part numbers with five-place code, which last shown designating component revisions. Consult factory current revision codes. Example: MT16LSDF3264(L)HG-133B1.
GENERAL DESCRIPTION
Micron MT16LSDF3264(L)HG MT16LSDF6464(L)HG high-speed CMOS, dynamic random-access, 256MB 512MB memory modules, organized configuration. These modules SDRAMs that internally configured quad-bank DRAMs with synchronous interface (all signals registered positive edge clock signal CK0). Read write accesses SDRAM modules burst oriented; accesses start selected location continue programmed number locations programmed sequence. Accesses begin with registration ACTIVE command, which then followed READ WRITE command. address bits registered coincident with ACTIVE command used select device bank accessed (BA0, select device bank, A0-A11 select device 256MB module; A0-A12 512MB
module). address bits registered coincident with READ WRITE command used select starting column location burst access. These modules provide programmable READ WRITE burst lengths locations, full page, with burst terminate option. auto precharge function enabled provide self-timed device precharge that initiated burst sequence. These modules internal pipelined architecture achieve high-speed operation. This architecture compatible with rule prefetch architectures, also allows device column address changed every clock cycle achieve high-speed, fully random access. Precharging device bank while accessing alternate device bank will hide PRECHARGE cycles provide seamless, high-speed, random-access operation. These modules designed operate 3.3V, lowpower memory systems. auto refresh mode provided, along with power-saving, power-down mode. inputs, outputs clocks LVTTL-compatible. SDRAM modules offer substantial advances DRAM operating performance, including ability synchronously burst data high data rate with automatic column-address generation, ability interleave between device banks order hide precharge time, capability randomly change device column addresses each clock cycle during burst access. more information regarding SDRAM operation, refer 128Mb 256Mb data sheets.
SERIAL PRESENCE-DETECT OPERATION
These modules incorporate serial presence-detect (SPD). function implemented using 2,048bit EEPROM. This nonvolatile storage device contains bytes. first bytes programmed Micron identify module type various SDRAM organizations timing parameters. remaining bytes storage available customer. System READ/WRITE operations between master (system logic) slave EEPROM device (DIMM) occur standard using DIMM's (clock) (data) signals.
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256, 512MB (x64) SDRAM SODIMM
FUNCTIONAL BLOCK DIAGRAM
DQMB0
DQMB4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQMB5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DQMB1 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQMB2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
DQMB6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQMB7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
DQMB3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
RAS# CAS# A0-A11 A0-A12 BA0, CKE0 CKE1 NOTE:
RAS#: SDRAMs U1-U16 CAS#: SDRAMs U1-U16 WE#: SDRAMs U1-U16 A0-A11: SDRAMs U1-U16 A0-A12: SDRAMs U1-U16 BA0, BA1: SDRAMs U1-U16 (U1-U8) (U9-U16) (U1-U8) (U9-U16) SDRAMs U1-U16 SDRAMs U1-U16 resistor values ohms unless otherwise specified.
(U1, U11) (U4, U12, U13) (U6, U14, U15) (U2, U10, U16)
SERIAL
MT16LSDF3264(L)HG (256MB): U1-U16 uses MT48LC16M8A2FB SDRAMs MT16LSDF6464(L)HG (512MB): U1-U16 uses MT48LC32M8A2FB SDRAMs
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256, 512MB (x64) SDRAM SODIMM
DESCRIPTIONS
NUMBERS SYMBOL TYPE DESCRIPTION Command Inputs RAS#, CAS#, (along with S0#,S1#) define command being entered. Clock: driven system clock. SDRAM input signals sampled positive edge also increments internal burst counter controls output registers. Clock Enable: CKE0 CKE1 activate (HIGH) deactivate (LOW) CK0-CK1 signals. Deactivating clock provides POWER-DOWN SELF REFRESH operation (all device banks idle) CLOCK SUSPEND operation (burst access progress). CKE0 CKE1 synchronous except after device enters power-down self refresh modes, where CKE0 CKE1 become asynchronous until after exiting same mode. input buffers, including CK0-CK1, disabled during power-down self refresh modes, providing standby power. Chip Select: enable (registered LOW) disable (registered HIGH) command decoder. commands masked when registered HIGH. considered part command code. Input Mask: DQMB input mask signal write accesses. Input data masked when DQMB sampled HIGH during WRITE cycle. output buffers placed High-Z state (after two-clock latency) when DQMB sampled HIGH during READ cycle. Bank Address: define which device device bank ACTIVE, READ, WRITE, PRECHARGE command being applied. also used program twelfth Mode Register. Address Inputs: A0-A11/A12 sampled during ACTIVE command (row-address A0-A11/A12) READ/WRITE command (column-address A0-A9, with defining auto precharge) select location memory array respective device bank. sampled during PRECHARGE command determine device banks precharged (A10 HIGH). address inputs also provide op-code during LOAD MODE REGISTER command. Serial Clock Presence-Detect: used synchronize presence-detect data transfer from module. RAS#, CAS#, Input CK0, Input
CKE0, CKE1
Input
S0#,
Input
115, 117, 116,
DQMB0- DQMB7
Input
106,110
BA0,
Input
103, 109, 111, 70(512MB), 104,
A0-A11 (256MB) A0-A12 (512MB)
Input
Input
Input/ Serial Presence-Detect Data: bidirectional used Output transfer addresses data into data presencedetect portion module.
NOTE: numbers listed module pin-out order necessarily correlate with symbols.
32/64 SDRAM SODIMM SD16C32_64x64HG_B.pm6; Rev. 11/01
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256, 512MB (x64) SDRAM SODIMM
DESCRIPTIONS (continued)
NUMBERS SYMBOL TYPE DESCRIPTION DQ0-DQ63 Input/ Data I/Os: Data bus. Output 121, 123, 125, 127,131, 133, 135, 137, 100, 122, 124, 126, 128, 132, 134, 136, 113, 129, 143, 102, 114, 130, 107, 119, 139, 108, 120, 70(256MB), Supply Power Supply: +3.3V ±0.3V.
Supply Ground.
Connect: These pins connected these modules.
NOTE: numbers listed module pin-out order necessarily correlate with symbols.
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256, 512MB (x64) SDRAM SODIMM
SDRAM COMPONENT DESCRIPTION
general, 128MB 256Mb SDRAM memory devices used these modules quad-bank DRAMs, that operate 3.3V include synchronous interface (all signals registered positive edge clock signal, CLK). four banks 128Mb device each configured 4,096 bit-rows, bit-columns, input/output bits. four banks 256Mb device configured 8,192 bit-rows columns, input/output bits.
Mode Register Definition
MODE REGISTER mode register used define specific mode operation SDRAM. This definition includes selection burst length, burst type, latency, operating mode write burst mode, shown Mode Register Definition Diagram. mode register programmed LOAD MODE REGISTER command will retain stored information until programmed again device loses power. Mode register bits M0-M2 specify burst length, specifies type burst (sequential interleaved), M4-M6 specify latency, specify operating mode, specifies write burst mode, reserved future use. Address (M12) undefined should driven during loading mode register. mode register must loaded when device banks idle, controller must wait specified time before initiating subsequent operation. Violating either these requirements will result unspecified operation. Burst Length Read write accesses SDRAM burst oriented, with burst length being programmable, shown Mode Register Definition Diagram. burst length determines maximum number column locations that accessed given READ WRITE command. Burst lengths locations available both sequential interleaved burst types, full-page burst available sequential type. full-page burst used conjunction with BURST TERMINATE command generate arbitrary burst lengths. Reserved states should used, unknown operation incompatibility with future versions result. When READ WRITE command issued, block columns equal burst length effectively selected. accesses that burst take place within this block, meaning that burst will wrap within block boundary reached, shown Burst Definition Table block uniquely selected A1-A8 when burst length two; A2-A8 when burst length four; A3-A8 when burst length eight. remaining (least significant) address bit(s) (are) used select starting location within block. Full-page bursts wrap within page boundary reached, shown Burst Definition Table.
MODULE FUNCTIONAL DESCRIPTION
Read write accesses SDRAM burst oriented; accesses start selected location continue programmed number locations programmed sequence. Accesses begin with registration ACTIVE command, which then followed READ WRITE command. address bits registered coincident with ACTIVE command used select device bank accessed select device bank, A0-A11 (for 256MB module), A0-A12 (for 512MB module), select device row. address bits A0-A8, registered coincident with READ WRITE command used select starting device column location burst access. Prior normal operation, SDRAM must initialized. following sections provide detailed information covering device initialization, register definition, command descriptions device operation.
Initialization
SDRAMs must powered initialized predefined manner. Operational procedures other than those specified result undefined operation. Once power applied VDDQ (simultaneously) clock stable (stable clock defined signal cycling within timing constraints specified clock pin), SDRAM requires 100µs delay prior issuing command other than COMMAND INHIBIT NOP. Starting some point during this 100µs period continuing least through this period, COMMAND INHIBIT commands should applied. Once 100µs delay been satisfied with least COMMAND INHIBIT command having been applied, PRECHARGE command should applied. device banks must then precharged, thereby placing device device banks idle state. Once idle state, AUTO REFRESH cycles must performed. After AUTO REFRESH cycles complete, SDRAM ready mode register programming. Because mode register will power unknown state, should loaded prior applying operational command.
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Burst Type Accesses within given burst programmed either sequential interleaved; this referred burst type selected ordering accesses within burst determined burst length, burst type starting column address, shown Burst Definition Table.
Address
Burst Definition Table
Burst Length Starting Column Address A0-A8 (location 0-y) Order Accesses Within Burst Type=Sequential Type=Interleaved 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Supported
Mode Register (Mx)
256MB Module
Reserved* Mode *Should program ensure compatibility with future devices.
Latency
Burst Length
Address
Mode Register (Mx)
512MB Module
Reserved*
Mode
Latency
Burst Length
*Should program M12, M11, ensure compatibility with future devices.
Burst Length Reserved Reserved Reserved Full Page Reserved Reserved Reserved Reserved
Full Page
Burst Type Sequential Interleaved
Latency Reserved Reserved Reserved Reserved Reserved Reserved
M6-M0 Defined
Operating Mode Standard Operation other states reserved
NOTE: full-page accesses: 1,024. burst length two, A1-A8 select blockof-two burst; selects starting column within block. burst length four, A2-A8 select blockof-four burst; A0-A1 select starting column within block. burst length eight, A3-A8 select blockof-eight burst; A0-A2 select starting column within block. full-page burst, full selected A0-A8 select starting column. Whenever boundary block reached within given sequence above, following access wraps within block. burst length one, A0-A8 select unique column accessed, mode register ignored.
Write Burst Mode Programmed Burst Length Single Location Access
Mode Register Definition Diagram
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Latency latency delay, clock cycles, between registration READ command availability first piece output data. latency three clocks. READ command registered clock edge latency clocks, data will available clock edge will start driving result clock edge cycle earlier provided that relevant access times met, data will valid clock edge example, assuming that clock cycle time such that relevant access times met, READ command registered latency programmed clocks, will start driving after data will valid shown Figure Table indicates operating frequencies which each latency setting used. Reserved states should used unknown operation incompatibility with future versions result. Operating Mode normal operating mode selected setting zero; other combinations values reserved future and/or test modes. programmed burst length applies both READ WRITE bursts. Test modes reserved states should used because unknown operation incompatibility with future versions result. Write Burst Mode When burst length programmed M0-M2 applies both READ WRITE bursts; when programmed burst length applies READ bursts, write accesses single-location (nonburst) accesses.
Table Latency
ALLOWABLE OPERATING FREQUENCY (MHz) SPEED LATENCY LATENCY
Figure Latency
COMMAND
-13E -133 -10E
READ
DOUT
Latency
COMMAND
READ
DOUT
Latency
DON'T CARE UNDEFINED
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COMMANDS
following Truth Table provides general reference available commands. more detailed description commands operations, refer 128Mb 256Mb SDRAM component data sheet.
TRUTH TABLE SDRAM COMMANDS DQMB OPERATION
(Note: NAME (FUNCTION) COMMAND INHIBIT (NOP) OPERATION (NOP) ACTIVE (Select bank activate row) READ (Select bank column, start READ burst) WRITE (Select bank column, start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate bank banks) AUTO REFRESH SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER Write Enable/Output Enable Write Inhibit/Output High-Z
NOTE:
RAS# CAS# DQMB ADDR L/H8 L/H8 Bank/Row Bank/Col Bank/Col Code Op-Code
NOTES Valid Active Active High-Z
HIGH commands shown except SELF REFRESH. A0-A11 (256MB), A0-A12 (512MB) define op-code written Mode Register, should driven low. A0-A11 (256MB), A0-A12 (512MB) provide device address. BA0, determine which device bank made active. A0-A8 provide device column address; HIGH enables auto precharge feature (nonpersistent), while disables auto precharge feature; BA0, determine which device bank being read from written LOW: BA0, determine which device bank being precharged. HIGH: both device banks precharged BA0, "Don't Care." This command AUTO REFRESH HIGH, SELF REFRESH LOW. Internal refresh counter controls addressing; inputs I/Os "Don't Care" except CKE. Activates deactivates during WRITEs (zero-clock delay) READs (two-clock delay).
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ABSOLUTE MAXIMUM RATINGS*
Voltage VDD, VDDQ Supply Relative +4.6V Voltage Inputs, Pins Relative +4.6V Operating Temperature, (commercial) +70°C Storage Temperature (plastic) -55°C +150°C Power Dissipation *Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only, functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
ELECTRICAL CHARACTERISTICS OPERATING CONDITIONS
(Notes: notes appear following parameter tables) (VDD, VDDQ +3.3V ±0.3V) PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic inputs INPUT VOLTAGE: Logic inputs INPUT LEAKAGE CURRENT: input (All other pins under test OUTPUT LEAKAGE CURRENT: disabled; VOUT VDDQ OUTPUT LEVELS: Output High Voltage (IOUT -4mA) Output Voltage (IOUT 4mA) SYMBOL VDD, VDDQ -0.3 UNITS NOTES
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SPECIFICATIONS CONDITIONS* 256MB MODULE
(Notes: notes appear following parameter tables) (VDD, VDDQ +3.3V ±0.3V) PARAMETER/CONDITION OPERATING CURRENT: Active Mode; Burst READ WRITE; (MIN) STANDBY CURRENT: Power-Down Mode; device banks idle; STANDBY CURRENT: Active Mode; HIGH; HIGH; device banks active after tRCD met; accesses progress OPERATING CURRENT: Burst Mode; Continuous burst; READ WRITE; device banks active AUTO REFRESH CURRENT HIGH; HIGH SELF REFRESH CURRENT: 0.2V
tRFC tRFC
SYMBOL -13E -133 -10E UNITS NOTES IDD1a IDD2b IDD3a 1,296 1,216 1,136
IDD4a IDD5b IDD6b IDD7b IDD7b
1,336 1,216 1,136 5,280 4,960 4,320
tRFC (MIN) 15.625
Standard power
SPECIFICATIONS CONDITIONS* 512MB MODULE
(Notes: notes appear following parameter tables) (VDD, VDDQ +3.3V ±0.3V) PARAMETER/CONDITION OPERATING CURRENT: Active Mode; Burst READ WRITE; (MIN) STANDBY CURRENT: Power-Down Mode; device banks idle; STANDBY CURRENT: Active Mode; HIGH; HIGH; device banks active after tRCD met; accesses progress OPERATING CURRENT: Burst Mode; Continuous burst; READ WRITE; device banks active AUTO REFRESH CURRENT HIGH; HIGH SELF REFRESH CURRENT: 0.2V
tRFC tRFC
SYMBOL -13E -133 -10E UNITS NOTES IDD1a IDD2b IDD3a 1,056 1,016 1,016
IDD4a IDD5b IDD6b IDD7b IDD7b
1,096 1,096 1,096 4,560 4,320 4,320
tRFC (MIN) 7.81
Standard power
*DRAM components only. Value calculated module bank this operating condition, other banks Power-Down Mode. Value calculated reflects module banks this operating condition.
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CAPACITANCE
(Note notes appear following parameter tables) PARAMETER Input Capacitance: A0-A12, BA0, BA1, RAS#, CAS#, Input Capacitance: CK0, Input Capacitance: CKE0, CKE, S0#, Input Capacitance: DQMB0-DQMB7 Input/Output Capacitance: SCL, SA0-SA2, Input/Output Capacitance: DQ0-DQ63 SYMBOL UNITS 60.8 30.4
ELECTRICAL CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS
(Notes: notes appear following parameter tables) (VDD, VDDQ +3.3V ±0.3V)
CHARACTERISTICS PARAMETER Access time from (pos. edge) Address hold time Address setup time high-level width low-level width Clock cycle time -13E -133 -10E 120,000 120,000 120,000 7.5ns
hold time setup time CS#, RAS#, CAS#, WE#, hold time CS#, RAS#, CAS#, WE#, setup time Data-in hold time Data-in setup time Data-out high-impedance time Data-out low-impedance time Data-out hold time (load) Data-out hold time load) ACTIVE PRECHARGE command ACTIVE ACTIVE command period ACTIVE READ WRITE delay Refresh period (8,192 rows) AUTO REFRESH period PRECHARGE command period ACTIVE bank ACTIVE bank command Transition time WRITE recovery time
SYMBOL tAC(3) tAC(2) tCK(3) tCK(2) tCKH tCKS tCMH tCMS tHZ(3) tHZ(2) tRAS tRCD tREF tRFC tRRD
UNITS
NOTES
Exit SELF REFRESH ACTIVE command
tXSR
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FUNCTIONAL CHARACTERISTICS
(Notes: notes appear following parameter tables) (0°C +70°C)
PARAMETER READ/WRITE command READ/WRITE command clock disable power-down entry mode clock enable power-down exit setup mode input data delay data mask during WRITEs data high-impedance during READs WRITE command input data delay Data-in ACTIVE command Data-in PRECHARGE command Last data-in burst STOP command Last data-in READ/WRITE command Last data-in PRECHARGE command LOAD MODE REGISTER command ACTIVE REFRESH command Data-out high-impedance from PRECHARGE command SYMBOL tCCD tCKED tPED tDQD tDQM tDQZ tDWD tDAL tDPL tBDL tCDL tRDL tMRD tROH(3) tROH(2) -13E -133 -10E UNITS NOTES
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NOTES
voltages referenced VSS. This parameter sampled. VDD, VDDQ +3.3V; MHz, 25°C; under test biased 1.4V. dependent output loading cycle rates. Specified values obtained with minimum cycle time outputs open. Enables on-chip refresh address counters. minimum specifications used only indicate cycle time which proper operation over full temperature range ensured (0°C +70°C). initial pause 100µs required after powerup, followed AUTO REFRESH commands, before proper device operation ensured. (VDD VDDQ must powered simultaneously. must same potential.) AUTO REFRESH command wake-ups should repeated time tREF refresh requirement exceeded. characteristics assume 1ns. addition meeting transition rate specification, clock must transit between between VIH) monotonic manner. Outputs measured 1.5V with equivalent load: Timing actually specified tCKS; clock(s) specified reference only minimum cycle rate. Timing actually specified plus tRP; clock(s) specified reference only minimum cycle rate. Timing actually specified tWR. Required clocks specified JEDEC functionality dependent timing parameter. current will increase decrease proportionally according amount frequency alteration test condition. Address transitions average transition every clocks. must toggled minimum times during this period. Based 10ns -10E, 7.5ns -13E. overshoot: (MAX) VDDQ pulse width 3ns, pulse width cannot greater than third cycle rate. undershoot: (MIN) pulse width 3ns. clock frequency must remain constant (stable clock defined signal cycling within timing constraints specified clock pin) during access precharge states (READ, WRITE, including tWR, PRECHARGE commands). used reduce data rate. Auto precharge mode only. precharge timing budget (tRP) begins -13E; 7.5ns -133 -10E after first clock delay, after last WRITE executed. exceed limit precharge mode. Precharge mode only. JEDEC PC100 specify three clocks. -133/-13E with load 4.6ns guaranteed design. Parameter guaranteed design. value tRAS used -13E speed grade module SPDs calculated from tRP. -10E, 10ns; -133, 7.5ns; -13E, 7.5ns. HIGH during refresh command period tRFC (MIN) else LOW. IDD6 limit actually nominal value does result fail value. Leakage number reflects worst case leakage possible through module pin, what each memory device contributes.
50pF
defines time which output achieves open circuit condition; reference VOL. last valid data element will meet before going High-Z. timing tests have with timing referenced 1.5V crossover point. input transition time longer than then timing referenced (MAX) (MIN) longer 1.5V crossover point. Refer Micron Technical Note, TN-48-09, additional information SDRAM timing. Other input signals allowed transition more than once every clocks otherwise valid levels. specifications tested after device properly initialized.
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CLOCK DATA CONVENTIONS Data states line change only during LOW. state changes during HIGH reserved indicating start stop conditions indicated Figures START CONDITION commands preceded start condition, which HIGH-to-LOW transition when HIGH. device continuously monitors lines start condition will respond command until this condition been met. STOP CONDITION communications terminated stop condition, which LOW-to-HIGH transition when HIGH. stop condition also used place device into standby power mode. ACKNOWLEDGE Acknowledge software convention used indicate successful data transfers. transmitting device, either master slave, will release after transmitting eight bits. During ninth clock cycle, receiver will pull line acknowledge that received eight bits data indicated Figure device will always respond with acknowledge after recognition start condition slave address. both device WRITE operation have been selected, device will respond with acknowledge after receipt each subsequent eight-bit word. read mode device will transmit eight bits data, release line monitor line acknowledge. acknowledge detected stop condition generated master, slave will continue transmit data. acknowledge detected, slave will terminate further data transmissions await stop condition return standby power mode.
Figure Data Validity
Figure Definition Start Stop
DATA STABLE DATA CHANGE DATA STABLE
START
STOP
Figure Acknowledge Response From Receiver
from Master
Data Output from Transmitter
Data Output from Receiver Acknowledge
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EEPROM DEVICE SELECT CODE
most significant (b7) sent first DEVICE TYPE IDENTIFIER Memory Area Select Code (two arrays) Protection Register Select Code CHIP ENABLE
EEPROM OPERATING MODES
MODE Current Address Read Random Address Read Sequential Read Byte Write Page Write
NOTE: VIL.
BYTES
INITIAL SEQUENCE START, Device Select, START, Device Select, `0', Address reSTART, Device Select, Similar Current Random Address Read START, Device Select, START, Device Select,
EEPROM TIMING DIAGRAM
HIGH
SU:STA HD:STA HD:DAT SU:DAT SU:STO
UNDEFINED
SERIAL PRESENCE-DETECT EEPROM TIMING PARAMETERS
SYMBOL
tBUF tHD:DAT tHD:STA
UNITS
SYMBOL tHIGH tLOW
tSU:DAT tSU:STA tSU:STO
UNITS
32/64 SDRAM SODIMM SD16C32_64x64HG_B.pm6; Rev. 11/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
256, 512MB (x64) SDRAM SODIMM
SERIAL PRESENCE-DETECT EEPROM OPERATING CONDITIONS
(Note: (VDD +3.3V ±0.3V) PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic inputs INPUT VOLTAGE: Logic inputs OUTPUT VOLTAGE: IOUT INPUT LEAKAGE CURRENT: OUTPUT LEAKAGE CURRENT: VOUT STANDBY CURRENT: 0.3V; other inputs 3.3V +10% POWER SUPPLY CURRENT: clock frequency SYMBOL UNITS
SERIAL PRESENCE-DETECT EEPROM OPERATING CONDITIONS
(Note: (VDD +3.3V ±0.3V)
PARAMETER/CONDITION data-out valid Time must free before transition start Data-out hold time fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant SCL, inputs Clock period rise time clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time NOTE: voltages referenced VSS. voltages referenced VSS. Timing actually specified tWR. SYMBOL tBUF tHD:DAT tHD:STA tHIGH tLOW tSCL tSU:DAT tSU:STA tSU:STO tWRC UNITS NOTES
32/64 SDRAM SODIMM SD16C32_64x64HG_B.pm6; Rev. 11/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
256, 512MB (x64) SDRAM SODIMM
SERIAL PRESENCE-DETECT MATRIX
(Note:
MT16LSDF3264G ENTRY (VERSION) VALUE SDRAM LVTTL (-13E) (-133) (-10E) (-13E/-133) (-10E) PARITY 15.625/SELF NONE MT16LSDF6464HG ENTRY (VERSION) VALUE SDRAM LVTTL (-133) (-10E) (-13E/-133 (-10E) PARITY 7.8/SELF NONE FULL-PAGE UNBUFFERED (-13E) (-133/-10E) (-13E) (-133/-10E) (-13E) (-133/-10E) (-13E)* (-133) (-10E)
BYTE
DESCRIPTION NUMBER BYTES USED MICRON TOTAL NUMBER MEMORY BYTES MEMORY TYPE NUMBER ADDRESSES NUMBER COLUMN ADDRESSES NUMBER BANKS MODULE DATA WIDTH (bit LSB) MODULE DATA WIDTH (bit MSB) MODULE VOLTAGE INTERFACE LEVELS SDRAM CYCLE TIME, (CAS LATENCY
SDRAM ACCESS FROM CLOCK, (CAS LATENCY MODULE CONFIGURATION TYPE REFRESH RATE/TYPE SDRAM WIDTH (PRIMARY SDRAM) ERROR-CHECKING SDRAM DATA WIDTH MIN. CLOCK DELAY FROM BACK-TO-BACK RANDOM COLUMN ADDRESSES, tCCD BURST LENGTHS SUPPORTED FULL-PAGE NUMBER BANKS SDRAM DEVICE LATENCIES SUPPORTED LATENCY LATENCY SDRAM MODULE ATTRIBUTES UNBUFFERED SDRAM DEVICE ATTRIBUTES: GENERAL SDRAM CYCLE TIME, (-13E) (CAS LATENCY (-133/-10E) SDRAM ACCESS FROM CLK, (-13E) (CAS LATENCY (-133/-10E) SDRAM CYCLE TIME, (CAS LATENCY SDRAM ACCESS FROM CLK, (CAS LATENCY MINIMUM PRECHARGE TIME, (-13E) (-133/-10E) MINIMUM ACTIVE ACTIVE, (-13E) tRRD (-133) (-10E) MINIMUM RAS# CAS# DELAY, tRCD (-13E) (-133/-10E) MINIMUM RAS# PULSE WIDTH, (-13E)* (tRAS MODULE tRP) (-133) (-10E)
NOTE: "1"/"0": Serial Data, "driven HIGH"/"driven LOW." value tRAS used -13E module calculated from tRP. Actual device spec value 37ns.
32/64 SDRAM SODIMM SD16C32_64x64HG_B.pm6; Rev. 11/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
256, 512MB (x64) SDRAM SODIMM
SERIAL PRESENCE-DETECT MATRIX (continued)
(Note2:
MT16LSDF3264G ENTRY (VERSION) VALUE 128MB (-13E/-133) (-10E) (-13E/133) (-10E) (-13E/-133) (-10E) (-13E/-133) (-10E) REV. 1.2B -13E -133 -10E MICRON 100/133 MT16LSDF6464HG ENTRY (VERSION) VALUE 256MB (-13E/-133) (-10E) (-13E/133) (-10E) (-13E/-133) (-10E) (-13E/-133) (-10E) REV. 1.2B -13E -133 -10E MICRON 100/133
BYTE 36-61
DESCRIPTION MODULE BANK DENSITY COMMAND ADDRESS SETUP TIME, tAS, tCMS COMMAND ADDRESS HOLD TIME, tAH, tCMH DATA SIGNAL INPUT SETUP TIME, DATA SIGNAL INPUT HOLD TIME, RESERVED REVISION CHECKSUM BYTES 0-62
65-71
MANUFACTURER'S JEDEC CODE MANUFACTURER'S JEDEC CODE (CONT.) MANUFACTURING LOCATION
73-90
MODULE PART NUMBER (ASCII) IDENTIFICATION CODE
95-98 99-125
IDENTIFICATION CODE (CONT.) YEAR MANUFACTURE WEEK MANUFACTURE MODULE SERIAL NUMBER MANUFACTURER-SPECIFIC DATA (RSVD) SYSTEM FREQUENCY SDRAM COMPONENT CLOCK DETAIL
NOTE: "1"/"0": Serial Data, "driven HIGH"/"driven LOW." Variable Data.
32/64 SDRAM SODIMM SD16C32_64x64HG_B.pm6; Rev. 11/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
256, 512MB (x64) SDRAM SODIMM
FRONT VIEW
2.666 (67.72) 2.656 (67.45) .150 (3.80)
.079 (2.00) (2X) 1.255 (31.88) 1.245 (31.62) .787 (20.00) .236 (6.00) .100 (2.55) .157 (4.00) .043 (1.10) .035 (0.90)
.071 (1.80) (2X)
.079 (2.00) .83.82 (3.30)
.059 (1.50) .024 (.60) 2.386 (60.60) 2.504 (63.60)
.0315 (.80)
BACK VIEW
NOTE: dimensions inches (millimeters) typical where noted.
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E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron registered trademark Micron logo logo trademarks Micron Technology, Inc.
32/64 SDRAM SODIMM SD16C32_64x64HG_B.pm6; Rev. 11/01 Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
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