Overview Power Saving Mechanisms used Architecture Portable consu

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Overview Power Saving Mechanisms used Architecture Portable consu

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Designing Power
Overview Power Saving Mechanisms used Architecture
Portable consumer electronics, such cellular phones, messaging devices, represent lucrative market opportunity embedded systems applications. Developers portable systems have over-riding concern battery life. This need driven demand type embedded processor: which minimal power consumption provides processing performance required sophisticated applications. traditional approach developing low-power processors been spin variants existing architectures. However, these architectures were originally designed provide optimal performance rather than optimal power consumption. meet demands portable applications, processor must designed from ground optimize power consumption. architecture first processor designed specifically sophisticated, power, applications. architecture provides very voltage cores combines number attributes achieve outstanding power consumption. addition providing mechanisms power down processor system logic, architecture focuses minimizing dynamic power consumption when system active. combining performance 32-bit processor with cost power advantages previously available only with 16-bit architectures, architecture enabling technology range embedded applications aimed mass market.
need power
Market requirements driving emergence class highly portable, sophisticated devices. Digital cellular phones continue smaller smarter. Messaging devices, such pagers, functionality such e-mail. Finally, there completely applications, such handheld systems. overriding concern such applications battery life, since highly inconvenient users have constantly recharge device carry spare battery sets. These devices, therefore, present designer with paradox. hand, their small form factor prevents heavy batteries. other hand, their sophistication demands more processing power. Since battery performance increasing fast market requires, designers need improved electronics that provide high performance also maximize battery life reducing power consumption. power consumption provides other benefits portable consumer electronics. some devices, desirable smaller battery reduce weight, making device easier carry around long periods. Another important driver consumer electronics course, cost. addition smaller batteries reducing cost, power consumption helps reduce cost enabling lower cost packaging used. advantages power consumption exclusive portable devices. Although might counterintuitive think that car-borne device requires power consumption, this indeed case airbag controller. Since airbags most likely triggered serious collision, impossible assume that battery will continue supply power electronics. airbag controller must therefore able function from capacitor charge, necessitating minimal power consumption. power something that achieved simply accident. must designed both architectural implementation levels. response market demand truly power solution, Motorola introduced architecture.
power choice
past, most processors were variants processors designed desktop applications. Typically would moved process shrunk reduce power consumption some power management functions added. However, notebook computer user tell you, such variants lead sufficiently long battery life lightweight product. major reason this that original processor architecture designed with optimizing power consumption mind. architecture, designed specifically provide high performance minimal power consumption, sets benchmark power consumption. architecture achieves exceptionally power consumption through variety mechanisms, each which discussed more detail below. System-level power management provide optimal static power management overall system, architecture provides three instructions (stop, wait, doze) that enable external logic disable power parts system. Execution these instructions causes processor assert LPMD1-0 output signals manner described Table LPMD1 LPMD0 Mode STOP WAIT DOZE normal Table power mode signal encoding external logic uses LPMD1-0 inputs determine exactly which parts overall system logic should placed low-power state. external logic also place processor power mode forcing input high. Dynamic power consumption Although reducing static power usage achieves greatest overall reduction power consumption, true power solution must address issue dynamic power consumption. dynamic power consumption, referring power required system when actually being used. architecture optimizes dynamic power consumption both minimizing power needed execute instruction minimizing number bytes that need fetched perform given function. instruction pipeline power instructions discussed earlier provide mechanism power down select parts system when used. With processors themselves becoming more complex, logical extension this only power parts processor that required execute instruction. architecture achieves this benefit through advanced pipeline. instruction pipeline recognizes which processor functions required execute particular instruction. This enables ensure that data only transitioned through processor blocks that actually needed implement instruction. example, instruction would cause data transition through adder through barrel shifter. eliminating unnecessary transitions, architecture prevents switching gates, loads, wires unused blocks, which would otherwise consume additional power. Code density Code density measure many bytes code required implement application function. Code density affects power consumption both statically dynamically. high code density results smaller executable image. This reduces memory requirements, which turn reduces system cost system power consumption. However, there second benefit code density. Every time processor fetches instruction from memory, must cycle. cycles, course, consume power. Since
dense code allows perform equivalent functionality with fewer bytes code, program executing processor will consume less power because will fetch fewer bytes from memory. Although 32-bit architecture, utilizes 16-bit instruction achieve high code density. addition, providing improved code density, 16-bit instruction provides performance advantage over conventional RISC architectures many low-cost applications. common such applications minimize cost through 16-bit bus. Since conventional RISC architectures 32bit wide instructions, they have perform cycles fetch instruction, negatively impacting overall instruction throughput. contrast, architecture would only require single cycle perform instruction fetch, enabling full speed even with 16-bit bus. Rich register further minimize activity, architecture reduces need read write data from memory. achieves this providing rich registers that enables program keep data variables memory while they architecture provides total 32-bit data registers that available system programmers, general purpose registers, alternate register file with registers, scratch registers. Support multiple data sizes Some commonly used data types such chars shorts have 16-bit, rather than 32-bit, representations. This provides additional opportunity architecture reduce power consumption when fetching data from memory. example, architecture would only toggle bits required read write char, minimizing power consumption logic external processor core. Voltage Since dynamic power consumption proportional square supply voltage required, lowering voltage provides disproportionately large boost battery life. processors designed require only volts operate, with future versions planned little volts.
Conclusion
arrival portable mass-market consumer electronic devices created need processor that maximizes battery life through power consumption. architecture represents first processor specifically designed meet requirements such devices. architecture combines high performance with exceptionally power consumption through both static dynamic power management techniques combined with high code density. more information, please refer site http://www.motorola.com/mcore call Motorola Technical Resource Center 800.521.6274.

Overview Power Saving Mechanisms used Architecture Portable consu

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