PAL/NTSC DIGITAL ENCODER NTSC-M, PAL-M, PAL-B, PAL-N EASILY PROGR

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PAL/NTSC DIGITAL ENCODER NTSC-M, PAL-M, PAL-B, PAL-N EASILY PROGR

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STV0117
PAL/NTSC DIGITAL ENCODER
NTSC-M, PAL-M, PAL-B, PAL-N EASILY PROGRAMMABLE VIDEO OUTPUTS MATRIXING RESPECTIVELY NTSC ENCODING DIGITAL FRAME SYNC INPUT/OUTPUT (ODDEVEN) DIGITAL FRAME SYNC EXTRACTION FROM MULTIPLEXED 8-BIT INPUT PORT DIGITAL FIELD SYNC OUTPUT (FSYNC) DIGITAL COMPOSITE SYNC OUTPUT (VCS/HSYNC VCS) DIGITAL HORIZONTAL SYNC INPUT/OUTPUT (VCS/HSYNC HSYNC) SLAVE MASTER OPERATION MODES DUAL MODE CCIR601/SQUARE_PIXEL ENCODING WITH EASILY PROGRAMMABLE COLOR SUBCARRIER FREQUENCIES INTERLACED NON-INTERLACED OPERATION MODE 625LINES/50Hz 525LINES/60Hz 8-BIT MULTIPLEXED CB-Y-CR DIGITAL INPUT INSERTION INTERFACE 6-BIT CLUT CLOSED CAPTIONING MACROVISION COPY PROTECTION PROCESS (VERSION 6.0/6.1) ALLOWED CVBS, LUMINANCE FILTERING WITH TIMES OVERSAMPLING SINX/X CORRECTION PROGRAMMABLE DELAY LUMINANCE PATH DIGITALLY COMPENSATE DELAYS CHROMINANCE FILTERING WITH TIMES OVERSAMPLING SWITCHABLE DEDICATED FILTER COMPONENT 22-BIT DIRECT DIGITAL FREQUENCY SYNTHESIZER COLOR SUBCARRIER MODULATION SERIAL INPUT COLOR SUBCARRIER FREQUENCY CONTROL (CFC) CVBS, SIMULTANEOUS ANALOG OUTPUTS THROUGH 9-BIT DACS
CONTROLLED RISE/FALL TIMES ANALOG SYNCHRONIZATION OUTPUT POWER-DOWN MODE AVAILABLE INDEPENDENTLY EACH 9-BIT DIGITAL INPUT DIGITIZED ANALOG VIDEO WITH DIRECT ACCESS CVBS EASILY CONTROLLED HARDWARE CHIP ADDRESSES ON-CHIP COLOR PATTERN GENERATOR HIGH TESTABILITY WITH FULL SCAN METHODOLOGY (FAULT COVERAGE 98%) COMPATIBILITY WITH STV0116 (PAL/NTSC DIGITAL ENCODER WITH OUTPUTS) APPLICATIONS SATELLITE CABLE DECODERS, MULTIMEDIA TERMINALS
DESCRIPTION STV0117is digital video device implemented pure CMOS technology multimedia, digital computer applications. STV0117converts digital output Video MPEG Decoder into standard analog baseband NTSC/PAL signal with color subcarrier modulation. STV0117 handle interlaced mode (with line standards), non-interlaced mode (with line standards), with square rectangular pixels encoding. STV0117 performs closed captions encoding allows MACROVISION 6.0/6.1copy protection process. Both composite SVHS format video signals simultaneously issued three analog outputs, respectively CVBS,
PLCC44 (Plastic Chip Carrier) ORDER CODE STV0117
Note This device protected patent numbers 4631603, 4577216 4819098 other intellectual property rights. This device protected U.S. patent numbers 4,631,603, 4,577,216 4,819,098 other intellectual property rights. Macrovision's copy protection technology device must authorized Macrovision intended home other limited pay-per-view uses only, unless otherwise authorized writing Macrovision. Reverse engineering disassembly prohibited. Please contact your nearest SGS-THOMSON Microelectronics sales office more information.
1996
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STV0117
CONNECTIONS
TESTSCAN NRESET H6OSD
VDDC
VSSP
ODDEVEN VCS/HSYNC YCRCB7 YCRCB6 YCRCB5 YCRCB4 YCRCB3 YCRCB2 YCRCB1 YCRCB0 DVID0
TESTAUTO IREF CVBS VDDA VSSA CSI2C FSYNC EDVID
DVID1
DVID2
DVID3
DVID4
DVID5
DVID6
DVID7
CKREF
DVID8
VDDP
VSSC
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0117-01.EPS
STV0117
DESCRIPTION
Symbol NRESET Type Input Input Triggered Input Input Function Second pixel index 1-bit input. Minimum OSD_pixel width H6OSD period. First pixel index (MSB) 1-bit input. Minimum OSD_pixel width H6OSD period. serial clock line (internal 5-bit majority logic). serial data line triggered input (internal 5-bit majority logic). Open drain output, minimum level duration 200ns. Asynchronous reset, active LOW. priority over software reset (see REGISTER4). NRESET imposes default states (see REGISTERS DESCRIPTION reset procedure FUNCTIONAL DESCRIPTION). Minimum level required duration CKREF periods. Digital positive supply voltage core (+5V). ODDEVEN video frame signal input slave modes, except when SYNC extracted from YCRCB data, output master modes when SYNC extracted from YCRCB data. Synchronous rising edge CKREF. Default polarity odd(top) field HIGH level, even(bottom) field level. Default mode slave ODDEVEN HSYNC, both with rising active edge. Composite horizontal synchronization signal input slave mode HSYNC input (defined sym2 output other modes HSYNC. Synchronous rising edge CKREF. Default polarity leading edge pulse rising Default mode slave ODDEVEN HSYNC, both with rising active edge. Time multiplexed 4:2:2 luminance chrominance data defined CCIR Rec601-2 Rec656 (except input levels). Timing Rec656-partII CCIR rectangular pixels square pixels data chapter DATA INPUT FORMAT FUNCTIONAL DESCRIPTION. This interfaces with MPEG video decoder output port.
VDDC ODDEVEN
Supply
VCS/HSYNC
YCRCB7 YCRCB6 YCRCB5 YCRCB4 YCRCB3 YCRCB2 YCRCB1 YCRCB0 DVID0 DVID1 DVID2 DVID3 DVID4 VDDP CKREF
Input
Input (default mode) LSBs digitized analog video direct access CVBS 9-bit inputs. Enabled software or/and hardware. Tristate output test purpose only. Digital positive supply voltage ring (+5V). Clock reference signal rising edge reference setup hold times inputs, propagation delay outputs (except output). Frequency 27MHz CCIR601 square pixel mode 24.5454MHz 29.50MHz. Digital ground core. Input (default mode) MSBs digitized analog video direct access CVBS 9-bit inputs. Enabled software or/and hardware. Tristate output test purpose only. Hardware control signal DVID inputs select when this control allowed software EDVID HIGH level, then DVID data enabled DVID data input CVBS 9-bit DAC, EDVID level, then DVID data disabled DVID data ignored CVBS 9-bit DAC. When this control disabled software DVID[8:0] inputs controlled software whatever level EDVID input.
Supply Input
VSSC DVID5 DVID6 DVID7 DVID8 EDVID
Supply
Input
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0117-01.TBL
STV0117
DESCRIPTION (continued)
Symbol Type Input Function Color subcarrier frequency control line 23-bit stream line, synchronous CKREF. standby mode, must HIGH level. Reception starts with level then 22-bit word received increment color subcarrier direct digital frequency synthesizer, then line returns standby mode HIGH level. This real time control enabled software color lock interface. This line ignored default. Field synchronization signal, synchronous CKREF. horizontal sync signal generated every field beginning. Default polarity positive (like HSYNC). Hardware chip address select when LOW, chip addresses hexadecimal, when HIGH, chip addresses hexadecimal. Analog ground DACs. Analog positive supply voltage DACs (+5V). Current analog video composite signal CVBS must connected analog ground over load resistor (RL). Between load resistor video equipment, analog pass filter necessary suppress alias signal. CVBS amplitude typically 2.48VPP proportional IREF. Current analog chrominance signal S-VHS output set. must connected analog ground over load resistor (RL). Between load resistor video equipment, analog pass filter necessary suppress alias signal. amplitude typically 1.6VPP proportional IREF. Reference current source 9-bit DACs CVBS,YS,C. IREF must connected analog ground over reference resistor REF). IREF range from 6mA. Current analog luminance with composite synchronization signal S-VHS output set. must connected analog ground over load resistor (RL). Between load resistor video equipment, analog pass filter necessary suppress alias signal. amplitude typically 2.0VPP proportional IREF. Hardware autotest mode control, active HIGH. TESTAUTO input forces master mode with color pattern outputs. Digital ground ring. CKREF/4 clock signal external generator clock output stage. Synchronous CKREF controlled software inactive default (LOW level). Full scan test mode control, active HIGH. TESTSCAN must ground normal operation. Fast blanking signal control 3x1bit inputs, active HIGH. Synchronous H6OSD CKREF. must level autotest mode. Third pixel index (LSB) 1-bit input. Minimum OSD_pixel width H6OSD period.
FSYNC
Output
CSI2C
Input
VSSA VDDA CVBS
Supply Supply Output
Output
IREF
Input
Output
TESTAUTO VSSP H6OSD
Input Supply Output
TESTSCAN
Input Input
Input
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0117-01.TBL
Interpolation TESTAUTO VDDC VDDP
ODDEVEN VCS/HSYNC FSYNC
BLOCK DIAGRAM
CLUT
VDDA
COLOR BARS CKREF DELAY 6MHz
CKREF
CLOSED-CAPTION GENERATOR SYNC
COPY PROTECTION GENERATOR
OFFSET
Output Stage CVBS
DELAY
DVID
YCRCB
DEMUX
MATRIX CKREF
Output Stage
0.5MHz COLOR BURST
MODULATOR GAIN
Pins
1.3MHz
Synchro
Output Stage
DVID TEST DECODER COLOR SUBCARRIER SYNTHESIZER
RESET Pins TESTSCAN CSI2C NRESET DVID
CLOCK Reset
VSSC
STV0117
IREF
VSSP VSSA H6OSD CKREF EDVID
STV0117
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0117-02.EPS
STV0117
FUNCTIONAL DESCRIPTION STV0117 operate either slave mode locking onto vertical parity synchronization signal received from MPEG video decoder, master mode supplying sync signal this device. using bus, allowed control following main functions selection standard, synchronization mode polarity, CCIR601 square pixel data format, interlaced non-interlaced mode, reset synchronization, luminance delay adjustment, chrominance filter selection, reset oscillator, subcarrier phase frequency adjustment, color killer, closed captions encoding, MACROVISION 6.0/6.1 copy protection processing, insertion, power-down mode each DAC. Data Input Format digital input time multiplexed [[CB,Y,CR], 8-bit stream. Input samples taken into account rising edge CKREF clock input signal (see Figure Dual mode CCIR601/square_pixelencoding performed with semi-automaticprogrammation subcarrier frequencies from master clock (CKREF) shown Table Table
Application Vertical Resolution CKREF Frequency (MHz) Field Rate (Hz) Pixel Rate (MHz) Standard
Table
Active Pixels Line
PAL-B, PAL-N NTSC-M, PAL-M PAL-B, PAL-N NTSC-M, PAL-M
CCIR601 CCIR601 Square Pixel (graphics) Square Pixel (graphics)
13.5 13.5 14.75 12.2727
Square pixel and/or non-interlaced modes updated beginning frame (see Figure non-interlaced mode, 624/2 line mode 524/2 line mode with waveforms like first field CCIR SMPTE specifications (see Figures 10). Video Timing STV0117 outputs interlaced non-interlaced video PAL-B, PAL-N, PAL-M NTSCM standards. field (for PAL) field (for NTSC) burst sequences internally generated, with CKREF reference. Rise fall times synchronization tip, blanking burst envelope areinternally controlledaccording composite video specification. Lines inside Vertical Interval blanked others included Blanking Interval blanked controls (not assumed default). Vertical Blanking Interval corresponds following lines 525/60 system lines 1-19 half line line (SMPTE line number convention), 625/50 system half line line lines 311-335 (CCIR line number convention). Video half lines assumed only when preceding Vertical Interval. This case following lines 525/60 system line (SMPTE line number convention), 625/50 system line (CCIR line number convention).
PAL-B, PAL-N NTSC-M, PAL-M PAL-B, PAL-N NTSC-M, PAL-M
CCIR601
13.5
CCIR601 Square Pixel (graphics) Square Pixel (graphics)
29.50
13.5 14.75
24.5454
12.2727
input pixel data STV0117 integer relationship number clock cycles horizontal line detailed Table
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Total Pixels Line
Application
Pixel Clock (MHz)
Standard
STV0117
FUNCTIONAL DESCRIPTION (continued) CCIR656 compliant digital line, "active" portion line portion included between (Start Active Video) (End Active Video) words. However, this digital active line starts somewhat earlier than active line usually defined analogue standards. approach retained STV0117 encode full digital line. Thus, output waveform will reflect full YCRCB stream included between Figure reFigure Data Input Format flects. Should absolutely necessary obtain analogue active line that starts later than digital active line, solution input YCRCB stream that starts with samples black level after word. Autotest mode operating when allowed TESTAUTO (HIGH level) programming. This mode master mode which encodes color pattern appropriate selected standard (see Figure 11).
128T
NTSC,
244T 1440T Digital Active Line 1716T 137T 146T (PAL 128T 264T 1440T
1728T 151T
115T
Square Pixel 525/60 System
236T
1280T
1560T 131T
139T
Square Pixel 625/50 System
300T
1536T
1888T 169T
Note burst envelope shown here indicates location from which first subcarrier positive zero crossing seeked (with respect reference). burst always start with such positive zero crossing.
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0117-03.EPS
Clock Period NTSC 37.037ns Square Pixel 33.898ns Square Pixel NTSC 40.75ns
STV0117
FUNCTIONAL DESCRIPTION (continued) Figure Square Pixel and/or Non-interlaced Mode Switch
MASTER MODE
ODDEVEN (Output)
(see Figure other timings) Field2 Field1 Clock period change square pixel mode switches
CKREF Update sqpix intrl bits HSYNC (Output)
SLAVE MODE ODDEVEN HSYNC
ODDEVEN (Input) HSYNC (Input) Field1
(see Figure other timings)
Clock period change square pixel mode switches CKREF Update sqpix nintrl bits
SLAVE MODE ODDEVEN ONLY
ODDEVEN (Input)
(see Figure other timings)
Field1 Clock period change square pixel mode switches
0117-04.EPS
CKREF Update sqpix nintrl bits
Notes These diagrams valid with contents "delay" "synchro-delay" registers equal default value. on-the-fly format changing required, clock switching must synchronized onto start frame shown above waveforms. Internally, "sqpix" "nintrl" bits update taken into account beginning frame.
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STV0117
FUNCTIONAL DESCRIPTION (continued) Figure Interlaced Mode (nintrl I2C) Master Mode
Frame Active Edge
ODDEVEN
EVEN
HSYNC
FSYNC Line Number SMPTE CCIR
Figure Non-interlaced Mode (nintrl I2C) Master Mode
Frame Active Edge
ODDEVEN
EVEN
HSYNC
FSYNC Line Number SMPTE-like CCIR-like .262,1. .262,1.
0117-06.EPS
Notes These diagrams valid sys0 sys1 Register (i.e. synchro active edges defined rising). slave mode, only edge (the "active edge") incoming ODDEVEN taken into account synchronization. "non-active edge" critical position differ half line from location shown master mode.
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0117-05.EPS
STV0117
FUNCTIONAL DESCRIPTION (continued) Figure NTSC-M Typical Waveforms (interlaced mode) (SMPTE-525 line numbering convention)
VBI1
0.5H
VBI2
0.5H VBI3
VBI4
0117-39.EPS
Figure
NTSC-M Typical Waveforms (non-interlaced mode) ("SMPTE-like" line numbering convention)
0117-40.EPS
0.5H
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STV0117
FUNCTIONAL DESCRIPTION (continued) Figure PAL-M Typical Waveforms (interlaced mode) (CCIR-525 line numbering convention)
Figure PAL-M Typical Waveforms (non-interlaced mode) ("CCIR-like" line numbering convention)
Burst phase toggles every line
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0117-42.EPS
0117-41.EPS
III,
Frame synchronizationreference 5th, 6th, 7th, fields Burst phase nominal value +135° Burst phase nominal value -135° Burst suppressioninternal
STV0117
FUNCTIONAL DESCRIPTION (continued) Figure PAL-BGHI Typical Waveforms (interlaced mode) (CCIR-625 line numbering convention)
Figure PAL-BGHI Typical Waveforms (non-interlaced mode) ("CCIR-like" line numbering convention)
Burst phase toggles every line
Figure Video Timing Master Mode Auto-test Mode NTSC CVBS Signal
line
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0117-07.EPS
0117-44.EPS
0117-43.EPS
Frame synchronizationreference III, 5th, 6th, 7th, fields Burst phase nominal value +135° Burst phase nominal value -135° Burst suppression internal
STV0117
FUNCTIONAL DESCRIPTION (continued) Reset Procedure hardware reset performed grounding NRESET. This will STV0117 slave mode driven ODDEVEN HSYNC input Pins, NTSC-M standard, with CCIR601 rectangular pixel interlaced mode encoding. After power-on reset, MACROVISION copy protection process disabled closed captions encoded then, programming and/or software reset will STV0117 customized operation mode partially fully automatic way. registers never reset, their contents unknown until first loading (see REGISTERS DESCRIPTION). During reset hardware operation after reset released, digital stages input mode. This case ODDEVEN, HSYNC signals DVID[8:0] data. also possible perform software reset setting "softrst" register IC's response that case similar response after hardware reset, except that control configuration registers altered (register Note that after writing into "softrst" (register necessary stop sequence after register start transfer sequence send data next registers. Master Mode After software reset, synchronization generator starts counting CKREF clock pulses provides complete repetitive composite synchronization pulse sequence. that mode, time base circuit runs continuously. This field sequence NTSC-M field sequence PAL. Whatever standard, ODDEVEN signal composite horizontal synchronization signal (VCS/HSYNC Pin) delivered control MPEG video decoder. Non-interlaced and/or square pixel encoding performed when selected programmation. timings sync signals depend whether square pixel non-interlaced modes have been selected also affected "delayregisters" "synchro-delay-registers" (see Figure 12). Slave Modes Three slave modes selectable bus, "mod" (register should enable slave mode. Line-locked Sync (sym2 sym1 register After sofware reset, synchronization counter waits rising edge ODDEVEN HSYNC signals sent video source. slave mode ODDEVEN HSYNC, first active transition ODDEVEN initializes internal line counter simultaneous first following active transition HSYNC intializes sample counter. line length shorter equal nominal value sample counter reinitialized internal active signals depending sample counter inactive. last pixels digital line output that case however encoded video within analog video requirements. line length longer than nominal value: sample counter stopped when reaching nominal line waiting next HSYNC active edge reinitialize itself. Note that phase relationship between HSYNC incoming YCRCB data should such that first clock rising edge following HSYNC active edge always samples "Cb" (see Figure 13). Field count incremented each ODDEVEN transition. Line counter reset each active edge ODDEVEN. Frame-locked Sync (sym2 sym1 register Alternatively, slave mode performed with ODDEVEN input only, STV0117 extract synchronizationfrom YCRCB input data sequence ODDEVEN signal from sequence (see Figure 14)). After sofware reset, synchronization counter waits first active edge ODDEVEN first falling edge sent digital video source. Once appropriate sync signals have been selected, sequence identical that master mode start repeated until consecutive checks ODDEVEN location fail. latter case, stops outputting HSYNC and, applicable, ODDEVEN, blanks video outputs until rising edge occurs ODDEVEN onto which locks again (see Figure 15). Note that phase relationship between ODDEVEN incoming YCRCB data should such that first clock rising edge following ODDEVEN active edge always samples "Cb".
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STV0117
FUNCTIONAL DESCRIPTION (continued) Figure Master (with sys0 sys1 Register
MasterSignal
ODDEVEN
FSYNC
ODDEVEN
HSYNC
FSYNC ODDEVEN Output DODD CKREF HSYNC Output DSYNC FSYNC Synchro-delay registers 4.7µs
0117-09.EPS
Delay registers
Synchro-delay registers
YCRCB
Notes These diagrams valid when delay registers loaded (default values) delay register value then ODDEVEN edge shifted left, else ODDEVEN edge shifted right. synchro_delay register value then HSYNC FSYNC edges shifted right, else they shifted left. Master signal goes when soft/hard autotest mode master mode selected. keep sequence correct, synchro-delay register must changed four steps four steps.
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STV0117
FUNCTIONAL DESCRIPTION (continued) Figure HSYNC ODDEVEN Based Slave Mode Sync Signals
CKREF
ODDE
registers
0117-45.EPS
YCRCB
Notes Diagram valid contents "delay" "synchro-delay" register default. ODDEVEN HSYNC synchronization mode, ODDEVEN HSYNC change level same time, alternatively ODDEVEN change first next HSYNC flags start first line frame.
Figure Slave Mode, Synchro (extracted from EAV)
YCRCB CKREF igna ODDE
Note Diagram valid both registers delay synchro-delay loaded (default values).
0117-10.EPS
gisters cr128 cb129 y129
Adjustment ynchro-de giste
Figure Slave Mode, Synchro ODDEVEN
Delay gisters YCRCB CKREF ODDEVEN FSYNC
Note Diagram valid both registers delay synchro-delay loaded (default values).
0117-11.EPS
cr128
cb129 y129
Adjus tment (synchro-de registe
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STV0117
FUNCTIONAL DESCRIPTION (continued) Chrominance Encoding demultiplexed samples feed chrominance matrix NTSC-M matrix PAL). signals then band limited according CCIR Rec624 interpolated CKREF clock rate. This processing makes easier filtering conversion allows more accurate encoding. Figure Chroma Filter
(dB)
0117-12.EPS
modulation with color subcarrier signal, components band limited 1.3MHz 0.5MHz case data issued from graphics source, bandwidth extended 1.8MHz components (see Figures curves different filters). Figure Chroma Filter (zoom)
(dB)
0117-13.EPS 0117-15.EPS
x106 (Hz)
x105 (Hz)
Figure Chroma Filters
(dB)
0117-14.EPS
Figure Chroma Filters (zoom)
1.75MHz 1.25MHz
(dB)
1.75MHz 1.25MHz
x106 (Hz)
x106 (Hz)
Note Those filter curves include sinX/X attenuation DACs.
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STV0117
FUNCTIONAL DESCRIPTION (continued) Color Subcarrier Generator Direct Digital Frequency Synthesizer (DDFS), using 22-bit phase accumulator, generates required color subcarrier frequency. This oscillator feeds quadrature modulator which modulates baseband chrominance signal components. Color subcarrier frequency computed according following equation (22-bit increment word/222) CKREF phase frequency color subcarrier adjusted software. external clock considered sufficiently stable ensure correct encoding. When performing external Gen-locking, frequency reference generated clock slightly deviate dependingon line length measurement. prevent this drift from corrupting colors, color subcarrier frequency control line (CFC Pin) used update 22-bit increment DDFS keep color subcarrier stable (see Figure 20). Internal options provide reset color subcarrier phase every fields compensate drift introduced finite accuracy calculations. Burst Insertion start time color burst positive zero crossing color subcarrier waveform that follows burst window. This window location given Table first last half cycles have reduced amplitude that burst envelope starts ends smoothly. Table
Application CKREF Frequency (MHz) Standard Burst Window Location from
burst inserted PAL-N standards) (PAL-B, subcarrier cycles. Phase shift directly performed within DDFS during burst insertion specified Table Table
Subcarrier Freq. (MHz) CCIR601/ Square Pixel Phase Shift Line (Degrees)
(plus line alternance) (plus line alternance) +180 (plus line alternance)
PAL-B, PAL-N NTSC-M PAL-M
Standard
4.4336187 3.5820558 3.5795452 3.5756114
Note that except square pixel mode, subcarrier frequencies readily customized with following procedure Program required increment registers "selrst" register Perform software reset (register Luminance Encoding demultiplexed samples band limited interpolated CKREF clock rate. Then gain offset compensation applied luminance signal before inserting closed captions data, Macrovision copy protection signals synchronization pulses. pedestal selected automatically 60Hz field rate mode added 50Hz field rate mode distinguish PAL-N standards (see REGISTERS DESCRIPTION). interpolation filter compensates sinx/x attenuation conversion greatly simplifies external output stage filter (see Figures curves). programmable delay inserted luminance data pathto offset chroma/luma delay introduction off-chip filtering (see REGISTERS DESCRIPTION). default, luminance chrominance transitions aligned analogue outputs.
PAL-B, PAL-N NTSN-M PAL-M PAL-B, PAL-N NTSN-M, PAL-M
CCIR601 CCIR601 CCIR601 Square Pixel (Graphics) Square Pixel (Graphics)
29.50 24.5454
+151 CKREF periods +137 CKREF periods +146 CKREF periods +169 CKREF periods +131 CKREF periods
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STV0117
FUNCTIONAL DESCRIPTION (continued) Figure Color Subcarrier Frequency Control Word Transmission Format
CKREF
Stand-by Start level 22-bit increment (absolute value)
Stand-by level
Active edge CKREF rising edge. Possible parallel load 22-bit increment update
COLOR SUBCARRIER FREQUENCY CONTROL WORD UPDATE
Burst Location
HSYNC Input HSYNC Output
Loading Oscillator 22-bit Increment Update
TCKREF
Figure Luma Filters
(dB)
0117-16.EPS
Figure Luma Filters (zoom)
x106 (Hz)
x106 (Hz)
Note Those filter curves include sinX/X attenuation DACs.
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0117-17.EPS
(dB)
0117-28.EPS
Immediate update after serial loading CKREF period) Update next line start (HSYNC active edge) Update next burst start word ignored
STV0117
FUNCTIONAL DESCRIPTION (continued) Closed Captions Encoding Data, according closed caption specifications, extended data service encoded circuit. closed caption data delivered circuit through control interface. dedicated pairs bytes (two bytes field), each pair preceded clock run-in start encoded inserted luminance path selected line. serial loading should performed odd-parity first, then US-ASCII 7-bit character last. Register (resp. register first byte sent (LSB first) after start appropriate line field1 (resp. field2), register (resp. register second byte. line number where data encoded programmable (see REGISTERS DESCRIPTION). Direct Digital Frequency Synthesizer (DDFS), using phase accumulator, generates required run-in frequency. phase frequency run-in oscillator generated different standards. nominal instantaneousdata rate 503496.5Hz (i.e. times NTSC line frequency). Should closedFigure Closed Caption Line CKREF 27MHz NTSC-M CVBS Analog Signal
0117-21.EPS
captioning needed conjunction with PAL, this same data clock frequency would still used, closed-caption absolute timings would unchanged. Closed captions also encoded square pixel mode nominal data rate keeps same. Data corresponds nominally IRE, data HIGH corresponds outputs. When closed-captioning microcontroller should load relevant registers (reg. once every frame (possibly less) average. closed caption encoder considers that closed caption data been loaded valid completion write operation into register field1, into register field closed caption encoding data bytes have been written into closed caption dataregisters when closed caption data slot starts appropriate line, then circuit outputs US-ASCII NULL characters with parity after start (see Figures 26). Figure Closed Caption Line CKREF 27MHz PAL/CCIR CVBS Analog Signal
61µs
61µs 27.35µs 13.9µs 10µs
cycles 504kHz
1000
Characters NULL
27.35µs 13.9µs 10µs
cycles 504kHz
Transition time 220ns
Transition time 220ns
Figure Closed Caption Line CKREF 24.5454MHz NTSC-M CVBS Analog Signal Square Pixel
0117-23.EPS
Figure Closed Caption Line CKREF 29.5MHz Lines CVBS Analog Signal Square Pixel
1200
61.2µs
61.2µs 27.4µs Characters NULL 13.9µs 10µs
cycles 504kHz
1000
10.2µs
27.5µs 13.9µs
cycles 504kHz
Transition time 240ns
Transition time 200ns
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0117-24.EPS
0117-22.EPS
STV0117
FUNCTIONAL DESCRIPTION (continued) CVBS SVHS Outputs luminance band-stop filter implemented remove chrominance from luminance part composite video channel. Each digital video signal drives 9-bit converter operating CKREF clock rate. outputs current sources proporTable
Signal CVBS Resolution bits bits bits Maximum Voltage (IREF 2mA, 300) 1.24VPP 1.24VPP (0.8VPP nominal 100/0/100 625l color bar) 1.24VPP (1.0VPP nominal 100/0/100 625l color bar)
tional current reference source (IREF Pin). integrated oversampling stages make external antialiasing pass filters simpler (see Figures 29). Unused must connected ground disabled control (separate power-down modes).
Figure Composite NTSC Output (100% Saturation, 100% Amplitude Color Bars)
MAGENTA YELLOW GREEN BLACK WHITE LEVEL 3.58MHz COLOUR BURST CYCLES)
WHITE
CYAN
1205
BLANK LEVEL
BLUE
BLACK LEVEL BLANK LEVEL
0117-25.EPS
8LSB
SYNC LEVEL
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STV0117
FUNCTIONAL DESCRIPTION (continued) Figure Composite PAL-B, PAL-N setup) Output (100% Saturation, 100% Amplitude Color Bars)
MAGENTA YELLOW GREEN BLACK WHITE LEVEL 4.43MHz COLOUR BURST CYCLES) 21.5 21.5
0117-26.EPS
WHITE
CYAN
1240 1000
BLACK/BLANK LEVEL
cycles 3.58MHz PAL-N 8LSB
BLUE
SYNC LEVEL
Figure Composite PAL-M Output (100% Saturation, 100% Amplitude Color Bars)
MAGENTA YELLOW GREEN BLACK
WHITE LEVEL
BLACK LEVEL BLANK LEVEL
0117-27.EPS
WHITE
CYAN
1205
3.58MHz COLOUR BURST CYCLES) 21.5
21.5
8LSB
BLUE
SYNC LEVEL
Inputs (Fast Blanking) input controls switching from YCRCB normal input data transcoded inputs. These inputs must locked HSYNC, ODDEVEN CKREF H6OSD signals. They latched rising edge CKREF clock signal. inputs allow color combinations that will address 6-bit CLUT. Each values will address 6-bit samples that will extended 8-bit samples with normal input samples. samples will filtered make sure that their bandwith similar YCRCB input samples. Mixing between data YCRCB normal input performed before filtering stages. H6OSD output clock signal dedicated output stage external generator. latter synchronized with HSYNC ODDEVEN FSYNC) signals (see Figures 32).
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STV0117
FUNCTIONAL DESCRIPTION (continued) Figure Data Insertion
H6OSD CKRi,
Vide KREF
H6OSD oftwa clock progra mming, H6OSD continuous clock. frame ynchroniza tion locke This inte clock. CKREF H6OSD CKRi, ible H6OSD TH6OSD -2TC KREF
Figure Synchronization Timing Master Mode Slave Mode ODDEVEN from YCRCB data)
HSYNC
Line (fields
Line position limits
TCKREF Max.
TCKREF Min.
Adjustment (synchro-delay registers)
FSYNC Line Interlaced HSYNC Output CKREF Field1 Field2 Line Non-interlaced
0117-30.EPS 0117-38.EPS
Figure Synchronization Timing Slave Mode (ODDEVEN HSYNC)
HSYNC Input FSYNC
CKREF 56TCKREF 56TCKREF
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0117-29.EPS
STV0117
FUNCTIONAL DESCRIPTION (continued) Hamming Decoding timing reference sequence present YCRCB input data, then Hamming decoded.Only signal extracted from used slave mode frame synchronization input signal. Hamming decoding words give information signal transmission; multiples errors detected flag inform microcontroller interestedin Hamming decoding results (see STATUS REGISTER). Digitized Video Input DVID 9-bit digital input from digitized analog video source directly routed CVBS input. DVID data latched rising edge CKREF clock signal. This access controlled hardware (EDVID Pin) programmation (see Figures 34). Figure Digitized Video Timing
CKREF
Pinning Compatibility with STV0116 STV0116 PAL/NTSC digital encoder device that additional converters encoded analog outputs. does support either closed captions encoding MACROVISION copy protection process. CCIR601 interlaced mode encoder. does offer possibility convert digitized video input into analog CVBS output, (like DVID STV0117). does support slave mode ODDEVEN HSYNC, HSYNC input) (see Figure 35). Waveforms STV0117 controlled internal 8-bit registers addressed write read mode. Write read operations detailed Figures
DVID[8:0]
CVBS
TCKREF Max.
CVBS num. (internal)
Figure Digitized Video Interface
IREF
cvbs internal DVID
CVBS
Downcvbs (I2C) reset RESET) CKREF
0117-32.EPS
dvidc EDVID
dvids (I2C)
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0117-31.EPS
EDVID (with hardware control enabled)
STV0117
FUNCTIONAL DESCRIPTION (continued) Figure Pinning Compatibility with STV0116
TESTSCAN NRESET H6OSD
VDDC
VSSP
ODD/EVEN YCRCB7 YCRCB6 YCRCB5 YCRCB4 YCRCB3 YCRCB2 YCRCB1 YCRCB0 TEST8
TESTAUTO IREF1 CVBS VDDA VSSA IREF2
STV0116
VDDP
TEST7
TEST6
TEST5
TEST4
TEST3
TEST2
TEST1 H6OSD
TESTSCAN
Modified Function that NRESET
VDDC
VSSP
TEST0
VSSC
ODD/EVEN VCS/HSYNC YCRCB7 YCRCB6 YCRCB5 YCRCB4 YCRCB3 YCRCB2 YCRCB1 YCRCB0 DVID0
TESTAUTO IREF CVBS VDDA VSSA CSI2C FSYNC EDVID
STV0117
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0117-33.EPS
CKREF
DVID1
DVID2
DVID3
DVID4
DVID5
DVID6
DVID7
DVID8
VSSC
VDDP
STV0117
FUNCTIONAL DESCRIPTION (continued) Figure STV0117/I2C Write Operation (CSI2C
Start Slave Address
STV0117
STV0117
STV0117
Address
Data Byte
STV0117
STV0117
STV0117 Stop
0117-34.AI 0117-35.EPS
Data Byte
Data Byte
Data Byte
Figure STV0117/I2C Read Operation (CSI2C
Start
STV0117
Slave Address
Address
STV0117
Stop
Start
Slave Address
STV0117
Data Byte
micro
Data Byte
micro
Stop
MACROVISION COPY PROTECTION PROCESS When enabled, chrominance, luminance composite video signals simultaneously modified according MACROVISION copy protection process applications, revision 6.0/6.1 dated September, 1995. control this process performed bus. more information please contact your nearest SGS-THOMSON Microelectronics sales office. programming document provided ONLY those customers SGS-THOMSON have executed license non-disclosure agreement with MACROVISION Corporation. Sample request sales orders require following procedure Sample Requests Procedure Non-licensed Customers Contact Sales Marketing, ACP-PPV MACROVISION Corporation Phone (408) 743-86-00 (408) 743-86-10 MACROVISIONwill send NDAto customer will initiate sampling process whereby customer receive MACROVISION capable from SGS-THOMSON Samples will then sent customer Sales Orders customer MACROVISION license customer provides SGS-THOMSON with written confirmation license. Marketing will retain written confirmation. Customer then purchase part. customer DOES HAVE MACROVISION license customer must obtain license waiver from MACROVISION. customer must provide SGS-THOMSON with written confirmation license waiver from MACROVISION. Marketing retains written confirmation. Customer purchases part. Neither parts norprogramming information will sent customer until above conditions met.
MACROVISION 6.0/6.1 copy protection process programming guide confidential document). Contact Video Marketing SGS-THOMSON Microelectronics Grenoble (France) (33) 76-58-56-10
Note customers need MACROVISION copy protection process, modified version STV0117 device available upon specific request.
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STV0117
ABSOLUTE MAXIMUM RATINGS
Symbol VDDx VOUT IREF IOUT Toper Tstg Ptot Supply Voltage Digital Input Voltage Digital Output Voltage Analog Input Reference Current Analog Output Current Operating Temperature Storage Temperature Total Power Dissipation Parameter Value -0.3, -0.3, -40, +150 1000 Unit
THERMAL DATA
th(j-a) Junction-Ambient Thermal Resistance with sample soldered Typ. °C/W
0117-03.TBL 0117-04.TBL
Symbol
Parameter
Value
Unit
ELECTRICAL CHARACTERISTICS (Tamb 25°C/70oC, VDDA VDDC VDDP unless otherwise specified)
Symbol SUPPLY VDDA VDDP VDDC IDDA Analog Positive Supply Voltage Digital Output Buffer Supply Voltage Digital Core Supply Voltage Analog Current Consumption Digital Current Consumption IREF 3.5mA, 300, 50pF, CKREF 30MHz, autotest mode, static input signals 4.75 4.75 4.75 5.25 5.25 5.25 Parameter Test Conditions Min. Typ. Max. Unit
DIGITAL INPUTS Input Voltage Input Voltage Input Leakage Current Input Capacitance level (any other pins) High level (any other pins) -0.3 VDD-0.5
OUTPUT Output Voltage Output Current level, During Acknowledge
DIGITAL OUTPUT Output Voltage Output Voltage High level (standard load) level (standard load)
CONVERTER IREF Reference Current Source Converters External Load Resistance Current Gain Integral Non-linearity Differential Non-linearity with IREF 2.9mA IREF 2.9mA, 300, Max. code IREF 2.9mA, IREF 2.9mA,
Gain Matching (YS, IREF 2.9mA,
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0117-02.TBL
STV0117
ELECTRICAL CHARACTERISTICS (Tamb 25°C/70oC, VDDA VDDC VDDP unless otherwise specified)
Symbol Parameter Test Conditions Min. Typ. Max. Unit DIGITAL INPUT (YCRCB[7:0], SCL, SDA, NRESET, ODDEVEN, HSYNC, DVID[8:0], EDVID, CFC) Input Data Set-up Time Input Data Hold Time CKREF rising edge, CKREF 30MHz CKREF rising edge, CKREF 30MHz
ACTIVE PERIOD NRESET tRSTL Input Time
DIGITAL INPUTS (other inputs static TESTSCAN, TESTAUTO, CSI2C) Input Data Set-up Time Input Data Hold Time CKREF rising edge, CKREF 30MHz CKREF rising edge, CKREF 30MHz
REFERENCE CLOCK CKREF tC_REF Clock Cycle Time CCIR601 application Square pixel/525lines Square pixel/625lines 37.04 40.75 33.90
tD_REF tR_REF tF_REF CLOCK tC_SCL tD_SCL tL_SCL DIGITAL OUTPUTS td_H6OSD td_FSYNC td_ODDEVEN td_VCS_HSYNC
Clock Duty Cycle Clock Rise Time Clock Fall Time
Clock Cycle Time Clock Duty Cycle Level Cycle
Rpull_up 4.7k Rpull_up 4.7k
Delay Time Delay Time Delay Time Delay Time
CKREF rising edge CKREF 30MHz, 50pF CKREF rising edge CKREF 30MHz, 50pF CKREF rising edge CKREF 30MHz, 50pF CKREF rising edge CKREF 30MHz, 50pF
0117-05.TBL
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STV0117
REGISTERS DESCRIPTION STV0117 controlled internal REGISTERS read written external microcontroller. Encoder addresses CSI2C then write 8-bit address hex) read 8-bit address hex) CSI2C then write 8-bit address hex) read 8-bit address hex) REGISTERS organized follows Standard selection, sync mode selection, sync polarity selection, master/slave mode Sync output selection, lines blanking, filter selection, sync enable free-run, color killer, PALNsetup, closed caption/extended data encoding mode Non-interlaced mode, autotest, burst control, square pixel mode, oscillator reset value selection, oscillator reset, phase reset cycle definition Color frequency control, DVID controls, luma delay adjustment Software reset, power-down mode DACs, H6OSD control Programmable delay time base with reference data Synchro delay time base with reference synchronization mode 9-10-11 Increment color subcarrier frequencies 12-13-14 Offset color subcarrier phase 15-.-22 clut inputs encoding 23-.-30 clut inputs encoding 31-.-38 clut inputs encoding 39-40 Closed caption characters/extended data field (odd) 41-42 Closed caption characters/extended data field (even) Closed caption/extended data line insertion select field (odd) Closed caption/extended data line insertion select field (even) 45-.-60 Reserved Chip part identification number Chip revision identification number Status Hamming decoding, frame synchro flag, closed caption data access, field counter, limit adjustment value Registers read control reserved modes
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STV0117
REGISTERS DESCRIPTION (continued)
Register
control configuration1 configuration2 configuration3 configuration4 delay_msb delay_lsb sync_delay_msb sync_delay_lsb increment increment increment phase phase phase palety palety palety palety palety palety palety palety paletcr paletcr paletcr paletcr paletcr paletcr paletcr paletcr paletcb paletcb paletcb paletcb paletcb paletcb paletcb paletcb char char char char line line reserved reserved chipID revID status test reserved
Access Address
std1 syncsel nintrl cfc1 softrst cr75 cr65 cr55 cr45 cr35 cr25 cr15 cr05 cb75 cb65 cb55 cb45 cb35 cb25 cb15 cb05 opc11 opc12 opc21 opc22 std0 blkli testauto cfc0 downcvbs cr74 cr64 cr54 cr44 cr34 cr24 cr14 cr04 cb74 cb64 cb54 cb44 cb34 cb24 cb14 cb04 c117 c127 c217 c227 sym2 filred bursten dvids downys cr73 cr63 cr53 cr43 cr33 cr23 cr13 cr03 cb73 cb63 cb53 cb43 cb33 cb23 cb13 cb03 c116 c126 c216 c226 sym1 syncok sqpix dvidc downc cr72 cr62 cr52 cr42 cr32 cr22 cr12 cr02 cb72 cb62 cb52 cb42 cb32 cb22 cb12 cb02 c115 c125 c215 c225 reserved atfr b2_free b1_free fldct2 fldct1 fldct0 sym0 coki selrst del3 enh6osd cr71 cr61 cr51 cr41 cr31 cr21 cr11 cr01 cb71 cb61 cb51 cb41 cb31 cb21 cb11 cb01 c114 c124 c214 c224 reserved sys1 PALNsetup rstosc del2 cr70 cr60 cr50 cr40 cr30 cr20 cr10 cr00 cb70 cb60 cb50 cb40 cb30 cb20 cb10 cb00 c113 c123 c213 c223 sys0 valrst1 del1 c112 c122 c212 c222
valrst0 del0 c111 c121 c211 c221
over_delay
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STV0117
REGISTERS DESCRIPTION (continued) Format WRITE MODE (all Registers except STATUS, chipID, revID) case CSI2C
Slave address Sub-address Data Data
Slave address Sub-address Data Data
Start condition 0100000 Write flag Acknowledge, generated slave (STV0117) when else Sub-address Register (content made byte) First data byte Continued data bytes address automaticaly incremented) Stop condition
READ MODE (STATUS, chipID revID Registers) case CSI2C
Slave address Sub-address
then
Slave address Data Data
Slave address Sub-address Data Data
Start condition 7-bit address STV0117 0100000 Write flag Acknowledge, generated slave (STV0117) when '0', else Read flag 8-bit register sub-address Data byte Register sent STV0117 Data byte Register (address automaticaly incremented) Acknowledge, generated microcontroller when Acknowledge else Stop condition (when last '1')
Remarks case CSI2C Writing Register Registers loaded sequentiallywith only start/stop condition followed sub-address first Register desired. Example loading configuration Registers start followed address hexa sub-address then bytes data stop. specified, registers loaded sequentially most cases. However, when this would involve performing soft reset writing into "softrst" register necessary stop after register start transfer sequence send next registers. Reading REGISTER Example reading Register (STATUS) start followed address hexa, then sub-address dec, stop. Then start, address hexa, '0', then data Register dec, stop condition.
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STV0117
REGISTERS MAPPING DESCRIPTION Default Mode when NRESET active (LOW level) Register Control (read/write)
std1 std0 sym2 sym1 sym0 sys1 sys0
std1 sym2 sym1 sym0 sys1 sys0
std0
Standard Selection (see Note BDGHI (Argentina Paraguay/Uruguay setup Register1) NTSC Synchronization Source Slave Mode Synchro source defined sym0, VCS/HSYNC output only Line-based synchronization, STV0117 locks HINPUT ODDEVEN inputs Must contains same value sym2
Frame Synchronization Input Source Slave Mode (see Note ODDEVEN synchro input, VCS/HSYNC output YCRCB[7:0] input (extraction from EAV) ODDEVEN VCS/HSYNC output signals Synchro polarity outputs VCS/HSYNC (when sym2 '0'), FSYNC Positive (leading edge rising edge) Negative (leading edge falling edge) Synchro polarity selection defines polarity ODDEVEN cases, HSYNC when HSYNC input (i.e. sym2 ODDEVEN falling edge flags start field (odd field) sym2 HSYNC falling edge line synchro input active edge ODDEVEN rising edge flags start field (odd field) sym2 HSYNC rising edge line synchro input active edge slave master (freerun forced) (see Note
Notes Standard hardware reset NTSC standard modification must followed software reset order select right parameters color subcarrier frequency. sym0 taken into account when sym2 '1', when master mode active (mod testauto '1'). Master mode forced when TESTAUTO HIGH when testauto REGISTER2 '1'.
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STV0117
REGISTERS MAPPING DESCRIPTION (continued) Default Mode when NRESET active (LOW level) Register Configuration (read/write)
syncsel blkli filred syncok coki PALNsetup
syncsel blkli
Signal Selection VCS/HSYNC Output Useful master mode, slave mode with sym2 Composite sync VCS/HSYNC Horizontal sync VCS/HSYNC HSYNC Blanking Lines Selection Active Video Lines Area (see Note Only following lines inside Vertical Interval blanked 525/60 system lines lines (half)-272 (SMPTE line number convention) 625/50 system lines (half)-5 lines 311-318 (CCIR line number convention) lines inside blanked 525/60 system lines 1-19 lines (half)-282 (SMPTE line number convention) 625/50 system lines 623(half)-22 lines 311-335 (CCIR line number convention) Chroma Pass Band Filter Select (see Note 1.3MHz (for PAL), NTSC 1.3MHz 0.5MHz 1.8MHz (extended bandwidth PAL, NTSC) Synchros availability case input synchronization loss with free-run active sym1 synchro output signals Output synchros available VCS/HSYNC, ODDEVEN, CVBS same behaviour free-run except that video output still blanked (luminance chrominance black level) Color Killer Color Color suppressed CVBS output signal (CVBS color still exists output
filred syncok
coki
PALNsetup Pedestal make difference between PAL-N when std[1:0] Blanking level black level identical lines. This only valid PAL-N (Argentina). Black level above blanking level un-blanked lines. This only valid PAL-N (Paraguay Uruguay). PAL-N (Paraguay Uruguay), black level above blanking level lines 23-310 336-623 only (CCIR line number convention). cases, gain factor fixed obtain chrominance required levels. other standards, this ignored setup automatically performed PAL-M NTSC-M Closed caption/extended data encoding mode Closed caption/extended data encoding disabled Closed caption/extended data encoding enabled field (odd) Closed caption/extended data encoding enabled field (even) Closed caption/extended data encoding enabled both fields
Notes blkli must when closed captions encoded 525/60 system before line (SMPTE) before line (SMPTE) 625/50 system before line (CCIR) before line (CCIR) (reduced blanking allows preservation analogue Wide Screen Signalling (line 23), Video Programing Service (line 16), etc) Three filters encoding with CKREF 27MHz (Chroma becomes 1.7MHz/1.2MHz, 0.45MHz with sin(x)/x DAC). When synchro lost (frame synchro flag (=atfr bit) low), filred forced '0'.
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STV0117
REGISTERS MAPPING DESCRIPTION (continued) Default Mode when NRESET active (LOW level) Register Configuration (read/write)
nintrl testauto bursten sqpix selrst rstosc valrst1 valrst0
nintrl testauto bursten sqpix selrst rstosc valrst1 valrst0
Non-interlaced Mode Select (see Note Interlaced mode (625/50 525/60 system) Non-interlaced mode Color Pattern Software Control Color pattern hardware testauto (Pin low. Color pattern enabled (100% luma, chroma), whatever value TESTAUTO. Chrominance Burst Control Burst turned OFF, chrominance output affected this Burst enabled Square Pixel Mode Select (see Note CCIR pixel rate (13.5MHz) (pixel with aspect ratio) Square pixel rate (pixel with aspect ratio pixel clock frequency defined according NTSC) Selects Reset Values Direct Digital Frequency Synthesizer (see Note Hardware reset values phase increment subcarrier oscillator loaded reset values selected (see contents Registers Software Phase Reset DDFS (Direct Digital Frequency Synthesizer) (see Note Transition generates pulse reset oscillator phase (only) Selects Phase Reset Cycle DDFS (see Note reset phase oscillator Reset oscillator with phase_value every fields Reset oscillator with phase_value every fields Reset oscillator with phase_value every fields
Notes non-interlaced mode, 624/2 line mode 524/2 line mode with waveforms same first field CCIR SMPTE. nintrl update synchronized beginning next frame. circuit non-interlaced mode conjunction with 625-line standards, circuit should first initialised interlaced mode, then switched non-interlaced mode. sqpix update synchronized beginning next frame. rstosc automatically disabled (rstosc forced '0') after generation phase reset pulse; rstosc active during CKREF period. Phase_value DEFAULT phase that loaded REGISTERS 12,13 square pixel format, possible modify loading D.D.F.S. increment used color subcarrier frequency generator.
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STV0117
REGISTERS MAPPING DESCRIPTION (continued) Default Mode when NRESET active (LOW level) Register Configuration (read/write)
cfc1 cfc0 dvids dvidc del3 del2 del1 del0
cfc1 dvids dvidc
cfc0
Color Frequency Control Line Disable (update done loading Registers Update increment DDFS just after serial loading Update increment DDFS next active edge HSYNC Update increment DDFS just before next color burst Digitized Video Data Control Select Software control (see dvidc) Hardware control (Pin EDVID, same role dvidc) Digitized Video Data Multiplexer controlled software dvidc taken into account when dvids DVID[8:0] ignored DVID[8:0] selected Delay Luma Path with Reference Chroma Path
del(3:0)
pixel clock period delay luma pixel clock period delay luma pixel clock period delay luma pixel clock period delay luma pixel clock period delay luma pixel clock period delay luma pixel clock period delay luma pixel clock period delay luma pixel clock period delay luma pixel clock period delay luma
others
CCIR601 mode, pixel clock period 1/13.5MHz (74.04ns) square pixel lines mode, pixel clock period 1/12.27MHz (81.5ns) square pixel lines mode, pixel clock period 1/14.75MHz (67.8ns)
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STV0117
REGISTERS MAPPING DESCRIPTION (continued) Default Mode when NRESET active (LOW level) Register Configuration (read/write)
softrst downcvbs downys downc enh6osd
softrst
Software Reset reset Software reset
downcvbs Down Mode 9-bit CVBS CVBS normal operation CVBS input forced 000000000 reduce consumption have lowest analog output downys downc enh6osd Down Mode 9-bit normal operation input forced 000000000 reduce consumption have lowest analog output Down Mode 9-bit normal operation input forced 000000000 reduce consumption have lowest analog output H6OSD Output Enable Control H6OSD generated (H6OSD '0') H6OSD generated (phase defined reset operation) clock period equal CKREF/4 clock period
Note softrst automatically reset stop condition, software reset active during CKREF periods when softrst activated, device reset with hardware reset except first five REGISTERS (control configurations).
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STV0117
REGISTERS MAPPING DESCRIPTION (continued) Default Mode when NRESET active (LOW level) Register Delay_msb (read/write) Register Delay_lsb (read/write)
Register Register
Note When adjustment needed (DEFAULT values application), these delay Registers loaded anytime (remember however that software reset forces default values).
MASTER mode (mod autotest modes) (see Figure Position ODDEVEN output signal adjusted with reference analog horizontal sync according complement value loaded these Registers value must within range [-1536,+1536]. case, value taken into account maximum allowed depending sign. ODDEVEN transition occurs sample number (max line length delay(11:0) modulo [max line length]. Thus, changing "delay", possible shift location ODDEVEN with reference analogue video outputs equivalently, YCRCB input data samples). d[11:0] complement value d[11] when ODDEVEN lags with reference main sample counter (=d[10:0]) samples. ODDEVEN closer analog horizontal sync output signal. d[11] when ODDEVEN leads with reference main sample counter (=not d[10:0] samples. ODDEVEN further away from analog horizontal sync output signal. Default value d[11:4] hexa, d[3:0], xxxx hexa, that ODDEVEN signal toggles when main sample 11-bit-counter value hexa. SLAVE mode (mod sym2 (VCS/HSYNC input) Main sample counter loaded with value d[10:0] when either ODDEVEN input signal), signal (extracted from YCRCB[7:0] input) changes with programmed transition frame beginning. Main sample counter loaded with value:(max line length delay(11:0)) modulo [max line length], CKREF clock periods after frame synchro input ODDEVEN). Thus position analog synchronization output signal adjusted with reference YCRCB[7:0] input data. Position ODDEVEN output signal, only when slave from YCRCB) also defined with d[11:0] master mode (see Figure 14). d[11:0] complement value d[11] when '0', analog synchronization output signal leads with reference YCRCB[7:0] input data d[10:0]) samples. d[11] when '1', analog synchronization output signal lags with reference YCRCB[7:0] input data d[10:0] samples. Hardware Reset Values when sym0 (synchro ODDEVEN), DEFAULT value delay REGISTERS 0000h when sym0 (synchro from YCRCB[7:0]), DEFAULT value delay REGISTERS 525/60 systems :FE60 hexa (1st byte:254 byte:96) 625/50 systems :FEE0 hexa (1st byte:254 byte:224) With these DEFAULT values, ODDEVEN output signal image timing reference frame transmitted YCRCB[7:0] input data (EAV decoding))
sym2 (VCS/HSYNC HSYNC synchro input with ODDEVEN) allowed values delay REGISTERS within range [-44.-1,0,.+43]. case, value taken into account maximum allowed depending sign.
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STV0117
REGISTERS MAPPING DESCRIPTION (continued) Default Mode when NRESET active (LOW level) Register Synchro_delay_msb (read/write) Register Synchro_delay_lsb (read/write)
Register Register
sym2 (VCS/HSYNC synchro output) synchro_delay register used adjust position VCS/HSYNC FSYNC output signals with reference analog video outputs. VCS/HSYNC FSYNC decoded from fixed reference value auxillary sample counter. possible change relation between this auxillary counter main sample counter, thus causing VCS/HSYNC FSYNC locations shifted. synchro_delay register codes shift required terms clock periods with reference default position. Figures illustrate this default position. d[11:0] d[11] d[11] complement value that codes desired shift, when '0', VCS/HSYNC FSYNC output signals lead with reference default location d[10:0]) samples. when '1', VCS/HSYNC FSYNC output signals with reference default location d[10:0] samples.
sym2 (VCS/HSYNC HSYNC synchro input) synchro_delay register effect. that particular case, FSYNC output synchronous with analog synchronization present output analog video signals CVBS). default value synchro delay register 0000 hex, they should FCE0 direct compatibility with SGS-THOMSON MPEG application. Caution changing synchro delay from default value (0000 hex) value must done whilst chip master mode sync.
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STV0117
REGISTERS MAPPING DESCRIPTION (continued) Default Mode when NRESET active (LOW level) Registers 9-10-11 Increment Direct Digital Frequency Synthesizer (read/write)
Register Register Register
22-bit increment sinus address
6.44Hz CCIR 7.03Hz square pixel-625 5.85Hz square pixel-525
Hardware reset values with reference standard selected these values those selected when selrst equals '0', that case, content Registers 9-10-11 taken into account). Moreover, Registers 9-10-11 never reset must explicitly written into contain sensible information. Rectangular Pixel Mode d(21:0) d(21:0) d(21:0) d(21:0) 087C1F 0A8263 087DA5 0879BC hexa, 556063 hexa, 688739 hexa, 556453 hexa, 555452 NTSC BGHIN Synthesized Subcarrier Frequency 3.5795452MHz 4.43361875MHz 3.5820558MHz 3.57561149MHz Synthesized Subcarrier Frequency 3.579545MHz 4.43361875MHz 3.582056MHz 3.575610MHz Ref. Clock 27MHz 27MHz 27MHz 27MHz Ref. Clock 24.5454MHz 29.50MHz 29.50MHz 24.5454MHz
Square Pixel Mode d(22:0) d(22:0) d(22:0) d(22:0) 095555 099E63 07C570 0952B5 hexa, 611669 hexa, 630371 hexa, 509296 hexa, 610997 NTSC BGHIN
These hard-wired values being user register, they cannot read from STV0117.
Note value loaded these registers taken into account after software reset with selrst equals (see register selrst) (refer Figure 12).
Registers 12-13-14 Static Phase Offset Direct Digital Frequency Synthesizer (read/write)
Register Register Register
Hardware reset values with reference standard selected these values those selected when selrst equals '0', that case, content Registers 12-13-14 taken into account). Moreover, Registers 12-13-14 never reset must explicitly written into contain sensible information. Hard-wired values being register they cannot read from STV0117. hard-wired values phase offset following Rectangular Pixel Format o(21:0) 1E2DE8 hexa NTSC o(21:0) 000F40 hexa BGHIN, Square Pixel Format o(21:0) 000000 hexa standards recommended values 05BFA0 BGI-N-MPAL 17F4FF M-NTSC.
Note value loaded these registers taken into account after oscillator reset (bit rstosc Register with selrst equals (see Register selrst).
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STV0117
REGISTERS MAPPING DESCRIPTION (continued) Default Mode when NRESET active (LOW level) Registers 15-16-17-18-19-20-21-22 Palety (read/write)
Register Register Register Register Register Register Register Register
6-bit words component DEFAULT value Register15 Register16 Register17 Register18 Register19 Register20 Register21 Register22 Y(hexa) Y(dec) y7x=EC y6x=A0 y5x=50 y4x=40 y3x=84 y2x=74 y1x=24 y0x=10 Color (100% white black) white yellow magenta cyan green blue black (OSD index inputs)
DEFAULT color pattern display from left right white, yellow, cyan, green, magenta, red, blue, black Registers 23-24-25-26-27-28-29-30 Paletcr (read/write)
Register Register Register Register Register Register Register Register cr75 cr65 cr55 cr45 cr35 cr25 cr15 cr05 cr74 cr64 cr54 cr44 cr34 cr24 cr14 cr04 cr73 cr63 cr53 cr43 cr33 cr23 cr13 cr03 cr72 cr62 cr52 cr42 cr32 cr22 cr12 cr02 cr71 cr61 cr51 cr41 cr31 cr21 cr11 cr01 cr70 cr60 cr50 cr40 cr30 cr20 cr10 cr00
6-bit words component DEFAULT value Register23 Register24 Register25 Register26 Register27 Register28 Register29 Register30 CR(hexa) cr7x=80 cr6x=8C cr5x=C4 cr4x=D4 cr3x=2C cr2x=38 cr1x=70 cr0x=80 CR(dec) Color (75% white yellow magenta cyan green blue black (OSD index inputs)
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STV0117
REGISTERS MAPPING DESCRIPTION (continued) Default Mode when NRESET active (LOW level) Registers 31-32-33-34-35-36-37-38 Paletcb (read/write)
Register Register Register Register Register Register Register Register cb75 cb65 cb55 cb45 cb35 cb25 cb15 cb05 cb74 cb64 cb54 cb44 cb34 cb24 cb14 cb04 cb73 cb63 cb53 cb43 cb33 cb23 cb13 cb03 cb72 cb62 cb52 cb42 cb32 cb22 cb12 cb02 cb71 cb61 cb51 cb41 cb31 cb21 cb11 cb01 cb70 cb60 cb50 cb40 cb30 cb20 cb10 cb00
6-bit words component DEFAULT value Register31 Register32 Register33 Register34 Register35 Register36 Register37 Register38 CB(hexa) CB(dec) cb7x=80 cb6x=2C cb5x=B8 cb4x=64 cb3x=9C cb2x=48 cb1x=D4 cb0x=80 Color (75% white yellow magenta cyan green blue black (OSD index inputs)
Registers 39-40 cccf1 (read/write) closed caption characters/extended data field (see Note) First byte encode
Register opc11 c117 c116 c115 c114 c113 c112 c111
opc11 odd-parity US-ASCII 7-bit character c11(7:1) Second byte encode
Register opc12 c127 c126 c125 c124 c123 c122 c121
opc12 odd-parity US-ASCII 7-bit character c12(7:1) Default value none, closed captions enabling without loading these registers will issue character NULL. Registers 39-40 never reset.
Note There rotation when reading values stored these registers. register contains following bits b8.b7.b6.b5.b4.b3.b2.b1, value read will b1.b8.b7.b6.b5.b4.b3.b2.
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STV0117
REGISTERS MAPPING DESCRIPTION (continued) Default Mode when NRESET active (LOW level) Registers 41-42 cccf2 (read/write) closed caption characters/extended data field (see Note) First byte encode
Register opc21 c217 c216 c215 c214 c213 c212 c211
opc21 odd-parity US-ASCII 7-bit character c21(7:1) Second byte encode
Register opc22 c227 c226 c225 c224 c223 c222 c221
opc22 odd-parity US-ASCII 7-bit character c22(7:1) Default value none, closed captions enabling without loading these registers will issue character NULL. Registers 41-42 never reset.
Note There rotation when reading values stored these registers. register contains following bits b8.b7.b6.b5.b4.b3.b2.b1, value read will b1.b8.b7.b6.b5.b4.b3.b2.
Register cclif1 (read/write) closed caption/extended data line insertion field field1 line number where closed caption/extended data encoded programmable through following Register
525/60 system (525-SMPTE line number convention). Only lines through should used closed caption extendeddata services (line through contain vertical sync pulses with equalizing pulses). l1(4:0) 00000 line selected closed caption encoding l1(4:0) 000xx these codes l1(4:0) 00100 line (SMPTE) selected encoding l1(4:0) 10000 line (SMPTE) selected encoding l1(4:0) others from line upto (SMPTE) 625/50 system (625-CCIR line number convention). Only lines through should used closed caption extended data services. l1(4:0) 00000 line selected closed caption encoding l1(4:0) 00001 line (CCIR) selected encoding l1(4:0) 10001 line (CCIR) selected encoding l1(4:0) others from line upto (CCIR) DEFAULT value 01111 line (525/60, 525-SMPTE line number convention) line (625/50, 625-CCIR line number convention)
Note also Note concerning "blkli" configuration register
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STV0117
REGISTERS MAPPING DESCRIPTION (continued) Default Mode when NRESET active (LOW level) Register cclif2 (read/write) closed caption/extended data line insertion field field2 line number where closed caption/extended data encoded programmable through following Register
525/60 system (525-SMPTE line number convention). Only lines through should used closed caption extendeddata services (preceding lines contain vertical sync pulses with equalizing pulses), although possible program over wider range. l2(4:0) 00000 line selected closed caption encoding l2(4:0) 000xx these codes l2(4:0) 00100 line (SMPTE) selected encoding l2(4:0) 01111 line (SMPTE) selected encoding l2(4:0) others from line upto (SMPTE) 625/50 system (625-CCIR line number convention). Only lines through should used closed caption extendeddata services (preceding lines contain vertical sync pulses with equalizing pulses), although possible program over wider range. l2(4:0) 00000 line selected closed caption encoding l2(4:0) 00001 line (CCIR) selected encoding l2(4:0) 00010 line (CCIR) selected encoding l2(4:0) 10010 line (CCIR) selected encoding l2(4:0) others from line upto (CCIR) DEFAULT value 01111 line (525/60, 525-SMPTE line number convention) line (625/50, 625-CCIR line number convention)
Note also Note concerning "blkli" configuration register
Registers Reserved Registers Register chipID (read only) chip part identification number
Register revID (read only) chip revision identification number
used manufacturer indicate revision level silicon (the revID register version contains 0000 0001).
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STV0117
REGISTERS MAPPING DESCRIPTION (continued) Default Mode when NRESET active (LOW level) Register Status (read only)
atfr buf2_free buf1_free fieldct2 fieldct1 fieldct0 over_delay
atfr buf2_free
Hamming Decoding odd/even Signal from YCRCB (see Note) multiple errors error Frame Synchronization Flag encoder synchronized slave mode encoder synchronized Closed Caption Field2-Registers Access Condition. Closed caption data buffered before being output relevant line buf2_free reset buffer temporarily unavailable. microcontroller guarantee that Registers (cccf2) never written more than once between frame reference signals, then buf2_free will always true (set). Otherwise, closed caption field2 register access might temporarily forbidden resetting buf2_free until next field2 closed caption line occurs. Note that this false (reset) when pairs data bytes awaiting encoded, back immediately after these pairs been encoded that time, encoding last pair bytes still pending) Reset value (access authorized) Closed Caption Field1-Registers Access Condition. Same signification buf2_free closed caption field1. Reset value (free access) Digital Field Identification Number indicates field indicates field fieldct[0] odd/even information ('0' field, even field) Limit Registers Adjustment Value overflow with loaded value Registers value loaded Registers outside allowed limits, forced maximum authorized
buf1_free fieldct[2:0] over_delay
Note Signal quality detector issued from Hamming decoding EAV, from YCRCB.
Registers 64-65-66-67 Reserved Registers Register Test (read/write)
Default value hex. registers accessed read mode writing this register. other values reserved should used.
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STV0117
TYPICAL APPLICATION DIAGRAM
4.7k VDDC 100nF 10µF NRESET VDDP 4.7k VDDP H6OSD INTERFACE
GENERATOR ptio
ODDEVEN HSYNC
ODD/EVEN Y/CR/CB7 Y/CR/CB6 Y/CR/CB5 Y/CR/CB4 Y/CR/CB3 Y/CR/CB2 Y/CR/CB1 Y/CR/CB0
INTERFACE
Vide Output
IREF LUMINANCE PROCES SING TRIDAC
1.2k (from n-lock) EDVID
Vide Output Vide Output
CVBS
CVBS
100nF
DVID
(MASTER)
CHROMINANCE PROCES SING
DVID1 DVID2
YNCHRONISM PROCES SING DVID5 DVID6 DVID7 DVID8
MPEG DECODER
DVID0
HSYNC ODDEVEN
10µF
CCIR INTERFACE
TV0117
VDDA
VDDA
DVID3
DVID4
VDDA VDDC VDDP
VSSA (0V) (0V) VSSP VSSC
CKREF
VSSC
VDDP 100nF
Video Filter
Note When unused, DVID (8:0), EDVID, inputs must tied ground (VSSP) input must tied VDDp.
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0117-36.EPS
STV0117
PACKAGE MECHANICAL DATA PINS PLASTIC CHIP CARRIER
Dimensions
Min. 17.4 16.51 3.65 2.59 14.99
Millimeters Typ.
Max. 17.65 16.65 4.57 2.74
Min. 0.685 0.650 0.144 0.165 0.102 0.590
Inches Typ.
Max. 0.695 0.656 0.146 0.180 0.108 0.630
0.68 1.27 12.7 0.46 0.71 0.101 1.16 1.14
0.027 0.050 0.500 0.018 0.028 0.046 0.045
PLCC44.TBL
0.004
Information furnished believed accurate reliable. However, SGS-THOMSON Microelectronics assumes responsibility consequences such information infringement patents other rights third parties which result from use. licence granted implication otherwise under patent patent rights SGS-THOMSON Microelectronics. Specifications mentioned this publication subject change without noti This publication supersedes replaces information previously supplied. SGS-THOMSON Microelectronics products authorized critical components life support devices systems without express written approval SGS-THOMSON Microelectronics. 1996 SGS-THOMSON Microelectronics Rights Reserved Purchase Components SGS-THOMSON Microelectronics, conveys license under Philips Patent. Rights these components system, granted provided that system conforms Standard Specifications defined Philips. SGS-THOMSON Microelectronics GROUP COMPANIES Australia Brazil Canada China France Germany Hong Kong Italy Japan Korea Malaysia Malta Morocco Netherlands Singapore Spain Sweden Switzerland Taiwan Thailand United Kingdom U.S.A.
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PMPLCC44.EPS

PAL/NTSC DIGITAL ENCODER NTSC-M, PAL-M, PAL-B, PAL-N EASILY PROGR

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