H8S/2138F-ZTATHD64F2138, HD64F2138V HD64F2138A, HD64F2138AV H8S/2134F-
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H8S/2138 Series H8S/2134 Series H8S/2138 H8S/2137 H8S/2134 H8S/2133 H8S/2132 H8S/2130 HD6432138SW, HD6432138S HD6432137SW, HD6432137S HD6432134S HD6432133S HD6432132 HD6432130
H8S/2138F-ZTATHD64F2138, HD64F2138V HD64F2138A, HD64F2138AV H8S/2134F-ZTATHD64F2134, HD64F2134V HD64F2134A, HD64F2134AV H8S/2132F-ZTATHD64F2132R, HD64F2132RV
ADE-602-144B Rev. 4/5/01 Hitachi, Ltd.
Hardware Manual
Cautions
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Preface
H8S/2138 Series H8S/2134 Series comprise high-performance microcomputers with 32-bit H8S/2000 core, on-chip supporting functions required system configuration. H8S/2000 execute basic instructions state, provided with sixteen internal 16-bit general registers with 32-bit configuration, concise optimized instruction set. handle 16-Mbyte linear address space (architecturally Gbytes). Programs based high-level language also efficiently. Single-power-supply flash memory (F-ZTATTM*) mask versions available, providing quick flexible response conditions from ramp-up through full-scale volume production, even applications with frequently changing specifications. On-chip peripheral functions include 16-bit free-running timer (FRT), 8-bit timer (TMR), watchdog timer (WDT), timers (PWM PWMX), serial communication interface (SCI, IrDA), host interface (HIF), converter (DAC), converter (ADC), ports. interface (IIC) also incorporated option. on-chip data transfer controller (DTC) also provided, enabling high-speed data transfer without intervention. H8S/2138 Series above on-chip supporting functions, also provided with module option. H8S/2134 Series comprises reduced-function versions, with fewer channels, PWM, HIF, IIC, modules. H8S/2138 H8S/2134 Series enables compact, high-performance systems implemented easily. comprehensive PC-related interface functions matrix keyscan functions ideal applications such notebook keyboard control intelligent battery power supply control, while various timer functions their interconnectability (timer connection), plus interlinked operation interface data transfer controller (DTC), particular, make these devices ideal monitors. addition, combination F-ZTATTM* reduced-function versions ideal applications such system units which on-chip program memory essential meet performance requirements, product start-up times short, program modifications necessary after end-product assembly. This manual describes hardware H8S/2138 Series H8S/2134 Series. Refer H8S/2600 Series H8S/2000 Series Programming Manual detailed description instruction set. Note: F-ZTAT(Flexible-ZTAT) trademark Hitachi, Ltd.
On-Chip Supporting Modules
Series Product names controller (BSC) Data transfer controller (DTC) 8-bit timer (PWM) 14-bit timer (PWMX) 16-bit free-running timer (FRT) 8-bit timer (TMR) Timer connection Watchdog timer (WDT) Serial communication interface (SCI) interface (IIC) Host interface (HIF) converter converter
H8S/2138 Series H8S/2138, 2137 Available bits) Available Available (option) (analog input)
H8S/2134 Series H8S/2134, 2133, 2132, 2130 Available bits) (analog input)
(expansion inputs) (expansion inputs)
Main Revisions Additions this Edition
Main Revisions Additions this Edition
Page pages this manual Overview Item Revision (See Manual Details) Amendments introduction mask versions (HD64F2138A, HD64F2134A) Table Overview Product lineup amended Internal Block Diagram Figure Internal Block Diagram H8S/2138 Series VCC2 (VCL) amended Figure Internal Block Diagram H8S/2134 Series VCC2 (VCL) amended 1.3.1 Arrangement Figure Arrangement H8S/2138 Series (FP-80A, TFP-80C: View) No.8: VCC2 (VCL) amended Figure Arrangement H8S/2134 Series (FP-80A, TFP-80C: View) VCC2 (VCL) amended 1.3.2 Functions Each Table H8S/2138 Series Functions Each Operating Mode operating Mode VCC2 (VCL) amended Table H8S/2134 Series Functions Each operating Mode VCC2 (VCL) amended 1.3.3 Functions Table Functions Power supply: added Serial communication interface (SCI0, SCI1, SCI2): Serial clock description amended ports: Port Port description amended Note amended pages section 3.2.2 System Control Register (SYSCR) Notes instruction added Notes STM/LDM instruction added description amended Note added
3.2.3 Control Register Note added (BCR)
Page
Item 3.2.4 Serial Timer Control Register (STCR) Memory Each Operating Mode
Revision (See Manual Details) description amended Description added access reserved area .when these regions accessed. Figure H8S/2138 F-ZTAT A-mask Version Memory Each Operating Mode added
4.1.1 Exception Handling Types Priority Interrupts
Table Exception Types Priority Trace description amended Description amended Interrupts other than address break
Notes Stack 5.1.1 Features
Figure Operation when Value amended Priorities settable with description amended interrupts except address break
5.1.2 Block Diagram
Figure Block Diagram Interrupt Controller Internal interrupt requests amended
5.1.4 Register Configuration 5.2.2 Interrupt Control Registers (ICRA ICRC) 5.2.5 status register 5.2.6 Keyboard Matrix Interrupt Mask Register (KMIMR) 5.3.1 External Interrupts
Table Interrupt Controller Registers Note amended Description amended Interrupts other than address break Note added Description amended Bits Note amended IRQ7 IRQ0 Interrupts: description added When IRQ6 assigned IRQ6 interrupt input pin, then KMIMR6
5.5.1 Interrupt Control Modes Interrupt Operation
Description amended address break interrupts Table Interrupts Selected Each Interrupt Control Mode Address break interrupts added
5.5.3 Interrupt Control Mode
Address break Interrupts description added
Page
Item 6.2.2 Wait State Control Register (WSCR) 6.3.2 Advanced Mode 6.3.4 Select Signal
Revision (See Manual Details) description amended Description amended addition H8S/2138F-ZTAT mask version. Table Signal Output Range Note added Figure Example Wait State Insertion Timing timing amended Table Timer Module Registers Note added Table 10.2 Register Configuration Note amended
6.4.5 Wait Control 9.1.4 Register Configuration 10.1.4 Register Configuration
11.3.5 Timing Input Figure 11.11 Setting Input Capture Flag (ICFA/B/C/D) Capture Flag (ICF) Setting ICRA/B/C/D timing amended 11.6 Usage Note Figure 11.21 Contention between OCRAR/OCRAF Write Compare-Match (When Automatic Addition Function Used) added
12.2.6. Serial/Timer Control description amended Register (STCR) 12.3.6 Input Capture Operation 13.3.1 Decoding (PDC Signal Generation) Added Figure 13.2 Timing Chart Decoding amended
14.2.2 Timer Control/Status Note added Register (TCSR) 15.1.1 Features 16.2.1 Data Register (ICDR) 16.2.5 Control Register (ICCR) Capability transmit receive clock output description added TDRE: description amended description amended description amended 16.2.6 Status Register (ICSR)
description amended
16.3.1 Data Format Figure 16.4 Formatless added 16.3.2 Master Transmit Operation Completely amended
Page 475,
Item 16.3.3 Master Receive Operation 16.3.10 Sample Flowchart
Revision (See Manual Details) Completely amended Figure 16.14 Flowchart Master Transmit Mode (Example) Figure 16.15 Flowchart Master Receive Mode (Example) completely amended
16.3.11 Initialization Internal State
Description amended Executed accordance with setting bits CLR3 CLR0 DDCSWR register clearing Notes Start Condition Issuance Retransmission Notes Interface Stop Condition Instruction Issuance
16.4 Usage Notes
added 19.2.3 Control Register Bits description amended (ADCR) 20.3.2 Single-Chip Mode Description amended (Modes (EXPE=0)) Undefined values always read from these bits, writing invalid. Description added introduction H8S/2138 H8S/2134 A-mask version (Mask version, H8S/2138F-ZTAT, H8S/2134F-ZTAT, H8S/2132F-ZTAT) (H8S/2138F-ZTAT A-mask version H8S/2134F-ZTAT A-mask version) 21.4.3 Flash Memory Operating Modes Figure 21.3 Flash Memory Mode Transitions name amended between user mode user program mode
21.5.4 Serial/Timer Control description amended Register (STCR) 21.6.1 Boot Mode Figure 21.10 Areas Boot Mode added
21.10.1 Programmer Mode Notes added Setting 21.11 Flash Memory Programming Erasing Precautions Description amended
Page
Item 21.12 Note Switching from F-ZTAT Version Version 23.9. Clock Selection Circuit 24.1.1 Register Configuration 24.5.1 Module Stop Mode Electrical Characteristics
Revision (See Manual Details) Added
Added Added Table 24.3 Power-Down State Registers Note added MSTP2 bit: Description amended Note amended Completely amended Notes instruction added
pages Appendix 846,
Register Selection Conditions
H8S/2134 Series H'FF83 SYSCR2 amended H8S/2138 Series H8S/2134 Series H'FF94, H'FF95 H'FF98 H'FF9D amended Registers amended H'FEEB: H'FF86, H'FF87 MSTPCRH/L H'FF88, H'FFD8 ICCR1/0 H'FFC4: SYSCR H'FFC6:
962,
Functions
Port Block Diagrams Figure C.2, C.3, Port Block Diagram amended Port Block Diagram Figure Port Block Diagram amended Port Block Diagrams Figure C.6, C.7, C.8, C.9, C.10, C.11, C.12 Port Block Diagram amended Port Block Diagrams Figure C.13, C.14, C.15 Port Block Diagram amended Port Block Diagrams Figure C.23, C.24, C.25, C.26, C.27, C.28 Port Block Diagram amended Port Block Diagrams Figure C.29, C.30, C.31, C.33 Port Block Diagram amended Product Code Lineup Amendments introduction A-mask versions (HD64F2138A, HD64F2134A)
Contents
Section
Overview Overview. Internal Block Diagram Arrangement Functions. 1.3.1 Arrangement. 1.3.2 Functions Each Operating Mode. 1.3.3 Functions Overview. 2.1.1 Features. 2.1.2 Differences between H8S/2600 H8S/2000 CPU. 2.1.3 Differences from H8/300 CPU. 2.1.4 Differences from H8/300H Operating Modes. Address Space. Register Configuration. 2.4.1 Overview. 2.4.2 General Registers. 2.4.3 Control Registers 2.4.4 Initial Register Values Data Formats. 2.5.1 General Register Data Formats. 2.5.2 Memory Data Formats. Instruction 2.6.1 Overview. 2.6.2 Instructions Addressing Modes 2.6.3 Table Instructions Classified Function. 2.6.4 Basic Instruction Formats. 2.6.5 Notes Bit-Manipulation Instructions. Addressing Modes Effective Address Calculation 2.7.1 Addressing Mode. 2.7.2 Effective Address Calculation Processing States 2.8.1 Overview. 2.8.2 Reset State 2.8.3 Exception-Handling State. 2.8.4 Program Execution State 2.8.5 Bus-Released State
Section
2.8.6 Power-Down State Basic Timing. 2.9.1 Overview. 2.9.2 On-Chip Memory (ROM, RAM) 2.9.3 On-Chip Supporting Module Access Timing. 2.9.4 External Address Space Access Timing. 2.10 Usage Note. 2.10.1 Instruction 2.10.2 STM/LDM Instruction.
Section
Operating Modes. Overview. 3.1.1 Operating Mode Selection 3.1.2 Register Configuration Register Descriptions. 3.2.1 Mode Control Register (MDCR) 3.2.2 System Control Register (SYSCR). 3.2.3 Control Register (BCR). 3.2.4 Serial Timer Control Register (STCR). Operating Mode Descriptions 3.3.1 Mode 3.3.2 Mode 3.3.3 Mode Functions Each Operating Mode. Memory Each Operating Mode. Exception Handling Overview. 4.1.1 Exception Handling Types Priority 4.1.2 Exception Handling Operation 4.1.3 Exception Sources Vector Table Reset. 4.2.1 Overview. 4.2.2 Reset Sequence. 4.2.3 Interrupts after Reset. Interrupts Trap Instruction Stack Status after Exception Handling Notes Stack.
Section
Section
Interrupt Controller. Overview. 5.1.1 Features.
5.1.2 Block Diagram. 5.1.3 Configuration 5.1.4 Register Configuration Register Descriptions. 5.2.1 System Control Register (SYSCR). 5.2.2 Interrupt Control Registers (ICRA ICRC). 5.2.3 Enable Register (IER). 5.2.4 Sense Control Registers (ISCRH, ISCRL). 5.2.5 Status Register (ISR) 5.2.6 Keyboard Matrix Interrupt Mask Register (KMIMR). 5.2.7 Address Break Control Register (ABRKCR). 5.2.8 Break Address Registers (BARA, BARB, BARC). Interrupt Sources. 5.3.1 External Interrupts 5.3.2 Internal Interrupts 5.3.3 Interrupt Exception Vector Table. Address Breaks 5.4.1 Features. 5.4.2 Block Diagram. 5.4.3 Operation 5.4.4 Usage Notes Interrupt Operation. 5.5.1 Interrupt Control Modes Interrupt Operation 5.5.2 Interrupt Control Mode 5.5.3 Interrupt Control Mode 5.5.4 Interrupt Exception Handling Sequence. 5.5.5 Interrupt Response Times. Usage Notes 5.6.1 Contention between Interrupt Generation Disabling. 5.6.2 Instructions that Disable Interrupts. 5.6.3 Interrupts during Execution EEPMOV Instruction Activation Interrupt 5.7.1 Overview. 5.7.2 Block Diagram. 5.7.3 Operation
Section
Controller Overview. 6.1.1 Features. 6.1.2 Block Diagram. 6.1.3 Configuration 6.1.4 Register Configuration Register Descriptions.
6.2.1 Control Register (BCR). 6.2.2 Wait State Control Register (WSCR). Overview Control. 6.3.1 Specifications 6.3.2 Advanced Mode. 6.3.3 Normal Mode. 6.3.4 Select Signal. Basic Interface 6.4.1 Overview. 6.4.2 Data Size Data Alignment 6.4.3 Valid Strobes 6.4.4 Basic Timing. 6.4.5 Wait Control Burst Interface 6.5.1 Overview. 6.5.2 Basic Timing. 6.5.3 Wait Control Idle Cycle. 6.6.1 Operation 6.6.2 States Idle Cycle. Arbitration. 6.7.1 Overview. 6.7.2 Operation 6.7.3 Transfer Timing.
Section
Data Transfer Controller [H8S/2138 Series]
Overview. 7.1.1 Features. 7.1.2 Block Diagram. 7.1.3 Register Configuration Register Descriptions. 7.2.1 Mode Register (MRA). 7.2.2 Mode Register (MRB) 7.2.3 Source Address Register (SAR) 7.2.4 Destination Address Register (DAR) 7.2.5 Transfer Count Register (CRA). 7.2.6 Transfer Count Register (CRB) 7.2.7 Enable Registers (DTCER) 7.2.8 Vector Register (DTVECR) 7.2.9 Module Stop Control Register (MSTPCR). Operation 7.3.1 Overview. 7.3.2 Activation Sources.
7.3.3 Vector Table 7.3.4 Location Register Information Address Space. 7.3.5 Normal Mode. 7.3.6 Repeat Mode. 7.3.7 Block Transfer Mode. 7.3.8 Chain Transfer 7.3.9 Operation Timing 7.3.10 Number Execution States 7.3.11 Procedures Using 7.3.12 Examples DTC. Interrupts Usage Notes
Section
Ports.
Overview. Port 8.2.1 Overview. 8.2.2 Register Configuration 8.2.3 Functions Each Mode. 8.2.4 Input Pull-Up Function Port 8.3.1 Overview. 8.3.2 Register Configuration 8.3.3 Functions Each Mode. 8.3.4 Input Pull-Up Function Port 8.4.1 Overview. 8.4.2 Register Configuration 8.4.3 Functions Each Mode. 8.4.4 Input Pull-Up Function Port 8.5.1 Overview. 8.5.2 Register Configuration 8.5.3 Functions Port 8.6.1 Overview. 8.6.2 Register Configuration 8.6.3 Functions Port 8.7.1 Overview. 8.7.2 Register Configuration 8.7.3 Functions 8.7.4 Input Pull-Up Function
Port 8.8.1 Overview. 8.8.2 Register Configuration 8.8.3 Functions Port 8.9.1 Overview. 8.9.2 Register Configuration 8.9.3 Functions 8.10 Port 8.10.1 Overview. 8.10.2 Register Configuration 8.10.3 Functions
Section
8-Bit Timers [H8S/2138 Series]
Overview. 9.1.1 Features. 9.1.2 Block Diagram. 9.1.3 Configuration 9.1.4 Register Configuration Register Descriptions. 9.2.1 Register Select (PWSL) 9.2.2 Data Registers (PWDR0 PWDR15) 9.2.3 Data Polarity Registers (PWDPRA PWDPRB). 9.2.4 Output Enable Registers (PWOERA PWOERB) 9.2.5 Peripheral Clock Select Register (PCSR). 9.2.6 Port Data Direction Register (P1DDR) 9.2.7 Port Data Direction Register (P2DDR) 9.2.8 Port Data Register (P1DR) 9.2.9 Port Data Register (P2DR) 9.2.10 Module Stop Control Register (MSTPCR). Operation 9.3.1 Correspondence between Data Register Contents Output Waveform
Section 14-Bit
10.1 Overview. 10.1.1 Features. 10.1.2 Block Diagram. 10.1.3 Configuration 10.1.4 Register Configuration 10.2 Register Descriptions. 10.2.1 Counter (DACNT) 10.2.2 Data Registers (DADRA DADRB).
10.2.3 Control Register (DACR). 10.2.4 Module Stop Control Register (MSTPCR). 10.3 Master Interface 10.4 Operation
Section 16-Bit Free-Running Timer
11.1 Overview. 11.1.1 Features. 11.1.2 Block Diagram. 11.1.3 Input Output Pins. 11.1.4 Register Configuration 11.2 Register Descriptions. 11.2.1 Free-Running Counter (FRC). 11.2.2 Output Compare Registers (OCRA, OCRB) 11.2.3 Input Capture Registers (ICRA ICRD). 11.2.4 Output Compare Registers (OCRAR, OCRAF) 11.2.5 Output Compare Register (OCRDM) 11.2.6 Timer Interrupt Enable Register (TIER). 11.2.7 Timer Control/Status Register (TCSR) 11.2.8 Timer Control Register (TCR) 11.2.9 Timer Output Compare Control Register (TOCR). 11.2.10 Module Stop Control Register (MSTPCR). 11.3 Operation 11.3.1 Increment Timing. 11.3.2 Output Compare Output Timing. 11.3.3 Clear Timing 11.3.4 Input Capture Input Timing 11.3.5 Timing Input Capture Flag (ICF) Setting. 11.3.6 Setting Output Compare Flags (OCFA, OCFB) 11.3.7 Setting Overflow Flag (OVF) 11.3.8 Automatic Addition OCRA OCRAR/OCRAF. 11.3.9 ICRD OCRDM Mask Signal Generation 11.4 Interrupts 11.5 Sample Application 11.6 Usage Notes
Section 8-Bit Timers
12.1 Overview. 12.1.1 Features. 12.1.2 Block Diagram. 12.1.3 Configuration 12.1.4 Register Configuration 12.2 Register Descriptions.
12.3
12.4 12.5 12.6
Timer Counter (TCNT). Time Constant Register (TCORA) Time Constant Register (TCORB) Timer Control Register (TCR) Timer Control/Status Register (TCSR) Serial/Timer Control Register (STCR). System Control Register (SYSCR). Timer Connection Register (TCONRS) Input Capture Register (TICR) [TMRX Additional Function]. Time Constant Register (TCORC) [TMRX Additional Function]. Input Capture Registers (TICRR, TICRF) [TMRX Additional Functions] 12.2.12 Timer Input Select Register (TISR) [TMRY Additional Function]. 12.2.13 Module Stop Control Register (MSTPCR). Operation 12.3.1 TCNT Incrementation Timing. 12.3.2 Compare-Match Timing 12.3.3 TCNT External Reset Timing. 12.3.4 Timing Overflow Flag (OVF) Setting. 12.3.5 Operation with Cascaded Connection 12.3.6 Input Capture Operation Interrupt Sources. 8-Bit Timer Application Example Usage Notes 12.6.1 Contention between TCNT Write Clear 12.6.2 Contention between TCNT Write Increment. 12.6.3 Contention between TCOR Write Compare-Match 12.6.4 Contention between Compare-Matches 12.6.5 Switching Internal Clocks TCNT Operation.
12.2.1 12.2.2 12.2.3 12.2.4 12.2.5 12.2.6 12.2.7 12.2.8 12.2.9 12.2.10 12.2.11
Section Timer Connection [H8S/2138 Series]
13.1 Overview. 13.1.1 Features. 13.1.2 Block Diagram. 13.1.3 Input Output Pins. 13.1.4 Register Configuration 13.2 Register Descriptions. 13.2.1 Timer Connection Register (TCONRI). 13.2.2 Timer Connection Register (TCONRO). 13.2.3 Timer Connection Register (TCONRS) 13.2.4 Edge Sense Register (SEDGR). 13.2.5 Module Stop Control Register (MSTPCR). 13.3 Operation
viii
Decoding (PDC Signal Generation). Clamp Waveform Generation (CL1/CL2/CL3 Signal Generation) Measurement 8-Bit Timer Divided Waveform Period. Signal Modification Signal Fall Modification Synchronization. Internal Synchronization Signal Generation (IHG/IVG/CL4 Signal Generation) 13.3.7 HSYNCO Output. 13.3.8 VSYNCO Output. 13.3.9 CBLANK Output.
13.3.1 13.3.2 13.3.3 13.3.4 13.3.5 13.3.6
Section Watchdog Timer (WDT)
14.1 Overview. 14.1.1 Features. 14.1.2 Block Diagram. 14.1.3 Configuration 14.1.4 Register Configuration 14.2 Register Descriptions. 14.2.1 Timer Counter (TCNT). 14.2.2 Timer Control/Status Register (TCSR) 14.2.3 System Control Register (SYSCR). 14.2.4 Notes Register Access 14.3 Operation 14.3.1 Watchdog Timer Operation 14.3.2 Interval Timer Operation 14.3.3 Timing Setting Overflow Flag (OVF) 14.4 Interrupts 14.5 Usage Notes 14.5.1 Contention between Timer Counter (TCNT) Write Increment 14.5.2 Changing Value CKS2 CKS0 14.5.3 Switching between Watchdog Timer Mode Interval Timer Mode. 14.5.4 Counter Value Transitions between High-Speed Mode, Subactive Mode, Watch Mode. 14.5.5 Flag Clear Condition
Section Serial Communication Interface (SCI, IrDA)
15.1 Overview. 15.1.1 Features. 15.1.2 Block Diagram. 15.1.3 Configuration 15.1.4 Register Configuration 15.2 Register Descriptions. 15.2.1 Receive Shift Register (RSR).
15.2.2 Receive Data Register (RDR). 15.2.3 Transmit Shift Register (TSR). 15.2.4 Transmit Data Register (TDR) 15.2.5 Serial Mode Register (SMR) 15.2.6 Serial Control Register (SCR) 15.2.7 Serial Status Register (SSR). 15.2.8 Rate Register (BRR). 15.2.9 Serial Interface Mode Register (SCMR) 15.2.10 Module Stop Control Register (MSTPCR). 15.2.11 Keyboard Comparator Control Register (KBCOMP) 15.3 Operation 15.3.1 Overview. 15.3.2 Operation Asynchronous Mode. 15.3.3 Multiprocessor Communication Function 15.3.4 Operation Synchronous Mode 15.3.5 IrDA Operation. 15.4 Interrupts. 15.5 Usage Notes
Section Interface [H8S/2138 Series Option]
16.1 Overview. 16.1.1 Features. 16.1.2 Block Diagram. 16.1.3 Input/Output Pins. 16.1.4 Register Configuration 16.2 Register Descriptions. 16.2.1 Data Register (ICDR). 16.2.2 Slave Address Register (SAR) 16.2.3 Second Slave Address Register (SARX). 16.2.4 Mode Register (ICMR) 16.2.5 Control Register (ICCR) 16.2.6 Status Register (ICSR) 16.2.7 Serial/Timer Control Register (STCR). 16.2.8 Switch Register (DDCSWR). 16.2.9 Module Stop Control Register (MSTPCR). 16.3 Operation 16.3.1 Data Format. 16.3.2 Master Transmit Operation. 16.3.3 Master Receive Operation 16.3.4 Slave Receive Operation. 16.3.5 Slave Transmit Operation. 16.3.6 IRIC Setting Timing Control. 16.3.7 Automatic Switching from Formatless Mode Format
16.3.8 Operation Using DTC. 16.3.9 Noise Canceler. 16.3.10 Sample Flowcharts 16.3.11 Initialization Internal State. 16.4 Usage Notes
Section Host Interface
17.1 Overview. 17.1.1 Features. 17.1.2 Block Diagram. 17.1.3 Input Output Pins. 17.1.4 Register Configuration 17.2 Register Descriptions. 17.2.1 System Control Register (SYSCR). 17.2.2 System Control Register (SYSCR2) 17.2.3 Host Interface Control Register (HICR). 17.2.4 Input Data Register (IDR1) 17.2.5 Output Data Register (ODR1) 17.2.6 Status Register (STR1) 17.2.7 Input Data Register (IDR2) 17.2.8 Output Data Register (ODR2) 17.2.9 Status Register (STR2) 17.2.10 Module Stop Control Register (MSTPCR). 17.3 Operation 17.3.1 Host Interface Operation. 17.3.2 Control States 17.3.3 Gate. 17.3.4 Host Interface Shutdown Function. 17.4 Interrupts 17.4.1 IBF1, IBF2. 17.4.2 HIRQ11, HIRQ1, HIRQ12 17.5 Usage Note.
Section Converter
18.1 Overview. 18.1.1 Features. 18.1.2 Block Diagram. 18.1.3 Input Output Pins. 18.1.4 Register Configuration 18.2 Register Descriptions. 18.2.1 Data Registers (DADR0, DADR1). 18.2.2 Control Register (DACR). 18.2.3 Module Stop Control Register (MSTPCR).
18.3 Operation
Section Converter
19.1 Overview. 19.1.1 Features. 19.1.2 Block Diagram. 19.1.3 Configuration 19.1.4 Register Configuration 19.2 Register Descriptions. 19.2.1 Data Registers (ADDRA ADDRD). 19.2.2 Control/Status Register (ADCSR) 19.2.3 Control Register (ADCR). 19.2.4 Keyboard Comparator Control Register (KBCOMP) 19.2.5 Module Stop Control Register (MSTPCR). 19.3 Interface Master. 19.4 Operation 19.4.1 Single Mode (SCAN 19.4.2 Scan Mode (SCAN 19.4.3 Input Sampling Conversion Time 19.4.4 External Trigger Input Timing 19.5 Interrupts 19.6 Usage Notes
Section
20.1 Overview. 20.1.1 Block Diagram. 20.1.2 Register Configuration 20.2 System Control Register (SYSCR). 20.3 Operation 20.3.1 Expanded Mode (Modes (EXPE 1)). 20.3.2 Single-Chip Mode (Modes (EXPE
Section (Mask Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, H8S/2132 F-ZTAT)
21.1 Overview. 21.1.1 Block Diagram. 21.1.2 Register Configuration 21.2 Register Descriptions. 21.2.1 Mode Control Register (MDCR) 21.3 Operation 21.4 Overview Flash Memory. 21.4.1 Features. 21.4.2 Block Diagram.
21.5
21.6
21.7
21.8
21.9 21.10
21.11 21.12
21.4.3 Flash Memory Operating Modes 21.4.4 Configuration 21.4.5 Register Configuration Register Descriptions. 21.5.1 Flash Memory Control Register (FLMCR1). 21.5.2 Flash Memory Control Register (FLMCR2). 21.5.3 Erase Block Registers (EBR1, EBR2) 21.5.4 Serial/Timer Control Register (STCR). On-Board Programming Modes. 21.6.1 Boot Mode 21.6.2 User Program Mode Programming/Erasing Flash Memory. 21.7.1 Program Mode 21.7.2 Program-Verify Mode 21.7.3 Erase Mode. 21.7.4 Erase-Verify Mode Flash Memory Protection. 21.8.1 Hardware Protection. 21.8.2 Software Protection 21.8.3 Error Protection. Interrupt Handling when Programming/Erasing Flash Memory Flash Memory Programmer Mode. 21.10.1 Programmer Mode Setting 21.10.2 Socket Adapters Memory 21.10.3 Programmer Mode Operation. 21.10.4 Memory Read Mode. 21.10.5 Auto-Program Mode. 21.10.6 Auto-Erase Mode. 21.10.7 Status Read Mode. 21.10.8 Status Polling 21.10.9 Programmer Mode Transition Time. 21.10.10 Notes Memory Programming Flash Memory Programming Erasing Precautions Note Switching from F-ZTAT Version Mask Version.
Section (H8S/2138 F-ZTAT A-mask Version, H8S/2134 F-ZTAT A-mask Version).
22.1 Overview. 22.1.1 Block Diagram. 22.1.2 Register Configuration 22.2 Register Descriptions. 22.2.1 Mode Control Register (MDCR) 22.3 Operation
xiii
22.4 Overview Flash Memory. 22.4.1 Features. 22.4.2 Block Diagram. 22.4.3 Flash Memory Operating Modes 22.4.4 Configuration 22.4.5 Register Configuration 22.5 Register Descriptions. 22.5.1 Flash Memory Control Register (FLMCR1). 22.5.2 Flash Memory Control Register (FLMCR2). 22.5.3 Erase Block Registers (EBR1, EBR2). 22.5.4 Serial/Timer Control Register (STCR). 22.6 On-Board Programming Modes. 22.6.1 Boot Mode 22.6.2 User Program Mode 22.7 Programming/Erasing Flash Memory. 22.7.1 Program Mode 22.7.2 Program-Verify Mode 22.7.3 Erase Mode. 22.7.4 Erase-Verify Mode 22.8 Flash Memory Protection. 22.8.1 Hardware Protection. 22.8.2 Software Protection 22.8.3 Error Protection 22.9 Interrupt Handling when Programming/Erasing Flash Memory 22.10 Flash Memory Programmer Mode. 22.10.1 Programmer Mode Setting 22.10.2 Socket Adapters Memory 22.10.3 Programmer Mode Operation. 22.10.4 Memory Read Mode. 22.10.5 Auto-Program Mode. 22.10.6 Auto-Erase Mode. 22.10.7 Status Read Mode. 22.10.8 Status Polling 22.10.9 Programmer Mode Transition Time. 22.10.10 Notes Memory Programming 22.11 Flash Memory Programming Erasing Precautions 22.12 Note Switching from F-ZTAT Version Mask Version.
Section Clock Pulse Generator.
23.1 Overview. 23.1.1 Block Diagram. 23.1.2 Register Configuration 23.2 Register Descriptions.
23.3
23.4 23.5 23.6 23.7 23.8 23.9
23.2.1 Standby Control Register (SBYCR). 23.2.2 Low-Power Control Register (LPWRCR). Oscillator. 23.3.1 Connecting Crystal Resonator 23.3.2 External Clock Input. Duty Adjustment Circuit. Medium-Speed Clock Divider. Master Clock Selection Circuit. Subclock Input Circuit. Subclock Waveform Shaping Circuit Clock Selection Circuit
Section Power-Down State
24.1 Overview. 24.1.1 Register Configuration 24.2 Register Descriptions. 24.2.1 Standby Control Register (SBYCR). 24.2.2 Low-Power Control Register (LPWRCR). 24.2.3 Timer Control/Status Register (TCSR) 24.2.4 Module Stop Control Register (MSTPCR). 24.3 Medium-Speed Mode. 24.4 Sleep Mode 24.4.1 Sleep Mode. 24.4.2 Clearing Sleep Mode 24.5 Module Stop Mode 24.5.1 Module Stop Mode 24.5.2 Usage Note 24.6 Software Standby Mode. 24.6.1 Software Standby Mode 24.6.2 Clearing Software Standby Mode. 24.6.3 Setting Oscillation Settling Time after Clearing Software Standby Mode. 24.6.4 Software Standby Mode Application Example 24.6.5 Usage Note. 24.7 Hardware Standby Mode 24.7.1 Hardware Standby Mode 24.7.2 Hardware Standby Mode Timing 24.8 Watch Mode. 24.8.1 Watch Mode 24.8.2 Clearing Watch Mode. 24.9 Subsleep Mode. 24.9.1 Subsleep Mode 24.9.2 Clearing Subsleep Mode. 24.10 Subactive Mode
24.10.1 Subactive Mode 24.10.2 Clearing Subactive Mode 24.11 Direct Transition 24.11.1 Overview Direct Transition.
Section Electrical Characteristics
25.1 Voltage Power Supply Operating Range 25.2 Electrical Characteristics H8S/2138 F-ZTAT. 25.2.1 Absolute Maximum Ratings. 25.2.2 Characteristics 25.2.3 Characteristics 25.2.4 Conversion Characteristics 25.2.5 Conversion Characteristics 25.2.6 Flash Memory Characteristics 25.2.7 Usage Note 25.3 Electrical Characteristics H8S/2138 F-ZTAT (A-mask version), Mask Versions H8S/2138 H8S/2137. 25.3.1 Absolute Maximum Ratings. 25.3.2 Characteristics. 25.3.3 Characteristics 25.3.4 Conversion Characteristics 25.3.5 Conversion Characteristics 25.3.6 Flash Memory Characteristics 25.3.7 Usage Note 25.4 Electrical Characteristics H8S/2134 F-ZTAT, H8S/2132 F-ZTAT, Mask Versions H8S/2132 H8S/2130. 25.4.1 Absolute Maximum Ratings. 25.4.2 Characteristics 25.4.3 Characteristics 25.4.4 Conversion Characteristics 25.4.5 Conversion Characteristics 25.4.6 Flash Memory Characteristics 25.4.7 Usage Note 25.5 Electrical Characteristics H8S/2134 F-ZTAT (A-mask Version), Mask Versions H8S/2134 H8S/2133. 25.5.1 Absolute Maximum Ratings. 25.5.2 Characteristics 25.5.3 Characteristics 25.5.4 Conversion Characteristics 25.5.5 Conversion Characteristics 25.5.6 Flash Memory Characteristics 25.5.7 Usage Note 25.6 Operational Timing.
25.6.1 25.6.2 25.6.3 25.6.4
Clock Timing Control Signal Timing Timing Timing On-Chip Supporting Modules
Appendix Instruction
Instruction Instruction Codes Operation Code Map. Number States Required Execution. States during Instruction Execution.
Appendix Internal Registers
Addresses. Register Selection Conditions. Functions.
Appendix Port Block Diagrams
Port Block Diagram Port Block Diagrams. Port Block Diagram Port Block Diagrams. Port Block Diagrams. Port Block Diagrams. Port Block Diagrams. Port Block Diagrams. Port Block Diagrams.
Appendix States
Port States Each Processing State.
Appendix Timing Transition Recovery from Hardware Standby Mode
Timing Transition Hardware Standby Mode. Timing Recovery from Hardware Standby Mode.
Appendix Product Code Lineup. Appendix Package Dimensions
xvii
Section Overview
Overview
H8S/2138 Series H8S/2134 Series comprise microcomputers (MCUs) built around H8S/2000 CPU, employing Hitachi's proprietary architecture, equipped with supporting modules on-chip. H8S/2000 internal 32-bit architecture, provided with sixteen 16-bit general registers concise, optimized instruction designed high-speed operation, address 16-Mbyte linear address space. instruction upward-compatible with H8/300 H8/300H instructions object-code level, facilitating migration from H8/300, H8/300L, H8/300H Series. On-chip supporting modules required system configuration include data transfer controller (DTC) master, memory, a16-bit free-running timer module (FRT), 8-bit timer module (TMR), watchdog timer module (WDT), timers (PWM PWMX), serial communication interface (SCI), host interface (HIF), converter (DAC), converter (ADC), ports. interface (IIC) also incorporated option. on-chip either flash memory (F-ZTATTM*) mask ROM, with capacity 128, kbytes. connected 16-bit data bus, enabling both byte word data accessed state. Instruction fetching been speeded processing speed increased. Three operating modes, modes provided, there choice address space single-chip mode externally expanded modes. features H8S/2138 Series H8S/2134 Series shown Table 1.1. Note: F-ZTATis trademark Hitachi, Ltd.
Table
Item
Overview
Specifications General-register architecture Sixteen 16-bit general registers (also usable sixteen 8-bit registers eight 32-bit registers) High-speed operation suitable real-time control Maximum operating frequency: MHz/5 MHz/3 High-speed arithmetic operations 8/16/32-bit register-register add/subtract: operation) 16-bit register-register multiply: 1000 operation) 16-bit register-register divide: 1000 operation) Instruction suitable high-speed operation Sixty-five basic instructions 8/16/32-bit transfer/arithmetic logic instructions Unsigned/signed multiply divide instructions Powerful bit-manipulation instructions operating modes Normal mode: 64-kbyte address space Advanced mode: 16-Mbyte address space Three operating modes External Data Operating Mode Mode Description Normal Expanded mode with on-chip disabled Expanded mode with on-chip enabled Single-chip mode Normal Expanded mode with on-chip enabled Single-chip mode Enabled On-Chip Initial Value Disabled bits Maximum Value bits
Operating modes
Advanced
Enabled
bits
bits
None bits bits
None
controller
2-state 3-state access space designated external expansion areas Number program wait states external expansion areas
Item Data transfer controller (DTC) (H8S/2138 Series)
Specifications activated internal interrupt software Multiple transfers multiple types transfer possible activation source Transfer possible repeat mode, block transfer mode, etc. Request sent interrupt that activated 16-bit free-running counter (also usable external event counting) output compare outputs Four input capture inputs (with buffer operation capability) 8-bit up-counter (also usable external event counting) time constant registers channels connected Measurement input signal frequency-divided waveform pulse width cycle (FRT, TMR1) Output waveform obtained modification input signal edge (FRT, TMR1) Determination input signal duty cycle (TMRX) Output waveform synchronized with input signal (FRT, TMRX, TMRY) Automatic generation cyclical waveform (FRT, TMRY) Watchdog timer interval timer function selectable Subclock operation capability (channel only) outputs Pulse duty cycle settable from 100% Resolution: 1/256 1.25 maximum carrier frequency operation) outputs Resolution: 1/16384 312.5 maximum carrier frequency operation) Asynchronous mode synchronous mode selectable Multiprocessor communication function
16-bit free-running timer module (FRT: channel) 8-bit timer module channels: TMR0, TMR1)
Each channel has:
Timer connection 8-bit timer (TMR) module channels: TMRX, TMRY) (Timer connection TMRX provided H8S/2138 Series)
Input/output FRT, TMR1, TMRX, TMRY interconnected
Watchdog timer module (WDT: channels) 8-bit timer (PWM) (H8S/2138 Series)
14-bit timer (PWMX)
Serial communication interface (SCI: channels, SCI0 SCI1)
Item with IrDA: channel (SCI2)
Specifications Asynchronous mode synchronous mode selectable Multiprocessor communication function Compatible with IrDA specification version encoding/decoding IrDA format 8-bit host interface (ISA) port Three host interrupt requests (HIRQ11, HIRQ1, HIRQ12) Normal fast gate output register sets (each comprising data registers status registers) Matrix keyboard control using keyboard scan with wakeup interrupt sense port configuration Resolution: bits Input: channels (dedicated analog pins) channels (same pins keyboard sense port) High-speed conversion: minimum conversion time operation) Single scan mode selectable Sample-and-hold function conversion activated external trigger timer trigger Resolution: bits Output: channels input/output pins (including with drive capability) input-only pins Flash memory mask High-speed static kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes
Host interface (HIF) (H8S/2138 Series)
Keyboard controller converter
converter ports Memory
Product Name H8S/2134, H8S/2138 H8S/2133 H8S/2132, H8S/2137 H8S/2130
Item Interrupt controller
Specifications Nine external interrupt pins (NMI, IRQ0 IRQ7) internal interrupt sources Three priority levels settable Medium-speed mode Sleep mode Module stop mode Software standby mode Hardware standby mode Subclock operation Built-in duty correction circuit 80-pin plastic (FP-80A) 80-pin plastic TQFP (TFP-80C) Conforms Philips interface standard Single master mode/slave mode Arbitration lost condition identified Supports slave addresses Product Code* Series H8S/2138 Mask Versions HD6432138S F-ZTATVersions ROM/RAM (Bytes) Packages FP-80A, TFP-80C
Power-down state
Clock pulse generator Packages interface (IIC: channels) (option H8S/2138 Series) Product lineup (preliminary)
HD64F2138
HD6432138SW HD64F2138A HD6432137S HD6432137SW H8S/2134 HD6432134S HD6432133S HD6432132 HD64F2134 HD64F2134A
HD64F2132R
HD6432130 Notes: indicates option. FP-80A only version, added product code. Appendix Product Code Lineup.
Internal Block Diagram
internal block diagram H8S/2138 Series shown figure 1.1, internal block diagram H8S/2134 Series figure 1.2.
VCC1 VCC2 (VCL)
Clock pulse generator
XTAL EXTAL STBY
Internal address
Internal data
H8S/2000
controller
P97/WAIT/SDA0 P95/AS/IOS/CS1 P94/WR/IOW P93/RD/IOR P92/IRQ0 P91/IRQ1 P90/IRQ2/ADTRG/ECS2 P67/TMOX/CIN7/KIN7/IRQ7 P66/FTOB/CIN6/KIN6/IRQ6 P65/FTID/CIN5/KIN5 P64/FTIC/CIN4/KIN4/CLAMPO P63/FTIB/CIN3/KIN3/VFBACKI P62/FTIA/CIN2/KIN2/VSYNCI/TMIY P61/FTOA/CIN1/KIN1/VSYNCO P60/FTCI/CIN0/KIN0/HFBACKI/TMIX P47/PWX1 P46/PWX0 P45/TMRI1/HIRQ12/CSYNCI P44/TMO1/HIRQ1/HSYNCO P43/TMCI1/HIRQ11/HSYNCI P42/TMRI0/SCK2/SDA1 P41/TMO0/RxD2/IrRxD P40/TMCI0/TxD2/IrTxD
Port
WDT0, WDT1
Port
Interrupt controller
P27/A15/PW15/CBLANK P26/A14/PW14 P25/A13/PW13 P24/A12/PW12 P23/A11/PW11 P22/A10/PW10 P21/A9/PW9 P20/A8/PW8 P17/A7/PW7 P16/A6/PW6 P15/A5/PW5 P14/A4/PW4 P13/A3/PW3 P12/A2/PW2 P11/A1/PW1 P10/A0/PW0 P37/D7/HDB7 P36/D6/HDB6 P35/D5/HDB5 P34/D4/HDB4 P33/D3/HDB3 P32/D2/HDB2 P31/D1/HDB1 P30/D0/HDB0
Port
16-bit
8-bit
14-bit 8-bit timer (TMR0, TMR1, TMRX, TMRY) Timer connection
Port
Host interface
Port
10-bit
(IrDA 1ch)
Port
8-bit
P52/SCK0/SCL0 P51/RxD0 P50/TxD0
(option)
Port
Port
AVCC AVSS
Figure Internal Block Diagram H8S/2138 Series
P86/IRQ5/SCK1/SCL1 P85/IRQ4/RxD1 P84/IRQ3/TxD1 P82/HIFSD P81/CS2/GA20 P80/HA0
P77/AN7/DA1 P76/AN6/DA0 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0
Port
EXTAL STBY
Clock pulse generator
XTAL
VCC1 VCC2 (VCL)
Internal address
Internal data
H8S/2000
controller
P27/A15 P26/A14 Port P25/A13 P24/A12 P23/A11 P22/A10 P21/A9 P20/A8
P97/WAIT Port P95/AS/IOS P94/WR P93/RD P92/IRQ0 P91/IRQ1 P90/IRQ2/ADTRG P67/CIN7/KIN7/IRQ7 P66/FTOB/CIN6/KIN6/IRQ6 P65/FTID/CIN5/KIN5 P64/FTIC/CIN4/KIN4 P63/FTIB/CIN3/KIN3 P62/FTIA/CIN2/KIN2/TMIY P61/FTOA/CIN1/KIN1 P60/FTCI/CIN0/KIN0 P47/PWX1 P46/PWX0 P45/TMRI1 P44/TMO1 P43/TMCI1 P42/TMRI0/SCK2 P41/TMO0/RxD2/IrRxD P40/TMCI0/TxD2/IrTxD
Interrupt controller
WDT0, WDT1 Port
P17/A7 P16/A6 P15/A5 P14/A4 P13/A3 P12/A2 P11/A1 P10/A0 P37/D7 P36/D6 P35/D5 P34/D4 P33/D3 P32/D2 P31/D1 P30/D0
Port
16-bit
14-bit Port Port 8-bit timer (TMR0, TMR1, TMRY) 10-bit (IrDA 1ch) Port 8-bit Port Port P86/IRQ5/SCK1 P85/IRQ4/RxD1 P84/IRQ3/TxD1 AVCC AVSS
P52/SCK0 P51/RxD0 P50/TxD0
Figure Internal Block Diagram H8S/2134 Series
P77/AN7/DA1 P76/AN6/DA0 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0
1.3.1
Arrangement Functions
Arrangement
arrangement H8S/2138 Series shown figure 1.3, arrangement H8S/2134 Series figure 1.4.
P45/TMRI1/HIRQ12/CSYNCI P43/TMCI1/HIRQ11/HSYNCI
P44/TMO1/HIRQ1/HSYNCO
P27/A15/PW15/CBLANK
PW3/A3/P13 PW2/A2/P12 PW1/A1/P11 PW0/A0/P10 HDB0/D0/P30 HDB1/D1/P31 HDB2/D2/P32 HDB3/D3/P33 HDB4/D4/P34 HDB5/D5/P35 HDB6/D6/P36 HDB7/D7/P37 HA0/P80 GA20/CS2/P81 HIFSD/P82 TxD1/IRQ3/P84 RxD1/IRQ4/P85 SCL1/SCK1/IRQ5/P86
P42/TMRI0/SCK2/SDA1
P22/A10/PW10
P23/A11/PW11
P24/A12/PW12
P25/A13/PW13
P26/A14/PW14
P14/A4/PW4
P15/A5/PW5
P16/A6/PW6
P17/A7/PW7
P20/A8/PW8
P21/A9/PW9
P47/PWX1
P46/PWX0
VCC1
P41/TMO0/RxD2/IrRxD P40/TMCI0/TxD2/IrTxD AVSS P77/AN7/DA1 P76/AN6/DA0 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 AVCC P67/TMOX/CIN7/KIN7/IRQ7 P66/FTOB/CIN6/KIN6/IRQ6 P65/FTID/CIN5/KIN5 P64/FTIC/CIN4/KIN4/CLAMPO P63/FTIB/CIN3/KIN3/VFBACKI P62/FTIA/CIN2/KIN2/VSYNCI/TMIY P61/FTOA/CIN1/KIN1/VSYNCO P60/FTCI/CIN0/KIN0/HFBACKI/TMIX
FP-80A TFP-80C (Top view)
Figure Arrangement H8S/2138 Series (FP-80A, TFP-80C: View)
ADTRG/IRQ2/ECS2/P90
SDA0/WAIT/P97
CS1/IOS/AS/P95
IOW/WR/P94
EXCL/ /P96
IOR/RD/P93
VCC2 (VCL)
IRQ0/P92
SCL0/SCK0/P52
RxD0/P51
TxD0/P50
IRQ1/P91
EXTAL
XTAL
STBY
A3/P13 A2/P12 A1/P11 A0/P10 D0/P30 D1/P31 D2/P32 D3/P33 D4/P34 D5/P35 D6/P36 D7/P37 TxD1/IRQ3/P84 RxD1/IRQ4/P85 SCK1/IRQ5/P86
P42/TMRI0/SCK2
P45/TMRI1
P43/TMCI1
P47/PWX1
P46/PWX0
P44/TMO1
P22/A10
P23/A11
P24/A12
P25/A13
P26/A14
P27/A15
P14/A4
P15/A5
P16/A6
P17/A7
P20/A8
P21/A9
VCC1
P41/TMO0/RxD2/IrRxD P40/TMCI0/TxD2/IrTxD AVSS P77/AN7/DA1 P76/AN6/DA0 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 AVCC P67/CIN7/KIN7/IRQ7 P66/FTOB/CIN6/KIN6/IRQ6 P65/FTID/CIN5/KIN5 P64/FTIC/CIN4/KIN4 P63/FTIB/CIN3/KIN3 P62/FTIA/CIN2/KIN2/TMIY P61/FTOA/CIN1/KIN1 P60/FTCI/CIN0/KIN0
FP-80A TFP-80C (Top view)
Figure Arrangement H8S/2134 Series (FP-80A, TFP-80C: View)
ADTRG/IRQ2/P90
EXCL/ /P96
VCC2 (VCL)
RxD0/P51
IOS/AS/P95
SCK0/P52
TxD0/P50
WAIT/P97
IRQ0/P92
IRQ1/P91
WR/P94
RD/P93
EXTAL
XTAL
STBY
1.3.2
Functions Each Operating Mode
Tables show functions H8S/2138 Series H8S/2134 Series each operating modes. Table H8S/2138 Series Functions Each Operating Mode
Name FP-80A TFP-80C Mode XTAL EXTAL STBY VCC2 (VCL) P51/RxD0 P50/TxD0 AS/IOS P92/IRQ0 P91/IRQ1 P90/IRQ2/ ADTRG P60/FTCI/CIN0/ KIN0/TMIX/ HFBACKI Expanded Modes Mode (EXPE Mode (EXPE XTAL EXTAL STBY VCC2 (VCL) P51/RxD0 P50/TxD0 AS/IOS P92/IRQ0 P91/IRQ1 P90/IRQ2/ADTRG P60/FTCI/CIN0/ KIN0/TMIX/ HFBACKI Single-Chip Modes Mode (EXPE Mode (EXPE XTAL EXTAL STBY VCC2 (VCL) P52/SCK0/SCL0 P51/RxD0 P50/TxD0 P97/SDA0 P95/CS1 P94/IOW P93/IOR P92/IRQ0 P91/IRQ1 P90/IRQ2/ADTRG/ ECS2 P60/FTCI/CIN0/ KIN0/TMIX/ HFBACKI P61/FTOA/CIN1/ KIN1/VSYNCO P62/FTIA/CIN2/ KIN2/TMIY/ VSYNCI Flash Memory Programmer Mode XTAL EXTAL FA17 FA16 FA15
P52/SCK0/SCL0 P52/SCK0/SCL0
P97/WAIT/SDA0 P97/WAIT/SDA0
P61/FTOA/CIN1/ P61/FTOA/CIN1/ KIN1/VSYNCO KIN1/VSYNCO P62/FTIA/CIN2/ KIN2/TMIY/ VSYNCI P62/FTIA/CIN2/ KIN2/TMIY/ VSYNCI
Name FP-80A TFP-80C Mode P63/FTIB/CIN3/ KIN3/VFBACKI P64/FTIC/CIN4/ KIN4/CLAMPO P65/FTID/CIN5/ KIN5 Expanded Modes Mode (EXPE Mode (EXPE P63/FTIB/CIN3/ KIN3/VFBACKI P64/FTIC/CIN4/ KIN4/CLAMPO P65/FTID/CIN5/ KIN5 Single-Chip Modes Mode (EXPE Mode (EXPE P63/FTIB/CIN3/ KIN3/VFBACKI P64/FTIC/CIN4/ KIN4/CLAMPO P65/FTID/CIN5/ KIN5 P66/FTOB/CIN6/ KIN6/IRQ6 P67/TMOX/CIN7/ KIN7/IRQ7 AVCC P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 AVSS P40/TMCI0/ TxD2/IrTxD P41/TMO0/ RxD2/IrRxD P42/TMRI0/ SCK2/SDA1 P43/TMCI1/HIRQ11/ HSYNCI P44/TMO1/HIRQ1/ HSYNCO P45/TMRI1/HIRQ12/ CSYNCI P46/PWX0 P47/PWX1 VCC1 Flash Memory Programmer Mode
P66/FTOB/CIN6/ P66/FTOB/CIN6/ KIN6/IRQ6 KIN6/IRQ6 P67/TMOX/CIN/ KIN7/IRQ7 AVCC P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 AVSS P40/TMCI0/ TxD2/IrTxD P41/TMO0/ RxD2/IrRxD P42/TMRI0/ SCK2/SDA1 P43/TMCI1/ HSYNCI P44/TMO1/ HSYNCO P45/TMRI1/ CSYNCI P46/PWX0 P47/PWX1 VCC1 P67/TMOX/CIN7/ KIN7/IRQ7 AVCC P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 AVSS P40/TMCI0/ TxD2/IrTxD P41/TMO0/ RxD2/IrRxD P42/TMRI0/ SCK2/SDA1 P43/TMCI1/ HSYNCI P44/TMO1/ HSYNCO P45/TMRI1/ CSYNCI P46/PWX0 P47/PWX1 VCC1
Name FP-80A TFP-80C Mode Expanded Modes Mode (EXPE Mode (EXPE A15/P27/PW15/ CBLANK A14/P26/PW14 A13/P25/PW13 A12/P24/PW12 A11/P23/PW11 A10/P22/PW10 A9/P21/PW9 A8/P20/PW8 A7/P17/PW7 A6/P16/PW6 A5/P15/PW5 A4/P14/PW4 A3/P13/PW3 A2/P12/PW2 A1/P11/PW1 A0/P10/PW0 Single-Chip Modes Mode (EXPE Mode (EXPE P27/PW15/CBLANK P26/PW14 P25/PW13 P24/PW12 P23/PW11 P22/PW10 P21/PW9 P20/PW8 P17/PW7 P16/PW6 P15/PW5 P14/PW4 P13/PW3 P12/PW2 P11/PW1 P10/PW0 P30/HDB0 P31/HDB1 P32/HDB2 P33/HDB3 P34/HDB4 P35/HDB5 P36/HDB6 P37/HDB7 P80/HA0 P81/CS2/GA20 P82/HIFSD Flash Memory Programmer Mode FA14 FA13 FA12 FA11 FA10
Name FP-80A TFP-80C Mode P84/IRQ3/TxD1 P85/IRQ4/RxD1 Expanded Modes Mode (EXPE Mode (EXPE P84/IRQ3/TxD1 P85/IRQ4/RxD1 Single-Chip Modes Mode (EXPE Mode (EXPE P84/IRQ3/TxD1 P85/IRQ4/RxD1 P86/IRQ5/SCK1/ SCL1 Flash Memory Programmer Mode
P86/IRQ5/SCK1/ P86/IRQ5/SCK1/ SCL1 SCL1
Table
H8S/2134 Series Functions Each Operating Mode
Name
FP-80A TFP-80C Mode XTAL EXTAL STBY
Expanded Modes Mode (EXPE Mode (EXPE XTAL EXTAL STBY VCC2 (VCL) P52/SCK0 P51/RxD0 P50/TxD0 P97/WAIT AS/IOS P92/IRQ0 P91/IRQ1 P90/IRQ2/ADTRG P60/FTCI/CIN0/ KIN0 P61/FTOA/CIN1/ KIN1 P62/FTIA/CIN2/ KIN2/TMIY P63/FTIB/CIN3/ KIN3 P64/FTIC/CIN4/ KIN4 P65/FTID/CIN5/ KIN5
Single-Chip Modes Mode (EXPE Mode (EXPE XTAL EXTAL STBY VCC2 (VCL) P52/SCK0 P51/RxD0 P50/TxD0 P92/IRQ0 P91/IRQ1 P90/IRQ2/ADTRG P60/FTCI/CIN0/ KIN0 P61/FTOA/CIN1/ KIN1 P62/FTIA/CIN2/ KIN2/TMIY P63/FTIB/CIN3/ KIN3 P64/FTIC/CIN4/ KIN4 P65/FTID/CIN5/ KIN5
Flash Memory Programmer Mode XTAL EXTAL FA17 FA16 FA15
VCC2 (VCL) P52/SCK0 P51/RxD0 P50/TxD0 P97/WAIT AS/IOS P92/IRQ0 P91/IRQ1 P90/IRQ2/ ADTRG P60/FTCI/CIN0/ KIN0 P61/FTOA/ CIN1/KIN1 P62/FTIA/CIN2/ KIN2/TMIY P63/FTIB/CIN3/ KIN3 P64/FTIC/CIN4/ KIN4 P65/FTID/CIN5/ KIN5
Name FP-80A TFP-80C Mode Expanded Modes Mode (EXPE Mode (EXPE Single-Chip Modes Mode (EXPE Mode (EXPE P66/FTOB/CIN6/ KIN6/IRQ6 P67/CIN7/KIN7/ IRQ7 AVCC P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 AVSS P40/TMCI0/ TxD2/IrTxD P41/TMO0/ RxD2/IrRxD P42/TMRI0/ SCK2 P43/TMCI1 P44/TMO1 P45/TMRI1 P46/PWX0 P47/PWX1 VCC1 Flash Memory Programmer Mode FA14 FA13 FA12 FA11 FA10
P66/FTOB/CIN6/ P66/FTOB/CIN6/ KIN6/IRQ6 KIN6/IRQ6 P67/CIN7/KIN7/ IRQ7 AVCC P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 AVSS P40/TMCI0/ TxD2/IrTxD P41/TMO0/ RxD2/IrRxD P42/TMRI0/ SCK2 P43/TMCI1 P44/TMO1 P45/TMRI1 P46/PWX0 P47/PWX1 VCC1 P67/CIN7/KIN7/ IRQ7 AVCC P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 AVSS P40/TMCI0/ TxD2/IrTxD P41/TMO0/ RxD2/IrRxD P42/TMRI0/ SCK2 P43/TMCI1 P44/TMO1 P45/TMRI1 P46/PWX0 P47/PWX1 VCC1 A15/P27 A14/P26 A13/P25 A12/P24 A11/P23 A10/P22
Name FP-80A TFP-80C Mode P84/IRQ3/TxD1 P85/IRQ4/RxD1 P86/IRQ5/SCK1 Expanded Modes Mode (EXPE Mode (EXPE A9/P21 A8/P20 A7/P17 A6/P16 A5/P15 A4/P14 A3/P13 A2/P12 A1/P11 A0/P10 P84/IRQ3/TxD1 P85/IRQ4/RxD1 P86/IRQ5/SCK1 Single-Chip Modes Mode (EXPE Mode (EXPE P84/IRQ3/TxD1 P85/IRQ4/RxD1 P86/IRQ5/SCK1 Flash Memory Programmer Mode
1.3.3
Functions
Table summarizes functions H8S/2138 Series H8S/2134 Series pins. Table Functions
Type Power supply Symbol VCC1, VCC2 FP-80A TFP-80C Input Name Function Power supply: connection power supply. VCC1 VCC2* pins should connected system power supply. Internal step-down voltage pin: power supply product, applicable product lines that have internal step-down voltage. versions, connect external capacitors stabilize internal step-down voltage between this pin. connect Vcc. version, connect this VCC1 power supply system. details, Section Electrical Characteristics. Ground: connection power supply pins should connected system power supply Connected crystal oscillator. section Clock Pulse Generator, typical connection diagrams crystal oscillator external clock input. Connected crystal oscillator. EXTAL also input external clock. section Clock Pulse Generator, typical connection diagrams crystal oscillator external clock input.
Input
Input
Clock
XTAL
Input
EXTAL
Input
EXCL
Output System clock: Supplies system clock external devices. Input External subclock input: Input 32.768 external subclock.
Type Operating mode control Symbol FP-80A TFP-80C Input Name Function Mode pins: These pins operating mode. relation between settings pins operating mode shown below. These pins should changed while operating. Operating Mode Description Mode Normal Expanded mode with on-chip disabled Advanced Expanded mode with on-chip enabled single-chip mode Normal Expanded mode with on-chip enabled single-chip mode
Mode
Mode
System control
STBY
Input Input
Reset input: When this driven low, chip reset. Standby: When this driven low, transition made hardware standby mode.
Address Data control
WAIT
Output Address bus: These pins output address. Input/ output Input Data (upper): Bidirectional data bus. Used 8-bit data. Wait: Requests insertion wait state cycle when accessing external 3-state address space.
AS/IOS
Output Read: When this low, indicates that external address space being read. Output Write: When this low, indicates that external address space being written Output Address strobe: When this low, indicates that address output address valid.
Type Interrupt signals Symbol IRQ0 IRQ7 16-bit free- FTCI running timer (FRT) FTOA FTOB FTIA FTIB FTIC FTID 8-bit timer (TMR0, TMR1, TMRX, TMRY) TMO0 TMO1 TMOX TMCI0 TMCI1 TMRI0 TMRI1 TMIX TMIY timer (PWM) PW15 FP-80A TFP-80C Input Input Name Function Nonmaskable interrupt: Requests nonmaskable interrupt. Interrupt request These pins request maskable interrupt. counter clock input: Input external clock signal free-running counter (FRC).
Input
Output output compare output: output compare output pin. Output output compare output: output compare output pin. Input Input Input Input input capture input: input capture input pin. input capture input: input capture input pin. input capture input: input capture input pin. input capture input: input capture input pin.
Output Compare-match output: TMR0, TMR1, TMRX compare-match output pins. Input Counter external clock input: Input pins external clock input TMR0 TMR1 counters. Counter external reset input: TMR0 TMR1 counter reset input pins. Counter external clock input reset input: Dual function TMRX TMRY counter clock input reset input pin.
Input Input
Output timer output: timer pulse output pins. Output PWMX timer output: pulse output pins.
14-bit PWX0 timer PWX1 (PWMX)
Type Symbol TxD0 TxD1 TxD2 FP-80A TFP-80C Name Function
Serial communication interface (SCI0, SCI1, RxD0 SCI2) RxD1 RxD2 SCK0 SCK1 SCK2
Output Transmit data: Data output pins.
Input
Receive data: Data input pins.
Input/ output
Serial clock: Clock input/output pins. SCK0 output type NMOS push-pull H8S/2138 series CMOS output H8S/2134 series.
with IrTxD IrDA (SCI2) IrRxD Host interface (HIF) HDB7 HDB0 CS1, CS2, ECS2 GA20 HIRQ11 HIRQ1 HIRQ12 HIFSD
Output IrDA transmit data/receive data: Input output Input pins data encoded IrDA use. Input/ output Input Host interface data bus: Bidirectional 8-bit accessing host interface. Chip select Input pins selecting host interface channel read: Input that enables reading from host interface. write: Input that enables writing host interface. Command/data: Input that indicates whether access data access command access.
Input Input Input
Output GATE A20: gate control signal output pin. Output Host interrupt Output pins interrupt requests host. Input Host interface shutdown: Control input used place host interface input/output pins highimpedance/cutoff state. Keyboard input: Matrix keyboard input pins. Normally, used key-scan outputs. This enables maximum 16output 16-input, 256-key matrix configured.
Keyboard control
KIN0 KIN7
Input
Type converter (ADC) Symbol FP-80A TFP-80C Input Name Function Analog input: converter analog input pins.
Input
Expansion inputs: Expansion input pins connected converter, since they also used digital input/output pins, precision will fall. conversion external trigger input: input external trigger start conversion.
ADTRG converter (DAC) converter converter AVCC
Input
Output Analog output: converter analog output pins.
Input
Analog reference voltage: analog power supply converter converter. When converters used, this should connected system power supply
AVSS
Input
Analog ground: ground converter converter. This should connected system power supply Timer connection input: Timer connection synchronous signal input pins.
Timer connection
VSYNCI, HSYNCI, CSYNCI, VFBACKI, HFBACKI VSYNCO, HSYNCO, CLAMPO, CBLANK
Input
Output Timer connection output: Timer connection synchronous signal output pins.
interface (IIC) (option)
SCL0 SCL1
Input/ output
clock input/output (channels clock pins. These pins have drive function. SCL0 output form NMOS open-drain data input/output (channels data pins. These pins have drive function. SDA0 output form NMOS open-drain.
SDA0 SDA1
Input/ output
Type ports Symbol FP-80A TFP-80C Input/ output Name Function Port Eight input/output pins. data direction each selected port data direction register (P1DDR). These pins have built-in input pull-ups, also have drive capability. Port Eight input/output pins. data direction each selected port data direction register (P2DDR). These pins have built-in input pull-ups, also have drive capability. Port Eight input/output pins. data direction each selected port data direction register (P3DDR). These pins have built-in input pull-ups, also have drive capability. Port Eight input/output pins. data direction each selected port data direction register (P4DDR). Port Three input/output pins. data direction each selected port data direction register (P5DDR). NMOS pushpull output H8S/2138 series CMOS output H8S/2134 series. Port Eight input/output pins. data direction each selected port data direction register (P6DDR). These pins have built-in input pull-ups. Port Eight input pins. Port Seven input/output pins. data direction each selected port data direction register (P8DDR). Port Eight input/output pins. data direction each (except P96) selected port data direction register (P9DDR). NMOS push-pull output H8S/2138 series CMOS output H8S/2134 series.
Input/ output
Input/ output
Input/ output Input/ output
Input/ output
Input Input/ output Input/ output
Note: F-ZTAT mask versions HD64F2138A, HD64F2134A, HD6432138S, HD6432138SW HD6432137S, HD6432137SW, HD6432134S, HD6432133S, VCC2 pin) pin.
Section
Overview
H8S/2000 high-speed central processing unit with internal 32-bit architecture that upward-compatible with H8/300 H8/300H CPUs. H8S/2000 sixteen 16-bit general registers, address 16-Mbyte (architecturally 4-Gbyte) linear address space, ideal realtime control. 2.1.1 Features
H8S/2000 following features. Upward-compatible with H8/300 H8/300H CPUs execute H8/300 H8/300H object programs General-register architecture Sixteen 16-bit general registers (also usable sixteen 8-bit registers eight 32-bit registers) Sixty-five basic instructions 8/16/32-bit arithmetic logic instructions Multiply divide instructions Powerful bit-manipulation instructions Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) @(d:32,ERn)] Register indirect with post-increment pre-decrement [@ERn+ @-ERn] Absolute address [@aa:8, @aa:16, @aa:24, @aa:32] Immediate [#xx:8, #xx:16, #xx:32] Program-counter relative [@(d:8,PC) @(d:16,PC)] Memory indirect [@@aa:8] 16-Mbyte address space Program: Mbytes Data: Mbytes Gbytes architecturally)
High-speed operation frequently-used instructions execute states Maximum clock rate: 8/16/32-bit register-register add/subtract: 8-bit register-register multiply: 8-bit register-register divide: 16-bit register-register multiply: 1000 16-bit register-register divide: 1000 operating modes Normal mode Advanced mode Power-down state Transition power-down state SLEEP instruction clock speed selection 2.1.2 Differences between H8S/2600 H8S/2000
differences between H8S/2600 H8S/2000 shown below. Register configuration register supported only H8S/2600 CPU. Basic instructions four instructions MAC, CLRMAC, LDMAC, STMAC supported only H8S/2600 CPU. Number execution states number execution states MULXU MULXS instructions differ follows.
Number Execution States Instruction MULXU Mnemonic MULXU.B MULXU.W MULXS MULXS.B MULXS.W H8S/2600 H8S/2000
There also differences address space, register functions, power-down state, etc., depending product.
2.1.3
Differences from H8/300
comparison H8/300 CPU, H8S/2000 following enhancements. More general registers control registers Eight 16-bit extended registers, 8-bit control register, have been added. Expanded address space Normal mode supports same 64-kbyte address space H8/300 CPU. Advanced mode supports maximum 16-Mbyte address space. Enhanced addressing addressing modes have been enhanced make effective 16-Mbyte address space. Enhanced instructions Addressing modes bit-manipulation instructions have been enhanced. Signed multiply divide instructions have been added. Two-bit shift instructions have been added. Instructions saving restoring multiple registers have been added. test instruction been added. Higher speed Basic instructions execute twice fast. 2.1.4 Differences from H8/300H
comparison H8/300H CPU, H8S/2000 following enhancements. Additional control register 8-bit control register been added. Enhanced instructions Addressing modes bit-manipulation instructions have been enhanced. Two-bit shift instructions have been added. Instructions saving restoring multiple registers have been added. test instruction been added. Higher speed Basic instructions execute twice fast.
Operating Modes
H8S/2000 operating modes: normal advanced. Normal mode supports maximum 64-kbyte address space. Advanced mode supports maximum 16-Mbyte total address space (architecturally maximum total address space Gbytes, with maximum Mbytes program area maximum Gbytes data area). mode selected mode pins microcontroller.
Maximum kbytes program data areas combined
Normal mode
operating modes
Advanced mode
Maximum Mbytes program data areas combined
Figure Operating Modes Normal Mode exception vector table stack have same structure H8/300 CPU. Address Space: maximum address space kbytes accessed. Extended Registers (En): extended registers used 16-bit registers, upper 16-bit segments 32-bit registers. When used 16-bit register contain value, even when corresponding general register (Rn) used address register. general register referenced register indirect addressing mode with pre-decrement (@-Rn) post-increment (@Rn+) carry borrow occurs, however, value corresponding extended register (En) will affected. Instruction Set: instructions addressing modes used. Only lower bits effective addresses (EA) valid.
Exception Vector Table Memory Indirect Branch Addresses: normal mode area starting H'0000 allocated exception vector table. branch address stored bits. configuration exception vector table normal mode shown figure 2.2. details exception vector table, section Exception Handling.
H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B
Reset exception vector
(Reserved system use)
Exception vector table
Exception vector Exception vector
Figure Exception Vector Table (Normal Mode) memory indirect addressing mode (@@aa:8) employed instructions uses 8-bit absolute address included instruction code specify memory operand that contains branch address. normal mode operand 16-bit word operand, providing 16bit branch address. Branch addresses stored area from H'0000 H'00FF. Note that this area also used exception vector table.
Stack Structure: When program counter (PC) pushed onto stack subroutine call, condition-code register (CCR) pushed onto stack exception handling, they stored shown figure 2.3. extended control register (EXR) pushed onto stack. details, section Exception Handling.
bits)
CCR* bits)
Subroutine Branch Note: Ignored when returning.
Exception Handling
Figure Stack Structure Normal Mode Advanced Mode Address Space: Linear access provided 16-Mbyte maximum address space (architecturally maximum 16-Mbyte program area maximum 4-Gbyte data area, with maximum Gbytes program data areas combined). Extended Registers (En): extended registers used 16-bit registers, upper 16-bit segments 32-bit registers address registers. Instruction Set: instructions addressing modes used.
Exception Vector Table Memory Indirect Branch Addresses: advanced mode area starting H'00000000 allocated exception vector table units bits. each bits, upper bits ignored branch address stored lower bits (figure 2.4). details exception vector table, section Exception Handling.
H'00000000 Reserved Reset exception vector H'00000003 H'00000004 Reserved
H'00000007 H'00000008 Exception vector table
H'0000000B H'0000000C
(Reserved system use)
H'00000010
Reserved Exception vector
Figure Exception Vector Table (Advanced Mode) memory indirect addressing mode (@@aa:8) employed instructions uses 8-bit absolute address included instruction code specify memory operand that contains branch address. advanced mode operand 32-bit longword operand, providing 32-bit branch address. upper bits these bits reserved area that regarded H'00. Branch addresses stored area from H'00000000 H'000000FF. Note that first part this range also exception vector table.
Stack Structure: advanced mode, when program counter (PC) pushed onto stack subroutine call, condition-code register (CCR) pushed onto stack exception handling, they stored shown figure 2.5. extended control register (EXR) pushed onto stack. details, section Exception Handling.
Reserved bits)
bits)
Subroutine Branch
Exception Handling
Figure Stack Structure Advanced Mode
Address Space
Figure shows memory H8S/2000 CPU. H8S/2000 provides linear access maximum 64-kbyte address space normal mode, maximum 16-Mbyte (architecturally 4-Gbyte) address space advanced mode.
H'0000 H'00000000
H'FFFF
Program area
H'00FFFFFF
Data area Cannot used H8S/2138 Series H8S/2134 Series
H'FFFFFFFF Normal Mode Advanced Mode
Figure Memory
2.4.1
Register Configuration
Overview
internal registers shown figure 2.7. There types registers: general registers control registers.
General Registers (Rn) Extended Registers (En) (SP) Control Registers (CR) EXR* Legend: EXR: CCR:
Stack pointer Program counter Extended control register Trace Interrupt mask bits Condition-code register Interrupt mask User interrupt mask
Half-carry flag User Negative flag Zero flag Overflow flag Carry flag
Note: Does affect operation H8S/2138 Series H8S/2134 Series.
Figure Registers
2.4.2
General Registers
eight 32-bit general registers. These general registers functionally alike used both address registers data registers. When general register used data register, accessed 32-bit, 16-bit, 8-bit register. When general registers used 32-bit registers address registers, they designated letters (ER0 ER7). registers divide into 16-bit general registers designated letters R7). These registers functionally equivalent, providing maximum sixteen 16-bit registers. registers also referred extended registers. registers divide into 8-bit general registers designated letters (R0H R7H) (R0L R7L). These registers functionally equivalent, providing maximum sixteen 8bit registers. Figure illustrates usage general registers. usage each register selected independently.
Address registers 32-bit registers
16-bit registers registers (extended registers)
8-bit registers
registers (ER0 ER7) registers
registers (R0H R7H)
registers (R0L R7L)
Figure Usage General Registers General register function stack pointer (SP) addition general-register function, used implicitly exception handling subroutine calls. Figure shows stack.
Free area
(ER7)
Stack area
Figure Stack 2.4.3 Control Registers
control registers 24-bit program counter (PC), 8-bit extended control register (EXR), 8-bit condition-code register (CCR). Program Counter (PC): This 24-bit counter indicates address next instruction will execute. length instructions bytes (one word), least significant ignored. (When instruction fetched, least significant regarded Extended Control Register (EXR): 8-bit register. H8S/2138 Series H8S/2134 Series, this register does affect operation. 7-Trace (T): This reserved. H8S/2138 Series H8S/2134 Series, this does affect operation. Bits 3-Reserved: These bits reserved. They always read Bits 0-Interrupt Mask Bits I0): These bits reserved. H8S/2138 Series H8S/2134 Series, these bits affect operation. Condition-Code Register (CCR): This 8-bit register contains internal status information, including interrupt mask half-carry (H), negative (N), zero (Z), overflow (V), carry flags. 7-Interrupt Mask (I): Masks interrupts other than when (NMI accepted regardless setting.) hardware start exceptionhandling sequence. details, refer section Interrupt Controller.
6-User Interrupt Mask (UI): written read software using LDC, STC, ANDC, ORC, XORC instructions. This also used interrupt mask bit. details, refer section Interrupt Controller. 5-Half-Carry Flag (H): When ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, NEG.B instruction executed, this flag there carry borrow cleared otherwise. When ADD.W, SUB.W, CMP.W, NEG.W instruction executed, flag there carry borrow cleared otherwise. When ADD.L, SUB.L, CMP.L, NEG.L instruction executed, flag there carry borrow cleared otherwise. 4-User (U): written read software using LDC, STC, ANDC, ORC, XORC instructions. 3-Negative Flag (N): Stores value most significant (sign bit) data. 2-Zero Flag (Z): indicate zero data, cleared indicate non-zero data. 1-Overflow Flag (V): when arithmetic overflow occurs, cleared otherwise. 0-Carry Flag (C): when carry occurs, cleared otherwise. Used instructions, indicate carry Subtract instructions, indicate borrow Shift rotate instructions, store carry carry flag also used accumulator bit-manipulation instructions. Some instructions leave some flag bits unchanged. action each instruction flag bits, refer Appendix A.1, List Instructions. Operations performed bits LDC, STC, ANDC, ORC, XORC instructions. flags used branching conditions conditional branch (Bcc) instructions. 2.4.4 Initial Register Values
Reset exception handling loads CPU's program counter (PC) from vector table, clears trace sets interrupt mask bits other bits general registers initialized. particular, stack pointer (ER7) initialized. stack pointer should therefore initialized MOV.L instruction executed immediately after reset.
Data Formats
process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), 32-bit (longword) data. Bit-manipulation instructions operate 1-bit data accessing byte operand data. decimal-adjust instructions treat byte data digits 4-bit data. 2.5.1 General Register Data Formats
Figure 2.10 shows data formats general registers.
Data Type General Register Data Format
1-bit data
Don't care
1-bit data
Don't care
4-bit data
Upper digit Lower digit
Don't care
4-bit data
Don't care
Upper digit Lower digit
Byte data
Don't care Don't care
Byte data
Figure 2.10 General Register Data Formats
Data Type
General Register
Data Format
Word data
Word data Longword data
Legend: ERn: General register General register General register RnH: General register RnL: General register MSB: Most significant LSB: Least significant
Figure 2.10 General Register Data Formats (cont)
2.5.2
Memory Data Formats
Figure 2.11 shows data formats memory. access word data longword data memory, word longword data must begin even address. attempt made access word longword data address, address error occurs least significant address regarded access starts preceding address. This also applies instruction fetches.
Data Type Address Data Format
1-bit data Address
Byte data
Address
Word data
Address Address
Longword data
Address Address Address Address
Figure 2.11 Memory Data Formats When (SP) used address register access stack, operand size should word size longword size.
2.6.1
Instruction
Overview
H8S/2000 types instructions. instructions classified function table 2.1. Table
Function Data transfer
Instruction Classification
Instructions POP* PUSH* LDM* STM*
Size
Types
MOVFPE* MOVTPE* Arithmetic operations ADD, SUB, CMP,
ADDX, SUBX, DAA, INC, ADDS, SUBS MULXU, DIVXU, MULXS, DIVXS EXTU, EXTS TAS*
Logic operations Shift manipulation Branch System control
AND, XOR,
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR Bcc* JMP, BSR, JSR,
TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC,
Block data transfer EEPMOV
Total: types Notes: byte size; word size; longword size. POP.W PUSH.W identical MOV.W @SP+, MOV.W @-SP. POP.L PUSH.L identical MOV.L @SP+, MOV.L ERn, @-SP. general name conditional branch instructions. Cannot used H8S/2138 Series H8S/2134 Series. Only register ER0, ER1, ER4, should used when using instruction. Only registers should used when using STM/LDM instruction.
2.6.2
Instructions Addressing Modes
Table indicates combinations instructions addressing modes that H8S/2000 use. Table Combinations Instructions Addressing Modes
Addressing Modes @-ERn/@ERn+
@(d:16,ERn)
@(d:32,ERn)
@(d:8,PC)
@@aa:8
Function
Instruction @ERn
@(d:16,PC)
@aa:16
@aa:24
@aa:32
@aa:8
Data transfer
POP, PUSH LDM* STM* MOVFPE* MOVTPE*
Arithmetic operations
ADD, ADDX, SUBX ADDS, SUBS INC, DAA, MULXU, DIVXU MULXS, DIVXS EXTU, EXTS TAS*
Logic operations
AND,
Shift manipulation Branch Bcc, JMP,
Notes: Cannot used H8S/2138 Series H8S/2134 Series. Only register ER0, ER1, ER4, should used when using instruction. Only registers should used when using STM/LDM instruction.
Addressing Modes @-ERn/@ERn+
@(d:16,ERn)
@(d:32,ERn)
@(d:8,PC)
@@aa:8
Function
Instruction @ERn
@(d:16,PC)
@aa:16
@aa:24
@aa:32
@aa:8
System control
TRAPA SLEEP ANDC, ORC, XORC
Block data transfer
Legend: Byte Word Longword
2.6.3
Table Instructions Classified Function
Table summarizes instructions each functional category. notation used table defined below.
Operation Notation (EAd) (EAs) #IMM disp :8/:16/:24/:32 General register (destination)* General register (source)* General register* General register (32-bit register) Destination operand Source operand Extended control register Condition-code register (negative) flag (zero) flag (overflow) flag (carry) flag Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical Logical Logical exclusive Move (logical complement) 16-, 24-, 32-bit length
Note: General registers include 8-bit registers (R0H R7H, R7L), 16-bit registers E7), 32-bit registers (ER0 ER7).
Table
Type Data transfer
Instructions Classified Function
Instruction Size* B/W/L Function (EAs) (EAd) Moves data between general registers between general register memory, moves immediate data general register. Cannot used H8S/2138 Series H8S/2134 Series. Cannot used H8S/2138 Series H8S/2134 Series. @SP+ Pops general register from stack. POP.W identical MOV.W @SP+, POP.L identical MOV.L @SP+, ERn. PUSH @-SP Pushes general register onto stack. PUSH.W identical MOV.W @-SP. PUSH.L identical MOV.L ERn, @-SP. LDM*
MOVFPE MOVTPE
@SP+ (register list) Pops more general registers from stack. (register list) @-SP Pushes more general registers onto stack.
STM*
Type Arithmetic operations
Instruction
Size* B/W/L
Function #IMM Performs addition subtraction data general registers, immediate data data general register. (Immediate byte data cannot subtracted from byte data general register. SUBX instruction.) #IMM Performs addition subtraction with carry byte data general registers, immediate data data general register. Increments decrements general register (Byte operands incremented decremented only.) Adds subtracts value from data 32-bit register. decimal adjust Decimal-adjusts addition subtraction result general register referring produce 4-bit data. Performs unsigned multiplication data general registers: either bits bits bits bits bits bits. Performs signed multiplication data general registers: either bits bits bits bits bits bits. Performs unsigned division data general registers: either bits bits 8-bit quotient 8-bit remainder bits bits 16-bit quotient 16bit remainder.
ADDX SUBX
B/W/L
ADDS SUBS
MULXU
MULXS
DIVXU
Type Arithmetic operations
Instruction DIVXS
Size*
Function Performs signed division data general registers: either bits bits 8-bit quotient 8-bit remainder bits bits 16-bit quotient 16bit remainder. #IMM Compares data general register with data another general register with immediate data, sets bits according result. Takes two's complement (arithmetic complement) data general register. (zero extension) Extends lower bits 16-bit register word size, lower bits 32-bit register longword size, padding with zeros left. (sign extension) Extends lower bits 16-bit register word size, lower bits 32-bit register longword size, extending sign bit. @ERd (<bit @ERd)* Tests memory contents, sets most significant (bit
B/W/L
B/W/L
EXTU
EXTS
Type Logic operations
Instruction
Size* B/W/L
Function #IMM Performs logical operation general register another general register immediate data. #IMM Performs logical operation general register another general register immediate data. #IMM Performs logical exclusive operation general register another general register immediate data. (Rd) (Rd) Takes one's complement (logical complement) general register contents. (shift) Performs arithmetic shift general register contents. 1-bit 2-bit shift possible. (shift) Performs logical shift general register contents. 1-bit 2-bit shift possible. (rotate) Rotates general register contents. 1-bit 2-bit rotation possible. (rotate) Rotates general register contents through carry flag. 1-bit 2-bit rotation possible.
B/W/L
B/W/L
B/W/L
Shift operations
SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR
B/W/L
B/W/L
B/W/L
B/W/L
Type Bitmanipulation instructions
Instruction BSET
Size*
Function (<bit-No.> <EAd>) Sets specified general register memory operand number specified 3-bit immediate data lower three bits general register. (<bit-No.> <EAd>) Clears specified general register memory operand number specified 3-bit immediate data lower three bits general register. (<bit-No.> <EAd>) (<bit-No.> <EAd>) Inverts specified general register memory operand. number specified 3-bit immediate data lower three bits general register. (<bit-No.> <EAd>) Tests specified general register memory operand sets clears flag accordingly. number specified 3-bit immediate data lower three bits general register. (<bit-No.> <EAd>) ANDs carry flag with specified general register memory operand stores result carry flag. (<bit-No.> <EAd>) ANDs carry flag with inverse specified general register memory operand stores result carry flag. number specified 3-bit immediate data. (<bit-No.> <EAd>) carry flag with specified general register memory operand stores result carry flag. (<bit-No.> <EAd>) carry flag with inverse specified general register memory operand stores result carry flag. number specified 3-bit immediate data.
BCLR
BNOT
BTST
BAND
BIAND
BIOR
Type Bitmanipulation instructions
Instruction BXOR
Size*
Function (<bit-No.> <EAd>) Exclusive-ORs carry flag with specified general register memory operand stores result carry flag. (<bit-No.> <EAd>) Exclusive-ORs carry flag with inverse specified general register memory operand stores result carry flag. number specified 3-bit immediate data. (<bit-No.> <EAd>) Transfers specified general register memory operand carry flag. (<bit-No.> <EAd>) Transfers inverse specified general register memory operand carry flag. number specified 3-bit immediate data. (<bit-No.> <EAd>) Transfers carry flag value specified general register memory operand. (<bit-No.> <EAd>) Transfers inverse carry flag value specified general register memory operand. number specified 3-bit immediate data.
BIXOR
BILD
BIST
Type Branch instructions
Instruction
Size*
Function Branches specified address specified condition true. branching conditions listed below. Mnemonic BRA(BT) BRN(BF) BCC(BHS) BCS(BLO) Description Always (true) Never (false) High same Carry clear (high same) Carry (low) equal Equal Overflow clear Overflow Plus Minus Greater equal Less than Greater than Less equal Condition Always Never CZ=0 CZ=1 NV=0 NV=1
Branches unconditionally specified address. Branches subroutine specified address. Branches subroutine specified address. Returns from subroutine
Type
Instruction
Size*
Function Starts trap-instruction exception handling. Returns from exception-handling routine. Causes transition power-down state. (EAs) CCR, (EAs) Moves contents general register memory immediate data EXR. Although 8-bit registers, word-size transfers performed between them memory. upper bits valid. (EAd), (EAd) Transfers contents general register memory. Although 8-bit registers, word-size transfers performed between them memory. upper bits valid. #IMM CCR, #IMM Logically ANDs contents with immediate data. #IMM CCR, #IMM Logically contents with immediate data. #IMM CCR, #IMM Logically exclusive-ORs contents with immediate data. Only increments program counter.
System control TRAPA instructions SLEEP
ANDC
XORC
Type Block data transfer instructions
Instruction EEPMOV.B
Size*
Function then Repeat @ER5+ @ER6+ R4L-1 Until else next; then Repeat @ER5+ @ER6+ R4-1 Until else next; Block transfer instruction. Transfers number data bytes specified from locations starting address indicated locations starting address indicated ER6. After transfer, next instruction executed.
EEPMOV.W
Notes: Size refers operand size. Byte Word Longword Only register ER0, ER1, ER4, should used when using instruction. Only registers should used when using STM/LDM instruction.
2.6.4
Basic Instruction Formats
instructions consist 2-byte (1-word) units. instruction consists operation field field), register field field), effective address extension field), condition field (cc). Operation Field: Indicates function instruction, addressing mode, operation carried operand. operation field always includes first four bits instruction. Some instructions have operation fields. Register Field: Specifies general register. Address registers specified bits, data registers bits bits. Some instructions have register fields. Some have register field. Effective Address Extension: Eight, bits specifying immediate data, absolute address, displacement. Condition Field: Specifies branching condition instructions. Figure 2.12 shows examples instruction formats.
Operation field only NOP, RTS, etc.
Operation field register fields ADD.B etc.
Operation field, register fields, effective address extension (disp) Operation field, effective address extension, condition field (disp) d:16, MOV.B @(d:16, Rn), etc.
Figure 2.12 Instruction Formats (Examples) 2.6.5 Notes Bit-Manipulation Instructions
BSET, BCLR, BNOT, BST, BIST instructions read byte data, carry manipulation, then write back byte data. Caution therefore required when using these instructions register containing write-only bits, port. BCLR instruction used clear internal register flags this case, relevant flag need read beforehand clear that been interrupt handling routine, etc.
2.7.1
Addressing Modes Effective Address Calculation
Addressing Mode
supports eight addressing modes listed table 2.4. Each instruction uses subset these addressing modes. Arithmetic logic instructions register direct immediate modes. Data transfer instructions addressing modes except program-counter relative memory indirect. Bit-manipulation instructions register direct, register indirect, absolute addressing mode specify operand, register direct (BSET, BCLR, BNOT, BTST instructions) immediate (3-bit) addressing mode specify number operand.
Table
Addressing Modes
Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol @ERn @(d:16,ERn)/@(d:32,ERn) @ERn+ @-ERn @aa:8/@aa:16/@aa:24/@aa:32 #xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @@aa:8
Register Direct-Rn: register field instruction code specifies 16-, 32-bit general register containing operand. specified 8-bit registers. specified 16-bit registers. specified 32-bit registers. Register Indirect-@ERn: register field instruction code specifies address register (ERn) which contains address operand memory. address program instruction address, lower bits valid upper bits assumed (H'00). Register Indirect with Displacement-@(d:16, ERn) @(d:32, ERn): 16-bit 32-bit displacement contained instruction added address register (ERn) specified register field instruction, gives address memory operand. 16-bit displacement sign-extended when added. Register Indirect with Post-Increment Pre-Decrement-@ERn+ @-ERn: Register indirect with post-increment-@ERn+ register field instruction code specifies address register (ERn) which contains address memory operand. After operand accessed, added address register contents stored address register. value added byte access, word access, longword access. word longword access, register value should even. Register indirect with pre-decrement-@-ERn value subtracted from address register (ERn) specified register field instruction code, result becomes address memory operand. result also stored address register. value subtracted byte access, word access, longword access. word longword access, register value should even.
Absolute Address-@aa:8, @aa:16, @aa:24, @aa:32: instruction code contains absolute address memory operand. absolute address bits long (@aa:8), bits long (@aa:16), bits long (@aa:24), bits long (@aa:32). access data, absolute address should bits (@aa:8), bits (@aa:16), bits (@aa:32) long. 8-bit absolute address, upper bits assumed (H'FFFF). 16-bit absolute address upper bits sign extension. 32-bit absolute address access entire address space. 24-bit absolute address (@aa:24) indicates address program instruction. upper bits assumed (H'00). Table indicates accessible absolute address ranges. Table Absolute Address Access Ranges
Normal Mode bits (@aa:8) bits (@aa:16) bits (@aa:32) Program instruction address bits (@aa:24) H'FF00 H'FFFF H'0000 H'FFFF Advanced Mode H'FFFF00 H'FFFFFF H'000000 H'007FFF, H'FF8000 H'FFFFFF H'000000 H'FFFFFF
Absolute Address Data address
Immediate-#xx:8, #xx:16, #xx:32: instruction contains 8-bit (#xx:8), 16-bit (#xx:16), 32-bit (#xx:32) immediate data operand. ADDS, SUBS, INC, instructions contain immediate data implicitly. Some manipulation instructions contain 3-bit immediate data instruction code, specifying number. TRAPA instruction contains 2-bit immediate data instruction code, specifying vector address. Program-Counter Relative-@(d:8, @(d:16, PC): This mode used instructions. 8-bit 16-bit displacement contained instruction sign-extended added 24-bit contents generate branch address. Only lower bits this branch address valid; upper bits assumed (H'00). value which displacement added address first byte next instruction, possible branching range -126 +128 bytes (-63 words) -32766 +32768 bytes (-16383 +16384 words) from branch instruction. resulting value should even number.
Memory Indirect-@@aa:8: This mode used instructions. instruction code contains 8-bit absolute address specifying memory operand. This memory operand contains branch address. upper bits absolute address assumed address range (H'0000 H'00FF normal mode, H'000000 H'0000FF advanced mode). normal mode memory operand word operand branch address bits long. advanced mode memory operand longword operand, first byte which assumed (H'00). Note that first part address range also exception vector area. further details, refer section Exception Handling.
Specified @aa:8
Branch address
Specified @aa:8
Reserved Branch address
Normal Mode
Advanced Mode
Figure 2.13 Branch Address Specification Memory Indirect Mode address specified word longword memory access, branch address, least significant regarded causing data accessed instruction code fetched address preceding specified address. (For further information, section 2.5.2, Memory Data Formats.) 2.7.2 Effective Address Calculation
Table indicates effective addresses calculated each addressing mode. normal mode upper bits effective address ignored order generate 16-bit address.
Table
Effective Address Calculation
Effective Address Calculation Effective Address (EA) Operand general register contents.
Addressing Mode Instruction Format Register direct (Rn)
Register indirect (@ERn)
General register contents Don't care
Register indirect with displacement @(d:16, ERn) @(d:32, ERn)
General register contents disp Sign extension disp Don't care
Register indirect with post-increment pre-decrement Register indirect with post-increment @ERn+
General register contents Don't care
Register indirect with pre-decrement @-ERn
General register contents Operand Size Byte Word Longword Value Added Don't care
Addressing Mode Instruction Format Absolute address
@aa:8
Effective Address Calculation
Effective Address (EA)
H'FFFF
Don't care
@aa:16
Don't care
Sign extension
@aa:24
Don't care
@aa:32
Don't care
Immediate #xx:8/#xx:16/#xx:32
Operand immediate data.
Program-counter relative @(d:8, PC)/@(d:16,
contents
disp
Sign extension
disp
Don't care
Addressing Mode Instruction Format Memory indirect @@aa:8 Normal mode
Effective Address Calculation
Effective Address (EA)
H'000000
Don't care Memory contents
H'00
Advanced mode
H'000000
Memory contents
Don't care
2.8.1
Processing States
Overview
five main processing states: reset state, exception-handling state, program execution state, bus-released state, power-down state. Figure 2.14 shows diagram processing states. Figure 2.15 indicates state transitions.
Reset state on-chip supporting modules have been initialized stopped. Exception-handling state transient state which changes normal processing flow response reset, interrupt, trap instruction. Processing states Program execution state executes program instructions sequence. Bus-released state external been released response request signal from master other than CPU. Sleep mode
Power-down state operation stopped conserve power.*
Software standby mode Hardware standby mode
Note: power-down state also includes medium-speed mode, module stop mode, sub-active mode, sub-sleep mode, watch mode.
Figure 2.14 Processing States
request request
Program execution state request request SLEEP instruction with LSON SSBY
SLEEP instruction with LSON SSBY
Bus-released state exception handling Request exception handling
Sleep mode
Interrupt request Exception-handling state External interrupt high Software standby mode
Reset state*1
STBY high,
Hardware standby mode*2 Power-down state*3
Notes: From state except hardware standby mode, transition reset state occurs whenever goes low. transition also made reset state when watchdog timer overflows. From state, transition hardware standby mode occurs when STBY goes low. power-down state also includes watch mode, subactive mode, subsleep mode, etc. details, refer section Power-Down State.
Figure 2.15 State Transitions 2.8.2 Reset State
When input goes current processing stops enters reset state. interrupts disabled reset state. Reset exception handling starts when signal changes from high. reset state also entered watchdog timer overflow. details, refer section Watchdog Timer.
2.8.3
Exception-Handling State
exception-handling state transient state that occurs when alters normal processing flow reset, interrupt, trap instruction. fetches start address (vector) from exception vector table branches that address. Types Exception Handling Their Priority: Exception handling performed resets, interrupts, trap instructions. Table indicates types exception handling their priority. Trap instruction exception handling always accepted program execution state. Exception handling stack structure depend interrupt control mode SYSCR. Table
Priority High
Exception Handling Types Priority
Type Exception Reset Detection Timing Synchronized with clock Start Exception Handling Exception handling starts immediately after low-to-high transition pin, when watchdog timer overflows. When interrupt requested, exception handling starts current instruction current exception-handling sequence. Exception handling starts when trap (TRAPA) instruction executed.*
Interrupt
instruction execution exception-handling sequence* When TRAPA instruction executed
Trap instruction
Notes: Interrupts detected ANDC, ORC, XORC, instructions, immediately after reset exception handling. Trap instruction exception handling always accepted program execution state.
Reset Exception Handling: After gone reset state been entered, when goes high again, reset exception handling starts. When reset exception handling starts fetches start address (vector) from exception vector table starts program execution from that address. interrupts, including NMI, disabled during reset exception handling after ends. Interrupt Exception Handling Trap Instruction Exception Handling: When interrupt trap-instruction exception handling begins, references stack pointer (ER7) pushes program counter other control registers onto stack. Next, alters settings interrupt mask bits control registers. Then fetches start address (vector) from exception vector table program execution starts from that start address.
Figure 2.16 shows stack after exception handling ends.
Normal mode Advanced mode
CCR* bits)
bits)
Note: Ignored when returning.
Figure 2.16 Stack Structure after Exception Handling (Examples) 2.8.4 Program Execution State
this state executes program instructions sequence. 2.8.5 Bus-Released State
This state which been released response request from master other than CPU. While released, halts except internal operations. There other master addition CPU: data transfer controller (DTC). further details, refer section Controller. 2.8.6 Power-Down State
power-down state includes both modes which stops operating modes which does stop. There five modes which stops operating: sleep mode, software standby mode, hardware standby mode, subsleep mode, watch mode. There also three other power-down modes: medium-speed mode, module stop mode, subactive mode. medium-speed mode, other masters operate medium-speed clock. Module stop mode permits halting operation individual modules, other than CPU. Subactive mode, subsleep mode, watch mode power-down modes that subclock input. details, refer section Power-Down State.
Sleep Mode: transition sleep mode made SLEEP instruction executed while software standby (SSBY) standby control register (SBYCR) LSON low-power control register (LPWRCR) both cleared sleep mode, operations stop immediately after execution SLEEP instruction. contents registers retained. Software Standby Mode: transition software standby mode made SLEEP instruction executed while SSBY SBYCR LSON LPWRCR WDT1 timer control/status register (TCSR) both cleared software standby mode, clock halt operations stop. long specified voltage supplied, contents registers on-chip retained. ports also remain their existing states. Hardware Standby Mode: transition hardware standby mode made when STBY goes low. hardware standby mode, clock halt operations stop. on-chip supporting modules reset, long specified voltage supplied, on-chip contents retained.
2.9.1
Basic Timing
Overview
driven system clock, denoted symbol period from rising edge next referred "state." memory cycle cycle consists one, two, three states. Different methods used access on-chip memory, on-chip supporting modules, external address space. 2.9.2 On-Chip Memory (ROM, RAM)
On-chip memory accessed state. data bits wide, permitting both byte word transfer instruction. Figure 2.17 shows on-chip memory access cycle. Figure 2.18 shows states.
cycle Internal address Internal read signal Internal data Internal write signal Write access Internal data Write data Read data Address
Read access
Figure 2.17 On-Chip Memory Access Cycle
cycle
Address Data
Unchanged High High High High impedance
Figure 2.18 States during On-Chip Memory Access
2.9.3
On-Chip Supporting Module Access Timing
on-chip supporting modules accessed states. data either bits bits wide, depending particular internal register being accessed. Figure 2.19 shows access timing on-chip supporting modules. Figure 2.20 shows states.
cycle
Internal address
Address
Internal read signal Read access Internal data Internal write signal Write access Internal data Write data
Read data
Figure 2.19 On-Chip Supporting Module Access Cycle
cycle
Address
Unchanged
High
High
High
Data
High impedance
Figure 2.20 States during On-Chip Supporting Module Access 2.9.4 External Address Space Access Timing
external address space accessed with 8-bit data width two-state three-state cycle. three-state access, wait states inserted. further details, refer section Controller.
2.10
2.10.1
Usage Note
Instruction
Only register ER0, ER1, ER4, should used when using instruction. instruction generated Hitachi H8/300 series C/C++ compilers. instruction used user-defined intrinsic function, ensure that only register ER0, ER1, ER4, used.
2.10.2
STM/LDM Instruction
used register that saved (STM)/restored (LDM) when using STM/LDM instruction, because stack pointer. Two, three, four registers saved/restored STM/LDM instruction. following ranges specified register list. registers: ER0-ER1, ER2-ER3, ER4-ER5 Three registers: ER0-ER2, ER4-ER6 Four registers: ER0-ER3 STM/LDM instruction including generated Hitachi H8/300 series C/C++compilers.
Section Operating Modes
3.1.1
Overview
Operating Mode Selection
H8S/2138 Series H8S/2134 Series have three operating modes (modes These modes enable selection operating mode enabling/disabling on-chip ROM, setting mode pins (MD1 MD0). Table lists operating modes. Table
Operating Mode
Operating Mode Selection
Operating Mode Normal Advanced On-Chip Disabled Enabled
Description Expanded mode with on-chip disabled Expanded mode with on-chip enabled Single-chip mode
Normal
Expanded mode with on-chip enabled Single-chip mode
CPU's architecture allows Gbytes address space, H8S/2138 Series H8S/2134 Series actually access maximum Mbytes. However, there external address output pins, advanced mode enabled only single-chip mode expanded mode with on-chip enabled when specific area external address space accessed using IOS. external data width bits. Mode externally expanded mode that allows access external memory peripheral devices. With modes operation begins single-chip mode after reset release, transition made external expansion mode setting EXPE MDCR. H8S/2138 Series H8S/2134 Series only used modes These means that mode pins must select these modes. changes inputs mode pins during operation.
3.1.2
Register Configuration
H8S/2138 Series H8S/2134 Series have mode control register (MDCR) that indicates inputs mode pins (MD1 MD0), system control register (SYSCR) control register (BCR) that control operation MCU, serial/timer control register (STCR) that controls operation supporting modules. Table summarizes these registers. Table
Name Mode control register System control register control register Serial/timer control register
Registers
Abbreviation MDCR SYSCR STCR Initial Value Undetermined H'09 H'D7 H'00 Address* H'FFC5 H'FFC4 H'FFC6 H'FFC3
Note: Lower bits address.
3.2.1
Register Descriptions
Mode Control Register (MDCR)
EXPE R/W* MDS1 MDS0
Initial value Read/Write
Note: Determined pins MD0.
MDCR 8-bit read-only register that indicates operating mode setting current operating mode MCU. EXPE initialized coordination with mode states reset hardware standby mode.
7-Expanded Mode Enable (EXPE): Sets expanded mode. mode this fixed cannot modified. modes this initial value read written.
EXPE Description Single chip mode selected Expanded mode selected
Bits 2-Reserved: These bits cannot modified always read Bits 0-Mode Select (MDS1, MDS0): These bits indicate input levels pins (the current operating mode). Bits MDS1 MDS0 correspond MD0. MDS1 MDS0 read-only bits-they cannot written mode (MD1 MD0) input levels latched into these bits when MDCR read. 3.2.2
Initial value Read/Write
System Control Register (SYSCR)
CS2E IOSE INTM1 INTM0 XRST NMIEG RAME
SYSCR 8-bit readable/writable register that performs selection system functions, reset source monitoring, interrupt control mode selection, detected edge selection, supporting module location selection, supporting module register access control, address space control. Only bits described here. detailed description these bits, refer also description relevant modules (host interface, controller, watchdog timer, RAM, etc.). information bits section 5.2.1, System Control Register (SYSCR). SYSCR initialized H'09 reset hardware standby mode. initialized software standby mode. 7-Chip Select Enable (CS2E): Specifies location host interface control (CS2). details, section Host Interface. H8S/2134 series does incorporate host interface, this H8S/2134 series.
6-IOS Enable (IOSE): Controls function AS/IOS expanded mode.
IOSE Description AS/IOS functions address strobe (AS) (Low output when accessing external area) (Initial value)
AS/IOS functions strobe (IOS) (Low output when accessing specified address from H'(FF)F000 H'(FF)FE4F)*
Note: H8S/2138 F-ZTAT A-mask version, address range from H'(FF)F000 H'(FF)F7FF.
3-External Reset (XRST): Indicates reset source. When watchdog timer used, reset generated watchdog timer overflow well external reset input. XRST read-only bit. external reset cleared watchdog timer overflow.
XRST Description reset generated watchdog timer overflow reset generated external reset (Initial value)
1-Host Interface Enable (HIE): This controls access host interface data registers control registers (HICR, IDR1, ODR1, STR1, IDR2, ODR2, STR2), keyboard controller input pull-up control registers (KMIMR KMPCR), 8-bit timer (channel data registers control registers (TCRX/TCRY, TCSRX/TCSRY, TICRR/TCORAY, TICRF/TCORBY, TCNTX/TCNTY, TCORC/TISR, TCORAX, TCORBX), timer connection control registers (TCONRI, TCONRO, TCONRS, SEDGR).
Description areas H'(FF)FFF0 H'(FF)FFF7 H'(FF)FFFC H'(FF)FFFF, access 8-bit timer (channel data registers control registers, timer connection control registers, permitted areas H'(FF)FFF0 H'(FF)FFF7 H'(FF)FFFC H'(FF)FFFF, access host interface data registers control registers, keyboard controller input pull-up control registers, permitted (Initial value)
0-RAM Enable (RAME): Enables disables on-chip RAM. RAME initialized when reset state released. initialized software standby mode.
RAME Description On-chip disabled On-chip enabled (Initial value)
3.2.3
Control Register (BCR)
ICIS1 IOS1 IOS0
ICIS0 BRSTRM BRSTS1 BRSTS0
Initial value Read/Write
8-bit readable/writable register that specifies external memory space access mode, area range when designated strobe. details bits section 6.2.1, Control Register (BCR). initialized H'D7 reset hardware standby mode. Bits 0-IOS Select (IOS1, IOS0): These bits specify addresses which AS/IOS output goes when IOSE
IOS1 IOS0 Description AS/IOS output goes accesses addresses H'(FF)F000 H'(FF)F03F AS/IOS output goes accesses addresses H'(FF)F000 H'(FF)F0FF AS/IOS output goes accesses addresses H'(FF)F000 H'(FF)F3FF AS/IOS output goes accesses addresses H'(FF)F000 H'(FF)FE4F* (Initial value)
Note: H8S/2138 F-ZTAT A-mask version, address range from H'(FF)F000 H'(FF)F7FF.
3.2.4
Serial Timer Control Register (STCR)
IICX1 IICX0 IICE FLSHE ICKS1 ICKS0
Initial value Read/Write
STCR 8-bit readable/writable register that controls register access, operating mode (when on-chip option included), on-chip flash memory control F-ZTAT versions), also selects TCNT input clock. details functions other than register access control, descriptions relevant modules. module controlled STCR used, write corresponding bit. STCR initialized H'00 reset hardware standby mode. 7-Reserved: write this bit. Bits 5-I2C Transfer Select (IICX1, IICX0): These bits control operation interface when on-chip option included. details, section 16.2.7, Serial Timer Control Register (STCR). 4-I2C Master Enable (IICE): Controls access interface data registers control registers (ICCR, ICSR, ICDR/SARX, ICMR/SAR), PWMX data registers control registers (DADRAH/DACR, DADRAL, DADRBH/DACNTH, DADRBL/DACNTL), control registers (SMR, BRR, SCMR).
IICE Description Addresses H'(FF)FF88 H'(FF)FF89, H'(FF)FF8E H'(FF)FF8F, used SCI1 control register access Addresses H'(FF)FFA0 H'(FF)FFA1, H'(FF)FFA6 H'(FF)FFA7, used SCI2 control register access Addresses H'(FF)FFD8 H'(FF)FFD9, H'(FF)FFDE H'(FF)FFDF, used SCI0 control register access Addresses H'(FF)FF88 H'(FF)FF89, H'(FF)FF8E H'(FF)FF8F, used IIC1 data register control register access Addresses H'(FF)FFA0 H'(FF)FFA1, H'(FF)FFA6 H'(FF)FFA7, used PWMX data register control register access Addresses H'(FF)FFD8 H'(FF)FFD9, H'(FF)FFDE H'(FF)FFDF, used IIC0 data register control register access (Initial value)
3-Flash Memory Control Register Enable (FLSHE): Controls access flash memory control registers (FLMCR1, FLMCR2, EBR1, EBR2), power-down mode control registers (SBYCR, LPWRCR, MSTPCRH, MSTPCRL), supporting module control registers (PCSR SYSCR2).
FLSHE Description Addresses H'(FF)FF80 H'(FF)FF87 used power-down mode control register supporting module control register access Addresses H'(FF)FF80 H'(FF)FF87 used flash memory control register access (F-ZTAT version only) (Initial value)
2-Reserved: write this bit. Bits 0-Internal Clock Select (ICKS1, ICKS0): These bits, together with bits CKS2 CKS0 TCR, select clock input TCNT. details, section 12.2.4, Timer Control Register (TCR).
3.3.1
Operating Mode Descriptions
Mode
access 64-kbyte address space normal mode. on-chip disabled. Ports function address bus, port function data bus, part port carries control signals. 3.3.2 Mode
access 16-Mbyte address space advanced mode. on-chip enabled. After reset, single-chip mode set, EXPE MDCR must order external addresses. However, these series have maximum address outputs, external address specified correctly only when strobe function AS/IOS used. When EXPE MDCR ports function input ports after reset. They output addresses setting corresponding bits data direction register (DDR) Port function data bus, part port carries control signals.
3.3.3
Mode
access 64-kbyte address space normal mode. on-chip enabled. After reset, single-chip mode set, EXPE MDCR must order external addresses. When EXPE MDCR ports function input ports after reset. They output addresses setting corresponding bits data direction register (DDR) Port function data bus, part port carries control signals. products with on-chip capacity kbytes more, amount on-chip that used limited kbytes.
Functions Each Operating Mode
functions ports vary depending operating mode. Table shows their functions each operating mode. Table
Port Port Port Port Port Legend: port Address output Data Control signals, clock After reset
Functions Each Mode
Mode P*/C Mode P*/A P*/A P*/D P*/C P*/C P*/C Mode P*/A P*/A P*/D P*/C P*/C P*/C
Memory Each Operating Mode
Figures show memory maps each operating modes. address space kbytes modes (normal modes), Mbytes mode (advanced mode).
on-chip capacity kbytes (H8S/2130), kbytes (H8S/2132 H8S/2137), kbytes (H8S/2133), kbytes (H8S/2134 H8S/2138), products with on-chip capacity kbytes more, amount on-chip that used limited kbytes mode (normal mode). access reserved area addresses modules supported product. Note that normal operation guaranteed when these regions accessed. details, section Controller.
Mode (normal expanded mode with on-chip disabled) Mode 3/EXPE (normal expanded mode with on-chip enabled) Mode 3/EXPE (normal single-chip mode)
H'0000
H'0000
H'0000
External address space
On-chip
On-chip
H'DFFF External address space H'E080 On-chip RAM* H'EFFF
External address space
H'DFFF
H'E080 On-chip RAM* H'EFFF
External address space
H'E080 On-chip H'EFFF H'FE50 H'FEFF Internal registers On-chip H'FF00 (128 bytes) H'FF7F H'FF80 Internal registers H'FFFF
H'FE50 H'FEFF Internal registers On-chip H'FF00 (128 bytes)* H'FF7F H'FF80 Internal registers H'FFFF
H'FE50 H'FEFF Internal registers On-chip H'FF00 (128 bytes)* H'FF7F H'FF80 Internal registers H'FFFF
Note: External addresses accessed clearing RAME SYSCR
Figure H8S/2138 (except F-ZTAT A-mask Version) H8S/2134 Memory Each Operating Mode
Mode 2/EXPE (advanced expanded mode with on-chip enabled) H'000000
Mode 2/EXPE (advanced single-chip mode)
H'000000
On-chip
On-chip
H'01FFFF H'020000 H'FFE080
H'01FFFF External address space*2 H'FFE080 On-chip RAM*1 On-chip H'FFEFFF
External address space*2
H'FFEFFF H'FFFE50 H'FFFEFF Internal registers On-chip H'FFFF00 (128 bytes)*1 H'FFFF7F H'FFFF80 Internal registers H'FFFFFF
H'FFFE50 H'FFFEFF H'FFFF00 H'FFFF7F H'FFFF80 H'FFFFFF
Internal registers
On-chip (128 bytes)
Internal registers
Notes: External addresses accessed clearing RAME SYSCR these models, maximum number external address pins external address only specified correctly area that uses strobe function.
Figure H8S/2138 (except F-ZTAT A-mask Version) H8S/2134 Memory Each Operating Mode (cont)
Mode (normal expanded mode with on-chip disabled)
Mode 3/EXPE (normal expanded mode with on-chip enabled)
Mode 3/EXPE (normal single-chip mode)
H'0000
H'0000
H'0000
External address space
On-chip
On-chip
H'DFFF External address space H'E080 On-chip RAM* H'EFFF
External address space
H'DFFF
H'E080 On-chip RAM* H'EFFF
External address space
H'E080 On-chip H'EFFF
H'F800 Reserved area H'FE4F H'FE50 H'FEFF Internal registers On-chip H'FF00 (128 bytes)* H'FF7F H'FF80 Internal registers H'FFFF
H'F800 Reserved area H'FE4F H'FE50 H'FEFF Internal registers On-chip H'FF00 (128 bytes)* H'FF7F H'FF80 Internal registers H'FFFF
H'FE50 H'FEFF Internal registers On-chip H'FF00 (128 byte
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GDB-80mA - GDB-80mA GDB-80mA Datasheet
GDB-100mA - GDB-100mA GDB-100mA Datasheet
GDB-125mA - GDB-125mA GDB-125mA Datasheet
GDB-160mA - GDB-160mA GDB-160mA Datasheet
GDB-200mA - GDB-200mA GDB-200mA Datasheet
GDB-250mA - GDB-250mA GDB-250mA Datasheet
GDB-315mA - GDB-315mA GDB-315mA Datasheet
GDB-400mA - GDB-400mA GDB-400mA Datasheet
GDB-500mA - GDB-500mA GDB-500mA Datasheet
GDB-630mA - GDB-630mA GDB-630mA Datasheet
GDB-800mA - GDB-800mA GDB-800mA Datasheet
GDB-1A - GDB-1A GDB-1A Datasheet
GDB-2A - GDB-2A GDB-2A Datasheet
GDB-4A - GDB-4A GDB-4A Datasheet
GDB-5A - GDB-5A GDB-5A Datasheet
GDB-8A - GDB-8A GDB-8A Datasheet
GDB-10A - GDB-10A GDB-10A Datasheet
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