IRS2168D(S)PbF ADVANCED BALLAST CONTROL PFC, ballast control
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Data Sheet PD60310
IRS2168D(S)PbF
ADVANCED BALLAST CONTROL
PFC, ballast control half-bridge driver Critical-conduction mode boost-type Programmable over-current protection Programmable half-bridge over-current protection Programmable preheat frequency Programmable preheat time Programmable ignition ramp Programmable frequency Closed-loop ignition current regulation RoHs compliant Fixed internal deadtime Voltage-controlled oscillator (VCO) End-of-life window comparator Internal 65-event current sense up/down fault counter undervoltage reset Lamp removal/auto-restart shutdown Internal bootstrap MOSFET Internal 15.6 Zener clamp diode Micropower startup (250 Latch immunity protection
Description
IRS2168D fully integrated, fully protected ballast control designed drive types fluorescent lamps. IRS2168D based popular IR2166 control with additional improvements increase ballast performance. circuitry operates critical conduction mode provides high regulation. IRS2168D features include programmable preheat frequencies, programmable preheat time, programmable over-current protection, closed-loop half-bridge ignition current regulation, programmable end-of-life protection. Comprehensive protection features such protection from failure lamp strike, filament failures, end-of-life protection, undervoltage reset well automatic restart function, have been included design.
System One-chip ballast control solution Wide range universal input multi-lamp ballasts Ultra Closed-loop ignition regulation reliable lamp ignition End-of-Life window comparator with internal Lamp removal/auto-restart function Fault counter robust noise immunity Brown-out protection reset Internal bootstrap MOSFET
Packages
16-Lead PDIP IRS2168DPbF
16-Lead SOIC IRS2168DSPbF
Application Diagram (Typical Only)
Rectified Line
VBUS1 SUPPLY
VBUS
VBUS
BLOCK LRES BOOT SNUB CRES
VBUS FMINR CCOMP GPFC
IRS2168D
FMIN
COMP
CVCC1
CVCC2
SD/EOL
Rectified Line
Please note that this datasheet contains advanced information that could change before product released production.
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IRS2168D(S)PbF
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage device occur. voltage parameters absolute voltages referenced COM, currents defned positive into lead. thermal resistance power dissipation ratings measured under board mounted still conditions.
Symbol
VPFC IO,MAX VBUS VCPH VCOMP VSD/EOL VVCO ICPH IVCO IFMIN ICOMP ISD/EOL dV/dt
Definition
high-side floating supply voltage high-side floating supply offset voltage high-side floating output voltage low-side output voltage gate driver output voltage Maximum allowable output current (HO, PFC) external power transistor miller effect current (see Note VBUS voltage voltage COMP voltage voltage voltage SD/EOL voltage voltage voltage current current FMIN current COMP current current current SD/EOL current current Allowable offset voltage slew rate Package power dissipation (TJMAX-TA)/RJA Thermal resistance, junction ambient Junction temperature Storage temperature Lead temperature (soldering, seconds) (16-Pin DIP) (16-Pin SOIC) (16-Pin DIP) (16-Pin SOIC)
Min.
-0.3 -0.3 -500
Max.
Units
-0.3
-0.3
V/ns
Note This contains Zener clamp structure between chip which nominal breakdown voltage 15.6 This supply should driven impedance power source greater than VCLAMP specified Electrical Characteristics section.
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IRS2168D(S)PbF
Recommended Operating Conditions
proper operation device should used within recommended conditions.
Symbol
VB-VS ISD/EOL VVCO RFMIN
Definition
High-side floating supply voltage Steady state high-side floating supply offset voltage Supply voltage supply current SD/EOL current current
Min.
VBSUV+ VCCUV+ Note
Max.
VCLAMP VCLAMP
Units
current current voltage FMIN programming resistor Junction temperature
Note Enough current should supplied into keep internal 15.6 Zener clamp diode this regulated voltage,
CLAMP
Electrical Characteristics
VBIAS=14 0.25 CPFC 1000 RFMIN 42.2 N/C, VCPH VVCO VSD/EOL COMP VBUS TA=25 unless otherwise specified.
Symbol
Definition
supply undervoltage positive going threshold supply undervoltage negative going threshold supply undervoltage lockout hysteresis UVLO mode quiescent current quiescent current fault mode
Units
Test Conditions
Supply Characteristics
VCCUV+ VCCUVVUVHYS IQCCUV IQCCFLT 11.5 -12.5 10.5 13.5 11.5 ICCRUN mode supply current -5.5 MODE=FAULT MODE VBUS=4 CSD/EOL=1 time rising from falling from
VCLAMP
Zener clamp voltage
14.6
15.6
16.6
Floating Supply Characteristics
VBSUV+ VBSUVILKVS supply current supply undervoltage positive going threshold supply undervoltage negative going threshold offset supply leakage current -8.0 -0.9 -1.3 10.0 falling from MODE=PREHEAT rising from
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IRS2168D(S)PbF
Electrical Characteristics (cont'd)
VBIAS=14 0.25 CPFC 1000 RFMIN 42.2 N/C, VCPH VVCO VSD/EOL VCOMP VBUS TA=25 unless otherwise specified.
Symbol
Definition
Units
Test Conditions
MODE VVBUS VCOMP=4.0 MODE VVBUS VCOMP=4.0 VBUS=3.5 ICOMP=ICOMPSOURCE-5
Error Amplifier Characteristics
ICOMP, SOURCE COMP error amplifier output current Sourcing COMP error amplifier output current Sinking error amplifier output voltage swing (high state) error amplifier output voltage swing (low state) error amplifier output voltage fault mode ICOMP, SINK
VCOMPOH
12.0
12.5
13.0
VCOMPOL VCOMPFLT
VBUS=5.0 ICOMP=ICOMPSINK+5 VBUS=4.0
Control Characteristics
VVBUSREG VVBUSOV VVBUSOVVZX VZXHYS VZXclamp tBLANK VBUS internal reference voltage VBUS overvoltage comparator threshold VBUS overvoltage fault reset threshold threshold voltage comparator hysterisis clamp voltage (high state) current-sensing blank time watch-dog pulse interval -150 4.15 -500 VBUS=4.0 VCOMP=4.0 VCOMP VCOMP
Protection Circuitry Characteristics
VVBUSUVVOCTH+ VBUS undervoltage reset threshold over-current sense threshold VBUS=VCOMP=4.0
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IRS2168D(S)PbF
Electrical Characteristics (cont'd)
VBIAS=14 0.25 CPFC 1000 RFMIN 42.2 N/C, VCPH VVCO VSD/EOL VCOMP VBUS TA=25 unless otherwise specified.
Symbol
Definition
Units Test Conditions
Ballast Control Oscillator Characteristics fOSC, fOSC,
VFMIN Half-bridge oscillator frequency Half-bridge oscillator preheat frequency Oscillator duty cycle output deadtime output deadtime FMIN voltage 42.5 -1.1 44.5 46.5 -2.1 14.0 MODE 42.2 MODE PREHEAT
Ballast Control Preheat, Ignition Mode Characteristics
VCPHEOP+ VCPHSOIVVCOPH VVCOIGN IVCOIGN VCPHRUN+ VVCORUN preheat rising threshold voltage start ignition falling threshold voltage preheat mode voltage ignition mode voltage ignition regulation discharge current mode rising threshold voltage mode voltage -9.3 (Open Drain) -MODE PREHEAT MODE IGNITION, VCSTH+ MODE IGNITION, VVCO VCSTH+ MODE IGNITION -MODE
(Open Drain)
Ballast Control Protection Circuitry Characteristics
VCSTH+ over-current sense threshold fault counter number events rising non-latched shutdown threshold voltage falling reset threshold voltage internal bias voltage rising latched shutdown threshold voltage falling latched shutdown threshold voltage 2.85 -1.2 3.15 IEOL, SINK VCPHFLT VVCOFLT VFMINFLT output sinking current fault mode voltage fault mode voltage FMIN fault mode voltage MODE FAULT MODE MODE MODE PREHEAT VEOL MODE PREHEAT VEOL -MODE PREHEAT
nEVENTS
VSDTH+ VSDTHVEOLBIAS VEOLTH+ VEOLTH-
IEOL, SOURCE output sourcing current
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IRS2168D(S)PbF
Electrical Characteristics (cont'd)
VBIAS=14 0.25 CPFC 1000 RFMIN 42.2 N/C, VCPH VVCO VSD/EOL VCOMP VBUS TA=25 unless otherwise specified.
Gate Driver Output Characteristics (HO, pins)
I0Low-level output voltage High-level output voltage Turn-on rise time Turn-off fall time Source current Sink current -COM -220
Bootstrap Characteristics
VB/ON IB/CAP IB/10V when bootstrap source current when source current when 13.0 13.4 -VB=10 CBS=0.1
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IRS2168D(S)PbF
Schematic Block Diagram
15.6V IFMIN Bootstrap Control Oscillator Driver Deadtime Logic HighSide Driver
Ignition Regulation
FMIN
IFMIN= 2.0V RRFMIN Event Fault Counter UVLO Fault Logic
LowSide Driver
Mode Logic
1.2V
+/-10uA
1.2V 200ns Blank Time
SD/EOL
VBUS
Gain
4.0V
OTA1
4.3V
Ballast Control Control
COMP
VBUS Under-Voltage Reset 400us Watchdog Timer
6.5V
Please Note: values shown block diagram typical values only.
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IRS2168D(S)PbF
State Diagram
Power Turned
UVLO Mode
/2-Bridge IQCCUV
10.5V (VCCUV-) (VCC Fault Power Down)
SD/EOL (VSDTH+) (Lamp Removal) 10.5 (VCCUV-) (Power Turned Off)
SD/EOL (VSDTH+) (Lamp Fault Lamp Removal)
12.5 (VCCUV+) SD/EOL (VSDTH-)
FAULT Mode
Fault Latch /2-Bridge IQCCFLT 15.6V
PREHEAT Mode
/2-Bridge oscillating RFMIN charging through RCPH Enabled (High Gain) Fault Counter Enabled (VCPHEOP+) (End PREHEAT Mode) discharged CPHSOICPH (VCPHSOI-) (Start IGNITION Mode)
(VCSTH+) events (nEVENTS)
CS<1.2 (VCSTH+) Regulation discharged slightly with current sink (IVCOIGN) CS>1.2 (VCSTH-) (VCSTH+) events (nEVENTS) SD/EOL (VEOLTH-) SD/EOL (VEOLTH+)
IGNITION Mode
charging through RCPH ramping through ramps fRUN High Gain Mode Fault Counter Disabled Ignition Regulation Enabled (VCPHRUN) (End IGNITION Mode)
Mode
1/2-Bridge Oscillating @fRUN Thresholds Enabled Gain Mode VBUS Threshold Enabled Fault Counter Enabled Ignition Regulation Disabled VBUS (VBUSUV-)
Discharge UVLO
values typical. Please refer application diagram page
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IRS2168D(S)PbF
Lead Assignments Definitions
VBUS
Symbol
VBUS FMIN COMP SD/EOL
Description
sensing input Preheat timing input Voltage controlled oscillator/ignition ramp input Oscillator minimum frequency setting error amplifier compensation zero-crossing detection gate driver output current sensing input Shutdown/end life sensing input Half-Bridge current sensing input Low-side gate driver output power signal ground Logic low-side gate driver supply High-side gate driver floating supply High voltage floating return High-side gate driver output
FMIN
IRS2168D
COMP
SD/EOL
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IRS2168D(S)PbF
Timing Diagrams Ballast Section
15.6V UVLO+ UVLO-
(2/3)*VCC (1/3)*VCC
tRAMP=RPH*CVCO
frun (RFMIN)
FREQ
(RFMIN//RPH)
1.25V
FAULT
UVLO
UVLO
1.25V
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IRS2168D(S)PbF
Ballast Section Functional Description Undervoltage Lockout Mode (UVLO)
undervoltage lockout mode (UVLO) defined state when below turn-on threshold identify different modes refer State Diagram shown page this document. IRS2168D undervoltage lockout designed maintain ultra supply current (IQCCUV), guarantee fully functional before high- low-side output drivers activated. Figure shows efficient supply voltage using micro-power start-up current IRS2168D together with snubber charge pump from half-bridge output (RVCC, CVCC1, CVCC2, CSNUB, DCP1 DCP2).
VRECT VBUS RVCC
BSFET BSFET CONTROL
CVCC DISCHARGE VUVLO+
VHYST INTERNAL ZENER CLAMP VOLTAGE
VUVLO-
DISCHARGE TIME
CHARGE PUMP OUTPUT RVCC CVCC1,2 TIME CONSTANT
Figure supply voltage
Load
VCC1 VCC2 DCP2
SNUB
IRS2168D VBUS(-) Load Return DCP1
Figure Start-up supply circuitry
capacitors (CVCC1 CVCC2) charged current through supply resistor (RVCC) minus start-up current drawn This resistor chosen desired line input voltage turn-on threshold ballast. When voltage exceeds start-up threshold (VCCUV+) below (VSDTH-), turns begins oscillate. capacitors begin discharge increase operating current (Fig. high-side supply voltage, VB-VS, begins increase capacitor charged through internal bootstrap MOSFET during ontime each switching cycle. When VB-VS voltage exceeds high-side start-up threshold (VBSUV+), then begins oscillate. This take several cycles charge VB-VS above VBSUV+ RDSon internal bootstrap MOSFET.
When both oscillating, external MOSFETs (MHS MLS) turned with duty cycle non-overlapping deadtime (td). half-bridge output (pin begins switch between voltage COM. During deadtime between turn-off turn-on half-bridge output voltage transitions from voltage dV/dt rate determined snubber capacitor (CSNUB). snubber capacitor charges, current will flow through charge pump diode (DCP2) VCC. After several switching cycles halfbridge output, charge pump internal 15.6 Zener clamp take over supply voltage. Capacitor CVCC2 supplies current during discharge time should large enough such that does decrease below UVLO- before charge pump takes over. Capacitor CVCC1 required noise filtering must placed close possible directly between COM, should lower than Resistors recommended limiting high currents that flow from charge pump during hard-switching half-bridge during lamp ignition. internal bootstrap MOSFET supply capacitor (CBS) comprise supply voltage high side driver circuitry. During UVLO mode, high- low-side driver outputs both low, internal oscillator disabled, connected internally resetting preheat time.
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IRS2168D(S)PbF
Preheat Mode (PH)
IRS2168D enters preheat mode when exceeds UVLO positive-going threshold (VCCUV+). internal MOSFET that connects turned external resistor (Fig. begins charge external preheat timing capacitor (CPH). begin oscillate higher soft-start frequency ramp down quickly preheat frequency. connected through internal resistor disconnected from COM. equivalent resistance FMIN increases from parallel combination (RPH//RFMIN) RFMIN rate programmed external capacitor (CVCO) resistor RPH. This causes operating frequency ramp down smoothly from preheat frequency through ignition frequency final frequency. During this ignition ramp, frequency sweeps through resonance frequency lamp output stage ignite lamp.
VCPH
VBUS
2/3*VCC
MODE HalfBridge Driver
1/3*VCC
HalfBridge Output ILOAD
RCPH
VVCO
tRAMP CVCO
FMIN
FMIN
OSC.
IRS2168D
PREHEAT
IGNITION
Load Return VBUS
Figure timing diagram
VBUS
Figure Preheat circuitry
MOSFET preheat frequency determined equivalent resistance FMIN formed parallel combination resistors RFMIN RPH. frequency remains preheat frequency until voltage exceeds approvixmately 2/3*VCC (VCPHEOP+) enters Ignition Mode. During preheat mode, over-current protection 65-cycle (nEVENTS) consecutive over-current fault counter both enabled. circuit working high-gain mode (see section) keeps voltage regulated constant level.
VBUS
MODE HalfBridge Driver
HalfBridge Output ILOAD
FMIN
FMIN
OSC.
IGN. REG.
1.25V
IRS2168D
Load Return
Ignition Mode (IGN)
IRS2168D ignition mode defined second time charges from 1/3*VCC (VCPHSOI-) 2/3*VCC (VCPHRUN+). When voltage exceeds 2/3*VCC (VCPHRUN+) first time, discharged quickly through internal MOSFET down 1/3*VCC (VCPHSOI-) (see Figs. internal MOSFET turns voltage begins increase again. internal MOSFET turn
Figure Ignition circuitry
over-current threshold will protect ballast against non-strike open-filament lamp fault condition. voltage defined lower half-bridge MOSFET current flowing through external current sensing resistor RCS. This resistor programs maximum peak ignition current (and therefore peak
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IRS2168D(S)PbF
ignition voltage) ballast output stage. Should this voltage exceed internal threshold (VCSTH+), ignition regulation circuit controls voltage increase frequency slightly (see Fig. This cycle-by-cycle feedback from will adjust frequency each cycle limit amplitude current entire duration ignition mode.
VOUT
VCPH
1.25V
tRAMP
tIGN
Figure Ballast output voltage during preheat ignition with deactivated lamp, time span 100ms
VVCO
VOUT
Figure Ignition regulation timing diagram
When exceeds 2/3*VCC (VCPHRUN+) second time, enters mode fault counter becomes enabled. ignition regulation disabled mode will enter fault mode after (nEVENTS) consecutive over-current faults gate driver outputs will latched low. output voltage ballast will increase during ignition ramp tRAMP because frequency ramp down from preheat frequency ignition frequency will constant during ignition because ignition regulation circuit will regulate amplitude current entire duration ignition time tIGN (Figs. During ignition mode, circuit working highgain mode keeps voltage regulated constant level. high-gain mode necessary prevent from decreasing during lamp ignition ignition regulation. Also during ignition mode, SD/EOL fault disabled.
VCPH
tIGN tRAMP
Figure Ballast output voltage during preheat ignition with deactivated lamp, time span 50ms
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IRS2168D(S)PbF
Mode (RUN)
Once exceeded 2/3*VCC (VCPHRUN+) second time, enters mode. continues charge VCC. operating frequency minimum frequency (after ignition ramp) programmed external resistor (RFMIN) FMIN pin. Should hard-switching occur half-bridge time (open-filament, lamp removal, etc.), voltage across current sensing resistor (RCS) will exceed internal threshold (VCSTH+) fault counter will begin counting (see Fig. Should number consecutive over-current faults exceed (nEVENTS), will enter fault mode gate driver outputs will latched low. During mode, end-of-life (EOL) window comparator undervoltage reset both enabled.
SD/EOL Fault Mode
Should voltage SD/EOL exceed (VEOLTH+) decrease below (VEOLTH-) during mode, end-of-life (EOL) fault condition occurred enters fault mode. gate driver outputs latched `low' state. discharged resetting preheat time discharged resetting frequency. exit fault mode, decreased below VCCUV(ballast power off) increased above (VSDTH+) (lamp removal). Either these will force enter UVLO mode (see State Diagram, page Once above VCCUV+ (ballast power pulled above (VSDTH+) back below (VSDTH-) (lamp re-insertion), will enter preheat mode begin oscillating again. current sense function will force enter fault mode only after voltage been greater than (VCSTH+) (nEVENTS) consecutive cycles voltage AND-ed with (see Fig. will work with pulses that occur during on-time over-current faults consecutive, then internal fault counter will count back down each cycle when there fault. Should over-current fault occur only cycles then occur again, counter will eventually reset zero. over-current fault counter enabled during preheat modes disabled during ignition mode.
Cycles
Undervoltage Reset
Should decrease during brown-out line condition over-load condition, resonant output stage lamp shift near below resonance. This produce hard switching half- bridge that damage half-bridge switches, decrease lamp extinguish. protect against this, VBUS includes undervoltage reset threshold VBUSUV-. When mode voltage VBUS decreases below (VBUSUV), will discharged through internal MOSFET down VCCUV- threshold gate driver outputs will latched low. proper ballast design, designer should over-current limit section such that does drop until line input voltage falls below minimum rated input voltage ballast (see section). When over-current limit correctly set, voltage will start decrease when over-current reached during low-line conditions. voltage measured VBUS will decrease below internal threshold VBUSUVand ballast will turn cleanly. pull-up resistor (RVCC) will then turn ballast again when input line voltage increases high enough again where exceeds VCCUV+. RVCC should turn ballast minimum specified ballast input voltage over-current should somewhere below this level. This hysteresis will result clean turn-on turnoff ballast.
1.25V
Preheat Mode
Fault Mode
Figure Fault counter timing diagram
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IRS2168D(S)PbF
Section Functional Description
most electronic ballasts necessary have circuit pure resistive load input line voltage. degree which circuit matches pure resistor measured phase shift between input voltage input current well shape input current waveform matches shape sinusoidal input voltage. cosine phase angle between input voltage input current defined power factor (PF), well shape input current waveform matches shape input voltage determined total harmonic distortion (THD). power factor (maximum) corresponds zero phase shift represents pure sinusoidal waveform distortion). this reason desirable have high THD. achieve this, IRS2168D includes active power factor correction (PFC) circuit. control method implemented IRS2168D boost-type converter (Fig. running criticalconduction mode (CCM). This means that during each switching cycle MOSFET, circuit waits until inductor current discharges zero before turning MOSFET again. MOSFET turned much higher frequency (>10 kHz) than line input frequency Hz).
LPFC DPFC
Figure Sinusoidal line input voltage (solid line), triangular Inductor current smoothed sinusoidal line input current (dashed line) over half-cycle line input voltage
When line input voltage (near zero crossing), inductor current will charge small amount discharge time will fast resulting high switching frequency. When input line voltage high (near peak), inductor current will charge higher amount discharge time will longer giving lower switching frequency. control circuit IRS2168D (Fig. includes five control pins: VBUS, COMP, VBUS measures voltage external resistor voltage divider. COMP programs on-time MPFC speed feedback loop with external capacitor. detects when inductor current discharges zero each switching cycle using secondary winding from inductor. low-side gate driver output external MOSFET, MPFC. senses current flowing through MPFC performs cycle-by-cycle over-current protection.
LPFC
MPFC CBUS
DFPC
Figure Boost converter circuit
RVBUS1
RVBUS2
When switch MPFC turned inductor LPFC connected between rectified line input causing current LPFC charge linearly. When MPFC turned off, LPFC connected between rectified line input capacitor CBUS (through diode DPFC) stored current LPFC flows into CBUS. MPFC turned high frequency voltage CBUS charges specified voltage. feedback loop IRS2168D regulates this voltage fixed value continuously monitoring voltage adjusting on-time MPFC accordingly. increasing on-time decreased, decreasing on-time increased. This negative feedback control performed with slow loop speed loop gain such that average inductor current smoothly follows low-frequency line input voltage high power factor THD. on-time MPFC therefore appears fixed (with additional modulation discussed later) over several cycles line voltage. With fixed on-time, off-time determined inductor current discharging zero, result system where switching frequency free-running constantly changing from high frequency near zero crossing input line voltage, lower frequency peaks (Fig. 11).
VBUS
Control
COMP
CBUS RPFC MPFC
RVBUS CCOMP
Figure IRS2168D simplified control circuit
VBUS regulated against fixed internal reference voltage regulating voltage (Fig. 13). feedback loop performed operational transconductance amplifier (OTA) that sinks sources current external capacitor COMP pin. resulting voltage COMP sets threshold charging internal timing capacitor (C1, Figure therefore programs on-time MPFC. During preheat ignition modes ballast section, gain high level raise level quickly minimize transient that occur during ignition. During mode, gain then decreased lower level necessary slower
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IRS2168D(S)PbF
loop speed achieving high power factor THD.
On-time Modulation Circuit
fixed on-time MPFC over entire cycle line input voltage produces peak inductor current which naturally follows sinusoidal shape line input voltage. smoothed averaged line input current phase with line input voltage high power factor total harmonic distortion (THD), well individual higher harmonics, current still high. This mostly cross-over distortion line current near zero-crossings line input voltage. achieve harmonics that acceptable international standard organizations general market requirements, additional on-time modulation circuit been added control. This circuit dynamically increases on-time MPFC line input voltage nears zero-crossings (Fig. 15). This causes peak LPFC current, therefore smoothed line input current, increase slightly higher near zerocrossings line input voltage. This reduces amount cross-over distortion line input current which reduces higher harmonics levels.
Mode Signal
Fault Mode Signal
VBUS
GAIN 4.0V OTA1 4.3V COMP4
COMP
COMP2 Discharge UVLOC1
COMP5
WATCH TIMER
3.0V
1.2V
5.1V 2.0V
COMP3
Figure IRS2168D detailed control circuit
off-time MPFC determined time takes LPFC current discharge zero. zero current level detected secondary winding LPFC that connected through external current limiting resistor RZX. positive-going edge exceeding internal threshold (VZXTH+) signals beginning off-time. negative-going edge falling below (VZXTH+ VZXHYS) will occur when LPFC current discharges zero which signals off-time MPFC turned again (Fig. 14). cycle repeats itself indefinitely until section disabled fault detected ballast section (Fault Mode), over-voltage undervoltage condition bus, negative transition voltage does occur. Should negative edge occur, MPFC will remain until watch-dog timer forces turn-on MPFC on-time duration programmed voltage COMP pin. watch-dog pulses occur every (tWD) indefinitely until correct positive- negative-going signal detected normal operation resumed. Should exceed (VOCTH+) over-current threshold during on-time, output will turn off. circuit will then wait negative-going transition forced turn-on from watch-dog timer turn output again.
ILPFC
near peak region rectified line
near zero-crossing region rectified line
Figure On-time modulation circuit timing diagram
Over-voltage Protection
Should over-voltage occur VBUS exceeds internal threshold (VBUSOV+), output disabled (set logic `low'). When decreases again VBUS decreases below internal 4.15 threshold (VBUSOV-), watch-dog pulse forced normal operation resumed.
ILPFC
Undervoltage Reset
1.2V
Figure Inductor current, pin, timing diagram
When input line voltage decreases, on-time MPFC increases keep constant. ontime will continue increase line voltage continues decrease until exceeds internal over-current threshold (VOCTH+). this time, on-time longer increase longer supply enough current keep fixed given load power. This will cause begin decrease. decreasing will cause VBUS decrease below internal threshold (VBUSUV-) (Fig. 12).
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IRS2168D(S)PbF
When this occurs, discharged internally UVLO. IRS2168D enters UVLO mode both ballast sections disabled. start-up supply resistor VCC, together with micro-power start-up current, should such that ballast turns line input voltage above level which begins drop. current-sensing resistor sets maximum current therefore sets maximum on-time MPFC. This prevents saturation inductor programs minimum low-line input voltage ballast. micro-power supply resistor current-sensing resistor program input line voltage thresholds ballast. With these thresholds correctly set, ballast will turn undervoltage threshold (VBUSUV-) VBUS pin, again higher voltage (hysterisis) supply resistor VCC.
Step Program Preheat Time Ignition Time preheat time defined time takes external capacitor charge VCPHEOP+. external resistor (RCPH) connected charges capacitor CPH. preheat time therefore given
RCPH
RCPH
ignition time defined time takes external capacitor charge second time from VCPHSOI- VCPHRUN. ignition time therefore given
III. Ballast Design Equations
Note: results from following design equations differ slightly from actual measurements tolerances, component tolerances, oscillator over- under-shoot internal comparator response time. Step Program Frequency frequency programmed with timing resistor RFMIN FMIN pin. graph Fig. (RFMIN Frequency) select RFMIN value desired frequency.
Frequency (kHz) RFMIN (kW)
Step Program Ignition Ramp Time
ignition ramp time defined time takes external capacitor charge external timing resistor (RPH) connected FMIN charges capacitor CVCO. ignition ramp time therefore given
RAMP CVCO
CVCO
tRAMP
Step Program Maximum Ignition Current maximum ignition current programmed with external resistor internal threshold (VCSTH+). This threshold determines over-current limit ballast, which will reached when frequency ramps down towards resonance during ignition lamp does ignite. maximum ignition current given
Figure fOSC RFMIN
Step Program Preheat Frequency preheat frequency programmed with timing resistors RFMIN RPH. timing resistors connected parallel duration preheat time. graph Fig. (RFMIN Frequency) select REQUIV value desired preheat frequency. Then given
(peak)
RFMIN REQUIV RFMIN REQUIV
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IRS2168D(S)PbF
Design Equations
Step1: Calculate inductor value:
LPFC
(VBUS VACRMS VACRMS POUT
where,
VBUS
POUT
voltage Nominal input voltage efficiency (typically 0.95) Ballast output power
Step Calculate peak inductor current:
POUT
(peak)
where,
Minimum input voltage
Note: inductor must saturate over specified ballast operating temperature range. Proper core sizing air-gapping should considered inductor design.
Step Calculate over-current resistor value:
Step Calculate start-up resistor RVCC value:
RVCC
IQCCUV
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IRS2168D(S)PbF
LOADED TAPE FEED DIRECTION
NOTE CONTROLLING ENSION
CARRIER TAPE DIMENSION Metric Code 7.90 8.10 3.90 4.10 15.70 16.30 7.40 7.60 6.40 6.60 10.20 10.40 1.50 1.50 1.60
16SOICN Imperial 0.311 0.318 0.153 0.161 0.618 0.641 0.291 0.299 0.252 0.260 0.402 0.409 0.059 0.059 0.062
REEL DIMENSIONS 16SOICN Metric Imperial Code 329.60 330.25 12.976 13.001 20.95 21.45 0.824 0.844 12.80 13.20 0.503 0.519 1.95 2.45 0.767 0.096 98.00 102.00 3.858 4.015 22.40 0.881 18.50 21.10 0.728 0.830 16.40 18.40 0.645 0.724
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IRS2168D(S)PbF
ORDER INFORMATION
16-Lead PDIP IRS2168DPbF 16-Lead SOIC IRS2168DSPbF 16-Lead SOIC Tape Reel IRS2168DSTRPbF
SOIC-16 MSL3 qualified. This product been designed qualified industrial level. Qualification standards found www.irf.com <http://www.irf.com> WORLD HEADQUARTERS: Kansas St., Segundo, California 90245, Tel: (310) 252-7105 Data specifications subject change without notice. 1/26/2007
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