IRS2166D(S)PbF BALLAST CONTROL PFC, ballast control half-bri
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Data Sheet PD60292
IRS2166D(S)PbF
BALLAST CONTROL
PFC, ballast control half-bridge driver Critical-conduction mode boost-type Programmable half-bridge over-current protection Programmable preheat frequency Programmable deadtime Programmable preheat time Programmable frequency RoHS compliant End-of-life window comparator Internal up/down current-sense fault counter undervoltage reset Lamp removal/auto-restart shutdown Internal bootstrap MOSFET Internal 15.6 zener clamp diode Micropower startup (250 Latch immunity protection
Description
IRS2166D fully integrated, fully protected ballast control designed drive types fluorescent lamps. IRS2166D based popular IR2166 control with additional improvements increase ballast performance. circuitry operates critical conduction mode provides high THD, regulation. IRS2166D features include programmable preheat frequencies, programmable preheat time, programmable end-of-life protection. Comprehensive protection features such protection from failure lamp strike, filament failures, end-of-life protection, undervoltage reset well automatic restart function, have been included design.
System Improved VBUS regulation voltage tolerance Increased shutdown voltage threshold hysteresis Changed internal bias +/-10 Internal bootstrap MOSFET
Packages
16-Lead PDIP IRS2166DPbF
16-Lead SOIC IRS2166DSPbF
Application Diagram (Typical Only)
LPFC DPFC RBUS
RVDC CVDC CBUS VBUS CVCC2 RLIM CBOOT
RSUPPLY
LRES
IRS2166D
CSNUB DCP2
REOL1 CRES REOL2
CVCC1
CCOMP COMP
DCP1
REOL3
SD/EOL
DCOMP
BALLAST CEOL CSD1 CSD2
REOL4
MPFC
RPFC
Note: Thick traces represent high-frequency, high-current paths. Lead lengths should minimized power grounds should separated avoid high-frequency noise problems.
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IRS2166D(S)PbF
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage device occur. voltage parameters absolute voltages referenced COM, currents defined positive into lead. thermal resistance power dissipation ratings measured under board mounted still conditions.
Symbol
VPFC IO,MAX VBUS VCPH VRPH IRPH ICOMP VSD/EOL ISD/EOL dV/dt
Definition
High-side floating supply voltage High-side floating supply offset voltage High-side floating output voltage Low-side output voltage gate driver output voltage Maximum allowable output current (HO, PFC) external power transistor miller effect VBUS voltage voltage voltage voltage current current voltage current current current (see Note SD/EOL voltage SD/EOL current voltage current Allowable offset voltage slew rate Package power dissipation (TJMAX-TA)/RJA Thermal resistance, junction ambient Junction temperature Storage temperature (16-Pin DIP) (16-Pin SOIC) (16-Pin DIP) (16-Pin SOIC)
Min.
-0.3 -0.3 -0.3 -500 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3
Max.
Units
V/ns
Lead temperature (soldering, seconds) -300 Note This contains zener clamp structure between chip which nominal breakdown voltage 15.6 This supply should driven impedance power source greater than VCLAMP specified electrical characteristics section.
Recommended Operating Conditions
proper operation device should used within recommended conditions.
Symbol
VB-VS ISD/EOL
Definition
High side floating supply voltage Steady state high-side floating supply offset voltage Supply voltage supply current (see Note capacitance SD/EOL current current current
Min.
VBSUV+ VCCUV+ Note
Max.
VCLAMP VCLAMP
Units
Junction temperature Note Enough current should supplied into keep internal 15.6 zener clamp diode this regulating voltage, VCLAMP.
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IRS2166D(S)PbF
Electrical Characteristics
VBIAS=14 0.25 39.2 CPFC 1000 unless otherwise specified. state diagram MODE.
Symbol
Supply Characteristics VCCUV+ VCCUVVUVHYS IQCCUV IQCC IQCCFLT ICC,RUN VCLAMP IQBS0 IQBS1 VBSUV+ VBSUVILKVS
Definition
supply undervoltage positive going threshold supply undervoltage negative going threshold supply undervoltage lockout hysteresis UVLO mode quiescent current Quiescent supply current Fault quiescent supply current current frequency zener clamp voltage Quiescent supply current Quiescent supply current supply undervoltage positive going threshold supply undervoltage negative going threshold offset supply leakage current
11.5 -14.6 -8.0
12.5 10.5 15.6
13.5 11.5 -16.6 10.0
Units
Test Conditions
rising from
falling from MODE FAULT MODE=RUN COMP=2 toff,PFC=2 rising from falling from
Floating Supply Characteristics
MODE VVBUS MODE VVBUS
Error Amplifier Characteristics ICOMP,SOURCE error amplifier output current sourcing ICOMP,SINK VCOMPOH VCOMPOL error amplifier output current sinking error amplifier output voltage swing (high state) error amplifier output voltage swing (low state) VBUS internal reference voltage (guaranteed design) VBUS over-voltage comparator positive going threshold VBUS over-voltage comparator negative going hysteresis positve edge triggered threshold voltage comparator hysterisis clamp voltage (high state) watch-dog pulse interval 12.0 12.5 13.0
Control Characteristics VVBUSREG VVBUSOV+ VVBUSOVVZX VZXHYS VZXclamp 4.15 CT=COM VCOMP CT=COM CT=COM VCOMP=4.0
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IRS2166D(S)PbF
Electrical Characteristics (cont'd)
VBIAS=14 0.25 VCPH=VSD/EOL VCOMP= VCS= VBUS =0.0 39.2 CPFC 1000 TA=25 unless otherwise specified. state diagram MODE.
Symbol
Definition
-13.2 -0.7 -2.6 -1.075 -1.8 -2.7
13.7 10.8 12.0 1.20
-220 -1.5 -4.6 -1.325 -2.2 -3.3
Units
Test Conditions
CT=COM
Protection Circuitry Characteristics VVBUSUVVBUS undervoltage reset threshold Gate Driver Output Characteristics (HO, pins) I0VB,ON IB,CAP IB,10V fRUN td,LO td,HO VCT+ VCTVCPHEOP VCPHRUN IRPHLK ICPH VCPHFLT VCSTH+ nEVENTS VSDTH+ VSDTHVSD,delay VEOLBIAS IEOL,SRC IEOL,SNK VEOLTH+ VEOLTHVEOL,delay VCTFLT VCPHFLT Low-level output voltage, High-level output voltage, Turn-on rise time Turn-off fall time Source current Sink current when bootstrap source current when source current when Preheat half-bridge oscillator frequency half-bridge oscillator frequency Oscillator duty cycle output deadtime output deadtime rising threshold voltage falling threshold voltage preheat threshold voltage mode threshold voltage leakage current charging current voltage fault mode over-current sense threshold fault counter number events rising non-latched shutdown threshold falling reset threshold voltage Delay from VSDTH+ until goes bias voltage internal source current internal sink current rising latched shutdown threshold (active during MODE) falling latched shutdown threshold (active during MODE) Delay from VEOLTH+ until goes fault mode voltage fault mode voltage
Bootstrap Characteristics CBS=0.1 VB=10 MODE=PREHEAT MODE=RUN, CPH=13
Ballast Control Oscillator Characteristics
Ballast Control Preheat Characteristics CT=COM, IRPH<2 VBUS=VCC, CT=COM, VSDEOL=3.5 MODE=RUN CPH=5 MODE FAULT
Ballast Control Protection Circuitry Characteristics MODE=PREHEAT, VBUS=0 VEOLBIAS MODE=RUN, CT=COM VBUS=4.0 CPH=13 MODE=RUN, CT=COM, CPH=13 MODE=FAULT CT=COM
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IRS2166D(S)PbF
Schematic Block Diagram
15.6
Soft Start Driver Logic
Bootstrap Control HighSide Driver
3.0K
Fault Counter LowSide Driver Fault Logic
1.25
Ballast
UVLO
SD/EO
Gain
Watch Timer
Please Note: values shown block diagram typical values only
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IRS2166D(S)PbF
State Diagram
Power Turned
UVLO Mode
-Bridge IQCCUV 250µA
10.5 (VCCUV-) (Power Turned Off) SD/EOL 5.0V (VSDTH+) (Lamp Removal)
SD/EOL (VSDTH+) (Lamp Removal) 10.5 (VCCUV-) (Power Turned Off)
12.5 (VCCUV+) SD/EOL (VSDTH-)
FAULT Mode
Fault Latch -Bridge IQCCFLT 600µA
PREHEAT Mode
(VCSTH+) events (nEVENTS)
/2-Bridge oscillating Charging Enabled (High Gain) Enabled Fault Counter Enabled
10.8 (VCPHEOP)
IGNITION Mode
(VCSTH+) events (nEVENTS) Open ramps fRUN charging High Gain Mode Enabled Fault Counter Enabled
12.0 (VCPHRUN) (VCSTH+) (single event) SD/EOL (VEOLTH-) Mode Open SD/EOL (VEOLTH+) 1/2-Bridge Oscillating @fRUN Gain Mode VBUS Threshold Enabled Enabled Fault Counter Disabled
VBUS Discharge (VBUSUV) UVLO
values typical. Applies application diagram page
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IRS2166D(S)PbF
Lead Assignments Definitions
VBUS
Symbol
VBUS COMP SD/EOL
Description
sensing input Preheat timing capacitor Oscillator timing resistor Preheat frequency timing resistor Oscillator timing capacitor error amplifier compensation zero-crossing detection gate driver output Shutdown/end life densing circuit Half-bridge current sensing input Low-side gate driver output power signal ground Logic low-side gate driver supply High-side gate driver floating supply High voltage floating return High-side gate driver output
IRS2166D
COMP
SD/EOL
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IRS2166D(S)PbF
Timing Diagrams Ballast Section
15.6V UVLO+ UVLO-
FREQ
1.25V
5.1V
FAULT
UVLO
UVLO
events CS>1.25V
OPEN
OPEN
1.25V
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IRS2166D(S)PbF
Ballast Section Functional Description Undervoltage Lock-Out Mode (UVLO)
undervoltage lock-out mode (UVLO) defined state when below turn-on threshold identify different modes refer State Diagram shown page this document. IRS2166D undervoltage lock-out designed maintain ultra supply current (IQCCUV), guarantee fully functional before high side output drivers activated. Fig. shows efficient supply voltage using start-up current IRS2166D together with charge pump from ballast output stage (RSUPPLY, CVCC, DCP1, DCP2).
VBUS(+) SUPPLY BOOT BOOT SNUB Half-Bridge Output
CVCC DISCHARGE VUVLO+
VHYST INTERNAL ZENER CLAMP VOLTAGE
VUVLO-
DISCHARGE TIME
CHARGE PUMP OUTPUT RSUPPLY CVCC TIME CONSTANT
Fig. Supply capacitor (CVCC) voltage
Preheat Mode (PH)
preheat mode defined state when lamp filaments being heated their correct emission temperature. This necessary maximizing lamp life reducing required ignition voltage. IRS2166D enters preheat mode when exceeds UVLO positive-going threshold VCCUV+. begin oscillate preheat frequency with duty cycle with deadtime which value external timing capacitor, internal deadtime resistor, RDT. disconnected from internal (ICPH) current source (Fig. charges external preheat timing capacitor linearly. over-current protection enabled during preheat. preheat frequency determined parallel combination resistors RPH, together with timing capacitor charges discharges between (VCT-) (VCT+) (see Timing Diagram, page charged exponentially through parallel combination connected internally through MOSFET charge time from on-time respective output gate driver, Once exceeds VCC, MOSFET turned off, disconnecting from VCC. then discharged exponentially through internal resistor, RDT, through MOSFET COM. discharge time from deadtime (both off) output gate drivers, selected value program desired deadtime (see Design Equations, page Equations Once discharges below VCC, MOSFET turned off, disconnecting from COM, MOSFET turned connecting again VCC. frequency remains preheat frequency until voltage exceeds enters ignition mode. During preheat mode, both overcurrent protection undervoltage reset enabled when exceeds (VCPHRUN).
IRS2166D
VBUS(-)
Fig. Start-up supply circuitry start-up capacitor (CVCC) charged current through supply resistor (RSUPPLY) minus start-up current drawn This resistor chosen line input voltage turn-on threshold ballast. Once capacitor voltage reaches start-up threshold VCCUV+, below (VSDTH-), turns begin oscillate. capacitor begins discharge increase operating current (Fig. During discharge cycle, rectified current from charge pump charges capacitor above turn-off threshold. charge pump internal 15.6 (VCLAMP) zener clamp take over supply voltage. start-up capacitor snubber capacitor must selected such that enough supply current available over ballast operating conditions. supply capacitor (CBOOT) comprises supply voltage high side driver circuitry. guarantee that high-side supply charged before first pulse first pulse from output drivers comes from pin. During undervoltage lock-out mode, high- low-side driver outputs both low, connected internally disable oscillator, connected internally resetting preheat time.
Ignition Mode (IGN)
ignition mode defined state when high voltage being established across lamp necessary igniting lamp. IRS2166D enters ignition mode when voltage exceeds 10.8 (VCPHEOP). connected internally
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IRS2166D(S)PbF
VBUS
OSC. HalfBridge Driver
HalfBridge Driver
HalfBridge Output ILOAD
HalfBridge Output LOAD
Fault Logic
1.3V
CCPH
Comp
Load Return
CCPH
Load Return
IRS2166D
IRS2166D
VBUS
Fig. Preheat circuitry gate p-channel MOSFET (S4) (see Fig. that connects with exceeds 10.8 (VCPHEOP), gate-to-source voltage MOSFET begins fall below turn-on threshold continues ramp towards VCC, switch turns slowly. This results resistor being disconnected smoothly from resistor which causes operating frequency ramp smoothly from preheat frequency, through ignition frequency, final frequency. over-current threshold will protect ballast against non-strike open-filament lamp fault condition. voltage defined lower half-bridge MOSFET current flowing through external current sensing resistor RCS. resistor therefore programs maximum allowable peak ignition current (and therefore peak ignition voltage) ballast output stage. peak ignition current must exceed maximum allowable current ratings output stage MOSFETs. Should this voltage exceed internal threshold 1.20 (VCSTH+), internal fault counter begins counting number sequential over-current faults (see timing diagram). number over-current faults exceeds (nEVENTS), will enter FAULT mode gate driver outputs will latched low.
Fig.4: Ignition circuitry
Undervoltage Reset
Should decrease during brown-out line condition over-load condition, resonant output stage lamp shift near below resonance. This produce hard-switching half-bridge which damage half-bridge switches decrease lamp extinguish. protect against this, VBUS includes undervoltage threshold (VBUSUV). Should voltage VBUS decrease below will discharged below VCCUV- threshold gate driver outputs will latched low. proper ballast design, designer should design section such that does drop until line input voltage falls below rated input voltage ballast (see section). When correctly designed, voltage measured VBUS will decrease below internal threshold (VBUSUV) ballast will turn cleanly. pull-up resistor (RSUPPLY) will then turn ballast again when input line voltage increases minimum specified value causing exceed VCCUV+. RSUPPLY should turn ballast minimum specified ballast input voltage. should then designed such that decreases input line voltage that lower than minimum specified ballast input voltage. This hysteresis will result clean turn-on turn-off ballast.
Mode (RUN)
Once lamp successfully ignited, ballast enters mode. mode defined state when lamp established lamp being driven given power level. mode oscillating frequency determined timing resistor timing capacitor (see Design Equations, page 15). Should hard-switching occur half-bridge time open-filament lamp removal, voltage across current sensing resistor, RCS, will exceed internal threshold 1.20 (VCSTH+) fault counter will begin counting (see timing diagram). Should number consecutive over-current faults exceed (nEVENTS), will enter fault mode gate driver outputs will latched low.
SD/EOL Fault Mode (FAULT)
Should voltage SD/EOL exceed (VEOLTH+) decrease below (VEOLTH-) during mode, end-of-life (EOL) fault condition occurred enters fault mode. gate driver outputs latched `low' state. discharged resetting preheat time. exit fault mode, decreased below VCCUV- (ballast power off) increased above (VSDTH+) (lamp removal). Either these will force enter UVLO mode (see State Diagram, page Once
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IRS2166D(S)PbF
Pulses
above VCCUV+ (ballast power pulled above (VSDTH+) back below (VSDTH-) (lamp re-insertion), will enter preheat mode begin oscillating again. current sense function will force enter fault mode only after voltage been greater than 1.20 (VCSTH+) (nEVENTS) consecutive cycles over-current function (see Fig. will only consecutive cycles overcurrent function (see Fig. will only work with over-current events that occur during on-time. over-current faults consecutive, then internal fault counter will count back down each cycle when there fault present. Should over-current fault occur only cycles then occur again, counter will eventually count back down zero. over-current fault counter enabled during preheat ignition modes disabled during mode. During mode, will enter fault mode after single overcurrent event pin.
2.0V
Preheat Ignition Mode
Fault Mode
Fig. Waveforms When switch MPFC turned inductor LPFC connected between rectified line input causing current LPFC charge linearly. When MPFC turned off, LPFC connected between rectified line input capacitor CBUS (through diode DPFC) stored current LPFC flows into CBUS. MPFC turned high-frequency, voltage CBUS charges specified voltage. feedback loop IRS2166D regulates this voltage fixed value continuously monitoring voltage adjusting on-time MPFC accordingly. increasing on-time decreased, decreasing on-time increased. This negative feedback control performed with slow loop speed loop gain such that average inductor current smoothly follows low-frequency line input voltage high power factor THD. on-time MPFC therefore appears fixed (with additional modulation discussed later) over several cycles line voltage. With fixed on-time, off-time determined inductor current discharging zero, result system where switching frequency free-running constantly changing from high frequency near zero crossing input line voltage, lower frequency peaks (Fig.
Section Functional Description
most electronic ballasts necessary have circuit pure resistive load input line voltage. degree which circuit matches pure resistor measured phase shift between input voltage input current well shape input current waveform matches shape sinusoidal input voltage. cosine phase angle between input voltage input current defined power factor (PF), well shape input current waveform matches shape input voltage determined total harmonic distortion (THD). power factor (maximum) corresponds zero phase shift represents pure sinewave distortion). this reason desirable have high THD. achieve this, IRS2166D includes active power factor correction (PFC) circuit which, line input voltage, produces line input current. control method implemented IRS2166D boost-type converter (Fig. running critical-conduction mode (CCM). This means that during each switching cycle MOSFET, circuit waits until inductor current discharges zero before turning MOSFET again. MOSFET turned much higher frequency (>10 kHz) than line input frequency Hz).
LPFC DPFC
Fig. Sinusoidal line input voltage (solid line), triangular inductor current smoothed sinusoidal line input current (dashed line) over half-cycle line input voltage When line input voltage (near zero crossing), inductor current will charge small amount discharge time will fast resulting high switching frequency. When input line voltage high (near peak), inductor current will charge higher amount discharge time will longer giving lower switching frequency. triangular inductor current then smoothed filter produce sinusoidal line input current.
MPFC CBUS
Fig. Boost-type circuit
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IRS2166D(S)PbF
control circuit IRS2166D (Fig. only requires four control pins: VBUS, COMP, PFC. VBUS sensing voltage (via external resistor voltage divider), COMP programs on-time MPFC speed feedback loop, detects when inductor current discharges zero (via secondary winding from inductor), low-side gate driver output MPFC.
LPFC
DFPC
off-time MPFC turned again (Fig. 10). cycle repeats itself indefinitely until section disabled fault detected ballast section (fault mode), over-voltage undervoltage condition bus, negative transition voltage does occur. Should negative edge occur, MPFC will remain until watch-dog timer forces turn-on MPFC on-time duration programmed voltage COMP pin. watch-dog pulses occur every (tWD) indefinitely until correct positive- negative-going signal detected normal operation resumed.
RVBUS1 VBUS
COMP
Control
CBUS RPFC MPFC
ILPFC
DCOMP RVBUS CCOMP
Fig. IRS2166D simplified control circuit VBUS regulated against fixed internal reference voltage (VBUSREG) regulating voltage (Fig. feedback loop performed operational transconductance amplifier (OTA) that sinks sources current external capacitor COMP pin. resulting voltage COMP sets threshold charging internal timing capacitor (C1) therefore programs on-time MPFC. During preheat ignition modes ballast section, gain high level raise level quickly minimize transient which occur during ignition. During mode, gain then decreased lower level necessary achieving high power factor THD.
Mode Signal Fault Mode Signal
Fig. LPFC current, timing diagram fixed on-time MPFC over entire cycle line input voltage produces peak inductor current which naturally follows sinusoidal shape line input voltage. smoothed averaged line input current phase with line input voltage high power factor total harmonic distortion (THD), well individual higher harmonics, current still high. This mostly cross-over distortion line current near zero-crossings line input voltage. achieve harmonics which acceptable international standard organizations general market requirements, additional on-time modulation circuit been added control. This circuit dynamically increases on-time MPFC line input voltage nears zero-crossings (Fig. 11). This causes peak LPFC current, therefore smoothed line input current, increase slightly higher near zero-crossings line input voltage. This reduces amount cross-over distortion line input current which reduces higher harmonics levels.
VBUS
GAIN 4.0V OTA1 4.3V COMP4
COMP
COMP2 Discharge UVLOC1
COMP5
WATCH TIMER
3.0V
7.6V 2.0V
COMP3
Fig. IRS2166D detailed control circuit off-time MPFC determined time takes LPFC current discharge zero. This zero current level detected secondary winding LPFC which connected pin. positive-going edge exceeding internal threshold (VZXTH+) signals beginning off-time. negative-going edge falling below (VZXTH+ VZXHYS) will occur when LPFC current discharges zero which signals
Over-Voltage Protection (OVP)
Should over-voltage occur causing VBUS exceed internal threshold (VBUSOV+), output disabled (set logic `low'). When decreases again causing VBUS
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IRS2166D(S)PbF
Over-Current Protection
ILPFC
near peak region rectified line
near zero-crossing region rectified line
Fig. On-time modulation near zero-crossings decrease below internal threshold (VBUSREG), watch-dog pulse forced normal operation resumed.
case fast on/off interruptions mains input voltage during normal lamp ignition, voltage level decrease below instantaneous rectified line voltage. Should this occur, inductor current MOSFET current increase high levels causing inductor saturate and/or MOSFET become damaged. During fast on/off interruptions input mains voltage, drop during time when mains voltage interrupted (off). Since still above UVLO-, will continue operate will increase COMP voltage increase MOSFET on-time dropping bus. When mains voltage returns again quickly, (before reaches UVLO-), on-time MOSFET long given mains voltage level resulting high inductor MOSFET currents that saturate inductor and/or damage MOSFET (Fig. 13).
Undervoltage Reset (UVR)
When line input voltage decreased, interrupted brown-out condition occurs, feedback loop causes on-time MPFC increase order keep constant. Should on-time increase far, resulting peak currents LPFC exceed saturation current limit LPFC. LPFC will then saturate very high peak currents di/dt levels will occur. prevent this, maximum on-time limited limiting maximum voltage COMP with external zener diode DCOMP (Fig. line input voltage decreases, COMP voltage therefore ontime will eventually limit. longer supply enough current keep fixed given load power will begin drop. Decreasing line input voltage further will cause VBUS eventually decrease below internal threshold (VBUSUV) (Fig. When this occurs, discharged internally below VCCUV-, IRS2166D enters UVLO mode both ballast sections disabled (see State Diagram). start-up supply resistor VCC, together with micro-power start-up current IRS2166D, determines line input turnon voltage. This should such that ballast turns line voltage level above undervoltage turn-off level, VCCUV+. correct selection value supply resistor zener diode COMP that correctly program line input voltage thresholds ballast. With these thresholds correctly set, ballast will turn undervoltage threshold (VBUSUV) VBUS pin, again higher line input voltage (hysteresis) supply resistor VCC. This hysteresis will result proper reset ballast without flickering lamp, bouncing re-ignition lamp when low.
Fig. High inductor current during fast mains on/off (upper trace: Bus, V/div; middle trace: line input voltage, V/div; lower trace: inductor current A/div). During lamp ignition, drop below rectified line voltage causing current conduct directly from output rectifier, through inductor diode, capacitor. This results low-frequency offset current inductor. Since zero-crossing detection circuit only detects high-frequency zero-crossing inductor current, MOSFET will turn again each cycle before inductor current reached zero. This causes work continuous conduction mode low-frequency high-frequency components current saturate inductor and/or damage MOSFET. protect against these conditions, current sense resistor (RS) inserted between source MOSFET ground, diode (D4) connected from this current sensing resistor VBUS (Fig. 14).
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IRS2166D(S)PbF
these reasons, ballast designer should perform these mains interrupt ignition tests carefully determine robustness their final design decide this additional over-current protection circuit necessary.
Ballast Design Equations
Note: results from following design equations differ slightly from experimental measurements tolerances, component tolerances, oscillator overand under-shoot internal comparator response time. Fig. External over-current protection circuit Should high currents occur, voltage across current-sensing resistor will exceed overvoltage protection threshold VBUS MOSFET will turn safely limiting current. watch-dog timer will then restart normal (Fig. 15). current sensing resistor value should selected such that over-current protection does false trip during normal operation over entire line voltage range load range. current-sensing resistor value, example, will over-current protection threshold about peak. Step Program Deadtime deadtime between gate driver outputs programmed with timing capacitor internal deadtime resistor RDT. deadtime discharge time capacitor from given
1475
1475
Step Program Frequency final frequency programmed with timing resistor timing capacitor charge time capacitor from determines ontime gate driver outputs. frequency therefore given
Fig. inductor current limited using over-current protection circuit (upper trace: Bus, V/div; middle trace: line input voltage, div; lower trace: inductor current A/div). effect that these line load conditions have performance ballast depends saturation level inductor, selection MOSFET, capacitor value, maximum ontime limit DZCOMP, and, fast decreases below UVLO- when drops during ignition (the reset VBUS does become active until mode).
(0.51 1475) 2892 1.02
[Hz]
Step Program Preheat Frequency preheat frequency programmed with timing resistors RPH, timing capacitor timing resistors connected parallel internally duration preheat time. preheat frequency therefore given
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IRS2166D(S)PbF
where,
0.51 1475
[Hz]
VBUS voltage Minimum input voltage efficiency (typically 0.95) Minimum switching frequency minimum
input voltage
1.02 2892 1.02 2892
POUT
Ballast output power
Step Calculate peak inductor current:
POUT
Step Program Preheat Time preheat time defined time takes capacitor charge internal current source (ICPH) flows CPH. preheat time therefore given Note: inductor must saturate over specified ballast operating temperature range. Proper core sizing air-gapping should considered inductor design. Step Calculate maximum on-time:
2.6e6
0.385e
Step Program Maximum Ignition Current
POUT LPFC
maximum ignition current programmed with external resistor internal threshold 1.20 This threshold determines over-current limit ballast, which exceeded when frequency ramps down towards resonance during ignition lamp does ignite. maximum ignition current given
Step Calculate maximum COMP voltage:
VCOMPMAX
VCSTH VCSTH
Step Select zener diode DCOMP value:
DCOMP zener voltage VCOMPMAX
(10)
Step Calculate resistor RSUPPY value:
SUPPLY
IQCCUV
Design Equations
Step1: Calculate inductor value:
(VBUS VACMIN POUT VBUS
LPFC
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IRS2166D(S)PbF
CaseOutlines
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IRS2166D(S)PbF
16-Lead Tape Reel
LOADED TAPE FEED DIRECTION
NOTE CONTROLLING ENSION
CARRIER TAPE DIMENSION Metric Code 7.90 8.10 3.90 4.10 15.70 16.30 7.40 7.60 6.40 6.60 10.20 10.40 1.50 1.50 1.60
16SOICN Imperial 0.311 0.318 0.153 0.161 0.618 0.641 0.291 0.299 0.252 0.260 0.402 0.409 0.059 0.059 0.062
REEL DIMENSIONS 16SOICN Metric Imperial Code 329.60 330.25 12.976 13.001 20.95 21.45 0.824 0.844 12.80 13.20 0.503 0.519 1.95 2.45 0.767 0.096 98.00 102.00 3.858 4.015 22.40 0.881 18.50 21.10 0.728 0.830 16.40 18.40 0.645 0.724
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IRS2166D(S)PbF
ORDER INFORMATION
16-Lead PDIP IRS2166DPbF 16-Lead SOIC IRS2166DSPbF 16-Lead SOIC Tape Reel IRS2166DSTRPbF
SOIC-16 MSL3 qualified. This product been designed qualified industrial level. Qualification standards found www.irf.com <http://www.irf.com> WORLD HEADQUARTERS: Kansas St., Segundo, California 90245, Tel: (310) 252-7105 Data specifications subject change without notice. 6/27/2006
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IRS2166D(S)PbF
REVISION HISTORY 2006
revision Symbol Definition Preheat half-bridge oscillator frequency when bootstrap source current when source current when revision Units
VB,ON IB,CAP IB,10
13.7
13.1
13.7
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IRS2166D(S)PbF
Sept 2006
revision Symbol IQCCUV IQCC IQCCFLT ICC,RUN IQBS0 IQBS1 Definition UVLO mode quiescent current Quiescent supply current Fault quiescent supply current current frequency Quiescent supply current Quiescent supply current -13.1 12.5 13.7 -Sept revision 12.0 -13.2 12.5 13.7 13.0 Units
ICOMP,SOURCE error amplifier output current sourcing ICOMP,SINK VCOMPOH VCOMPOL VZXHYS VZXclamp VCT+ nEVENTS VSD,delay VEOL,delay VB,ON IB,10 error amplifier output current sinking error amplifier output voltage swing (high state) error amplifier output voltage swing (low state) positve edge triggered threshold voltage comparator hysterisis clamp voltage (high state) watch-dog pulse interval Preheat half-bridge oscillator frequency rising threshold voltage fault counter number events Delay from VSDTH+ until goes Delay from VEOLTH+ until goes when bootstrap source current when
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