256-TAP NON-VOLATILE DIGITAL POTENTIOMETER Publication Release Da

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256-TAP NON-VOLATILE DIGITAL POTENTIOMETER Publication Release Da

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WMS7201
256-TAP NON-VOLATILE DIGITAL POTENTIOMETER
Publication Release Date: January 2003 Revision
WMS7201
GENERAL DESCRIPTION
WMS7201 256-tap, single-channel non-volatile digital potentiometer available 10K, 100K end-to-end resistances. These devices used three-terminal potentiometer terminal variable resistor wide variety applications. output potentiometer determined wiper position, which varies linearly between terminal according content stored volatile Register (TR). settings provided either directly user through industry standard interface, non-volatile memory (NVMEM0~3) where previous settings stored. When changes made establish wiper position, value setting saved into non-volatile memory location (NVMEM0~3) executing NVMEM save operation. Upon powerup content NVMEM0 automatically loaded Register. WMS7201 contains single potentiometer 8-pin PDIP, SOIC, MSOP TSSOP packages operate over wide operating voltage range from 2.7V 5.5V. selectable output buffer built-in those applications where output buffer required.
FEATURES
taps potentiometer End-to-end resistance available 10K, 100K Selectable output buffer each channel Serial Interface data transfer potentiometer control Daisy-chain operation multiple devices (10-pin TSSOP package only) Nonvolatile storage four wiper positions channel with power-on recall from NVMEM0 standby current (1µA Max. with output buffer inactive) Endurance 100K typical stores Register Data Retention years Industrial temperature range: 85°C Wide operating voltage range: 2.7V 5.5V Package option: 8-pin MSOP, 8-pin SOIC, 8-pin PDIP, 10-pin TSSOP
WMS7201
BLOCK DIAGRAM
Register
Decoder
Serial Interface
Memory Power on/Preset
Memory Control Addressable Preset values
FIGURE WMS7201 BLOCK DIAGRAM Note Available 10-pin TSSOP packages only.
Publication Release Date: January 2003 Revision
WMS7201
TABLE CONTENTS
GENERAL DESCRIPTION. FEATURES BLOCK DIAGRAM TABLE CONTENTS CONFIGURATION DESCRIPTION FUNCTIONAL DESCRIPTION. 7.1. Potentiometer Rheostat Modes 7.1.1. Rheostat Configuration 7.1.2. Potentiometer Configuration 7.2. Programming Modes 7.3. Non-Volatile Memory (NVMEM) 7.3.1 Write Protect NVMEM Flow Control. 7.5. Daisy Chain 7.6. Serial Data Iterface 7.7. Instruction Set. 7.8. Basic Operation 7.8.1 Sending Command 7.8.2 Wake Up/Sleep/Power Commands 7.8.3 Write Register (TR). 7.8.4 Programming Non-Volatile Memory (NVMEM). 7.8.5 Reading Register NVMEM Location (10-pin TSSOP package only). TIMING DIAGRAMS. ABSOLUTE MAXIMUM RATINGS. ELECTRICAL CHARACTERISTICS 10.1 Test Circuits. TYPICAL APPLICATION CIRCUIT 11.1. Layout Considerations PACKAGE DRAWINGS DEMINSIONS. ORDERING INFORMATION. VERSION HISTORY
WMS7201
CONFIGURATION
FIGURE PACKAGE TYPES
Publication Release Date: January 2003 Revision
WMS7201
DESCRIPTION
TABLE DESCRIPTION NAME DESCRIPTION Serial Clock pin. Data Shifts time positive clock (CLK) edges Chip Select pin. When HIGH, WMS7201 deselected high impedance, (unless internal write cycle underway) device will standby state. enables WMS7201, placing active power mode. should noted that after power-up, HIGH transition required prior start operation. Serial Data Input pin. opcodes, byte addresses data written registers input this pin. Data latched rising edge serial clock. Serial Data Output with open-drain output. During read cycle, data shifted this pin. Data clocked falling edge serial clock except bit, which clocked falling edge Also used daisy-chain several parts. (Only 10-pin TSSOP package) Hardware Write Protect pin. When active prevents changes present contents except retrieving NVMEM contents. (Only 10-pin TSSOP package) Power Supply Ground pin, logic ground reference terminal potentiometer `1', equivalent terminal connection mechanical potentiometer terminal potentiometer `1', equivalent terminal connection mechanical potentiometer Wiper terminal potentiometer `1', equivalent wiper terminal mechanical potentiometer
WMS7201
FUNCTIONAL DESCRIPTION
WMS7201 series, family 256-tap, nonvolatile digitally programmable potentiometers designed operate both potentiometer variable resistor depending upon output configuration selected. chip store four 9-bit words nonvolatile memory (NVMEM0 NVMEM3) word stored NVMEM0 will used register values when device powered WMS7201 controlled serial interface that allows setting register value well storing data nonvolatile memory. 7.1. POTENTIOMETER RHEOSTAT MODES WMS7201 operate either rheostat potentiometer (voltage divider). When potentiometer configuration there possible modes. without output buffer other mode with output buffer. Selecting mode done controlling data register. sets output buffer sets Note that this only loading value NVMEM with instructions then loading register with instruction from NVMEM. This cannot controlled directly writing value chip when register set. 7.1.1. Rheostat Configuration WMS7201 acts terminal resistive element rheostat configuration where terminal either point pins resistor other terminal wiper (VW) pin. This configuration controls resistance between terminals resistance adjusted sending corresponding register setting commands WMS7201 loading pre-set register value from nonvolatile memory NVMEM0 MVMEM3. 7.1.2. Potentiometer Configuration potentiometer configuration input voltage connected point pins VB). voltage wiper will proportional voltage difference between wiper setting. resistance cannot directly measured this configuration. 7.2. PROGRAMMING MODES program modes available WMS7201: Direct program mode. register setting changed either loading predetermined value from external microcontroller using UP/DOWN command. DOWN commands change register setting incrementally i.e., time. DOWN commands will wrap around ends scale. NVMEM restore mode. previously stored settings loaded into register from non-volatile memory. Four 9-bit non-volatile memories, available store register settings. first register, NVMEM0, stores favorite default register setting that will loaded into register system power software power reset operation.
Publication Release Date: January 2003 Revision
WMS7201
7.3. NON-VOLATILE MEMORY (NVMEM) WMS7201 four NVMEM positions available storing output buffer operating mode potentiometer setting. These NVMEM positions directly written through using write command (#5) with address data bytes. Another command (#7) available that stores current output buffer operating mode potentiometer settings into selected NVMEM position. instruction byte decide which NVMEM position used. (See Table potentiometer loaded with value stored NVMEM position power 7.3.1 Write Protect NVMEM Write-Protect disables changes current content NVMEM regardless commands, except that NVMEM setting retrieved using commands Table Therefore, Write-Protect provides hardware NVMEM protection feature with tied Vss. which active logic LOW, should tied directly being used. This function only available 10-pin package.
FLOW CONTROL Reading writing NVMEM requires internal access cycle complete before next command sent. Read Register (#2) Read NVMEM (#4) Program NVMEM (#5) Load Register(#6) Program NVMEM with Register (#7)
WMS7201
7.5. DAISY CHAIN Multiple devices controlled same without need extra lines from microcontroller daisy chaining devices with first device connected next device shown figure when using 10-pin package.
Micro controller Device Device
Device
FIGURE DAISY CHAIN CONFIGURATION [10-PIN TSSOP PACKAGE ONLY] complete command bits including instruction data bytes. When shifting bits first device chain, bits previous command will shifted out. devices daisy chain, total bits must sent where first bits will shifted second device bits shifted last will remain first device. Command data device shifted into device this will propagate Device when next bits shifted Device Command Data Data
Device
Command data device shifted into device Device correctly 10-pin TSSOP package only. Device Command Data Data
Device Command
Data
Data
FIGURE DAISY CHAIN COMMAND EXAMPLE
Publication Release Date: January 2003 Revision
WMS7201
7.6. SERIAL DATA ITERFACE WMS7201 contains four-wire interface: (Serial Data Output) Used reading internal register contents daisy chaining multiple devices 10-pin package. (Serial Data Input) Used clocking commands potentiometer settings. (Chip Select) This must pulled before starting send command pulled HIGH signal command; this used control multiple devices bus. (Clock) bits shifted rising edge clock data shifted falling edge clock.
features this interface include: Independently programmable Read Write registers Direct parallel refresh register from corresponding internal NVMEM registers Increment decrement instruction register Nonvolatile storage present register values into four NVMEM registers available. Configurable output buffer amplifier allow both functions potentiometer variable resistor Four 9-bit non-volatile registers store four preset wiper positions first will recalled wiper position during power
serial interface uses compatible uniform 24-bit word format shown below. This format used members WMS720x family. data sent first. TABLE 24-BIT DATA WORD FORMAT
C3-C0 command bits that control operation digital potentiometer according command instructions shown Instruction Table Section 7.7. address bits that determine which channel activated WMS720x family shown table below. WMS7201 always
WMS7201
TABLE ADDRESS DECODE TABLE Channel
address bits that decide which NVMEM memory accessed, shown table below. TABLE ADDRESS DECODE TABLE NVMEM
D7-D0 data values loaded into Register wiper position, while used output mode. loaded into NVMEM0~3 first then "Load Register" command (#6) executed load into output-selection output mode. D8=0 sets output Buffer mode while D8=1 sets Buffer mode.
taken before command starts
taken HIGH after command sent
Note: multiple bits must always sent command will valid Bits marked don't care bits.
FIGURE COMMAND WAVEFORMS Publication Release Date: January 2003 Revision
WMS7201
7.7. INSTRUCTION TABLE INSTRUCTION
Inst Instruction Byte Data Byte Data Byte Operation (NOP). nothing Read Register output selection register Write Register with D7-D0 Read NVMEM pointed A3-A0 Program NVMEM pointed A3-A0 with D8-D0 Load Register output selection register with contents NVMEM pointed A3-A0 Program NVMEM pointed A3-A0 with contents Register output selection register Increment setting Down: Decrement setting Sleep: Discontinue clock supply logic memories Wake Clock supply logic memories Byte-erase NVMEM pointed A3-A0 Power Reset: Software reset part power state Operation
Note: C3-C0 command op-code; NVMEM address; channel address.
7.8. BASIC OPERATION This chapter describes sequences commands send WMS7201 different features.
7.8.1 Sending Command Take chip SLEEP mode. Check that write protect correctly writing NVMEM (10-pin TSSOP package only). Pull before sending data device.
WMS7201
clock pulses sent each command. must valid rising edge clock, valid falling edge clock Take HIGH after command completed command sent, wait time before sending next command.
7.8.2 Wake Up/Sleep/Power Commands chip SLEEP mode after: applied Power Reset command sent SLEEP command sent
Before operations performed WAKE command must sent. When SLEEP command sent, chip retains resistor settings long chip powered cannot accept other commands than WAKE command. TABLE POWER RELATED COMMANDS Inst. Command Name: Wake Sleep Power Reset Command Byte 0001xxxx 1000xxxx 1001xxxx 0000xxxx Data Byte xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx Data Byte xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx Comment Wake entire chip Send chip into power save mode Reset Chip Dummy instruction
commands above control entire chip.
7.8.3 Write Register (TR) microcontroller write value directly into register send increment decrement command control register. Alternatively, contents NVMEM location written register. only change output buffer mode write desired value into NVMEM location then load corresponding NVMEM location into register.
Publication Release Date: January 2003 Revision
WMS7201
TABLE WRITING REGISTERS Inst. Comman Name: Write Register Down Load Register Command Byte 0100 Data Byte xxxxxxxx Data Byte Comment Writes value register. Increment register value Decrement register value Load selected NVMEM location into register
0111 1111
xxxxxxxx xxxxxxxx xxxxxxxx
xxxxxxxx xxxxxxxx xxxxxxxx
7.8.4 Programming Non-Volatile Memory (NVMEM) value stored NVMEM location bits, bits (D7-D0) register plus (D8) output buffer mode. NVMEM position must erased before writing There ways program value into NVMEM. Write value directly from microcontroller. Load current potentiometer setting into NVMEM. TABLE PROGRAMMING NVMEM Inst. Command Name Erase NVMEM Program NVMEM Program NVMEM with Register Command Byte Data Byte xxxxxxxx Data Byte Comment Erases word pointed Writes value NVMEM register. Takes current potentiometer settings saves selected NVMEM location.
xxxxxxxx
programming NVMEM, following sequence must followed: Erase word NVMEM location Program word NVMEM location
WMS7201
7.8.5 Reading Register NVMEM Location (10-pin TSSOP package only) contents register NVMEM location read back through pin. When command sent, data clocked falling edge clock. Since daisy-chain operation requires data from command clocked when next command arrives, read command must followed another command correct data pin. TABLE READING REGISTER Inst. Command Name: Read NVMEM Read Register Read Register Command Byte Data Byte xxxxxxxx Data Byte Comment Read value selected NVMEM location Read value selected register Output data
1100 0000
xxxxxxxx
read contents either register NVMEM location, following sequence must followed. Send desired read command Send another command such read falling edge clock. other command could command, make sure that chip does change anything, send either another Read command command (#1).
Publication Release Date: January 2003 Revision
WMS7201
TIMING DIAGRAMS
tCYC tLEAD tDSU tLAC tRSU
tLAG
tLRL
tWPSU
tWPH
FIGURE WMS7201 TIMING DIAGRAM Notes: Internal signal only. Only 10-pin TSSOP package.
WMS7201
TABLE TIMING PARAMETERS PARAMETER Clock Cycle Time Clock HIGH Time Clock Time Lead Time Time Setup Time Hold Time
Line Acquire Line Release
SYMBOL tCYC tLEAD tLAG tDSU tLAC tLRL tWPSU tWPH
MIN.
MAX.
UNIT
Propagation Delay Store NVMEM Save Time
Deselect Time
Startup Time
Setup Time Hold Time
Note: interface timing characteristics apply parts guaranteed design subject production test. Note 10-pin package only.
Publication Release Date: January 2003 Revision
WMS7201
ABSOLUTE MAXIMUM RATINGS
TABLE ABSOLUTE MAXIMUM RATINGS Condition Junction temperature Storage temperature Voltage applied (Vss 0.3V) (VDD 0.3V) -0.3 7.0V Value
Note: Exposure conditions beyond those listed under: Absolute Maximum Ratings, adversely affect life reliability device.
WMS7201
ELECTRICAL CHARACTERISTICS
TABLE ELECTRICAL CHARACTERISTICS
Parameters apply across specified operating ranges unless noted (VDD: 2.7V~5.5V; Temp: -40°C~85°C) Typical values: VDD=5V T=25°C
PARAMETER Rheostat Mode Nominal Resistance Different Linearity Integral Linearity Rheostat Tempco1 Wiper Resistance2
SYMBOL RAB/T
MIN.
MAX.
UNITS ppm/°
CONDITIONS open
Bits ppm/°
VDD=5V, I=VDD/RTotal VDD=2.7V, I=VDD/RTotal
Potentiometer Mode Resolution1 Different Linearity2 Integral Linearity2 Potentiometer Tempco1 Full Scale Error Zero Scale Error Resistor Terminal Voltage Range1 Terminal Capacitance1 Wiper Capacitance1 Dynamic Characteristics1
Vw/T VFSE VZSE VA,VB,VW
Code Code Full Scale Code Zero Scale
BW10K Bandwidth -3dB Settling Time BW50K BW100K
VDD=5V, VB=VSS
Code Full Scale
Code CL=30pf VDD=5.5V=VA, VB=VSS VO=1/2 scale VA=2.5V, VDD=5V, f=1kHz, VIN=1VRMS
Analog Output (Buffer enabled) Output Current2 IOUT Output Resistance2 Rout Total Harmonic Distortion1 Digital Inputs/Outputs Input High Voltage Input Voltage Output Voltage Input Leakage Current
0.08
0.7VDD 0.3VDD
IOL=2mA =VDD,Vin=Vss
Publication Release Date: January 2003 Revision
WMS7201
=VDD,Vin=VSS VDD=5V, 1Mhz Code VDD=5V, 1Mhz Code
Output Leakage Current Input Capacitance1 Output Capacitance1 Power Requirements Operating Voltage1 Operating Current Operating Current
COUT IDDR IDDW
LSB/V except NVMEM program During Nonvolatile memory program Buffer active, load Buffer inactive, Power Down, load VDD=5V±10%, Code=80h
Standby Current
ISB2 PSRR
Power Supply Rejection Ratio
Note: subject production test; Only Final Test; +2.7V 5.5V, unless otherwise noted.
WMS7201
10.1 TEST CIRCUITS
1LSB= V+/255 VMS*
±10% PSRR(dB) 20LOG( PSS(%/%)
WMS7201
*Assume infinite input impedance
WMS7201
VMS*
*Assume infinite input impedance
Potentiometer divider nonlinearity error test circuit (INL, DNL) Connection WMS7201
Power supply sensitivity test circuit (PSS, PSRR)
WMS7201
VOUT
*Assume infinite input impedance
2.5V Offset Capacitance test circuit
Resistor position nonlinearity error test circuit (Rheostat Operation: R-INL, R-DNL) WMS7201 /RTotal
WMS7201 OFFSET 2.5V
VOUT
*Assume infinite input impedance
Wiper resistance test circuit
Gain frequency test circuit FIGURE TEST CIRCUITS
Publication Release Date: January 2003 Revision
WMS7201
TYPICAL APPLICATION CIRCUIT
WMS7201
VOUT
VOUT
RABD
RAB(256
Total resistance potentiometer Wiper setting WMS7201
FIGURE PROGRAMMABLE INVERTING GAIN AMPLIFIER USING WMS7201
VOUT
WMS7201 VOUT
RAB(256 RABD
Total resistance potentiometer Wiper setting WMS7201 FIGURE PROGRAMMABLE NON-INVERTING GAIN AMPLIFIER USING WMS7201
WMS7201
32mA VREFH VREF 5.0v WMS7201
FIGURE WMS7201 TRIMMING VOLTAGE REFERENCE
CHOKE 0.1uF
FILTER POWER
WMS7201 WINPOT
Input
FIGURE WMS7201 CONTROL
Publication Release Date: January 2003 Revision
WMS7201
11.1. LAYOUT CONSIDERATIONS 0.1µF bypass capacitor close possible recommended best performance. Often this done placing surface mount capacitor bottom side board, directly between pins. Care should taken separate analog digital traces. Sensitive traces should under device close bypass capacitors. dedicated plane analog ground helps reducing ground noise sensitive analog signals.
FIGURE WMS7201 LAYOUT
WMS7201
PACKAGE DRAWINGS DEMINSIONS
Control demensions milmeters
FIGURE SOIC 150MIL
Publication Release Date: January 2003 Revision
WMS7201
Base Plane
Seating Plane
Symbol
Dimension inch
Dimension
0.010 0.125 0.016 0.058 0.008
0.175
0.25
4.45
0.130 0.018 0.060 0.010 0.360
0.135 0.022 0.064 0.014 0.380 0.310 0.255 0.110 0.140
3.18 0.41 1.47 0.20
3.30 0.46 1.52 0.25 9.14
3.43 0.56 1.63 0.36 9.65 7.87 6.48 2.79 3.56
0.290 0.245 0.090 0.120
0.300 0.250 0.100 0.130
7.37 6.22 2.29 3.05 8.51
7.62 6.35 2.54 3.30
0.335
0.355
0.375 0.045
9.02
9.53 1.14
FIGURE PDIP
WMS7201
FIGURE MSOP Publication Release Date: January 2003 Revision
WMS7201
ORDERING INFORMATION
Winbond's WinPot Part Number Description: WMS72
Winbond WinPot Products Features: Single channel with Interface Dual channels with Interface Quad channels with Interface
End-to-end Resistance: 010: 050: 100: 100K Package Index: TSSOP SOIC PDIP MSOP (Available only single channel devices)
latest product information, access Winbond's worldwide website http://www.winbond-usa.com
WMS7201
VERSION HISTORY
VERSION DATE Jan. 2003 PAGE Initial issue DESCRIPTION
contents this document provided only guide applications Winbond products. Winbond makes representation warranties with respect accuracy completeness contents this publication reserves right discontinue make changes specifications product descriptions time without notice. license, whether express implied, intellectual property other right Winbond others granted this publication. Except forth Winbond's Standard Terms Conditions Sale, Winbond assumes liability whatsoever disclaims express implied warranty merchantability, fitness particular purpose infringement Intellectual property. Winbond products designed, intended, authorized warranted components systems equipments intended surgical implantation, atomic energy control instruments, airplane spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, other applications intended support sustain life. Further, Winbond products intended applications wherein failure Winbond products could result lead situation wherein personal injury, death severe property environmental injury could occur.
Headquarters Creation Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/
Winbond Electronics Corporation America 2727 North First Street, Jose, 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441797 http://www.winbond-usa.com/
Winbond Electronics (Shanghai) Ltd. 27F, Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62356998
Taipei Office
480, Pueiguang Neihu District Taipei, Taiwan TEL: 886-2-81777168 FAX: 886-2-87153579
Winbond Electronics Corporation Japan
Daini-ueno BLDG. 3-7-18 Shinyokohama Kohokuku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Please note that data specifications subject change without notice. trademarks products companies mentioned this datasheet belong their respective owners. This product incorporates SuperFlash® technology licensed From SST.
Publication Release Date: January 2003 Revision

256-TAP NON-VOLATILE DIGITAL POTENTIOMETER Publication Release Da

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