Renesas Technology Corp. Hitachi SuperHRISC engine SH7709S
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Renesas Technology Corp.
Hitachi SuperHRISC engine
SH7709S
Hardware Manual
ADE-602-250 Rev. 09/21/01 Hitachi, Ltd.
Cautions
Hitachi neither warrants grants licenses rights Hitachi's third party's patent, copyright, trademark, other intellectual property rights information contained this document. Hitachi bears responsibility problems that arise with third party's rights, including intellectual property rights, connection with information contained this document. Products product specifications subject change without notice. Confirm that have received latest product standards specifications before final design, purchase use. Hitachi makes every attempt ensure that products high quality reliability. However, contact Hitachi's sales office before using product application that demands especially high quality reliability where failure malfunction directly threaten human life cause risk bodily injury, such aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment medical equipment life support. Design your application that product used within ranges guaranteed Hitachi particularly maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions other characteristics. Hitachi bears responsibility failure damage when used beyond guaranteed ranges. Even within guaranteed ranges, consider normally foreseeable failure rates failure modes semiconductor devices employ systemic measures such fail-safes, that equipment incorporating Hitachi product does cause bodily injury, fire other consequential damage operation Hitachi product. This product designed radiation resistant. permitted reproduce duplicate, form, whole part this document without written approval from Hitachi. Contact Hitachi's sales office questions regarding this document Hitachi semiconductor products.
Preface
This microprocessor with 32-bit SH-3 core peripheral functions necessary configuring user system. This built with variety peripheral functions such cache memory, memory management unit (MMU), interrupt controller, timer, three serial communication interfaces, realtime clock (RTC), break controller (UBC), state controller (BSC) ports. This used microcomputer devices that require both high speed power consumption. Target Readers: This manual designed people design application systems using SH7709S. this manual, basic knowledge electric circuits, logic circuits microcomputers required. Purpose: This manual provides information hardware functions electrical characteristics SH7709S. SH3, SH-3E, SH3-DSP Programming Manual contains detailed information executable instructions. Please read Programming Manual together with this manual. Book: understand general functions Read manuala from beginning. manual explains CPU, system control functions, peripheral functions electrical characteristics that order. understanding functions Refer separate SH3, SH-3E, SH3-DSP Programming Manual. Explanatory Note: sequence: upper left, lower right List Related Documents: latest documents available site. Please make sure that have latest version. User manuals SH7709S
Name Document SH7709S Series Hardware Manual SH3, SH-3E, SH3-DSP Programming Manual Document This manual ADE-602-156
User manuals development tools
Name Document C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual Simulator/Debugger User's Manual Hitachi Embedded Workshop User's Manual Document ADE-702-246 ADE-702-186 ADE-702-201
Application note
Name Document C/C++ Compiler Guide Document ADE-xxx-xxx
Contents
Section
Overview Functions
SH7709S Features Block Diagram. Description 1.3.1 Assignment 1.3.2 Function
Section
CPU. Register Configuration 2.1.1 Privileged Mode Banks 2.1.2 General Registers 2.1.3 System Registers 2.1.4 Control Registers. Data Formats 2.2.1 Data Format Registers. 2.2.2 Data Format Memory. Instruction Features 2.3.1 Execution Environment. 2.3.2 Addressing Modes 2.3.3 Instruction Formats Instruction 2.4.1 Instruction Classified Function 2.4.2 Instruction Code Map. Processor States Processor Modes. 2.5.1 Processor States. 2.5.2 Processor Modes Memory Management Unit (MMU) Overview 3.1.1 Features 3.1.2 Role MMU. 3.1.3 SH7709S 3.1.4 Register Configuration Register Description Functions. 3.3.1 Configuration TLB. 3.3.2 Indexing 3.3.3 Address Comparison 3.3.4 Page Management Information
Section
Functions 3.4.1 Hardware Management 3.4.2 Software Management. 3.4.3 Instruction (LDTLB). 3.4.4 Avoiding Synonym Problems Exceptions 3.5.1 Miss Exception 3.5.2 Protection Violation Exception 3.5.3 Invalid Exception. 3.5.4 Initial Page Write Exception 3.5.5 Processing Flow Event Exception (Same Processing Flow Address Error) Configuration Memory-Mapped TLB. 3.6.1 Data Array 3.6.2 Usage Examples Usage Note
Section
Exception Handling Overview 4.1.1 Features 4.1.2 Register Configuration Exception Handling Function. 4.2.1 Exception Handling Flow. 4.2.2 Exception Vector Addresses 4.2.3 Acceptance Exceptions 4.2.4 Exception Codes. 4.2.5 Exception Request Masks 4.2.6 Returning from Exception Handling Register Descriptions. Exception Handling Operation 4.4.1 Reset. 4.4.2 Interrupts 4.4.3 General Exceptions Individual Exception Operations. 4.5.1 Resets 4.5.2 General Exceptions 4.5.3 Interrupts Cautions. Cache
Overview 5.1.1 Features 5.1.2 Cache Structure
Section
5.1.3 Register Configuration Register Description 5.2.1 Cache Control Register (CCR). 5.2.2 Cache Control Register (CCR2) Cache Operation 5.3.1 Searching Cache. 5.3.2 Read Access 5.3.3 Prefetch Operation 5.3.4 Write Access 5.3.5 Write-Back Buffer. 5.3.6 Coherency Cache External Memory Memory-Mapped Cache. 5.4.1 Address Array 5.4.2 Data Array 5.4.3 Examples Usage.
Section
Interrupt Controller (INTC). Overview 6.1.1 Features 6.1.2 Block Diagram 6.1.3 Configuration 6.1.4 Register Configuration Interrupt Sources 6.2.1 Interrupt 6.2.2 Interrupts 6.2.3 Interrupts. 6.2.4 PINT Interrupts 6.2.5 On-Chip Peripheral Module Interrupts 6.2.6 Interrupt Exception Handling Priority. INTC Registers. 6.3.1 Interrupt Priority Registers (IPRA-IPRE) 6.3.2 Interrupt Control Register (ICR0). 6.3.3 Interrupt Control Register (ICR1). 6.3.4 Interrupt Control Register (ICR2). 6.3.5 PINT Interrupt Enable Register (PINTER) 6.3.6 Interrupt Request Register (IRR0) 6.3.7 Interrupt Request Register (IRR1) 6.3.8 Interrupt Request Register (IRR2) INTC Operation. 6.4.1 Interrupt Sequence 6.4.2 Multiple Interrupts Interrupt Response Time
Section
User Break Controller Overview 7.1.1 Features 7.1.2 Block Diagram 7.1.3 Register Configuration Register Descriptions. 7.2.1 Break Address Register (BARA) 7.2.2 Break Address Mask Register (BAMRA). 7.2.3 Break Cycle Register (BBRA) 7.2.4 Break Address Register (BARB) 7.2.5 Break Address Mask Register (BAMRB) 7.2.6 Break Data Register (BDRB) 7.2.7 Break Data Mask Register (BDMRB). 7.2.8 Break Cycle Register (BBRB) 7.2.9 Break Control Register (BRCR) 7.2.10 Execution Times Break Register (BETR) 7.2.11 Branch Source Register (BRSR) 7.2.12 Branch Destination Register (BRDR) 7.2.13 Break ASID Register (BASRA). 7.2.14 Break ASID Register (BASRB) Operation Description 7.3.1 Flow User Break Operation 7.3.2 Break Instruction Fetch Cycle. 7.3.3 Break Data Access Cycle 7.3.4 Sequential Break 7.3.5 Value Saved Program Counter. 7.3.6 Trace. 7.3.7 Usage Examples 7.3.8 Notes. Power-Down Modes Overview 8.1.1 Power-Down Modes. 8.1.2 Configuration 8.1.3 Register Configuration Register Descriptions. 8.2.1 Standby Control Register (STBCR). 8.2.2 Standby Control Register (STBCR2). Sleep Mode. 8.3.1 Transition Sleep Mode 8.3.2 Canceling Sleep Mode Standby Mode 8.4.1 Transition Standby Mode.
Section
8.4.2 Canceling Standby Mode 8.4.3 Clock Pause Function. Module Standby Function 8.5.1 Transition Module Standby Function. 8.5.2 Clearing Module Standby Function Timing STATUS Changes. 8.6.1 Timing Resets. 8.6.2 Timing Canceling Standby 8.6.3 Timing Canceling Sleep Mode. Hardware Standby Mode. 8.7.1 Transition Hardware Standby Mode 8.7.2 Canceling Hardware Standby Mode. 8.7.3 Hardware Standby Mode Timing.
Section
On-Chip Oscillation Circuits Overview 9.1.1 Features Overview 9.2.1 Block Diagram. 9.2.2 Configuration 9.2.3 Register Configuration Clock Operating Modes. Register Descriptions. 9.4.1 Frequency Control Register (FRQCR). Changing Frequency. 9.5.1 Changing Multiplication Rate 9.5.2 Changing Division Ratio Overview WDT. 9.6.1 Block Diagram WDT. 9.6.2 Register Configuration WDTRegisters 9.7.1 Watchdog Timer Counter (WTCNT). 9.7.2 Watchdog Timer Control/Status Register (WTCSR). 9.7.3 Notes Register Access. Using 9.8.1 Canceling Standby 9.8.2 Changing Frequency. 9.8.3 Using Watchdog Timer Mode. 9.8.4 Using Interval Timer Mode. Notes Board Design
Section State Controller (BSC)
10.1 Overview
10.1.1 Features 10.1.2 Block Diagram 10.1.3 Configuration 10.1.4 Register Configuration 10.1.5 Area Overview 10.1.6 PCMCIA Support. 10.2 Registers 10.2.1 Control Register (BCR1) 10.2.2 Control Register (BCR2) 10.2.3 Wait State Control Register (WCR1). 10.2.4 Wait State Control Register (WCR2). 10.2.5 Individual Memory Control Register (MCR). 10.2.6 PCMCIA Control Register (PCR). 10.2.7 Synchronous DRAM Mode Register (SDMR) 10.2.8 Refresh Timer Control/Status Register (RTCSR) 10.2.9 Refresh Timer Counter (RTCNT) 10.2.10 Refresh Time Constant Register (RTCOR) 10.2.11 Refresh Count Register (RFCR) 10.2.12 Cautions Accessing Refresh Control Related Registers 10.2.13 MCS0 Control Register (MCSCR0) 10.2.14 MCS1 Control Register (MCSCR1) 10.2.15 MCS2 Control Register (MCSCR2) 10.2.16 MCS3 Control Register (MCSCR3) 10.2.17 MCS4 Control Register (MCSCR4) 10.2.18 MCS5 Control Register (MCSCR5) 10.2.19 MCS6 Control Register (MCSCR6) 10.2.20 MCS7 Control Register (MCSCR7) 10.3 Operation. 10.3.1 Endian/Access Size Data Alignment. 10.3.2 Description Areas. 10.3.3 Basic Interface. 10.3.4 Synchronous DRAM Interface. 10.3.5 Burst Interface 10.3.6 PCMCIA Interface 10.3.7 Waits between Access Cycles 10.3.8 Arbitration. 10.3.9 Pull-Up 10.3.10 MCS[0] MCS[7] Control.
Section Direct Memory Access Controller (DMAC)
11.1 Overview 11.1.1 Features 11.1.2 Block Diagram
11.2
11.3
11.4
11.5
11.6
11.1.3 Configuration 11.1.4 Register Configuration Register Descriptions. 11.2.1 Source Address Registers (SAR0-SAR3) 11.2.2 Destination Address Registers (DAR0-DAR3) 11.2.3 Transfer Count Registers (DMATCR0-DMATCR3) 11.2.4 Channel Control Registers (CHCR0-CHCR3). 11.2.5 Operation Register (DMAOR). Operation 11.3.1 Transfer Flow. 11.3.2 Transfer Requests. 11.3.3 Channel Priority 11.3.4 Transfer Types 11.3.5 Number Cycle States DREQ Sampling Timing 11.3.6 Source Address Reload Function 11.3.7 Transfer Ending Conditions. Compare Match Timer (CMT) 11.4.1 Overview 11.4.2 Register Descriptions 11.4.3 Operation 11.4.4 Compare Match Examples Use. 11.5.1 Example Transfer between On-Chip IrDA External Memory 11.5.2 Example Transfer between Converter External Memory 11.5.3 Example Transfer between External Memory SCIF Transmitter (Indirect Address On). Usage Notes.
Section Timer (TMU)
12.1 Overview 12.1.1 Features 12.1.2 Block Diagram 12.1.3 Configuration 12.1.4 Register Configuration 12.2 Registers 12.2.1 Timer Output Control Register (TOCR) 12.2.2 Timer Start Register (TSTR). 12.2.3 Timer Control Registers (TCR) 12.2.4 Timer Constant Registers (TCOR). 12.2.5 Timer Counters (TCNT). 12.2.6 Input Capture Register (TCPR2). 12.3 Operation 12.3.1 General Operation
12.3.2 Input Capture Function. 12.4 Interrupts 12.4.1 Status Flag Setting Timing. 12.4.2 Status Flag Clearing Timing 12.4.3 Interrupt Sources Priorities. 12.5 Usage Notes. 12.5.1 Writing Registers 12.5.2 Reading Registers.
Section Realtime Clock (RTC)
13.1 Overview 13.1.1 Features 13.1.2 Block Diagram 13.1.3 Configuration 13.1.4 Register Configuration 13.2 Registers 13.2.1 64-Hz Counter (R64CNT) 13.2.2 Second Counter (RSECCNT). 13.2.3 Minute Counter (RMINCNT) 13.2.4 Hour Counter (RHRCNT) 13.2.5 Week Counter (RWKCNT). 13.2.6 Date Counter (RDAYCNT) 13.2.7 Month Counter (RMONCNT) 13.2.8 Year Counter (RYRCNT) 13.2.9 Second Alarm Register (RSECAR) 13.2.10 Minute Alarm Register (RMINAR) 13.2.11 Hour Alarm Register (RHRAR). 13.2.12 Week Alarm Register (RWKAR) 13.2.13 Date Alarm Register (RDAYAR) 13.2.14 Month Alarm Register (RMONAR) 13.2.15 Control Register (RCR1). 13.2.16 Control Register (RCR2). 13.3 Operation 13.3.1 Initial Settings Registers after Power-On 13.3.2 Setting Time 13.3.3 Reading Time 13.3.4 Alarm Function 13.3.5 Crystal Oscillator Circuit 13.4 Usage Notes. 13.4.1 Register Writing during Count 13.4.2 Realtime Clock (RTC) Periodic Interrupts.
Section Serial Communication Interface (SCI)
viii
14.1 Overview 14.1.1 Features 14.1.2 Block Diagram 14.1.3 Configuration 14.1.4 Register Configuration 14.2 Register Descriptions. 14.2.1 Receive Shift Register (SCRSR). 14.2.2 Receive Data Register (SCRDR) 14.2.3 Transmit Shift Register (SCTSR) 14.2.4 Transmit Data Register (SCTDR) 14.2.5 Serial Mode Register (SCSMR). 14.2.6 Serial Control Register (SCSCR). 14.2.7 Serial Status Register (SCSSR). 14.2.8 Port Control Register (SCPCR)/SC Port Data Register (SCPDR). 14.2.9 Rate Register (SCBRR). 14.3 Operation 14.3.1 Overview 14.3.2 Operation Asynchronous Mode 14.3.3 Multiprocessor Communication. 14.3.4 Synchronous Operation 14.4 Interrupts 14.5 Usage Notes.
Section Smart Card Interface
15.1 Overview 15.1.1 Features 15.1.2 Block Diagram 15.1.3 Configuration 15.1.4 Smart Card Interface Registers. 15.2 Register Descriptions. 15.2.1 Smart Card Mode Register (SCSCMR) 15.2.2 Serial Status Register (SCSSR). 15.3 Operation 15.3.1 Overview 15.3.2 Connections 15.3.3 Data Format. 15.3.4 Register Settings. 15.3.5 Clock 15.3.6 Data Transmission Reception. 15.4 Usage Notes. 15.4.1 Receive Data Timing Receive Margin Asynchronous Mode. 15.4.2 Retransmission (Receive Transmit Modes).
Section Serial Communication Interface with FIFO (SCIF).
16.1 Overview 16.1.1 Features 16.1.2 Block Diagram 16.1.3 Configuration 16.1.4 Register Configuration 16.2 Register Descriptions. 16.2.1 Receive Shift Register (SCRSR). 16.2.2 Receive FIFO Data Register (SCFRDR) 16.2.3 Transmit Shift Register (SCTSR) 16.2.4 Transmit FIFO Data Register (SCFTDR) 16.2.5 Serial Mode Register (SCSMR). 16.2.6 Serial Control Register (SCSCR). 16.2.7 Serial Status Register (SCSSR). 16.2.8 Rate Register (SCBRR). 16.2.9 FIFO Control Register (SCFCR) 16.2.10 FIFO Data Count Register (SCFDR) 16.3 Operation 16.3.1 Overview 16.3.2 Serial Operation 16.4 SCIF Interrupts 16.5 Usage Notes.
Section IrDA
17.1 Overview 17.1.1 Features 17.1.2 Block Diagram 17.1.3 Configuration 17.1.4 Register Configuration 17.2 Register Description 17.2.1 Serial Mode Register (SCSMR). 17.3 Operation Description 17.3.1 Overview 17.3.2 Transmitting 17.3.3 Receiving
Section Function Controller
18.1 Overview 18.2 Register Configuration 18.3 Register Descriptions. 18.3.1 Port Control Register (PACR) 18.3.2 Port Control Register (PBCR) 18.3.3 Port Control Register (PCCR)
18.3.4 18.3.5 18.3.6 18.3.7 18.3.8 18.3.9 18.3.10 18.3.11 18.3.12
Port Control Register (PDCR) Port Control Register (PECR). Port Control Register (PFCR). Port Control Register (PGCR) Port Control Register (PHCR). Port Control Register (PJCR) Port Control Register (PKCR) Port Control Register (PLCR). Port Control Register (SCPCR)
Section Ports
19.1 Overview 19.2 Port 19.2.1 Register Description. 19.2.2 Port Data Register (PADR) 19.3 Port 19.3.1 Register Description. 19.3.2 Port Data Register (PBDR). 19.4 Port 19.4.1 Register Description. 19.4.2 Port Data Register (PCDR). 19.5 Port 19.5.1 Register Description. 19.5.2 Port Data Register (PDDR) 19.6 Port 19.6.1 Register Description. 19.6.2 Port Data Register (PEDR). 19.7 Port 19.7.1 Register Description. 19.7.2 Port Data Register (PFDR) 19.8 Port 19.8.1 Register Description. 19.8.2 Port Data Register (PGDR) 19.9 Port 19.9.1 Register Description. 19.9.2 Port Data Register (PHDR) 19.10 Port 19.10.1 Register Description. 19.10.2 Port Data Register (PJDR). 19.11 Port 19.11.1 Register Description. 19.11.2 Port Data Register (PKDR) 19.12 Port
19.12.1 Register Description. 19.12.2 Port Data Register (PLDR). 19.13 Port. 19.13.1 Register Description. 19.13.2 Port Data Register (SCPDR)
Section Converter
20.1 Overview 20.1.1 Features 20.1.2 Block Diagram 20.1.3 Input Pins 20.1.4 Register Configuration 20.2 Register Descriptions. 20.2.1 Data Registers (ADDRA ADDRD) 20.2.2 Control/Status Register (ADCSR) 20.2.3 Control Register (ADCR). 20.3 Master Interface 20.4 Operation 20.4.1 Single Mode (MULTI 20.4.2 Multi Mode (MULTI 20.4.3 Scan Mode (MULTI 20.4.4 Input Sampling Conversion Time 20.4.5 External Trigger Input Timing 20.5 Interrupts 20.6 Definitions Conversion Accuracy 20.7 Usage Notes. 20.7.1 Setting Analog Input Voltage. 20.7.2 Processing Analog Input Pins 20.7.3 Access Size Read Data
Section Converter
21.1 Overview 21.1.1 Features 21.1.2 Block Diagram 21.1.3 Pins. 21.1.4 Register Configuration 21.2 Register Descriptions. 21.2.1 Data Registers (DADR0/1) 21.2.2 Control Register (DACR). 21.3 Operation
Section Hitachi User Debugging Interface (H-UDI).
22.1 Overview
22.2 Hitachi User Debugging Interface (H-UDI). 22.2.1 Descriptions 22.2.2 Block Diagram 22.3 Register Descriptions. 22.3.1 Bypass Register (SDBPR) 22.3.2 Instruction Register (SDIR) 22.3.3 Boundary Scan Register (SDBSR). 22.4 H-UDI Operation. 22.4.1 Controller. 22.4.2 Reset Configuration 22.4.3 H-UDI Reset. 22.4.4 H-UDI Interrupt 22.4.5 Bypass 22.4.6 Using H-UDI Recover from Sleep Mode 22.5 Boundary Scan. 22.5.1 Supported Instructions 22.5.2 Points Attention 22.6 Usage Notes. 22.7 Advanced User Debugger (AUD)
Section Electrical Characteristics
23.1 Absolute Maximum Ratings. 23.2 Characteristics. 23.3 Characteristics. 23.3.1 Clock Timing 23.3.2 Control Signal Timing 23.3.3 Timing 23.3.4 Basic Timing 23.3.5 Burst Timing 23.3.6 Synchronous DRAM Timing 23.3.7 PCMCIA Timing. 23.3.8 Peripheral Module Signal Timing 23.3.9 H-UDI-Related Timing 23.3.10 Characteristics Measurement Conditions 23.3.11 Delay Time Variation Load Capacitance 23.4 Converter Characteristics 23.5 Converter Characteristics
Appendix Functions
States Specifications Treatment Unused Pins States Access Each Address Space.
xiii
Appendix Memory-Mapped Control Registers
Register Address Register Bits
Appendix Product Lineup Appendix Package Dimensions
Section Overview Functions
SH7709S Features
This single-chip RISC microprocessor that integrates Hitachi-original RISC-type SuperH architecture core that on-chip multiplier, cache memory, memory management unit (MMU) well peripheral functions required system configuration such timer, realtime clock, interrupt controller, serial communication interface. This includes data protection, virtual memory, other functions provided incorporating into SuperH series microprocessor (SH-1 SH-2). High-speed data transfers performed on-chip direct memory access controller (DMAC) external memory access support function enables direct connection different types memory. SH7709S microprocessor also supports infrared communication function, converter, converter. powerful built-in power management function keeps power consumption low, even during highspeed operation. This times frequency system operating speed, making optimum electrical devices such PDAs that require both high speed power. features this listed table 1.1. specifications shown table 1.2. Note: SuperH trademark Hitachi, Ltd.
Table
Item
SH7709S Features
Features Original Hitachi SuperH architecture Object code level compatible with SH-1, SH-2 SH-3 (SH7708) 32-bit internal data General-register files Sixteen 32-bit general registers (eight 32-bit shadow registers) Eight 32-bit control registers Four 32-bit system registers RISC-type instruction Instruction length: 16-bit fixed length improved code efficiency Load-store architecture Delayed branch instructions Instruction based language Instruction execution time: instruction/cycle basic instructions Logical address space: Gbytes Space identifier ASID: bits, logical address space Five-stage pipeline Clock mode: input clock selected from external input (EXTAL CKIO) crystal oscillator. Three types clocks generated: clock: 1-24 times input clock, maximum clock: times input clock, maximum 66.67 Peripheral clock: 1/4-4 times input clock, maximum 33.34 Power-down modes: Sleep mode Standby mode Module standby mode One-channel watchdog timer Gbytes address space, address spaces (ASID bits) Page unit sharing Supports multiple page sizes: kbytes 128-entry, 4-way associative Supports software selection replacement method random-replacement algorithms Contents directly accessible address mapping
Clock pulse generator (CPG)
Memory management unit (MMU)
Table
Item
SH7709S Features (cont)
Features 16-kbyte cache, mixed instruction/data entries, 4-way associative, 16-byte block length Write-back, write-through, replacement algorithm 1-stage write-back buffer Maximum ways cache locked external interrupt pins (NMI, IRQ5-IRQ0, PINT15 PINT0) On-chip peripheral interrupts: priority levels each module break channels Addresses, data values, type access, data size break conditions Supports sequential break function Physical address space divided into areas (area areas each maximum Mbytes, with following features settable each area: size bits) Number wait cycles (also supports hardware wait function) Setting type space enables direct connection SRAM, Synchronous DRAM, burst Supports PCMCIA interface channels) Outputs chip select signal (CS0, CS2-CS6) corresponding area Synchronous DRAM refresh function Programmable refresh interval Support self-refresh mode Synchronous DRAM burst access function Usable either little endian machine E10A emulator support JTAG-standard assignment Realtime branch address trace 1-kB on-chip fast emulation program execution 3-channel auto-reload-type 32-bit timer Input capture function types counter input clocks selected Maximum resolution:
Cache memory
Interrupt controller (INTC) User break controller (UBC)
state controller (BSC)
Hitachi debugging Interface (H-UDI) Timer (TMU)
Table
Item
SH7709S Features (cont)
Features Built-in clock, calendar functions, alarm functions On-chip 32-kHz crystal oscillator circuit with maximum resolution (interrupt cycle) 1/256 second Asynchronous mode clock synchronous mode selected Full-duplex communication Supports smart card interface 16-byte FIFO transmission/reception transferred IrDA: interface based 16-byte FIFO transmission/reception transferred Hardware flow control channels Burst mode cycle-steal mode Twelve 8-bit ports bits LSB, channels Conversion time: Input range: 0-Vcc (max. bits LSB, channels Conversion time: Output range: 0-Vcc (max.
Power Supply Voltage Operating Internal Frequency 2.0±0.15V* 200MHz 1.9±0.15V 167MHz
Realtime clock (RTC)
Serial communi- cation interface (SCI0/SCI) Serial communi- cation interface (SCI1/IrDA) Serial communi- cation interface (SCI2/SCIF) Direct memory access controller (DMAC) port converter (ADC) converter (DAC) Product lineup
Abbr.
Model Name
Packege
SH7709S 3.3±0.3V
HD6417709SHF200 208-pin plastic HQFP (FP-208E) HD6417709SF167 208-pin plastic LQFP (FP-208C)
HD6417709SBP167 240-pin (BP-240A) 1.8+0.25V 1.8-0.15V 133MHz HD6417709SF133 208-pin plastic LQFP (FP-208C)
Table
SH7709S Features (cont)
Product lineup
Abbr.
Power Supply Voltage Operating Internal Frequency Model Name 1.8+0.25V 1.8-0.15V 1.7+0.25V 1.7-0.15V 133MHz 100MHz
Packege
SH7709S 3.3±0.3V
HD6417709SBP133 240-pin (BP-240A) HD6417709SF100 208-pin plastic LQFP (FP-208C)
HD6417709SBP100 240-pin (BP-240A) (+0.15, -0.1)V when IRLS interrupt used.
Table
Item
Characteristics
Characteristics I/O: ±0.3 Internal: ±0.15 (200 model)*, 1.9±0.15 (167 model), (+0.25, -0.15) (133 model), 1.7(+0.25, -0.15)V (100 model) Internal frequency: maximum MHz(200 model), (167 model) 133.34 (133 model), (100 model); external frequency: maximum 66.67 0.25-µm CMOS/5-layer metal
Power supply voltage
Operating frequency
Process
(+0.15, -0.1)V when IRLS interrupt used.
Block Diagram
SH-3
Peripheral
CACHE
BRIDGE
ASERAM IrDA
SCIF DMAC Peripheral
INTC
CPG/WDT
External interface
port
Legend: ADC: ASERAM: AUD: BSC: CACHE: CCN: CMT: CPG/WDT: CPU: DAC: DMAC: H-UDI:
converter memory Advanced user debugger state controller Cache memory Cache memory controller Compare match timer Clock pulse generator/watchdog timer Central processing unit converter Direct memory access controller Hitachi user-debugging interface
INTC: IrDA: MMU: RTC: SCI: SCIF: TLB: TMU: UBC:
Interrupt controller Serial communicatiion interface (with IrDA) Memory management unit Realtime clock Serial communication interface (with smart card interface) Serial communication interface (with FIFO) Address translation buffer Timer unit User break controller
Figure Block Diagram
1.3.1
Description
Assignment
EXTAL XTAL AUDCK/PTH[6] VCC-PLL2 CAP2 VSS-PLL2 VSS-PLL1 CAP1 VCC-PLL1 IRLS0/PTF[0]/PINT[8] IRLS1/PTF[1]/PINT[9] IRLS2/PTF[2]/PINT[10] IRLS3/PTF[3]/PINT[11] TCK/PTF[4]/PINT[12] TDI/PTF[5]/PINT[13] TMS/PTF[6]/PINT[14] TRST/PTF[7]/PINT[15] AUDATA[0]/PTG[0] AUDATA[1]/PTG[1] AUDATA[2]/PTG[2] AUDATA[3]/PTG[3] PTG[4]/CKIO2 ASEBRKAK/PTG[5] ASEMD0/PTG[6] IOIS16/PTG[7] ADTRG/PTH[5] RESEWAIT BREQ BACK TDO/PTE[0] PTE[1] RAS3U/PTE[2] PTE[3] PTE[6] DACK1/PTD[7] DACK0/PTD[5] PTJ[5] PTJ[4] VCCQ CASU/PTJ[3] VSSQ CASL/PTJ[2] PTJ[1] RAS3L/PTJ[0] CKE/PTK[5]
STATUS0/PTJ[6] STATUS1/PTJ[7] TCLK/PTH[7] IRQOUT VSSQ CKIO VCCQ TxD0/SCPT[0] SCK0/SCPT[1] TxD1/SCPT[2] SCK1/SCPT[3] TxD2/SCPT[4] SCK2/SCPT[5] RTS2/SCPT[6] RxD0/SCPT[0] RxD1/SCPT[2] RXD2/SCPT[4] CTS2/IRQ5/SCPT[7] MCS[7]/PTC[7]/PINT[7] MCS[6]/PTC[6]/PINT[6] MCS[5]/PTC[5]/PINT[5] MCS[4]/PTC[4]/PINT[4] VSSQ WAKEUP/PTD[3] VCCQ RESETOUT/PTD[2] MCS[3]/PTC[3]/PINT[3] MCS[2]/PTC[2]/PINT[2] MCS[1]/PTC[1]/PINT[1] MCS[0]/PTC[0]/PINT[0] DRAK0/PTD[1] DRAK1/PTD[0] DREQ0/PTD[4] DREQ1/PTD[6] RESETP AVSS AN[0]/PTL[0] AN[1]/PTL[1] AN[2]/PTL[2] AN[3]/PTL[3] AN[4]/PTL[4] AN[5]/PTL[5] AVCC AN[6]/DA[1]/PTL[6] AN[7]/DA[0]/PTL[7] AVSS
SH7709S FP-208C FP-208E (Top view)
INDEX MARK
CE2B/PTE[5] CE2A/PTE[4] CS6/CE1B CS5/CE1A/PTK[3] CS4/PTK[2] CS3/PTK[1] CS2/PTK[0] VCCQ CS0/MCS0 VSSQ AUDSYNC/PTE[7] RD/WR WE3/DQMUU/ICIOWR/PTK[7] WE2/DQMUL/ICIORD/PTK[6] WE1/DOMLU/WE WE0/DQMLL BS/PTK[4] VCCQ VSSQ VCCQ VSSQ VCCQ VSSQ
VCC-RTC XTAL2 EXTAL2 VSS-RTC IRQ0/IRL0/PTH[0] IRQ1/IRL1/PTH[1] IRQ2/IRL2/PTH[2] IRQ3/IRL3/PTH[3] IRQ4/PTH[4] D31/PTB[7] D30/PTB[6] D29/PTB[5] D28/PTB[4] D27/PTB[3] D26/PTB[2] VSSQ D25/PTB[1] VCCQ D24/PTB[0] D23/PTA[7] D22/PTA[6] D21/PTA[5] D20/PTA[4] D19/PTA[3] D18/PTA[2] D17/PTA[1] D16/PTA[0] VSSQ VCCQ VSSQ VCCQ
Figure Assignment (FP-208C, FP-208E)
SH7709S BP-240A (Top view)
Note: area enclosed broken lines inner view.
Figure Assignment (BP-240A)
1.3.2 Table
Function SH7709S Function
Number Pins FP-208C FP-208E BP-240A Name Vcc-RTC XTAL2 EXTAL2 Vss-RTC IRQ0/IRL0/PTH[0] IRQ1/IRL1/PTH[1] IRQ2/IRL2/PTH[2] IRQ3/IRL3/PTH[3] IRQ4/PTH[4] D31/PTB[7] D30/PTB[6] D29/PTB[5] D28/PTB[4] D27/PTB[3] D26/PTB[2] VssQ D25/PTB[1] VccQ D24/PTB[0] D23/PTA[7] D22/PTA[6] D21/PTA[5]
Description Clock mode setting Clock mode setting power supply (*4) On-chip crystal oscillator On-chip crystal oscillator power supply Nonmaskable interrupt request External interrupt request/input port External interrupt request/input port External interrupt request/input port External interrupt request/input port External interrupt request/input port Data input/output port Data input/output port Data input/output port Data input/output port Data input/output port Data input/output port Input/output power supply Data input/output port Input/output power supply (3.3 Data input/output port Data input/output port Data input/output port Data input/output port
Table
SH7709S Function (cont)
Number Pins FP-208C FP-208E BP-240A Name D20/PTA[4] D19/PTA[3] D18/PTA[2] D17/PTA[1] D16/PTA[0] VssQ VccQ VssQ VccQ Description Data input/output port Power supply Power supply Data input/output port Power supply (1.9 V/1.8 Power supply Data input/output port Data input/output port Data input/output port Input/output power supply Data Input/output power supply (3.3 Data Data Data Data Data Data Data Data Data Input/output power supply Data Input/output power supply (3.3 Data Data Data Data Data Address
Table
SH7709S Function (cont)
Number Pins FP-208C FP-208E BP-240A Name VssQ VccQ VssQ VccQ Description Address Address Address Input/output power supply Address Input/output power supply (3.3 Address Address Address Address Address Address Address Address Address Input/output power supply Address Input/output power supply (3.3 Address Address Address Address Address Address Address Power supply Power supply Address Power supply Power supply
Table
SH7709S Function (cont)
Number Pins FP-208C FP-208E BP-240A Name VssQ VccQ BS/PTK[4] WE0/DQMLL WE1/DQMLU/WE WE2/DQMUL/ICIORD/ PTK[6] Description Address Input/output power supply Address Input/output power supply (3.3 Address cycle start signal input/output port Read strobe D7-D0 select signal (SDRAM) D15-D8 select signal (SDRAM) D23-D16 select signal (SDRAM) PCMCIA input/output port read input/output port D31-D24 select signal (SDRAM) PCMCIA input/output port write input/output port Read/write synchronous input/output port Input/output power supply Chip select 0/mask chip select Input/output power supply (3.3 Chip select input/output port Chip select input/output port Chip select input/output port Chip select 5/CE1 (area PCMCIA) input/output port Chip select 6/CE1 (area PCMCIA)
WE3/DQMUU/ICIOWR/ PTK[7]
RD/WR AUDSYNC/PTE[7] VssQ CS0/MCS[0] VccQ CS2/PTK[0] CS3/PTK[1] CS4/PTK[2] CS5/CE1A/PTK[3] CS6/CE1B
Table
SH7709S Function (cont)
Number Pins FP-208C FP-208E BP-240A Name CE2A/PTE[4] CE2B/PTE[5] CKE/PTK[5] RAS3L/PTJ[0] PTJ[1] CASL/PTJ[2] VssQ CASU/PTJ[3] VccQ PTJ[4] PTJ[5] DACK0/PTD[5] DACK1/PTD[7] PTE[6] PTE[3] RAS3U/PTE[2] Description Area PCMCIA card enable input/output port Area PCMCIA card enable input/output port enable (SDRAM) input/output port Lower Mbytes address (SDRAM) input/output port Input/output port Lower Mbytes address (SDRAM) input/output port Input/output power supply Lower Mbytes address (SDRAM) input/output port Input/output power supply (3.3 Input/output port Input/output port acknowledge input/output port acknowledge input/output port Input/output port Input/output port Upper Mbytes address (SDRAM) input/output port Input/output port Test data output input/output port acknowledge request
PTE[1] TDO/PTE[0] BACK BREQ
Table
SH7709S Function (cont)
Number Pins FP-208C FP-208E BP-240A Name WAIT RESEADTRG/PTH[5] IOIS16/PTG[7] ASEMD0/PTG[6] ASEBRKAK/PTG[5] PTG[4]/CK102 AUDATA[3]/PTG[3] AUDATA[2]/PTG[2] AUDATA[1]/PTG[1] AUDATA[0]/PTG[0] TRST/PTF[7]/PINT[15] TMS/PTF[6]/PINT[14] TDI/PTF[5]/PINT[13] TCK/PTF[4]/PNT[12] IRLS3/PTF[3]/ PINT[11] IRLS2/PTF[2]/ PINT[10] IRLS1/PTF[1]/PINT[9] IRLS0/PTF[0]/PINT[8] Description Hardware wait request Manual reset request Analog trigger input port Area 16-bit input/output input port mode* input port break acknowledge input port Input port clock output data input port data input port Power supply Power supply data input port Power supply Power supply data input port Test reset input port port interrupt Test mode switch input port port interrupt Test data input input port port interrupt Test clock input port port interrupt External interrupt request input port port interrupt External interrupt request input port port interrupt External interrupt request input port port interrupt External interrupt request input port port interrupt
Table
SH7709S Function (cont)
Number Pins FP-208C FP-208E BP-240A Name Vcc-PLL1 CAP1 Vss-PLL1 Vss-PLL2 CAP2 Vcc-PLL2
Description Clock mode setting PLL1 power supply PLL1 external capacitance PLL1 power supply PLL2 power supply PLL2 external capacitance PLL2 power supply clock input port Power supply Power supply Power supply Power supply Power supply Clock oscillator External clock crystal oscillator Processor status input/output port Processor status input/output port clock input/output input/output port Interrupt request notification Input/output power supply System clock input/output Power supply (3.3 Transmit data output port Serial clock input/output port Transmit data output port Serial clock input/output port
AUDCK/PTH[6] XTAL EXTAL STATUS0/PTJ[6] STATUS1/PTJ[7] TCLK/PTH[7] IRQOUT VssQ CKIO VccQ TxD0/SCPT[0] SCK0/SCPT[1] TxD1/SCPT[2] SCK1/SCPT[3]
Table
SH7709S Function (cont)
Number Pins FP-208C FP-208E BP-240A Name TxD2/SCPT[4] SCK2/SCPT[5] RTS2/SCPT[6] RxD0/SCPT[0] RxD1/SCPT[2] RxD2/SCPT[4] CTS2/IRQ5/SCPT[7] MCS[7]/PTC[7]/PINT[7] MCS[6]/PTC[6]/PINT[6] MCS[5]/PTC[5]/PINT[5] MCS[4]/PTC[4]/PINT[4] VssQ WAKEUP/PTD[3] VccQ RESETOUT/PTD[2] MCS[3]/PTC[3]/PINT[3] MCS[2]/PTC[2]/PINT[2] MCS[1]/PTC[1]/PINT[1] Description Transmit data output port Serial clock input/output port Transmit request input/output port Transmit data output port Transmit data output port Power supply Power supply Transmit data output port Power supply Power supply Transmit clear external interrupt request input port
Mask chip select input/output port port interrupt Mask chip select input/output port port interrupt Mask chip select input/output port port interrupt Mask chip select input/output port port interrupt Input/output power supply Standby mode interrupt request notification input/output port Input/output power supply (3.3 Reset output input/output port
Mask chip select input/output port port interrupt Mask chip select input/output port port interrupt Mask chip select input/output port port interrupt
Table
SH7709S Function (cont)
Number Pins FP-208C FP-208E BP-240A Name MCS[0]/PTC[0]/PINT[0] DRAK0/PTD[1] DRAK1/PTD[0] DREQ0/PTD[4] DREQ1/PTD[6] RESETP AVss AN[0]/PTL[0] AN[1]/PTL[1] AN[2]/PTL[2] AN[3]/PTL[3] AN[4]/PTL[4] AN[5]/PTL[5] AVcc AN[6]/DA[1]/PTL[6] AN[7]/DA[0]/PTL[7] AVss Description
Mask chip select input/output port port interrupt request acknowledge input/output port request acknowledge input/output port request input port request input port Power-on reset request Chip activate hardware standby request Area width setting Area width setting Endian setting Analog power supply converter input input port converter input input port converter input input port converter input input port converter input input port converter input input port Analog power supply (3.3 converter input input port converter input input port Analog power supply
Notes: Must connected power supply even when used. Must connected power supply even when on-chip circuits used (except hardware standby mode). Except hardware standby mode, power supply pins must connected system power supply. (Supply power constantly.) hardware standby mode, power must supplied least -RTC -RTC. power being supplied power supply pins other than -RTC -RTC, hold low. model, model, model, model.
When this used user system alone, without emulator H-UDI, hold this high level. W17, W18, W19, V18, V19, B19, A19, B18, A18, A17, pins. connect anything these pins.
Section
2.1.1
Register Configuration
Privileged Mode Banks
Processor Modes: There processor modes: user mode privileged mode. SH7709S normally operates user mode, enters privileged mode when exception occurs interrupt accepted. There three kinds registers-general registers, system registers, control registers-and registers that accessed differ processor modes. General Registers: There general registers, designated R15. General registers banked registers which switched processor mode change. privileged mode, register bank (RB) status register (SR) defines which banked register accessed general registers, which accessed only through load control register (LDC) store control register (STC) instructions. When registers comprising BANK1 general registers R0_BANK1- R7_BANK1 non-banked general registers R8-R15 function general register set, with registers comprising BANK0 general registers R0_BANK0-R7_BANK0 accessed only LDC/STC instructions. When BANK0 general registers R0_BANK0-R7_BANK0 nonbanked general registers R8-R15 function general register set, with BANK1 general registers R0_BANK1- R7_BANK1 accessed only LDC/STC instructions. user mode, registers comprising bank general registers R0_BANK0-R7_BANK0 non-banked registers R8-R15 accessed general registers R0-R15, bank general registers R0_BANK1- R7_BANK1 cannot accessed. Control Registers: Control registers comprise global base register (GBR) status register (SR) which accessed both processor modes, saved status register (SSR), saved program counter (SPC), vector base register (VBR) which only accessed privileged mode. Some bits status register (such bit) only accessed privileged mode. System Registers: System registers comprise multiply accumulate registers (MACL/MACH), procedure register (PR), program counter (PC). Access these registers does depend processor mode. register configuration each mode shown figures 2.2. Switching between user mode privileged mode controlled processor mode (MD) status register.
R0_BANK0*1, R1_BANK0*2 R2_BANK0*2 R3_BANK0*2 R4_BANK0*2 R5_BANK0*2 R6_BANK0*2 R7_BANK0*2 MACH MACL
User mode register configuration
Notes:
functions index register indexed register-indirect addressing mode indexed GBR-indirect addressing mode. Banked register
Figure User Mode Register Configuration
R0_BANK1*1, R1_BANK1*2 R2_BANK1*2 R3_BANK1*2 R4_BANK1*2 R5_BANK1*2 R6_BANK1*2 R7_BANK1*2 MACH MACL R0_BANK0*1, R1_BANK0*3 R2_BANK0*3 R3_BANK0*3 R4_BANK0*3 R5_BANK0*3 R6_BANK0*3 R7_BANK0*3
R0_BANK0*1, R1_BANK0*3 R2_BANK0*3 R3_BANK0*3 R4_BANK0*3 R5_BANK0*3 R6_BANK0*3 R7_BANK0*3 MACH MACL R0_BANK1*1, R1_BANK1*2 R2_BANK1*2 R3_BANK1*2 R4_BANK1*2 R5_BANK1*2 R6_BANK1*2 R7_BANK1*2
Notes: functions index register indexed register-indirect addressing mode indexed GBRindirect addressing mode. Banked register When register register accessed general use. When only accessed with LDC/STC instruction. Banked register When register register accessed general use. When only accessed with LDC/STC instruction.
Privileged mode register configuration
Privileged mode register configuration
Figure Privileged Mode Register Configuration
Register values after reset shown table 2.1. Table
Type General registers Control registers
Initial Register Values
Registers Initial Value* Undefined 1111 (H'F), reserved bits others undefined Undefined H'00000000 Undefined H'A0000000
GBR, SSR, System registers MACH, MACL,
Note: Register values initialized power-on reset manual reset.
2.1.2
General Registers
There general registers, designated (figure 2.3). General registers banked registers, with different R0-R7 register bank (R0_BANK0-R7_BANK0 R0_BANK1-R7_BANK1) being accessed according processor mode. details, figure User Mode Register Configulation figure Privileged Mode Register Configulation. general register configuration shown figure 2.3.
General Registers R0*1, R1*2 R2*2 R3*2 R4*2 R5*2 R6*2 R7*2 Notes: functions index register indexed register-indirect addressing mode indexed GBR-indirect addressing mode. some instructions, only used source register destination register. R0-R7 banked registers. privileged mode, SR.RB specifies which banked registers accessed general registers (R0_BANK0-R7_BANK0 R0_BANK1-R7_BANK1).
Figure General Registers
2.1.3
System Registers
System registers accessed instructions. When exception occurs, contents program counter (PC) saved saved program counter (SPC). contents restored instruction used exception handling. There four system registers, follows. Multiply accumulate high register (MACH) Multiply accumulate register (MACL) Procedure register (PR) Program counter (PC)
system register configuration shown figure 2.4.
System Registers MACH MACL Multiply Accumulate High Registers (MACH/L) Store results multiply-and-accumulate operations.
Procedure Register (PR) Stores return address exiting subroutine procedure. Program Counter (PC) Indicates address four addresses (two instructions) ahead currently executing instruction. Initialized H'A0000000 reset.
Figure System Registers 2.1.4 Control Registers
Control registers accessed privileged mode using instructions. register also accessed user mode. There five control registers, follows: Status register (SR) Saved status register (SSR) Saved program counter (SPC) Global base register (GBR) Vector base register (VBR)
Saved Status Register (SSR) Stores current value time exception indicate processor status return instruction stream from exception handler. Saved Program Counter (SPC) Stores current value time exception indicate return address completion exception handling. Global Base Register (GBR) Stores base address GBR-indirect addressing mode. GBR-indirect addressing mode used on-chip supporting module register area data transfers logic operations. register also accessed user mode. contents undefined after reset. Vector Base Register (VBR) Stores base address exception handling vector area. Initialized H'0000000 reset.
Status 0---------------------0 register (SR)
Processor operation mode bit: Indicates processor operation mode follows: Privileged mode; User mode generation exception interrupt initialized reset. Register bank bit: Determines bank general registers R0-R7 used processing mode. R0_BANK1-R7_BANK1 R8-R15 general registers, R0_BANK0- R7_BANK0 accessed LDC/STC instructions. R0_BANK0-R7_BANK0 R8-R15 general registers, R0_BANK1- R7_BANK1 accessed LDC/STC instructions. generation exception interrupt initialized reset. Block Exceptions interrupts suppressed. section Exception Handling, details. Exceptions interrupts accepted. generation exception interrupt initialized reset. Cache lock When cache lock function used. bits: Used DIV0S/U DIV1 instructions. I3-I0 bits: Interrupt mask bits: 4-bit field indicating interrupt request mask level. I3-I0 change interrupt acceptance level when interrupt generated. Initialized B'1111 reset. bit: Used instruction. bit: Used MOVT, CMP/cond, TAS, TST, SETT, CLRT, instructions indicate true false (0). Used ADDV/C, SUBV/C, DIV0U/S, DIV1, NEGC, SHAR/L, SHLR/L, ROTR/L, ROTCR/L instructions indicate carry, borrow, overflow, underflow. bits: These bits always read write value should always Note: bits cleared special instructions user mode. Their values undefined after reset. other bits read written privileged mode.
Figure Register Overview, Control Registers
2.2.1
Data Formats
Data Format Registers
Register operands always longwords bits, figure 2.6). When memory operand only byte bits) word bits), sign-extended into longword when loaded into register.
Longword
Figure Longword 2.2.2 Data Format Memory
Memory data formats classified into bytes, words, longwords. Memory accessed 8-bit byte, 16-bit word, 32-bit longword form. memory operand less than bits length sign-extended before being stored register. word operand must accessed starting from word boundary (even address 2-byte unit: address 2n), longword operand starting from longword boundary (even address 4-byte unit: address 4n). address error will result this rule observed. byte operand accessed from address. Big-endian little-endian byte order selected data format. endian mode should with external power-on reset. Big-endian mode selected when low, little-endian when high. endian mode cannot changed dynamically. positions numbered left right from most-significant least-significant. Thus, 32-bit longword, leftmost bit, most significant rightmost bit, least significant bit. data format memory shown figure 2.7.
Address Address Address Address
Address Address Address Address Address Byte0 Byte1 Byte2 Byte3 Byte3 Byte2 Byte1 Byte0 Address Word0 Word1 Word1 Word0 Address Longword Longword Big-endian mode Little-endian mode
Address Address Address
Figure Data Format Memory
2.3.1
Instruction Features
Execution Environment
Data Length: SH7709S instruction implemented with fixed-length 16-bit wide instructions executed pipelined sequence with single-cycle execution most instructions. operations executed 32-bit longword units. Memory accessed 8-bit byte, 16-bit word, 32-bit longword units, with byte word units sign-extended into 32-bit longwords. Literals sign-extended arithmetic operations (MOV, ADD, CMP/EQ instructions) zero-extended logical operations (TST, AND, instructions). Load/Store Architecture: SH7709S features load-store architecture which basic operations executed registers. Operations requiring memory access executed registers following register loading, except bit-manipulation operations such logical functions, which executed directly memory. Delayed Branching: Unconditional branching implemented delayed branch operations. Pipeline disruptions branching minimized execution instruction following delayed branch instruction prior branching. Conditional branch instructions kinds, delayed normal. TRGET
;ADD executed prior branching TRGET
bit: status register (SR) used indicate result compare operations, read TRUE/FALSE condition determining conditional branch taken not. improve processing speed, logic state modified only specific operations. example used sequence operations shown below. CMP/EQ TRGET modified operation when ;branch taken TRGET when
Literals: Byte-length literals inserted directly into instruction code immediate data. maintain 16-bit fixed-length instruction code, word longword literals stored table main memory rather than inserted directly into instruction code. memory table accessed instruction using PC-relative addressing with displacement, follows: MOV.W @(disp, PC),
Absolute Addresses: with word longword literals, absolute addresses must also stored table main memory. value absolute address transferred register operand access specified indexed register-indirect addressing, with absolute address loaded (like word longword immediate data) during instruction execution. 16-Bit 32-Bit Displacements: same way, 16-bit 32-bit displacements also must stored table main memory. Exactly like absolute addresses, displacement value transferred register operand access specified indexed register-indirect addressing, loading displacement (like word longword immediate data) during instruction execution.
2.3.2
Addressing Modes
Addressing modes effective address calculation methods shown table 2.2. Table
Addressing Mode
Addressing Modes Effective Addresses
Instruction Format Effective Address Calculation Method Effective address register (Operand register contents.) Effective address register contents. After instruction execution Byte: Word: Longword: Calculation Formula
Register direct Register indirect
Register @Rn+ indirect with post-increment
Effective address register contents. constant added after instruction execution: byte operand, word operand, longword operand. 1/2/4 1/2/4
Register @-Rn indirect with pre-decrement
Effective address register contents, decremented constant beforehand: byte operand, word operand, longword operand. 1/2/4 1/2/4 1/2/4
Byte: Word: Longword: (Instruction executed with after calculation)
Table
Addressing Mode Register indirect with displacement
Addressing Modes Effective Addresses (cont)
Instruction Format Effective Address Calculation Method @(disp:4, Effective address register contents with 4-bit displacement disp added. After disp zero-extended, multiplied (byte), (word), (longword), according operand size.
disp (zero-extended) 1/2/4 disp 1/2/4
Calculation Formula Byte: disp Word: disp Longword: disp
Indexed @(R0, Effective address register register indirect contents. indirect with displacement @(disp:8, GBR) Effective address register contents with 8-bit displacement disp added. After disp zero-extended, multiplied (byte), (word), (longword), according operand size.
disp (zero-extended) 1/2/4 disp 1/2/4
Byte: disp Word: disp Longword: disp
Indexed @(R0, indirect GBR)
Effective address register contents.
Table
Addressing Mode PC-relative with displacement
Addressing Modes Effective Addresses (cont)
Instruction Format Effective Address Calculation Method @(disp:8, Effective address register contents with 8-bit displacement disp added. After disp zero-extended, multiplied (word), (longword), according operand size. With longword operand, lower bits masked.
(for longword) H'FFFFFFFC disp (zero-extended) disp PC&H'FFFFFFFC disp
Calculation Formula Word: disp Longword: H'FFFF FFFC disp
PC-relative
disp:8
Effective address register contents with disp 8-bit displacement disp added after being sign-extended multiplied
disp (sign-extended) disp
disp:12
Effective address register contents with disp 12-bit displacement disp added after being sign-extended multiplied
disp (sign-extended) disp
Table
Addressing Mode PC-relative
Addressing Modes Effective Addresses (cont)
Instruction Format Effective Address Calculation Method Effective address register contents. Calculation Formula
Immediate
#imm:8 #imm:8 #imm:8
8-bit immediate data TST, AND, instruction zero-extended. 8-bit immediate data MOV, ADD, CMP/EQ instruction sign-extended.
8-bit immediate data TRAPA instruction zero-extended multiplied
Note: addressing modes below that displacement (disp), assembler descriptions this manual show value before scaling performed according operand size. This done clarify operation Refer relevant assembler notation rules actual assembler descriptions. (disp:4, Register indirect with displacement (disp:8, indirect with displacement (disp:8, PC-relative with displacement disp:8, disp:12; PC-relative
2.3.3
Instruction Formats
Table explains meaning instruction formats source destination operands. meaning operands depends operation code. following symbols used. xxxx: mmmm: nnnn: iiii: dddd: Table Operation code Source register Destination register Immediate data Displacement Instruction Formats
Source Operand xxxx format xxxx nnnn xxxx xxxx Control register system register Control register system register format xxxx mmmm xxxx xxxx mmmm: register direct mmmm: register indirect with postincrement mmmm: register indirect mmmm: PCrelative using xxxx xxxx xxxx nnnn: register direct nnnn: register direct nnnn: register indirect with pre-decrement Control register system register Control register system register MOVT Destination Operand Instruction Example
Instruction Format format
MACH,Rn STC.L SR,@-Rn Rm,SR LDC.L @Rm+,SR BRAF
Table
Instruction Formats (cont)
Source Operand nnnn mmmm xxxx mmmm: register direct mmmm: register indirect mmmm: register indirect with postincrement (multiply-andaccumulate operation) nnnn: register indirect with postincrement (multiply-andaccumulate operation) mmmm: register indirect with postincrement mmmm: register direct mmmm: register direct nnnn: register direct nnnn: register indirect with pre-decrement nnnn: indexed register indirect (register direct) nnnndddd: register indirect with displacement MOV.L @Rm+,Rn MOV.L Rm,@-Rn MOV.L Rm,@(R0,Rn) MOV.B @(disp,Rm),R0 MOV.B R0,@(disp,Rn) Destination Operand nnnn: register direct nnnn: register indirect MACH,MACL Instruction Example Rm,Rn
Instruction Format format xxxx
MOV.L Rm,@Rn MAC.W @Rm+,@Rn+
format xxxx format xxxx xxxx nnnn dddd xxxx mmmm dddd
mmmmdddd: register indirect with displacement (register direct)
Table
Instruction Formats (cont)
Source Operand nnnn mmmm dddd mmmm: register direct Destination Operand nnnndddd: register indirect with displacement nnnn: register direct (register direct) dddddddd: indirect with displacement (register direct) Instruction Example MOV.L Rm,@(disp,Rn)
Instruction Format format xxxx
mmmmdddd: register indirect with displacement format xxxx xxxx dddd dddd dddddddd: indirect with displacement (register direct)
MOV.L @(disp,Rm),Rn MOV.L @(disp,GBR),R0 MOV.L R0,@(disp,GBR)
dddddddd: PC-relative with displacement dddddddd: PC-relative format xxxx format xxxx format xxxx xxxx iiii iiii iiiiiiii: immediate iiiiiiii: immediate format xxxx nnnn iiii iiii iiiiiiii: immediate nnnn dddd dddd dddd dddd dddd dddddddddddd: PC-relative dddddddd: PC-relative with displacement iiiiiiii: immediate
MOVA @(disp,PC),R0 label
label (label disp MOV.L @(disp,PC),Rn AND.B #imm, @(R0,GBR) #imm,R0 TRAPA #imm #imm,Rn
nnnn: register direct Indexed indirect (register direct) nnnn: register direct
Note: multiply-and-accumulate instruction, nnnn source register.
2.4.1
Instruction
Instruction Classified Function
SH7709S instruction includes basic instruction types, listed table 2.4. Table Classification Instructions
Operation Code MOVA MOVT SWAP XTRCT Arithmetic operations ADDC ADDV CMP/cond DIV1 DIV0S DIV0U DMULS DMULU EXTS EXTU Function Data transfer Effective address transfer transfer Swap upper lower bytes Extraction middle linked registers Binary addition Binary addition with carry Binary addition with overflow check Comparison Division Initialization signed division Initialization unsigned division Signed double-precision multiplication Unsigned double-precision multiplication Decrement test Sign extension Zero extension Multiply-and-accumulate operation, double-precision multiply-and-accumulate operation Instructions
Classification Types Data transfer
Table
Classification Instructions (cont)
Operation Code Function Double-precision multiplication bits) Signed multiplication bits) Unsigned multiplication bits) Negation Negation with borrow Binary subtraction Binary subtraction with borrow Binary subtraction with underflow check Logical inversion Logical Memory test Logical Exclusive One-bit left rotation One-bit right rotation One-bit left rotation with One-bit right rotation with One-bit arithmetic left shift One-bit arithmetic right shift One-bit logical left shift n-bit logical left shift One-bit logical right shift n-bit logical right shift Dynamic arithmetic shift Dynamic logical shift Instructions
Classification Types Arithmetic operations (cont)
MULS MULU NEGC SUBC SUBV
Logic operations
Shift
ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL SHLLn SHLR SHLRn SHAD SHLD
Table
Classification Instructions (cont)
Operation Code BRAF BSRF Function Conditional branch, delayed conditional branch Conditional branch, delayed conditional branch Unconditional branch Unconditional branch Branch subroutine procedure Branch subroutine procedure Unconditional branch Branch subroutine procedure Return from subroutine procedure register clear Clear Clear Load control register Load system register Load operation Prefetch data cache Return from exception handling Shift power-down mode Store from control register Store from system register Trap exception handling Instructions
Classification Types Branch
System control
CLRMAC CLRT CLRS LDTLB PREF SETS SETT SLEEP TRAPA
Total:
Table lists SH7709S instruction code formats. Table
Item Instruction mnemonic
Instruction Code Format
Format OP.Sz SRC,DEST Explanation Operation code Size SRC: Source DEST: Destination Source register Destination register imm: Immediate data disp: Displacement mmmm: Source register nnnn: Destination register 0000: 0001: 1111: iiii: Immediate data dddd: Displacement* Direction transfer Memory operand Flag bits Logical each Logical each Exclusive each Logical each n-bit shift Indicates whether privileged mode applies Value when wait states inserted execution cycles listed table minimums. actual number cycles increased cases such followsing: When contention occurs between instruction fetches data access When destination register load instruction (memory register) register used next instruction same
Instruction code
Operation summary
(xx) M/Q/T <<n,
Privileged mode Execution cycles
Value after instruction executed change
Note: Scaling performed according instruction operand size.
Table lists SH7709S data transfer instructions Table Data Transfer Instructions
Privileged Mode Cycles
Instruction #imm,Rn
Operation Sign extension (disp Sign extension (disp (Rn) (Rn) (Rn) (Rm) Sign extension (Rm) Sign extension (Rm) Rn-1 (Rn) Rn-2 (Rn) Rn-4 (Rn) (Rm) Sign extension (Rm) Sign extension
Code 1110nnnniiiiiiii
MOV.W
@(disp,PC),Rn
1001nnnndddddddd
MOV.L MOV.B MOV.W MOV.L MOV.B
@(disp,PC),Rn Rm,Rn Rm,@Rn Rm,@Rn Rm,@Rn @Rm,Rn
1101nnnndddddddd 0110nnnnmmmm0011 0010nnnnmmmm0000 0010nnnnmmmm0001 0010nnnnmmmm0010 0110nnnnmmmm0000
MOV.W
@Rm,Rn
0110nnnnmmmm0001
MOV.L MOV.B MOV.W MOV.L MOV.B
@Rm,Rn Rm,@-Rn Rm,@-Rn Rm,@-Rn @Rm+,Rn
0110nnnnmmmm0010 0010nnnnmmmm0100 0010nnnnmmmm0101 0010nnnnmmmm0110 0110nnnnmmmm0100
MOV.W
@Rm+,Rn
0110nnnnmmmm0101
MOV.L MOV.B MOV.W MOV.L MOV.B
@Rm+,Rn R0,@(disp,Rn) R0,@(disp,Rn) Rm,@(disp,Rn) @(disp,Rm),R0
(Rm) Rn,Rm 0110nnnnmmmm0110 (disp (disp (disp (disp Sign extension (disp Sign extension (disp 10000000nnnndddd 10000001nnnndddd 0001nnnnmmmmdddd 10000100mmmmdddd
MOV.W
@(disp,Rm),R0
10000101mmmmdddd
MOV.L MOV.B
@(disp,Rm),Rn Rm,@(R0,Rn)
0101nnnnmmmmdddd 0000nnnnmmmm0100
Table
Data Transfer Instructions (cont)
Privileged Mode Cycles
Instruction MOV.W MOV.L MOV.B Rm,@(R0,Rn) Rm,@(R0,Rn) @(R0,Rm),Rn
Operation Sign extension Sign extension
Code 0000nnnnmmmm0101 0000nnnnmmmm0110 0000nnnnmmmm1100
MOV.W
@(R0,Rm),Rn
0000nnnnmmmm1101
MOV.L MOV.B MOV.W MOV.L MOV.B
@(R0,Rm),Rn
0000nnnnmmmm1110 11000000dddddddd 11000001dddddddd 11000010dddddddd 11000100dddddddd
R0,@(disp,GBR) (disp GBR) R0,@(disp,GBR) (disp GBR) R0,@(disp,GBR) (disp GBR) @(disp,GBR),R0 (disp GBR) Sign extension @(disp,GBR),R0 (disp GBR) Sign extension @(disp,GBR),R0 (disp GBR) @(disp,PC),R0 disp Swap bottom bytes Swap consecutive words Middle bits
MOV.W
11000101dddddddd
MOV.L MOVA MOVT
11000110dddddddd 11000111dddddddd 0000nnnn00101001 0110nnnnmmmm1000
SWAP.B Rm,Rn
SWAP.W Rm,Rn
0110nnnnmmmm1001
XTRCT
Rm,Rn
0010nnnnmmmm1101
Table lists SH7709S arithmetic instructions. Table Arithmetic Instructions
Privileged Mode Cycles Carry Overflow Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Calculation result Calculation result
Instruction ADDC Rm,Rn #imm,Rn Rm,Rn
Operation Carry Overflow imm, with unsigned data, with signed data, with unsigned data, with signed data, have equivalent byte, Single-step division (Rn/Rm) M/Q/T
Code 0011nnnnmmmm1100 0111nnnniiiiiiii 0011nnnnmmmm1110
ADDV
Rm,Rn
0011nnnnmmmm1111
CMP/EQ
#imm,R0
10001000iiiiiiii
CMP/EQ
Rm,Rn
0011nnnnmmmm0000
CMP/HS
Rm,Rn
0011nnnnmmmm0010
CMP/GE
Rm,Rn
0011nnnnmmmm0011
CMP/HI
Rm,Rn
0011nnnnmmmm0110
CMP/GT
Rm,Rn
0011nnnnmmmm0111
CMP/PZ
0100nnnn00010001
CMP/PL
0100nnnn00010101
CMP/STR Rm,Rn
0010nnnnmmmm1100
DIV1
Rm,Rn
0011nnnnmmmm0100
DIV0S
Rm,Rn
0010nnnnmmmm0111
DIV0U
0000000000011001
Table
Arithmetic Instructions (cont)
Privileged Mode Cycles 2(to
Instruction DMULS.L Rm,Rn
Operation Signed operation MACH, MACL bits Unsigned operation MACH, MACL bits else byte signextended word signextended byte zeroextended word zeroextended
Code 0011nnnnmmmm1101
DMULU.L Rm,Rn
0011nnnnmmmm0101
2(to
0100nnnn00010000
Comparison result
EXTS.B Rm,Rn
0110nnnnmmmm1110
EXTS.W Rm,Rn
0110nnnnmmmm1111
EXTU.B Rm,Rn
0110nnnnmmmm1100
EXTU.W Rm,Rn
0110nnnnmmmm1101
MAC.L
@Rm+,@Rn+
Signed operation (Rn) 0000nnnnmmmm1111 (Rm) MAC, bits Signed operation (Rn) 0100nnnnmmmm1111 (Rm) MAC, bits MACL bits Signed operation bits Unsigned operation bits 0000nnnnmmmm0111
2(to
MAC.W
@Rm+,@Rn+
2(to
MUL.L
Rm,Rn
2(to 1(to
MULS.W Rm,Rn
0010nnnnmmmm1111
MULU.W Rm,Rn
0010nnnnmmmm1110
1(to
Table
Arithmetic Instructions (cont)
Privileged Mode Cycles Borrow Borrow Underflow
Instruction NEGC Rm,Rn Rm,Rn
Operation 0-Rm 0-Rm-T Borrow Rn-Rm Rn-Rm-T Borrow Rn-Rm Underflow
Code 0110nnnnmmmm1011 0110nnnnmmmm1010
SUBC
Rm,Rn Rm,Rn
0011nnnnmmmm1000 0011nnnnmmmm1010
SUBV
Rm,Rn
0011nnnnmmmm1011
Note: normal number execution cycles shown. value parentheses number cycles required case contention with preceding following instruction.
Table lists SH7709S logic operation instructions. Table Logic Operation Instructions
Privileged Mode Cycles Test result Test result Test result Test result
Instruction Rm,Rn #imm,R0
Operation GBR) GBR) GBR) GBR) (Rn) (Rn) result imm; result GBR) imm; result GBR) GBR)
Code 0010nnnnmmmm1001 11001001iiiiiiii 11001101iiiiiiii
AND.B #imm,@(R0,GBR)
OR.B
Rm,Rn Rm,Rn #imm,R0 #imm,@(R0,GBR)
0110nnnnmmmm0111 0010nnnnmmmm1011 11001011iiiiiiii 11001111iiiiiiii
TAS.B
0100nnnn00011011
Rm,Rn
0010nnnnmmmm1000
#imm,R0
11001000iiiiiiii
TST.B #imm,@(R0,GBR)
11001100iiiiiiii
Rm,Rn #imm,R0
0010nnnnmmmm1010 11001010iiiiiiii 11001110iiiiiiii
XOR.B #imm,@(R0,GBR)
Table lists SH7709S shift instructions. Table Shift Instructions
Privileged Mode Cycles
Instruction ROTL ROTR ROTCL ROTCR SHAD Rm,Rn
Operation [MSB
Code 0100nnnn00000100 0100nnnn00000101 0100nnnn00100100 0100nnnn00100101 0100nnnnmmmm1100
SHAL SHAR SHLD
Rm,Rn
0100nnnn00100000 0100nnnn00100001 0100nnnnmmmm1101
SHLL SHLR SHLL2 SHLR2 SHLL8 SHLR8
0100nnnn00000000 0100nnnn00000001 0100nnnn00001000 0100nnnn00001001 0100nnnn00011000 0100nnnn00011001 0100nnnn00101000 0100nnnn00101001
SHLL16 SHLR16
Table 2.10 lists SH7709S branch instructions. Table 2.10 Branch Instructions
Privileged Mode
Instruction label
Operation disp Delayed branch, disp disp Delayed branch, disp Delayed branch, disp Delayed branch, Delayed branch, disp Delayed branch, Delayed branch, Delayed branch, Delayed branch,
Code 10001011dddddddd
Cycles 3/1* 2/1*
BF/S
label
10001111dddddddd
label
10001001dddddddd
3/1*
BT/S
label
10001101dddddddd
2/1*
label
1010dddddddddddd
BRAF
0000mmmm00100011
label
1011dddddddddddd
BSRF
0000mmmm00000011
0100mmmm00101011 0100mmmm00001011
0000000000001011
Note: state when there branch.
Table 2.11 lists SH7709S system control instructions. Table 2.11 System Control Instructions
Privileged Mode Cycles
Instruction CLRMAC CLRS CLRT Rm,SR Rm,GBR Rm,VBR Rm,SSR Rm,SPC Rm,R0_BANK Rm,R1_BANK Rm,R2_BANK Rm,R3_BANK Rm,R4_BANK Rm,R5_BANK Rm,R6_BANK Rm,R7_BANK
Operation MACH, MACL R0_BANK R1_BANK R2_BANK R3_BANK R4_BANK R5_BANK R6_BANK R7_BANK (Rm) (Rm) GBR, (Rm) VBR, (Rm) SSR, (Rm) SPC, (Rm) R0_BANK, (Rm) R1_BANK, (Rm) R2_BANK, (Rm) R3_BANK,
Code 0000000000101000 0000000001001000 0000000000001000 0100mmmm00001110 0100mmmm00011110 0100mmmm00101110 0100mmmm00111110 0100mmmm01001110 0100mmmm10001110 0100mmmm10011110 0100mmmm10101110 0100mmmm10111110 0100mmmm11001110 0100mmmm11011110 0100mmmm11101110 0100mmmm11111110 0100mmmm00000111 0100mmmm00010111 0100mmmm00100111 0100mmmm00110111 0100mmmm01000111 0100mmmm10000111
LDC.L @Rm+,SR LDC.L @Rm+,GBR LDC.L @Rm+,VBR LDC.L @Rm+,SSR LDC.L @Rm+,SPC LDC.L @Rm+, R0_BANK LDC.L @Rm+, R1_BANK LDC.L @Rm+, R2_BANK LDC.L @Rm+, R3_BANK
0100mmmm10010111
0100mmmm10100111
0100mmmm10110111
Table 2.11 System Control Instructions (cont)
Privileged Mode Cycles
Instruction LDC.L @Rm+, R4_BANK LDC.L @Rm+, R5_BANK LDC.L @Rm+, R6_BANK LDC.L @Rm+, R7_BANK Rm,MACH Rm,MACL Rm,PR
Operation (Rm) R4_BANK, (Rm) R5_BANK, (Rm) R6_BANK, (Rm) R7_BANK, MACH MACL (Rm) MACH, (Rm) MACL, (Rm) PTEH/PTEL operation
Code 0100mmmm11000111
0100mmmm11010111
0100mmmm11100111
0100mmmm11110111
0100mmmm00001010 0100mmmm00011010 0100mmmm00101010 0100mmmm00000110 0100mmmm00010110 0100mmmm00100110 0000000000111000 0000000000001001 0000mmmm10000011 0000000000101011
LDS.L @Rm+,MACH LDS.L @Rm+,MACL LDS.L @Rm+,PR LDTLB PREF
(Rm) cache Delayed branch, Sleep
SETS SETT SLEEP SR,Rn GBR,Rn VBR,Rn SSR,Rn SPC,Rn R0_BANK,Rn R1_BANK,Rn R2_BANK,Rn R3_BANK,Rn
0000000001011000 0000000000011000 0000000000011011 0000nnnn00000010 0000nnnn00010010 0000nnnn00100010 0000nnnn00110010 0000nnnn01000010 0000nnnn10000010 0000nnnn10010010 0000nnnn10100010 0000nnnn10110010
R0_BANK R1_BANK R2_BANK R3_BANK
Note: number cycles until sleep state entered.
Table 2.11 System Control Instructions (cont)
Privileged Mode Cycles
Instruction R4_BANK,Rn R5_BANK,Rn R6_BANK,Rn R7_BANK,Rn
Operation R4_BANK R5_BANK R6_BANK R7_BANK Rn-4 (Rn) Rn-4 (Rn) Rn-4 (Rn) Rn-4 (Rn) Rn-4 (Rn) Rn-4 R0_BANK (Rn) Rn-4 R1_BANK (Rn) Rn-4 R2_BANK (Rn) Rn-4 R3_BANK (Rn) Rn-4 R4_BANK (Rn) Rn-4 R5_BANK (Rn) Rn-4 R6_BANK (Rn) Rn-4 R7_BANK (Rn) MACH MACL Rn-4 MACH (Rn) Rn-4 MACL (Rn) Rn-4 (Rn) SPC, SSR,
Code 0000nnnn11000010 0000nnnn11010010 0000nnnn11100010 0000nnnn11110010 0100nnnn00000011 0100nnnn00010011 0100nnnn00100011 0100nnnn00110011 0100nnnn01000011 0100nnnn10000011
STC.L SR,@-Rn STC.L GBR,@-Rn STC.L VBR,@-Rn STC.L SSR,@-Rn STC.L SPC,@-Rn STC.L R0_BANK, @-Rn STC.L R1_BANK, @-Rn STC.L R2_BANK, @-Rn STC.L R3_BANK, @-Rn STC.L R4_BANK, @-Rn STC.L R5_BANK, @-Rn STC.L R6_BANK, @-Rn STC.L R7_BANK, @-Rn MACH,Rn MACL,Rn PR,Rn
0100nnnn10010011
0100nnnn10100011
0100nnnn10110011
0100nnnn11000011
0100nnnn11010011
0100nnnn11100011
0100nnnn11110011
0000nnnn00001010 0000nnnn00011010 0000nnnn00101010 0100nnnn00000010 0100nnnn00010010 0100nnnn00100010 11000011iiiiiiii
STS.L MACH,@-Rn STS.L MACL,@-Rn STS.L PR,@-Rn TRAPA #imm
Notes: table shows minimum number execution cycles. actual number instruction execution cycles will increase cases such following: When there contention between instruction fetch data access When destination register load (memory-to-register) instruction also used next instruction With addressing modes using displacement (disp) listed below, assembler descriptions this manual show value before scaling performed. This done clarify operation chip. actual assembler descriptions, refer individual assembler notation rules. (disp:4, Register-indirect with displacement (disp:8, GBR-indirect with displacement (disp:8, PC-relative with displacement disp:8, disp:12 PC-relative
2.4.2
Instruction Code
Table 2.12 shows instruction code map. Table 2.12 Instruction Code
Instruction Code 0000 0000 0000 0001 SR,Rn SPC,Rn R0_BANK,Rn R4_BANK,Rn Rm,@(R0,Rn) MOV.W Rm,@(R0,Rn) SETT SETS DIV0U MOV.L CLRMAC Rm,@(R0,Rn) MUL.L LDTLB Rm,Rn R1_BANK,Rn R5_BANK,Rn BRAF R2_BANK,Rn R6_BANK,Rn R3_BANK,Rn R7_BANK,Rn GBR,Rn VBR,Rn SSR,Rn 0000 0001 0010 0011 1111
0000 00MD 0010 0000 01MD 0010 0000 10MD 0010 0000 11MD 0010 0000 00MD 0011 BSRF 0000 10MD 0011 PREF 0000 01MD MOV.B
0000 0000 00MD 1000 CLRT 0000 0000 01MD 1000 CLRS 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0010 0010 0010 0010 0011 0011 0011 0011 1001 1010 1011 1000 1001 1010 1011 MACH,Rn
SLEEP
MOVT MACL,Rn
PR,Rn
11MD MOV.B disp MOV.L
@(R0,Rm),Rn MOV.W @(R0,Rm),Rn Rm,@(disp:4,Rn) Rm,@Rn Rm,@-Rn Rm,Rn MOV.W Rm,@Rn MOV.W Rm,@-Rn XTRCT Rm,Rn Rm,Rn
MOV.L
@(R0,Rm),Rn
MAC.L
@Rm+,@Rn+
00MD MOV.B 01MD MOV.B 10MD
MOV.L MOV.L
Rm,@Rn Rm,@-Rn Rm,Rn DIV0S Rm,Rn Rm,Rn
11MD CMP/STR Rm,Rn 00MD CMP/EQ Rm,Rn 01MD DIV1 10MD 11MD Rm,Rn Rm,Rn Rm,Rn
MULU.W Rm,Rn CMP/HS Rm,Rn
MULSW Rm,Rn CMP/GE Rm,Rn CMP/GT Rm,Rn SUBV ADDV Rm,Rn Rm,Rn
DMULU.LRm,Rn
CMP/HI Rm,Rn SUBC Rm,Rn Rm,Rn
DMULS.LRm,Rn
ADDC
Table 2.12 Instruction Code (cont)
Instruction Code 0100 0100 0100 0000 SHLL 0001 SHLR 0010 STS.L 0000 MACH,@-Rn SR,@-Rn SPC,@-Rn
R0_BANK,@-Rn R4_BANK,@-Rn
0001 SHAL SHAR STS.L STC.L
0010 PR,@-Rn VBR,@-Rn
0011 1111
CMP/PZ STS.L STC.L MACL,@-Rn GBR,@-Rn
0100 00MD 0011 STC.L 0100 01MD 0011 STC.L 0100 10MD 0011 STC.L 0100 11MD 0011 STC.L 0100 0100 0100 0100 ROTL 0101 ROTR 0110 LDS.L
STC.L
SSR,@-Rn
STC.L STC.L
R1_BANK,@-Rn R5_BANK,@-Rn
STC.L STC.L ROTCL
R2_BANK,@-Rn R6_BANK,@-Rn
STC.L STC.L
R3_BANK,@-Rn R7_BANK,@-Rn
CMP/PL @Rm+,MACL @Rm+,GBR
ROTCR LDS.L LDC.L @Rm+,PR @Rm+,VBR LDC.L @Rm+,SSR
@Rm+,MACH LDS.L @Rm+,SR @Rm+,SPC
@Rm+,R0_BANK LDC.L @Rm+,R4_BANK LDC.L
0100 00MD 0111 LDC.L 0100 01MD 0111 LDC.L 0100 10MD 0111 LDC.L 0100 11MD 0111 LDC.L 0100 0100 0100 0100 0100 0100 1000 SHLL2 1001 SHLR2 1010 1011
LDC.L
BANK
LDC.L
@Rm+,R2_BANK LDC.L @Rm+,R6_BANK LDC.L
@Rm+,R3_BANK @Rm+,R7_BANK
@Rm+,R5_BANK LDC.L
Rm,MACH
SHLL8 SHLR8 TAS.B
Rm,MACL
SHLL16 SHLR16 Rm,PR
1100 SHAD 1101 SHLD
Rm,Rn Rm,Rn Rm,SR Rm,SPC Rm,R0_BANK Rm,R4_BANK @Rm+,@Rn+ @(disp:4,Rm),Rn @Rm,Rn @Rm+,Rn MOV.W @Rm,Rn MOV.W @Rm+,Rn SWAP.W Rm,Rn EXTU.W Rm,Rn MOV.L MOV.L NEGC @Rm,Rn @Rm+,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,R1_BANK Rm,R5_BANK Rm,R2_BANK Rm,R6_BANK Rm,R3_BANK Rm,R7_BANK Rm,GBR Rm,VBR Rm,SSR
0100 00MD 1110 0100 01MD 1110 0100 10MD 1110 0100 11MD 1110 0100 0101 0110 0110 0110 0110 0111 1111 MAC.W disp MOV.L
00MD MOV.B 01MD MOV.B
10MD SWAP.B Rm,Rn 11MD EXTU.B Rm,Rn #imm:8,Rn
EXTS.B Rm,Rn
EXTS.W Rm,Rn
Table 2.12 Instruction Code (cont)
Instruction Code 1000 00MD 0000 0001 MOV.W R0,@(disp:4,Rn) MOV.W @(disp:4,Rm),R0 BT/S MOV.W @(DISP:8,PC),RN label:12 label:12 MOV.W R0,@(disp:8,GBR) MOV.W @(disp:8,GBR),R0 #imm:8,R0 MOV.L R0,@(disp:8,GBR) MOV.L @(disp:8,GBR),R0 #imm:8,R0 TRAPA #imm:8 label:8 label:8 BF/S label:8 label:8 0010 0011 1111
disp MOV.B R0,@(disp:4,Rn) disp MOV.B @(disp:4,Rm),R0 CMP/EQ #imm:8,R0
1000 01MD
1000 10MD 1000 11MD 1001 1010 1011 1100 00MD
imm/disp imm/disp disp disp disp imm/disp
MOV.B R0,@(disp:8,GBR) MOV.B @(disp:8,GBR),R0 #imm:8,R0
1100 01MD
disp
MOVA @(disp:8,PC),R0 #imm:8,R0
1100 10MD 1100 11MD
TST.B #imm:8,@(R0,GBR) MOV.L
AND.B #imm:8,@(R0,GBR)
XOR.B #imm:8,@(R0,GBR)
OR.B #imm:8,@(R0,GBR)
1101 1110 1111 Note:
disp
@(disp:8,PC),Rn #imm:8,Rn
************ SH-3/SH-3E/SH3-DSP Programming Manual details.
2.5.1
Processor States Processor Modes
Processor States
SH7709S five processor states: reset state, exception-handling state, bus-released state, program execution state, power-down state. Reset State: this state reset. enters power-on reset state RESETP low, manual reset state RESEpin low. section Exception Handling, more information resets. power-on reset state, internal states on-chip supporting module registers initialized. manual reset state, internal states registers onchip supporting modules other than state controller (BSC) initialized. Since initialized manual reset state, refreshing operations continue. Refer register configurations relevant sections further details. Exception-Handling State: This transient state during which CPU's processor state flow altered reset, general exception, interrupt exception handling. case reset, branches address H'A0000000 starts executing usercoded exception handling program. case general exception interrupt, program counter (PC) contents saved saved program counter (SPC) status register (SR) contents saved saved status register (SSR). branches start address user-coded exception service routine found from contents vector base address vector offset. section Exception Processing, more information resets, general exceptions, interrupts. Program Execution State: this state executes program instructions sequence. Power-Down State: power-down state, operation halts power consumption reduced. There modes power-down state: sleep mode, standby mode. section Power-Down Modes, more information. Bus-Released State: this state released device that requested Transitions between states shown figure 2.8.
From state when RESETP
From state hardware standby mode when RESE=
Power-on reset state
RESETP
Manual reset state Reset state
RESETP
RESE=
Exception-handling state
Interrupt
exception Exception transition interrupt processing requ Bus-released state Program execution state
request request clearance SLEEP instruction with STBY cleared SLEEP instruction with STBY
Interrupt
Sleep mode Hardware standby mode*
Standby mode
1,RESETP=0
Power-down state
Note: hardware standby mode entered when goes from state.
Figure Processor State Transitions 2.5.2 Processor Modes
There processor modes: privileged mode user mode. processor mode determined processor mode (MD) status register (SR). User mode selected when privileged mode when When reset state exception state entered, When exception handling ends, cleared user mode entered. There certain registers bits which only accessed privileged mode.
Section Memory Management Unit (MMU)
3.1.1
Overview
Features
SH7709S on-chip memory management unit (MMU) that implements address translation. SH7709S features resident translation look-aside buffer (TLB) that caches information user-created address translation tables located external memory. enables highspeed translation virtual addresses into physical addresses. Address translation uses paging system supports page sizes Kbytes Kbytes). access right virtual address space privileged user modes provide memory protection. 3.1.2 Role
feature designed make efficient physical memory. shown figure 3.1, process smaller size than physical memory, entire process mapped onto physical memory. However, process increases size extent that longer fits into physical memory, becomes necessary partition process those parts requiring execution onto memory occasion demands ((1)). Having process itself consider this mapping onto physical memory would impose large burden process. lighten this burden, idea virtual memory born means performing bloc mapping onto physical memory ((2)). virtual memory system, substantially more virtual memory than physical memory provided, process mapped onto this virtual memory. Thus process only consider operation virtual memory. Mapping from virtual memory physical memory handled MMU. normally controlled operating system, switching physical memory allow virtual memory required process mapped onto physical memory smooth fashion. Switching physical memory carried secondary storage, etc. virtual memory system that came into being this particularly effective timesharing system (TSS) which number processes running simultaneously ((3)). processes running take mapping onto virtual memory into consideration while running, would possible increase efficiency. Virtual memory thus used reduce this load individual processes improve efficiency ((4)). virtual memory system, virtual memory allocated each process. task perform efficient mapping these virtual memory areas onto physical memory. also memory protection feature that prevents process from inadvertently accessing another process's physical memory. When address translation from virtual memory physical memory performed using MMU, occur that relevant translation information recorded MMU, with result that process inadvertently access virtual memory allocated another process. this
case, will generate exception, change physical memory mapping, record address translation information. Although functions could also implemented software alone, need translation performed software each time process accesses physical memory would result poor efficiency. this reason, buffer address translation (translation look-aside buffer: TLB) provided hardware hold frequently used address translation information. described cache storing address translation information. Unlike cache memory, however, address translation fails, that exception generated, switching address translation information normally performed software. This makes possible memory management performed flexibly software. methods mapping from virtual memory physical memory: paging method using fixed-length address translation, segment method using variable-length address translation. With paging method, unit translation fixed-size address space (usually Kbytes) called page. following text, SH7709S address space virtual memory referred virtual address space, address space physical memory physical memory space.
Virtual memory Process Physical memory Process Process Physical memory Physical memory
Process
Process Physical memory
Virtual memory
Process Process
,,,,,,,,,,,, ,,,,,,,,,,,, ,,,,,,,,,,,, ,,,,,,,,,,,, ,,,,,,,,,,,, ,,,,,,,, ,,,,,,,,,,,, ,,,,,,,,,,,, ,,,,,,,, ,,,,,,,,,,,,
Process
,,,,,,,,,,,, ,,,,,,,,,,,, ,,,,,,,,,,,, ,,,,,,,,,,,, ,,,,,,,,,,,, ,,,,,,,,,,,, ,,,,,,,,,,,, ,,,,,,,,,,,, ,,,,,,,,,,,, ,,,,,,,,,,,,
Process
,,,,
Physical memory
,,,,,,,,,,, ,,,,,,,,,,,,, ,,,,,,,,,,,,, ,,,,,,,,,,,,, ,,,,,,,,,,,,, ,,,,,,,,,,,,, ,,,,,,,,,,,,, ,,,,,,,,,,,,, ,,,,,,,,,,,,, ,,,,,,,,,,,,, ,,,,,,,,,,,, ,,,,,,,,,,,,, ,,,,,, ,,,,,,,,,,,,, ,,,,,,,,,,,,, ,,,,,,,,,,,,, ,,,,,,,,,,,,, ,,,,,,,,,,,,, ,,,,,,,,,,,,, ,,,,,,,,,,,,, ,,,,,,,,,,,,, ,,,,,,,,,,,,
Figure Functions
3.1.3
SH7709S
Virtual Address Space Areas areas, access through cache address translation using possible. These areas mapped external memory area units 4-Kbyte pages. When CCR.CE page also that page will accessed through cache. caching mode, copy-back write-through, selected setting CCR.WT. Some peripheral module's control registers allocated area physical address space. access these registers area, turn corresponding page select caching. Area area accessed through cache. mapping this area fixed within physical address space (H'00000000 H'1FFFFFFF). When CCR.CE this area accessed through cache. caching mode, copy-back write-through, selected setting CCR.CB. Areas Access areas through cache possible. mapping area fixed within physical address space (H'00000000 H'1FFFFFFF) area mapped control-register space. Area Access area through cache possible. This area only becomes usable when SR.DSP holds details area, description memory.
External memory space Area Area Area Area Area Area Area Area Area Area
Area
Area Address error Area
Area
Privileged mode
User mode
Figure Virtual Address Space (MMUCR.AT=1)
Physical Address Space: Areas areas accessed through cache. When CCR.CE these areas will accessed through cache. caching mode, copy-back write-through, selected setting CCR.WT. Some peripheral module's control registers allocated area physical address space. access these registers areas, bits cleared select caching. Area area accessed through cache. When CCR.CE this area accessed through cache. caching mode, copy-back write-through, selected setting CCR.CB. Areas Access areas through cache possible. Area Access area through cache possible. This area only becomes usable when SR.DSP holds details area, description memory.
External memory space H'0000 0000 Area Area Area Area Area Area Area Area Area Area Cacheable H'0000 0000
H'8000 0000 Area H'A000 0000 Area Address error H'C000 0000 Area H'E000 0000 Area H'FFFF FFFF Privileged mode User mode
H'8000 0000
H'FFFF FFFF
Figure Physical Address Space (MMUCR.AT=0) Single Address Translation: When enabled, virtual address space divided into units called pages. Physical addresses translated page units. Address translation tables external memory hold information such physical address that corresponds virtual address memory protection codes. When access areas occurs, there access physical address defined uniquely hardware. belongs area searched virtual address and, that virtual address registered TLB, access hits TLB. corresponding physical address page control information read from physical address determined.
virtual address registered TLB, miss exception occurs processing will shift miss handler. miss handler, address translation table external memory searched corresponding physical address page control information registered TLB. After returning from handler, instruction that caused miss re-executed. When enabled, address translation information that results physical address space H'80000000-H'FFFFFFFF should registered TLB. When disabled, virtual address used directly physical address. SH7709S supports 29-bit address space physical address space, bits physical address ignored, constitute shadow space (see section State Controller (BSC)). example, addresses H'00001000 area, H'80001000 area, H'A0001000 area, H'C0001000 area mapped onto same physical address. When access these addresses performed with cache enabled, address with bits physical address masked stored cache address array ensure data congruity. Single Virtual Memory Mode Multiple Virtual Memory Mode: There virtual memory modes: single virtual memory mode multiple virtual memory mode. single virtual memory mode, multiple processes parallel using virtual address space exclusively physical address corresponding given virtual address specified uniquely. multiple virtual memory mode, multiple processes parallel sharing virtual address space, given virtual address translated into different physical addresses depending process. value control register (MMUCR), either single multiple virtual mode selected. terms operation, only difference between single virtual memory mode multiple virtual memory mode address comparison method (see section 3.3.3, Address Comparison). Address Space Identifier (ASID): multiple virtual memory mode, address space identifier (ASID) used differentiate between processes running parallel sharing virtual address space. ASID bits length software setting ASID currently running process PTEH within MMU. When process switched using ASID, does have purged. single virtual memory mode, ASID used provide memory protection processes running simulataneously using virtual address space exclusively (see section 3.4.2, Software Management).
3.1.4
Register Configuration
register that undefined initial value must initialized software. Table shows configuration control registers. Table
Name Page table entry register high Page table entry register Translation table base register exception address register control register
Register Configuration
Abbreviation PTEH PTEL MMUCR Size Longword Longword Longword Longword Longword Initial Value* Undefined Undefined Undefined Undefined Address H'FFFFFFF0 H'FFFFFFF4 H'FFFFFFF8 H'FFFFFFFC H'FFFFFFE0
Notes: Initialized power-on reset manual reset. bit: undefined Other bits:
Register Description
There five registers processing. These peripheral module registers, they located address space area only accessed from privileged mode specifying address. These registers consist page table entry register high (PTEH) register residing address H'FFFFFFF0, which consists virtual page number (VPN) ASID. virtual address which exception generated case exception address error exception. When page size kbytes, upper bits virtual address, this case upper bits virtual address set. also modified software. ASID, software sets number currently executing process. ASID recorded LDTLB instruction. page table entry register (PTEL) register residing address H'FFFFFFF4, used store physical page number page management information recorded LDTLB instruction. contents this register only modified response software command. translation table base register (TTB) residing address H'FFFFFFF8, which points base address current page table. hardware does value automatically. available software general purposes.
exception address register (TEA) residing address H'FFFFFFFC, which stores virtual address corresponding address error exception. This value remains valid until next exception interrupt. control register (MMUCR) residing address H'FFFFFFE0, which makes settings described figure 3.4. program that modifies MMUCR should reside area. registers shown figure 3.4.
PTEH PTEL Virtual address causing TLB-related address error exception MMUCR Reserved bits. Always read Writing ignored. However, should also specified write MMUCR only. Single virtual memory mode bit. single virtual memory mode, cleared multiple virtual memory mode. 2-bit random counter, automatically updated hardware according following rules event exception. When miss exception occurs, entry ways corresponding virtual address which exception occurred checked, ways valid, added there more invalid way, they priority from order: event exception other than miss exception, which caused exception flush bit. Write flush (clear valid bits Always reads Index mode bit. When bits 16-12 used index number. When value obtained EX-ORing ASID bits PTEH bits 16-12 used index number. Address translation bit. Enables/disables MMU. disabled enabled 6543 ASID
Figure Register Contents
3.3.1
Functions
Configuration
caches address translation table information located external memory. address translation table stores physical page number translated from virtual page number control information page, which unit address translation. Figure shows overall configuration. 4-way associative with entries. There entries each way. Figure shows configuration virtual addresses entries.
Entry Entry
VPN(31-17)
VPN(11-10) ASID(7-0)
Entry PPN(28-10) PR(1-0) Entry
Entry Address array
Entry Data array
Figure Overall Configuration
Offset Virtual address (1-kbyte page)
Offset
Virtual address (4-kbyte page) (15) (19)
(31-17) (11-10) ASID entry Legend:
VPN: Virtual page number. bits virtual address 1-kbyte page, bits virtual address 4-kbyte page. Since bits 16-12 used index number, they stored entry. ASID: Address space identifier. Indicates process that access virtual page. single virtual memory mode user mode, multiple virtual memory mode, address compared with ASID PTEH when address comparison performed. Share status Page shared between processes Page shared between processes Page-size 1-kbyte page 4-kbyte page Valid bit. Indicates whether entry valid. Invalid Valid Cleared power-on reset. affected manual reset. PPN: Physical page number. bits physical address. bits 11-10 used case 4-kbyte page. Attention must paid synonym problem case 1-kbyte page (see section 3.4.4). most significant Protection field. 2-bit field encoded define access rights page. Reading only possible privileged mode. Reading/writing possible privileged mode. Reading only possible privileged/user mode. Reading/writing possible privileged/user mode. Cacheable bit. Indicates whether page cacheable. Non-cacheable Cacheable Dirty bit. Indicates whether page been written written Written
Figure Virtual Address Structure
3.3.2
Indexing
uses 4-way associative scheme, entries must selected index. bits ASID bits PTEH used index number regardless page size. index number generated different ways depending setting MMUCR. When bits 16-12 alone used index number When bits 16-12 EX-ORed with ASID bits generate 5-bit index number second method used prevent lowered efficiency that results when multiple processes simultaneously same virtual address space (multiple virtual memory) specific entry selected indexing each process. Figures show indexing schemes.
Virtual address
PTEH register
ASID(4-0)
ASID
Exclusive-OR Index
VPN(31-17)
VPN(11-10)
ASID(7-0)
PPN(31-10) PR(1-0)
Address array Data array
Figure Indexing
Virtual address
Index
VPN(31-17)
VPN(11-10)
ASID(7-0)
PPN(31-10) PR(1-0)
Address array Data array
Figure Indexing 3.3.3 Address Comparison
results address comparison determine whether specific virtual page number registered TLB. virtual page number virtual address that accesses external memory compared virtual page number indexed entry. ASID within PTEH compared ASID indexed entry. four ways searched simultaneously. compared values match, indexed entry valid registered. necessary have software ensure that hits occur simultaneously more than way, hardware operation guaranteed this occurs. example, there identical entries with same setting made such that made only process with ASID H'FF when shared state other non-shared state then ASID PTEH H'FF, there possibility simultaneous hits both these ways. therefore necessary ensure that this kind setting made software. object compared varies depending page management information (SZ, entry. also varies depending whether system supports multiple virtual memory single virtual memory. page-size information determines whether (11-10) compared. (11-10) compared 1-kbyte pages 4-kbyte pages
sharing information (SH) determines whether PTEH.ASID ASID entry compared. ASIDs compared when there sharing between processes when there sharing When single virtual memory supported (MMUCR.SV privileged mode engaged (SR.MD process resources accessed. This means that ASIDs compared when single virtual memory supported privileged mode engaged. objects address comparison shown figure 3.9.
(SR.MD MMUCR.SV
kbytes) kbyte) Bits compared: (31-17) (11-10) Bits compared: (31-17)
kbytes)
kbyte) Bits compared: (31-17) (11-10) ASID (7-0) Bits compared: (31-17) ASID (7-0)
Figure Objects Address Comparison
3.3.4
Page Management Information
addition bits, page management information entries also includes bits. entry indicates whether page dirty (i.e., been written to). attempt write page results initial page write exception. physical page swapping between secondary memory main memory, example, pages controlled that dirty page paged main memory only after that page written back secondary memory. entry indicates whether referenced page resides cacheable noncacheable area memory. When control register area mapped, field specifies access rights page privileged user modes used protect memory. Attempts nonpermitted accesses result protection violation exceptions. Access states designated bits shown table 3.2. Table Access States Designated Bits
Privileged Mode Reading Permitted Permitted Permitted caching) Permitted (with caching) Permitted Writing Initial page write exception Permitted Permitted caching) Permitted (with caching) protection violation exception Permitted Reading Permitted Permitted Permitted caching) Permitted (with caching) protection violation exception protection violation exception Permitted Permitted User Mode Writing Initial page write exception Permitted Permitted caching) Permitted (with caching) protection violation exception protection violation exception protection violation exception Permitted
Permitted
Permitted Permitted
protection violation exception Permitted
3.4.1
Functions
Hardware Management
There kinds hardware management follows: decodes virtual address accessed process performs address translation controlling accordance with MMUCR settings. address translation, receives page management information from TLB, determines exception whether cache accessed (using bit). details determination method hardware processing, section 3.5, Exceptions. 3.4.2 Software Management
There three kinds software management, follows. register setting. MMUCR setting, particular, should performed areas which address translation performed. Also, since changes constitute address translation system changes, this case, flushing should performed simultaneously writing also. Since exceptions generated disabled state with cleared disabled state must avoided with software that does MMU. entry recording, deletion, reading. entry recording done ways using LDTLB instruction, writing directly memory-mapped TLB. entry deletion reading, memory allocation accessed. section 3.4.3, Instruction (LDTLB), details LDTLB instruction, section 3.6, MemoryMapped Configuration, details memory-mapped TLB. exception processing. When exception generated, handled basis information from hardware side. section 3.5, Exceptions, details. When single virtual memory mode used, possible create state which physical memory access enabled privileged mode only clearing share status (SH) specify recording entries. This strengthens inter-process memory protection, enables special access levels created privileged mode only. Recording 1-kbyte page entry result synonym problem. section 3.4.4, Avoiding Synonym Problems.
3.4.3
Instruction (LDTLB)
load instruction (LDTLB) used record entries. When MMUCR LDTLB instruction changes entry specified MMUCR value specified PTEH PTEL, using bits 16-12 specified PTEH index number. When MMUCR EX-OR bits 16-12 specified PTEH ASID bits PTEH used index number. Figure 3.10 shows case where MMUCR When exception occurs, virtual page number virtual address that caused exception PTEH hardware. MMUCR each exception according rules shown figure 3.4. Consequently, LDTLB instruction issued after setting only PTEL exception processing routine, entry recording possible. entry updated software rewriting PTEH bits MMUCR. LDTLB instruction changes address translation information, there risk destroying address translation information this instruction issued area. Make sure, therefore, that this instruction issued area. Also, instruction associated with access area (such instruction) should issued least instructions after LDTLB instruction.
MMUCR Index
selection PTEL register
PTEH register
ASID
Write
Write
VPN(31-17)
VPN(11-10)
ASID(7-0)
PPN(31-10) PR(1-0)
Address array Data array
Figure 3.10 Operation LDTLB Instruction
3.4.4
Avoiding Synonym Problems
When 1-kbyte page recorded entry, synonym problem arise. number virtual addresses mapped onto single physical address, same physical address data will recorded number cache entries, will possible guarantee data congruity. reason this problem only occurs when using 1-kbyte page explained below with reference figure 3.11. achieve high-speed operation SH7709S cache, index number created using virtual address bits 11-4. When 4-kbyte page used, virtual address bits 11-4 included offset, since they subject address translation, they same physical address bits 11-4. cache-based address comparison recording address array, since cache address physical address, physical address bits 31-10 recorded. When 1-kbyte page used, also, cache index number created using virtual address bits 11-4. However, case 1-kbyte page, virtual address (11, subject address translation therefore same physical address (11, 10). Consequently, physical address recorded different entry from that index number indicated physical address cache address array. example, assume that, with 1-kbyte page entries, entries which following translation been performed recorded TLBs: Virtual address H'00000000 physical address Virtual address H'00000400 physical address H'00000400 H'00000400
Virtual address recorded cache entry H'00, virtual address cache entry H'C0. Since virtual addresses recorded different cache entries despite fact that physical addresses same, memory inconsistency will occur soon write performed either virtual address. Therefore, when recording 1-kbyte entry, physical address same physical address already used another entry, should recorded such that physical address (11, same. Note: readiness future expansion SuperH RISC engine family, recommend that, when multiple sets address translation information mapped onto same physical area memory, numbers that each [20:10] equal others. also recommend that multiple sets address-translation information that include 4-Kbyte pages single physical area.
When using 4-kbyte page Virtual address ,,,,,,
,,,,,, ,,,,,, ,,,,,, ,,,,,, ,,,,,,
Offset
Physical address ,,,,,,
,,,,,, ,,,,,, ,,,,,, ,,,,,,
Virtual address (11-4) Offset Cache address array
Physical address (31-10)
When using 1-kbyte page Virtual address
,,,,,, ,,,,,, ,,,,,, ,,,,,, ,,,,,,
Offset
Physical address
Virtual address (11-4) ,,,,,, ,,,,,, ,,,,,, Offset ,,,,,, ,,,,,, ,,,,,, Cache address array
Physical address (31-10)
Figure 3.11 Synonym Problem
Exceptions
There four exceptions: miss, protection violation, invalid, initial page write. 3.5.1 Miss Exception
miss results when virtual address address array selected entry compared match found. miss exception processing includes both hardware software operations. Hardware Operations: miss, SH7709S hardware executes prescribed operations, follows: field virtual address causing exception written PTEH register. virtual address causing exception written register. Either exception code H'040 load access, H'060 store access, written EXPEVT register. value indicating address instruction which exception occurred written save program counter (SPC). exception occurred delay slot, value indicating address related delayed branch instruction written SPC. contents status register (SR) time exception written save status register (SSR). mode (MD) place SH7709S privileged mode. block (BL) mask further exception requests. register bank (RB) random counter (RC) field control register (MMUCR) incremented when ways checked entry corresponding logical address which exception occurred, ways valid. more ways invalid, those ways prioritized order from through Execution branches address obtained adding value contents H'00000400 invoke user-written miss exception handler. Software (TLB Miss Handler) Operations: software searches page tables external memory allocates required page table entry. Upon retrieving required page table entry, software must execute following operations: Write value physical page number (PPN) field protection (PR), page size (SZ), cacheable (C), dirty (D), share status (SH), valid bits page table entry recorded address translation table external memory into PTEL register SH7709S.
using software selection entry replacement, write desired value field MMUCR. Issue LDTLB instruction load contents PTEH PTEL into TLB. Issue return from exception handler (RTE) instruction terminate handler routine return instruction stream. 3.5.2 Protection Violation Exception
protection violation exception results when virtual address address array selected entry compared valid entry found match, type access permitted access rights specified field. protection violation exception processing includes both hardware software operations. Hardware Operations: protection violation exception, SH7709S hardware executes prescribed operations, follows: field virtual address causing exception written PTEH register. virtual address causing exception written register. Either exception code H'0A0 load access, H'0C0 store access, written EXPEVT register. value indicating address instruction which exception occurred written into exception occurred delay slot, value indicating address related delayed branch instruction written into SPC). contents time exception written SSR. place SH7709S privileged mode. mask further exception requests. register bank (RB) that generated exception field MMUCR. Execution branches address obtained adding value contents H'00000100 invoke protection violation exception handler. Software (TLB Protection Violation Handler) Operations: Software resolves protection violation issues (return from exception handler) instruction terminate handler return instruction stream.
3.5.3
Invalid Exception
invalid exception results when virtual address compared selected entry address array match found entry valid (the invalid exception processing includes both hardware software operations. Hardware Operations: invalid exception, SH7709S hardware executes prescribed operations, follows: number virtual address causing exception written PTEH register. virtual address causing exception written register. number causing exception written MMUCR. Either exception code H'040 load access, H'060 store access, written EXPEVT register. value indicating address instruction which exception occurred written SPC. exception occurred delay slot, value indicating address delayed branch instruction written SPC. contents time exception written into SSR. mode (MD) place SH7709S privileged mode. block (BL) mask further exception requests. register bank (RB) Execution branches address obtained adding value contents H'00000100, protection violation exception handler starts. Software (TLB Invalid Exception Handler) Operations: software searches page tables external memory assigns required page table entry. Upon retrieving required page table entry, software must execute following operations: Write values physical page number (PPN) field values protection (PR), page size (SZ), cacheable (C), dirty (D), share status (SH), valid bits page table entry recorded external memory PTEL register. using software selection entry replacement, write desired value field MMUCR. Issue LDTLB instruction load contents PTEH PTEL into TLB. Issue instruction terminate handler return instruction stream. instruction should issued after LDTLB instructions.
3.5.4
Initial Page Write Exception
initial page write exception results write access when virtual address address array selected entry compared valid entry with appropriate access rights found match, (dirty) entry (the page been written to). Initial page write exception processing includes both hardware software operations. Hardware Operations: initial page write exception, SH7709S hardware executes prescribed operations, follows: field virtual address causing exception written PTEH register. virtual address causing exception written register. Exception code H'080 written EXPEVT register. value indicating address instruction which exception occurred written SPC. exception occurred delay slot, value indicating address related delayed branch instruction written SPC. contents time exception written SSR. place SH7709S privileged mode. mask further exception requests. register bank (RB) that caused exception field MMUCR. Execution branches address obtained adding value contents H'00000100 invoke user-written initial page write exception handler. Software (Initial Page Write Handler) Operations: software must execute following operations: Retrieve required page table entry from external memory. page table entry external memory Write value field bits page table entry external memory PTEL register. using software selection entry replacement, write desired value field MMUCR. Issue LDTLB instruction load contents PTEH PTEL into TLB. Issue instruction terminate handler return instruction stream. instruction should issued after LDTLB instructions. Figure 3.12 shows flowchart exceptions.
Start (MMUCR.SV SR.MD VPNs match? VPNs ASIDs match? invalid exception Privileged mode
miss exception User mode User privileged?
check 00/01 R/W? R/W? protection violation exception Initial page write exception (noncacheable) Memory access
check 01/11 R/W? 00/10 R/W?
protection violation
(cacheable) Cache access
Figure 3.12 Exception Generation Flowchart
3.5.5
Processing Flow Event Exception (Same Processing Flow Address Error)
Figure 3.13 shows exception signals instruction fetch mode.
Handler transition processing
exception handler
Exception source stage Instruction fetch Instruction decode Instruction execution Memory access Write back operation
Figure 3.13 Exception Signals Instruction Fetch
Figure 3.14 shows exception signals data access mode.
exception handler Handler transition processing
Exception source stage Stage cancellation instruction that begun execution Instruction fetch Instruction decode Instruction execution Memory access Write back operation
Figure 3.14 Exception Signals Data Access
Configuration Memory-Mapped
allow management operations software, instruction used, privileged mode, read write contents. mapped area virtual address space. address array (VPN, bit, ASID) mapped H'F2000000 H'F2FFFFFF, data array (PPN, bits) mapped H'F3000000 H'F3FFFFFF. also possible access bits address array from data array. Only longword access possible, both address data arrays. address array mapped H'F2000000 H'F2FFFFFF. access address array, 32bit address field (for read/write access) 32-bit data field (for write access) must specified. address field information that selects entry accessed; data field specifies VPN, bit, ASID written address array (figure 3.15 (1)). address field, specify bits 16-12 index address that selects entry, bits select way, H'F2 bits 31-24 indicate access address array. Selection index address depends MMUCR.IX setting.
following types operations address array possible. Address Array Read Reads VPN, bit, ASID from entry that corresponds entry address that were specified address field. Address Array Write Writes data data field entry that corresponds entry address that were specified address field. 3.6.1 Data Array
data array assigned H'F3000000 H'F3FFFFFF. access data array, 32-bit address field (for read/write operations), 32-bit data field (for write operations) must specified. These specified general register. address section specifies information selecting entry accessed; data section specifies longword data written data array (figure 3.15 (2)). address section, specify entry address selecting entry (bits 16-12), selecting (bits 9-8: H'F3 indicate data array access (bits 31-24). MMUCR indicates whether EX-OR taken entry address ASID. Both reading writing longword data array specified index address number. access size data array fixed longword.
Address Array Access Read access Address field Data field 11110010
ASID
Write access Address field Data field VPN: 11110010
ASID
Virtual page number ASID: Address space identifier Valid Don't care (00:
Data Array Access Read/write access Address field Data field 11110011
PPN: VPN:
Physical page number Valid Protection field Page-size Cacheable Dirty Share status Don't care Virtual page number read, don't care write (00:
Figure 3.15 Specifying Address Data Memory-Mapped Access
3.6.2
Usage Examples
Invalidating Specific Entries: Specific entries invalidated writing entry's bit. When ASID specified write data compared ASID within entry selected entry address data written matching way. match found, there operation. specifies write data specifies address.
R0=H'1547 381C MMUCR.IX=0 VPN(31-17)=B'0001 0101 0100 VPN(11-10)=B'10 ASID=B'0001 1100 R1=H'F201 3000
corresponding entry association made from entry selected VPN(16-12)=B'1 0011 index, cleared 0,achieving invalidation. MOV.L R0,@R1
Reading Data Specific Entry: This example reads data section specific entry. order indicated data field figure 3.15 read. specifies address data section selected entry read
R1=H'F300 4300 MOV.L @R0,R1 VPN(16-12)=B'00100
Usage Note
operations listed below must only performed when disabled area. subsequent operation that accesses area must take place more instructions after below operations. Change SR.MD SR.BL Execute LDTLB instruction Write memory-mapped Change MMUCR.
Section Exception Handling
4.1.1
Overview
Features
Exception handling separate from normal program processing, performed routine separate from normal program. response exception handling request abnormal termination executing instruction, control passed user-written exception handler. However, response interrupt request, normal program execution continues until executing instruction. Here, exceptions other than resets interrupts will called general exceptions. There thus three types exceptions: resets, general exceptions, interrupts. 4.1.2 Register Configuration
Table lists registers used exception handling. register with undefined initial value should initialized software. Table
Register
Register Configuration
Abbr. Size Longword Longword Longword Longword Initial Value Undefined Address H'FFFFFFD0
TRAPA exception regist
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