132COMMON 132RGB DRIVER 65,536-COLOR DISPLAY NJU6854 132COMMON 13
|
|
|
Top Searches for this datasheet
NJU6854
132COMMON 132RGB DRIVER 65,536-COLOR DISPLAY
NJU6854 132COMMON 132RGB driver 65,536-color display. contains common drivers, drivers, serial parallel interface circuit, internal power supply, grayscale palettes 278,784-bit display data RAM. segment drivers (Red, Green, Blue) independently produce optimum grayscales from built-in grayscale palette, achieves 65,536 colors (64x32x32). addition, NJU6854 operates with voltage 1.7V operating current, therefore ideally suited battery-powered handheld applications.
PACKAGE
BUMP CHIP
FEATURES
65,536-color driver Built-in Drivers 132-common 132RGB (396-segment drivers) Built-in Display Data (DDRAM) 278,784 bits Graphic Display Programmable Display Mode grayscales(Green) grayscales(Red, Blue) Areas Partial Display 8-/16-bit Parallel Interface Selectable 8-/16-bit Length Display Data Selectable 3-/4-line Serial Interface Selectable Programmable Duty Ratio Bias Ratio Programmable Internal Voltage Booster Maximum times Programmable Contrast Control 128-step Electronic Volume Register (EVR) Various Useful Instructions Operating Current Logic Voltage 1.7V 3.3V Wide Voltage Range 5.0V 18.0V C-MOS Technology Slim Chip Package Bump Chip
Ver.2004-08-05
NJU6854
TABLE CONTENTS GENERAL DESCRIPTION PACKAGE. FEATURES LOCATION. COORDINATES. BLOCK DIAGRAM POWER SUPPLY BLOCK DIAGRAM TERMINAL DESCRIPTION FUNCTIONAL DESCRIPTION
INTERFACE.
(1-1) Selection Parallel/Serial Interface Mode.17 (1-2) Selection Mode.17 (1-3) Data Recognition (1-4) Selection 3-/4-line Serial Interface Mode.17 (1-5) 4-line Serial Interface Mode.17 (1-6) 3-line Serial Interface Mode.18 (1-7) Data Write.19 (1-8) Data Read (1-9) Selection 8-/16-bit Length (Parallel Interface Mode)
INITIAL DISPLAY LINE. DDRAM.
(3-1) DDRAM Address Range.23 (3-2) Window Area DDRAM Access.23 (3-3) DDRAM Access Direction.24 (3-4) Segment Shift Direction.26 (3-5) Block Diagram DDRAM Peripheral Circuit.26 (3-6) DDRAM Mapping.27 (3-6-1) (REW, SWAP) (0,0), SHIFT1 "0", SHIFT0 "0", "84H" (1/132 Duty), "00H", "00H", SSC1 SSC2 "0", EN3PTL "0".27 (3-6-2) (REW, SWAP) (0,0), SHIFT1 "0", SHIFT0 "0", "70H" (1/112 Duty), "00H", "0AH", SSC1 SSC2 "0", EN3PTL "0".28 (3-7) Relationship among Assignment, address Segment Driver
CONTROL. FRAME RATE CONTROL(FRC) DISPLAY TIMING GENERATOR. DATA LATCH CIRCUIT. COMMON DRIVERS SEGMENT DRIVERS OSCILLATOR. (10) POWER SUPPLY
(10-1) Voltage Booster (10-2) Electrical Volume Register (EVR) (10-3) Voltage Converter.40 (10-3-1) Voltage Regulator (10-3-2) Reference Voltage Generator (10-3-3) Bias Voltage Generator.41 (10-4) External Components Power Supply.42 (10-5) Power ON/OFF.45 (10-6) Discharge Circuit (10-7) Reset Function
(11) INSTRUCTION TABLES. (12) INSTRUCTION DESCRIPTIONS
(12-1) 8-bit Access Mode (12-1-1) Instruction Register.51
Ver.2004-08-05
NJU6854
(12-1-2) Auto-increment Instruction Register Address.52 (12-2) 16-bit Access Mode (12-2-1) Instruction Register.53 (12-2-2) Auto Increment Instruction Register Address.53 (12-3) Oscillation Control (12-4) Display Data Assignment/ Window Area ONOFF/Increment Control.54 (12-5) Display Line Number (12-6) Blank Line Number (12-7) Address (12-8) Address (12-9) Window Address (12-10) Window Address (12-11) Display Mode/Grayscale Mode (12-12) Oscillating Frequency Adjustment/Frequency Dividing.60 (12-13) Header (12-14) Initial Display Line.61 (12-15) Scan Start 1.62 (12-16) Scan Start 2.62 (12-17) Line Number Partial Display (12-18) Line Number Partial Display (12-19) N-Line Inversion (12-20) Power Control 1.63 (12-21) Electronic Volume Control (12-22) Display Timing Signal Monitor/PBX Palette (12-23) Power Control 2.65 (12-24) Booster Level/Amplifier Gain (12-25) Voltage Booster Clock (12-26) Display Control (12-27) Control (12-28) Three Partial Display Areas/ Driver Control/REV Bit.70 (12-29) Discharge ON/OFF.72 (12-30) Driver Data (12-31) Instruction Table/Address (12-32) Scan Start 3.73 (12-33) Line Number Partial Display (12-34) Grayscale Palette (PA0~PA31, PB0~PB31, PC0~PC31)
(13) PARTIAL DISPLAY FUNCTION. (14) RELATIONSHIP BETWEEN LOGICAL NUMBER PHYSICAL COMMON DRIVER. (15) TYPICAL INSTRUCTION SEQUENCES
ABSOLUTE MAXIMUM RATINGS. RECOMMENDED OPERATING CONDITIONS CHARACTERISTICS. CHARACTERISTICS.
Write operation (80-type MPU) Read operation (80-type MPU). Write operation (68-type MPU) Read operation (68-type MPU). Serial interface Display control timing. Reset input timing
INPUT/OUTPUT BLOCK DIAGRAM CONNECTIONS.
Ver.2004-08-05
NJU6854
LOCATION
COMB1 COMB0 DUMMY DUMMY SEGC131 SEGB131 SEGA131 SEGC130 SEGB130 SEGA130 DUMMY COMB25 COMB24 COMB23 SEGC67 SEGB67 SEGA67 SEGC66 SEGB66 SEGA66
DUMMY COMB26 COMB27 COMB28 COMB29 COMB30 COMB31 COMB32
COMB59 COMB60 COMB61 COMB62 COMB63 COMB64 COMB65 DUMMY
VSSH LDAT LSCK LREQ LRESB TEST SEL68 VDDA RESB VDDA VSSA VDDA VSSA OSCO OSCI VSSL
VSSL
DUMMY VSSH
SEGA0~SEGC131, COMA0~COMA25, COMB0~COMB25, DUMMY
COMA26~COMA65, COMB26~COMB65, DUMMY
interface pads other pads
115,
Bump Material (gold)
Ver.2004-08-05
VREF VSSH
VREF
NJU6854
DUMMY COMA26 COMA27 COMA28 COMA29 COMA30 COMA31 COMA32
COMA59 COMA60 COMA61 COMA62 COMA63 COMA64 COMA65 DUMMY
VSSH
Note pads with same name connected within chip. Note Dummy pads kept open.
UNIT: ITEMS Chip size pitch space (bump) open side size (bump) BUMP height REMARK With scribe lane (100 Driver pads pitch Interface pads Driver sides Interface sides Driver sides Interface sides pads SIZE 17,643 70~170 17.5 2,180
ALIGN MARK DESIGN
bump metal only pattern forbidden area metal only bump right bottom align mark
left bottom align mark
Coordinates LEFT BOTTOM -8157.92 -515.62 RIGHT BOTTOM 8157.92 -515.62
Ver.2004-08-05
VSSH
VSSH
NJU6854
COORDINATES
chip size chip center
name DUMMY VSSH VSSH VSSH VSSH VSSH VSSH VSSH VSSH VSSH VSSH VSSH VSSH VSSH VSSH VSSH VSSH VSSH LDAT LSCK LREQ LRESb TEST SEL68 VDDA RESb VDDA VSSA VDDA VSSA
X(µm) -8620.0 -8530.0 -8465.0 -8400.0 -8335.0 -8270.0 -8205.0 -8140.0 -8075.0 -8010.0 -7945.0 -7880.0 -7815.0 -7750.0 -7685.0 -7620.0 -7555.0 -7490.0 -7375.0 -7260.0 -7145.0 -7030.0 -6915.0 -6800.0 -6685.0 -6570.0 -6455.0 -6340.0 -6225.0 -6110.0 -5995.0 -5880.0 -5765.0 -5650.0 -5535.0 -5420.0 -5305.0 -5190.0 -5075.0 -4960.0 -4845.0 -4730.0 -4615.0 -4500.0 -4385.0 -4270.0 -4155.0 -4040.0 -3925.0 -3810.0
Y(µm) -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5
name OSCO OSCI VREF VREF VREF VREF VREF VSSHA VSSHA VSSHA VSSHA VSSHA VSSHA
(µm) -3695.0 -3580.0 -3465.0 -3350.0 -3235.0 -3120.0 -3005.0 -2940.0 -2875.0 -2810.0 -2745.0 -2680.0 -2615.0 -2525.0 -2460.0 -2395.0 -2330.0 -2265.0 -2200.0 -2110.0 -2045.0 -1980.0 -1915.0 -1850.0 -1785.0 -1720.0 -1655.0 -1590.0 -1525.0 -1460.0 -1395.0 -1330.0 -1265.0 -1200.0 -1110.0 -1045.0 -980.0 -915.0 -850.0 -760.0 -695.0 -630.0 -565.0 -500.0 -410.0 -345.0 -280.0 -215.0 -150.0 -85.0
(µm) -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5
name VSSHA VSSHA VSSHA VSSHA VREG VREG VREG VREG VREG VOUT VOUT VOUT VOUT VOUT VOUT C1C1C1C1C1C1C2+ C2C2C2C2C2C2C3+ C3C3C3C3C3-
(µm) -20.0 45.0 110.0 175.0 340.0 405.0 470.0 535.0 600.0 690.0 755.0 820.0 885.0 950.0 1015.0 1105.0 1170.0 1235.0 1300.0 1365.0 1430.0 1520.0 1585.0 1650.0 1715.0 1780.0 1845.0 1935.0 2000.0 2065.0 2130.0 2195.0 2260.0 2350.0 2415.0 2480.0 2545.0 2610.0 2675.0 2765.0 2830.0 2895.0 2960.0 3025.0 3090.0 3180.0 3245.0 3310.0 3375.0 3440.0
(µm) -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5
Ver.2004-08-05
NJU6854
chip size (chip center
name C3C4+ C4C4C4C4C4C4C5+ C5C5C5C5C5C5V0 X(µm) 3505 3595 3660 3725 3790 3855 3920 4010 4075 4140 4205 4270 4335 4425 4490 4555 4620 4685 4750 4840 4905 4970 5035 5100 5165 5335 5400 5465 5530 5595 5660 5750 5815 5880 5945 6010 6075 6165 6230 6295 6360 6425 6490 6660 6725 6790 6855 6920 6985 7075 Y(µm) -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 name VSSH VSSH VSSH VSSH VSSH VSSH VSSH VSSH VSSH VSSH VSSH VSSH VSSH VSSH VSSH VSSH VSSH DUMMY DUMMY COMA65 COMA64 COMA63 COMA62 COMA61 COMA60 COMA59 COMA58 COMA57 COMA56 COMA55 COMA54 COMA53 COMA52 COMA51 COMA50 COMA49 COMA48 COMA47 COMA46 COMA45 COMA44 COMA43 COMA42 COMA41 COMA40 (µm) 7140 7205 7270 7335 7400 7490 7555 7620 7685 7750 7815 7880 7945 8010 8075 8140 8205 8270 8335 8400 8465 8530 8620 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 (µm) -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -794 -756 -718 -680 -642 -604 -566 -528 -490 -452 -414 -376 -338 -300 -262 -224 -186 -148 -110 name COMA39 COMA38 COMA37 COMA36 COMA35 COMA34 COMA33 COMA32 COMA31 COMA30 COMA29 COMA28 COMA27 COMA26 DUMMY DUMMY COMA25 COMA24 COMA23 COMA22 COMA21 COMA20 COMA19 COMA18 COMA17 COMA16 COMA15 COMA14 COMA13 COMA12 COMA11 COMA10 COMA9 COMA8 COMA7 COMA6 COMA5 COMA4 COMA3 COMA2 COMA1 COMA0 DUMMY DUMMY SEGA0 SEGB0 SEGC0 SEGA1 SEGB1 SEGC1 (µm) 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 8607 8569 8531 8493 8455 8417 8379 8341 8303 8265 8227 8189 8151 8113 8075 8037 7999 7961 7923 7885 7847 7809 7771 7733 7695 7657 7619 7581 7543 7505 7467 7429 7391 7353 7315 (µm) 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5
Ver.2004-08-05
NJU6854
chip size (chip center
name SEGA2 SEGB2 SEGC2 SEGA3 SEGB3 SEGC3 SEGA4 SEGB4 SEGC4 SEGA5 SEGB5 SEGC5 SEGA6 SEGB6 SEGC6 SEGA7 SEGB7 SEGC7 SEGA8 SEGB8 SEGC8 SEGA9 SEGB9 SEGC9 SEGA10 SEGB10 SEGC10 SEGA11 SEGB11 SEGC11 SEGA12 SEGB12 SEGC12 SEGA13 SEGB13 SEGC13 SEGA14 SEGB14 SEGC14 SEGA15 SEGB15 SEGC15 SEGA16 SEGB16 SEGC16 SEGA17 SEGB17 SEGC17 SEGA18 SEGB18 X(µm) 7277 7239 7201 7163 7125 7087 7049 7011 6973 6935 6897 6859 6821 6783 6745 6707 6669 6631 6593 6555 6517 6479 6441 6403 6365 6327 6289 6251 6213 6175 6137 6099 6061 6023 5985 5947 5909 5871 5833 5795 5757 5719 5681 5643 5605 5567 5529 5491 5453 5415 Y(µm) 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 name SEGC18 SEGA19 SEGB19 SEGC19 SEGA20 SEGB20 SEGC20 SEGA21 SEGB21 SEGC21 SEGA22 SEGB22 SEGC22 SEGA23 SEGB23 SEGC23 SEGA24 SEGB24 SEGC24 SEGA25 SEGB25 SEGC25 SEGA26 SEGB26 SEGC26 SEGA27 SEGB27 SEGC27 SEGA28 SEGB28 SEGC28 SEGA29 SEGB29 SEGC29 SEGA30 SEGB30 SEGC30 SEGA31 SEGB31 SEGC31 SEGA32 SEGB32 SEGC32 SEGA33 SEGB33 SEGC33 SEGA34 SEGB34 SEGC34 SEGA35 (µm) 5377 5339 5301 5263 5225 5187 5149 5111 5073 5035 4997 4959 4921 4883 4845 4807 4769 4731 4693 4655 4617 4579 4541 4503 4465 4427 4389 4351 4313 4275 4237 4199 4161 4123 4085 4047 4009 3971 3933 3895 3857 3819 3781 3743 3705 3667 3629 3591 3553 3515 (µm) 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 name SEGB35 SEGC35 SEGA36 SEGB36 SEGC36 SEGA37 SEGB37 SEGC37 SEGA38 SEGB38 SEGC38 SEGA39 SEGB39 SEGC39 SEGA40 SEGB40 SEGC40 SEGA41 SEGB41 SEGC41 SEGA42 SEGB42 SEGC42 SEGA43 SEGB43 SEGC43 SEGA44 SEGB44 SEGC44 SEGA45 SEGB45 SEGC45 SEGA46 SEGB46 SEGC46 SEGA47 SEGB47 SEGC47 SEGA48 SEGB48 SEGC48 SEGA49 SEGB49 SEGC49 SEGA50 SEGB50 SEGC50 SEGA51 SEGB51 SEGC51 (µm) 3477 3439 3401 3363 3325 3287 3249 3211 3173 3135 3097 3059 3021 2983 2945 2907 2869 2831 2793 2755 2717 2679 2641 2603 2565 2527 2489 2451 2413 2375 2337 2299 2261 2223 2185 2147 2109 2071 2033 1995 1957 1919 1881 1843 1805 1767 1729 1691 1653 1615 (µm) 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5
Ver.2004-08-05
NJU6854
chip size (chip center
name SEGA52 SEGB52 SEGC52 SEGA53 SEGB53 SEGC53 SEGA54 SEGB54 SEGC54 SEGA55 SEGB55 SEGC55 SEGA56 SEGB56 SEGC56 SEGA57 SEGB57 SEGC57 SEGA58 SEGB58 SEGC58 SEGA59 SEGB59 SEGC59 SEGA60 SEGB60 SEGC60 SEGA61 SEGB61 SEGC61 SEGA62 SEGB62 SEGC62 SEGA63 SEGB63 SEGC63 SEGA64 SEGB64 SEGC64 SEGA65 SEGB65 SEGC65 SEGA66 SEGB66 SEGC66 SEGA67 SEGB67 SEGC67 SEGA68 SEGB68 X(µm) 1577 1539 1501 1463 1425 1387 1349 1311 1273 1235 1197 1159 1121 1083 1045 1007 -133 -171 -209 -247 -285 Y(µm) 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 name SEGC68 SEGA69 SEGB69 SEGC69 SEGA70 SEGB70 SEGC70 SEGA71 SEGB71 SEGC71 SEGA72 SEGB72 SEGC72 SEGA73 SEGB73 SEGC73 SEGA74 SEGB74 SEGC74 SEGA75 SEGB75 SEGC75 SEGA76 SEGB76 SEGC76 SEGA77 SEGB77 SEGC77 SEGA78 SEGB78 SEGC78 SEGA79 SEGB79 SEGC79 SEGA80 SEGB80 SEGC80 SEGA81 SEGB81 SEGC81 SEGA82 SEGB82 SEGC82 SEGA83 SEGB83 SEGC83 SEGA84 SEGB84 SEGC84 SEGA85 (µm) -323 -361 -399 -437 -475 -513 -551 -589 -627 -665 -703 -741 -779 -817 -855 -893 -931 -969 -1007 -1045 -1083 -1121 -1159 -1197 -1235 -1273 -1311 -1349 -1387 -1425 -1463 -1501 -1539 -1577 -1615 -1653 -1691 -1729 -1767 -1805 -1843 -1881 -1919 -1957 -1995 -2033 -2071 -2109 -2147 -2185 (µm) 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 name SEGB85 SEGC85 SEGA86 SEGB86 SEGC86 SEGA87 SEGB87 SEGC87 SEGA88 SEGB88 SEGC88 SEGA89 SEGB89 SEGC89 SEGA90 SEGB90 SEGC90 SEGA91 SEGB91 SEGC91 SEGA92 SEGB92 SEGC92 SEGA93 SEGB93 SEGC93 SEGA94 SEGB94 SEGC94 SEGA95 SEGB95 SEGC95 SEGA96 SEGB96 SEGC96 SEGA97 SEGB97 SEGC97 SEGA98 SEGB98 SEGC98 SEGA99 SEGB99 SEGC99 SEGA100 SEGB100 SEGC100 SEGA101 SEGB101 SEGC101 (µm) -2223 -2261 -2299 -2337 -2375 -2413 -2451 -2489 -2527 -2565 -2603 -2641 -2679 -2717 -2755 -2793 -2831 -2869 -2907 -2945 -2983 -3021 -3059 -3097 -3135 -3173 -3211 -3249 -3287 -3325 -3363 -3401 -3439 -3477 -3515 -3553 -3591 -3629 -3667 -3705 -3743 -3781 -3819 -3857 -3895 -3933 -3971 -4009 -4047 -4085 (µm) 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5
Ver.2004-08-05
NJU6854
chip size (chip center
name SEGA102 SEGB102 SEGC102 SEGA103 SEGB103 SEGC103 SEGA104 SEGB104 SEGC104 SEGA105 SEGB105 SEGC105 SEGA106 SEGB106 SEGC106 SEGA107 SEGB107 SEGC107 SEGA108 SEGB108 SEGC108 SEGA109 SEGB109 SEGC109 SEGA110 SEGB110 SEGC110 SEGA111 SEGB111 SEGC111 SEGA112 SEGB112 SEGC112 SEGA113 SEGB113 SEGC113 SEGA114 SEGB114 SEGC114 SEGA115 SEGB115 SEGC115 SEGA116 SEGB116 SEGC116 SEGA117 SEGB117 SEGC117 SEGA118 SEGB118 X(µm) -4123 -4161 -4199 -4237 -4275 -4313 -4351 -4389 -4427 -4465 -4503 -4541 -4579 -4617 -4655 -4693 -4731 -4769 -4807 -4845 -4883 -4921 -4959 -4997 -5035 -5073 -5111 -5149 -5187 -5225 -5263 -5301 -5339 -5377 -5415 -5453 -5491 -5529 -5567 -5605 -5643 -5681 -5719 -5757 -5795 -5833 -5871 -5909 -5947 -5985 Y(µm) 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 name SEGC118 SEGA119 SEGB119 SEGC119 SEGA120 SEGB120 SEGC120 SEGA121 SEGB121 SEGC121 SEGA122 SEGB122 SEGC122 SEGA123 SEGB123 SEGC123 SEGA124 SEGB124 SEGC124 SEGA125 SEGB125 SEGC125 SEGA126 SEGB126 SEGC126 SEGA127 SEGB127 SEGC127 SEGA128 SEGB128 SEGC128 SEGA129 SEGB129 SEGC129 SEGA130 SEGB130 SEGC130 SEGA131 SEGB131 SEGC131 DUMMY DUMMY COMB0 COMB1 COMB2 COMB3 COMB4 COMB5 COMB6 COMB7 (µm) -6023 -6061 -6099 -6137 -6175 -6213 -6251 -6289 -6327 -6365 -6403 -6441 -6479 -6517 -6555 -6593 -6631 -6669 -6707 -6745 -6783 -6821 -6859 -6897 -6935 -6973 -7011 -7049 -7087 -7125 -7163 -7201 -7239 -7277 -7315 -7353 -7391 -7429 -7467 -7505 -7543 -7581 -7619 -7657 -7695 -7733 -7771 -7809 -7847 -7885 (µm) 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 name COMB8 COMB9 COMB10 COMB11 COMB12 COMB13 COMB14 COMB15 COMB16 COMB17 COMB18 COMB19 COMB20 COMB21 COMB22 COMB23 COMB24 COMB25 DUMMY DUMMY COMB26 COMB27 COMB28 COMB29 COMB30 COMB31 COMB32 COMB33 COMB34 COMB35 COMB36 COMB37 COMB38 COMB39 COMB40 COMB41 COMB42 COMB43 COMB44 COMB45 COMB46 COMB47 COMB48 COMB49 COMB50 COMB51 COMB52 COMB53 COMB54 COMB55 (µm) -7923 -7961 -7999 -8037 -8075 -8113 -8151 -8189 -8227 -8265 -8303 -8341 -8379 -8417 -8455 -8493 -8531 -8569 -8607 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 (µm) 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 -110 -148 -186 -224 -262 -300 -338 -376
Ver.2004-08-05
NJU6854
chip size (chip center
name COMB56 COMB57 COMB58 COMB59 COMB60 COMB61 COMB62 COMB63 COMB64 COMB65 DUMMY X(µm) -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 Y(µm) -414 -452 -490 -528 -566 -604 -642 -680 -718 -756 -794 name (µm) (µm) name (µm) (µm)
Ver.2004-08-05
NJU6854
BLOCK DIAGRAM
SEGA131 SEGB131 SEGC131
VSSHA VOUT C1C2+ C2C3+ C3C4+ C4C5+ C5VREG VREF OSCI OSCO TEST VDDA VSSA Bias Voltage Generator
Driver Power
Segment Driver
Common Driver
Grayscale Palettes Address Register Address Decoder Address Counter
Grayscale Control Circuit Data Latch Circuit
Driver Control
Line Address Decoder Line Address Register Ver.2004-08-05
Display Data 132RGB 278.784bit
address decoder Voltage Regulator Generator Display Timing Generator Oscillator Circuit Interface address counter address register Data manager
Display Control Duty Manager
Instruction Decoder
Register Control
Register
Interface
Buffer
SEL68 RESb D4/SPOL D3/SMODE D1/SDA D0/SCL LDAT LSCK LREQ LRESb
Line Counter
Voltage Booster
COMA0 COMA65 COMB0 COMB65 Decoder Holder
SEGA0 SEGB0 SEGC0
NJU6854
POWER SUPPLY BLOCK DIAGRAM
Temp Coefficient
Setting Register
temperature bias circuit
Bias setting register
VREG VREF
This point VREG
VOUT C1C2+ C2C3+ C3C4+ C4C5+ C5VEE DC/DC booster Voltage converter step setting register VREG gain setting register Electric volume Register
Note) When external VREF used, keep Reference Voltage Circuit open (VGOFF="0", VBON="0").
Ver.2004-08-05
NJU6854
TERMINAL DESCRIPTION
Power Supply
64-69 26,32,42 33,43 57-63 95-104 206-222 Terminal VDDA VSSA VSSHA VSSH C1C2+ C2C3+ C3C4+ C4C5+ C5VBA VREF VREG VOUT Power Power Power Power Power Power Description Power Supply Logic Circuits VDDA internally connected SEL68 necessary, cannot used main power supply. VDDA should open used VSSA internally connected SEL68 necessary, cannot used main GND. VSSA should open used. logic circuits voltage converter circuits voltage booster Bias Voltages When internal power supply used, internal bias voltages (V0-V4) activated "Power Control" instruction. Stabilizing capacitors required between each bias voltage VSS. When external power supply used, bias voltages externally supplied individually, with following relation maintained: VSSH<V4<V3<V2<V1<V0 Capacitor Connection Voltage Booster Capacitor Connection Voltage Booster Capacitor Connection Voltage Booster Capacitor Connection Voltage Booster Capacitor Connection Voltage Booster Reference-Voltage Generator Output (typically 1.9V with temperature compensation function) Voltage Booster Input normally connected VDD. Voltage Regulator Input Voltage Regulator Output Connect this with stabilizing capacitor Voltage Booster Output Connect this with stabilizing capacitor
176-205
Power/O
116-127 128-139 140-151 152-163 164-175 85-89 70-84 90-94 105-109 110-115
Power Power Power Power Power Power Power Power Power Power
Ver.2004-08-05
NJU6854
Interface
Terminal RESb D0/SCL D1/SDA D3/SMODE D4/SPOL D5~D7 Reset Active Parallel Interface 8-bit Bi-directional Bus(P/S="H") Serial Interface SDA: Serial Data SCL: Shift Clock SMODE: 3-/4-line Serial Mode Select SPOL: Polarity Select (3-line Serial Interface Mode) 8-bit Bi-directional 16-bit length mode, D15-D8 assigned upper 8-bit data bus. serial interface mode 8-bit parallel interface mode, D15-D8 should fixed "L". Chip Select Active Register Select This signal interprets transferred data display data instruction. Data Instruction Display Data Description
34-41
44-51
D8~D15
RDb(E)
(R/W)
80-series Interface (P/S="H", SEL68="L") Data Read (RDb) Signal Active 68-series Interface (P/S="H", SEL68="H") Enable Signal Active 80-series Interface (P/S="H", SEL68="L") Data Write (WRb) Signal Active 68-series Interface (P/S="H", SEL68="H") Data Read Write (R/W) Signal Status Mode Select Read Write
SEL68
SEL86
68-series
80-series
Parallel/Serial Interface Mode Select Display Read Data Serial Clock Instruction /Write RDb, (D1) Write Only (D0) serial interface mode (P/S="L"), RDb, WRb, D5-D15 should fixed "L",. Chip Select Maker test terminal This terminal must fixed user's application.
TEST
Ver.2004-08-05
NJU6854
Output
Terminal Segment Drivers Output Mode Normal Reverse SEGA0~ SEGA131, SEGB0~ SEGB131, SEGC0~ SEGC131 Turn-off Turn-on Description
295-690
signal Display Data
Nomal mode Reverse mode
Normally open. Normally open. Normally open. Common Divers Output Data
225-292
COMA0~ COMA65 COMB0~ COMB65
Output level VSSH
Oscillator
OSCI OSCO When using internal resistor, connect OSCI keep OSCO open When using external resistor, connect OSCI OSCO with external resistor, using external clock, input duty signal into OSCI.
White Driver Ports
LDAT LSCK LREQ LRESb White control port: data input/output White control port: shift clock output White control port: data request output White control port: reset output
Ver.2004-08-05
NJU6854
FUNCTIONAL DESCRIPTION
INTERFACE
(1-1) Selection Parallel/Serial Interface Mode
selects parallel serial interface mode, shown Table serial interface mode, neither display data DDRAM instruction data registers read out.
Table Selection Parallel/Serial Interface Mode Mode Parallel Serial NOTE) "L". (1-2) Selection Mode
SEL68 SEL68
Data D7-D0 (D15-D0)
parallel interface mode, SEL68 selects 80-series mode, shown Table
Table Selection Mode SEL68 Mode 68-series 80-series (1-3) Data Recognition Data D7-D0 (D15-D0) D7-D0 (D15-D0)
parallel interface mode, data from interpreted display data instruction according combination (R/W) signals, shown Table
Table Data Recognition (Parallel Interface Mode) 68-series 80-series
Function Read Instruction Write Instruction Read Display Data Write Display Data
(1-4) Selection 3-/4-line Serial Interface Mode
serial interface mode, SMODE selects 4-line serial interface mode, shown Table
Table Selection 3-/4-line Serial Interface Mode SMODE Serial Interface Mode 3-line 4-line (1-5) 4-line Serial Interface Mode
While chip select active (CSb="L"), enabled. While chip select inactive (CSb="H"), disabled, internal shift register internal counter being initialized. 8-bit serial data latched rising edge signal order D6,., converted into 8-bit parallel data timing internal signal produced from signal. data interpreted display data instruction according
Table Data Recognition (4-line Serial Interface) Data Recognition Instruction Display Data
Ver.2004-08-05
NJU6854
Note that should right after data transmission during non-access because serial interface susceptible external noises which cause malfunctions. added safety, inactivate chip-select (CSb="H") temporary whenever 8-bit data transmission completed. illustrates interface timing 4-line serial interface mode.
VALID
4-line Serial Interface Timing
(1-6) 3-line Serial Interface Mode
While chip select active (CSb="L"), enabled. While chip select active (CSb="H"), disabled, internal shift register internal counter being initialized. 9-bit serial data latched rising edge signal order D6,., then converted into 9-bit parallel data timing internal signal produced from signal. data interpreted display data instruction according combination SPOL status, follows.
Table Data Recognition (3-line Serial Interface) SPOL=L SPOL=H Data Recognition Data Recognition Display Data Instruction Instruction Display Data
Note that should right after data transmission during non-access because serial interface susceptible external noises which cause malfunctions. added safety, inactivate chip-select (CSb="H") temporary whenever 9-bit data transmission completed. illustrates interface timing 3-line serial interface mode.
3-line Serial Interface Timing
Ver.2004-08-05
NJU6854
(1-7) Data Write
While chip select active (CSb="L"), data from written into DDRAM instruction register. When "L", data interpreted display data which stored DDRAM. display data latched rising edge signal 80-series mode, falling edge signal 68-series mode.
Table Data Recognition Data Recognition Display Data Instruction
8-bit access DDRAM
D0~D7 DATA0 DATA1 DATA2 DATA3
Accessing Instruction Register Accessing DDRAM
8-bit access Instruction Register
MSB=0/Table Address /Register Address D0~D7 Data Access Datat0 MSB=1/Table Address /Counter Number Data Access Datat0 Datatn-1
Data Write Operations 8-bit
Ver.2004-08-05
NJU6854
16-bit access DDRAM
DATA0 DATA1 DATA2 DATA3
D8~D15 D0~D7
DATA0
DATA1
DATA2
DATA3
Accessing Instruction Register Accessing DDRAM
16-bit access Instruction Register
MSB=0/Table MSB=0/Table Address/Register Address/Register Address Address MSB=1/Table Address/Counter Number(n)
D8~D15
code
code
code invalid
DATA0
DATAn-2
D0~D7
DATA0
DATA0
DATA1
DATAn-2
Data Write Operations 16-bit
Ver.2004-08-05
NJU6854
(1-8) Data Read
Just after address setting data write operation, make sure conduct dummy read operation once. reason lies below, data from temporarily held built-in holder, then released internal data bus, therefore dummy data will read "Display Data Read" instruction, wanted data will read instruction.
Display Data Read 8-bit
dummy read code address set(AX,AY) address= address= address=
Display Data Read 16-bit
dummy read code dummy read address set(AX,AY) address=n data read address data read data read address address
Instruction Data Read 8-bit
D0~D7
instruction
address Table address /register address
data Data read
Instruction Data Read 16-bit
Data read instruction data invalid address data invalid
address Table address register address
Data Read Operations
Ver.2004-08-05
NJU6854
(1-9) Selection 8-/16-bit Length (Parallel Interface Mode)
Either 16-bit length selected (SWIF) register.
SWIF 8-bit
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
SWIF 16-bit
assignment determined (UDS) register.
16-bit access
Internal
Internal
8-bit access
Internal access
access
Internal
access
access
During 8-bit access, D15~D8 pins become high impedance, make sure them "L".
INITIAL DISPLAY LINE
Initial Display Line register(HST) specifies DDRAM address, display data corresponding this address will displayed Scan Start address specified Initial Display Line register preset into line counter whenever becomes "H". rising edge signal, line counter counted-up, then display data latched into data latch circuit. falling edge signal, latch data released grayscale control circuit decide grayscale level, then segment drivers (i=0 131) generate waveforms.
Ver.2004-08-05
NJU6854
DDRAM
(3-1) DDRAM Address Range
DDRAM capable bits address 2,112 bits (16-bit 132-segment) address. address from Address setting outside these ranges allowed, otherwise cause malfunctions. When auto-increment(auto-decrement) function used during DDRAM access, address and/or address will automatically increased(decreased). This operation independent from line counter count-up (count-down). X-address 16bit 16bit
Y-address
16bit
16bit
(3-2) Window Area DDRAM Access
Besides normal DDRAM access discussed previously, possible access only specified window area using CFG, ADRH, ADRL, EADRH EADRL registers define start point point. When auto-increment(auto-decrement) function enabled, address and/or address will automatically increased(decreased) whenever DDRAM accessed. And, start point specified address Register (ADRH) address Register(ADRL), point Window address Register(EADRH) Window address Register(EADRL). details, refer Instruction Table. typical sequence window area setting listed below. (AIM1), (AIM0), (VWR), (IDSY), (IDSX), (WIN) register. start point ADRH ADRL register. point EADRH EADRL register. Window area DDRAM accessed.
Address Start Point Address
Window Area
Point DDRAM Area
NOTE1)
following relationship should maintained avoid malfunctions. (Window Start address) (Window address) Maximum address (Window Start address) (Window address) Maximum address Auto-increment window area
Start Address Address Start Address Address
NOTE2)
Column Address
Address
NOTE3)
When AIM[1:0]=(0,1), read-modify-write operation valid.
Ver.2004-08-05
NJU6854
(3-3) DDRAM Access Direction
Registers setting EADRH EADRL ADRH ADRL IDSX IDSY DDDRAM Access Direction Remark
00,00 01,00 00,83 00,00 00,83 00,00 00,83 01,83 00,00 00,83
83,00
83,83 82,00 83,00
83,83 83,00
83,83 83,00
82,83 83,83
Window Area 06,10 07,10 06,6A 7D,6A 7D,10
Window Area 06,10 06,6A 7D,6A 7C,10 7D,10
Window Area 06,10 06,6A 07,6A 7D,6A 7D,10
Window Area 06,10 06,6A 7C,6A 7D,6A 7D,10
Ver.2004-08-05
NJU6854
Registers setting EADRH EADRL ADRH ADRL IDSX IDSY DDDRAM Access Direction Remark
00,00 00,01 00,83 00,00 00,83 00,00 00,82 00,83 00,00 00,83
83,00
83,83 83,00 83,01
83,83 83,00
83,83 83,00
83,82 83,83
Window Area 06,10 06,11 06,6A 7D,10 7D,6A
Window Area 06,10 06,6A 7D,10 7D,11 7D,6A
Window Area 06,10 06.69 06,6A 7D,6A 7D,10
Window Area 06,10 06,6A 7D,69 7D,6A 7D,10
Ver.2004-08-05
NJU6854
(3-4) Segment Shift Direction
DDRAM access direction selected through setting D7(REF) Display Control register (DISPLAY), This function enables reverse segment shift direction reduce restriction location module.
(3-5) Block Diagram DDRAM Peripheral Circuit
SEGMENT OUTPUT
Grayscale Control Circuit
Internal Data
Data write Read data
Data Latch
REF,SWAP Segment data
Address (00H~83H)
Display Data
address
X-Address (00H-83H)
Address Counter
Register
Line Counter
Register
Ver.2004-08-05
Register
Counter
NJU6854
(3-6) DDRAM Mapping (3-6-1) (REW, SWAP) (0,0), SHIFT1 "0", SHIFT0 "0", "84H" (1/132 Duty), "00H",
"00H", SSC1 SSC2 "0", EN3PTL
HST=00H HST=05H
output
Address
SEGA131 SEGB131 -SEGC0 -SEGC131 X=00H address -X=83H
address COMA0 COMA1 COMA2
COMA63 COMA64 COMA65 COMB0 COMB1 COMB2 COMB3
COMB63 COMB64 COMB65
Segment Output SEGA0 SEGB0
Ver.2004-08-05
NJU6854
(3-6-2) (REW, SWAP) (0,0), SHIFT1 "0", SHIFT0 "0", "70H" (1/112 Duty), "00H", "0AH", SSC1 SSC2 "0", EN3PTL
HST=00H HST=05H
output
Address
SEGA131 SEGB131 -SEGC0 SEGC131 X=00H address -X=83H
address COMA0 COMA1 COMA2 COMA3 COMA4 COMA5 COMA6 COMA7 COMA8 COMA9 COMA10 COMA11 COMA12 -Unused driver
COMA63 COMA64 COMA65 COMB0 COMB1 COMB2 COMB3 COMB4 COMB5 COMB6 COMB7 COMB8 COMB9 COMB10 COMB11 COMB12
Unused driver
COMB63 COMB64 COMB65
Segment Output SEGA0 SEGB0
Ver.2004-08-05
NJU6854
(3-7) Relationship among Assignment, address Segment Driver
Three pixels(R, individually driven segment drivers (SEGAi, SEGBi, SEGCi) consist pixel color panel. display mode, 5-bit display data SEGAi SEGCi output 32-level grayscale respectively, 6-bit display data SEGBi output 64-level grayscale, total quantity possible colors 65,536(32x32x64). 4k-color mode, 4-bit display data every SEGAi, SEGBi SEGCi, total quantity possible colors 4,096(16x16x16). Weighting value display data dependent status SWAP DISPLAY register.
16-bit Access (65k-color Mode)
(REF,SWAP)=(0,0) (1,1) MODED (65,536 color display) SEGCi SEGBi SEGAi
Palette
Palette
Palette
Grayscale Palette Grayscale control PWMM[1:0]=00 level PWMM[1:0]=01 level PWMM[1:0]=11 level
control
control
control
Address Note Internal Access Address (REF :83H (REF (REF,SWAP)=(0,1) (1,0) MODED (65,536 color display) SEGCi SEGBi SEGAi
Display data
Write Data MODE[1:0]
Palette
Palette
Palette
Grayscale Palette Grayscale control PWMM[1:0]=00 level PWMM[1:0]=01 level PWMM[1:0]=11 level
control
control
control
Display data
Write Data Address Note Internal Access Address (REF= :83H (REF=
Ver.2004-08-05
MODE[1:0]
NJU6854
16-bit Access (4k-color Mode
(REF,SWAP)=(0,0) (1,1) MODED (4,096 color display) SEGCi SEGBi SEGAi
Palette
Palette
Palette
Grayscale Palette Grayscale control PWMM[1:0]=00 level PWMM[1:0]=01 level PWMM[1:0]=10 level PWMM[1:0]=11 level
control
control
control
Display data
Write Data MODE[1:0]
Address Note Internal Access Address (REF :83H (REF
(REF,SWAP)=(0,1) (1,0) MODED (4,096 color display) SEGCi SEGBi SEGAi
Palette
Palette
Palette
Grayscale Palette Grayscale control PWMM[1:0]=00 level PWMM[1:0]=01 level PWMM[1:0]=10 level PWMM[1:0]=11 level
control
control
control
Display data
Write Data MODE[1:0]
Address Note Internal Access Address (REF :83H (REF
Ver.2004-08-05
NJU6854
16-bit Access (4k-color Mode
(REF,SWAP)=(0,0) (1,1) MODED (4,096 color display) SEGCi SEGBi SEGAi
Palette
Palette
Palette
Grayscale Palette Grayscale control PWMM[1:0]=00 level PWMM[1:0]=01 level PWMM[1:0]=10 level PWMM[1:0]=11 level
control
control
control
Display data
Address Note Internal Access Address (REF :83H (REF
Write Data MODE[1:0] (upper invalid)
(REF,SWAP)=(0,1) (1,0) MODED (4,096 color display) SEGCi SEGBi SEGAi
Palette
Palette
Palette
Grayscale Palette Grayscale control PWMM[1:0]=00 level PWMM[1:0]=01 level PWMM[1:0]=10 level PWMM[1:0]=11 level
control
control
control
Display data
Address Note Internal Access Address (REF :83H (REF
Write Data MODE[1:0] upper invalid
Ver.2004-08-05
NJU6854
Relationship among Display Data, address Segment Drivers(16-bit Access Mode) 65k-color mode, MODE[1:0]=0H
SWAP IDSX 00H83H 00H83H 83H00H 83H00H Address Display Data Grayscale Palette Segment Driver Palette SEGC0
Palette SEGA0
Palette SEGB0
Palette SEGA131
Palette SEGB131
Palette SEGC131
SWAP
IDSX 00H83H 00H83H 83H00H 83H00H
Address Display Data Grayscale Palette Segment Driver Palette SEGA131
Palette SEGA0
Palette SEGB0
Palette SEGC0
Palette SEGB131
Palette SEGC131
4k-color mode MODE[1:0]=1H
SWAP IDSX 00H83H 00H83H 83H00H 83H00H Address Display Data Grayscale Palette Segment Driver
Palette SEGA0
Palette SEGB0
Palette SEGC0
Palette SEGA131
Palette SEGB131
Palette SEGC131
SWAP
IDSX 00H83H 00H83H 83H00H 83H00H
Address Display Data Grayscale Palette Segment Driver Palette SEGC0 Palette SEGA131
Palette SEGA0
Palette SEGB0
Palette SEGB131
Palette SEGC131
Ver.2004-08-05
NJU6854
4k-color mode, MODE[1:0]=2H
SWAP IDSX 00H83H 00H83H 83H00H 83H00H Address Display Data Grayscale Palette Segment Driver Palette SEGC0 Palette SEGA131
Palette SEGA0
Palette SEGB0
Palette SEGB131
Palette SEGC131
SWAP
IDSX 00H83H 00H83H 83H00H 83H00H
Address Display Data Grayscale Palette Segment Driver Palette SEGC0 Palette SEGA131
Palette SEGA0
Palette SEGB0
Palette SEGB131
Palette SEGC131
Ver.2004-08-05
NJU6854
Relationship among Display Data, address Segment Drivers(8-bit Access Mode) write data write data
65k-color mode, MODE[1:0]=0H
SWAP IDSX 00H83H 00H83H 83H00H 83H00H Address Display Data Grayscale Palette Segment Driver
Palette SEGA0
Palette SEGB0
Palette SEGC0
Palette SEGA131
Palette SEGB131
Palette SEGC131
SWAP
IDSX 00H83H 00H83H 83H00H 83H00H
Address Display Data Grayscale Palette Segment Driver Palette SEGA131
Palette SEGA0
Palette SEGB0
Palette SEGC0
Palette SEGB131
Palette SEGC131
4k-color mode, MODE[1:0]=1H
SWAP IDSX 00H83H 00H83H 83H00H 83H00H Address Display Data Grayscale Palette Segment Driver
Palette SEGA0
Palette SEGB0
Palette SEGC0
Palette SEGA131
Palette SEGB131
Palette SEGC131
SWAP
IDSX 00H83H 00H83H 83H00H 83H00H
Address Display Data Grayscale Palette Segment Driver Palette SEGC0 Palette SEGA131
Palette SEGA0
Palette SEGB0
Palette SEGB131
Palette SEGC131
Ver.2004-08-05
NJU6854
4k-color mode, MODE[1:0]=2H
SWAP IDSX 00H83H 00H83H 83H00H 83H00H Address Display Data Grayscale Palette Segment Driver Palette SEGC0 Palette SEGA131
Palette SEGA0
Palette SEGB0
Palette SEGB131
Palette SEGC131
SWAP
IDSX 00H83H 00H83H 83H00H 83H00H
Address Display Data Grayscale Palette Segment Driver Palette SEGC0 Palette SEGA131
Palette SEGA0
Palette SEGB0
Palette SEGB131
Palette SEGC131
Ver.2004-08-05
NJU6854
CONTROL
There three variable grayscale modes fixed grayscale mode NJU6854. variable grayscale mode ((PWMM1,PWMM0)=(1,1)), every Cj(j=0-31) grayscale palette select values from levels(0/127~127/127). mode, every Cj(j=0-31) grayscale palette select values from levels (0/127~127/127).
Table Grayscale mode PWMM1 PWMM0 Grayscale Mode Variable Variable Fixed Variable Grayscale Display Mode options from levels 65k-color mode, options4k-color mode options from levels 65k-color mode, options4k-color mode options from levels 4k-color mode options from levels 65k-color mode, options4k-color mode
FRAME RATE CONTROL(FRC)
(Frame Rate control) method which averages value (grayscale level) changing this value frame. used SEGBi (palette combination with control mode, that SEGBi generate grayscales grayscales total bits data (5-bit data 1-bit data).
DISPLAY TIMING GENERATOR
display timing generator generates timing clocks such (Latch Pulse), (Frame Rate) (First Line Maker) dividing oscillation frequency. used line counter data latch circuit. rising edge signal, line counter counted then display data latched into data latch circuit. falling edge signal, latch data released grayscale control circuit, then segment drivers (i=0~131) produce driving waveforms. internal data-transmission timing between DDRAM segment drivers completely independent external data-transmission timing, that makes access without concern LSI's internal operation. toggles once every frame default status, programmed toggle once every lines. used specify initial display line, which preset whenever becomes "H".
DATA LATCH CIRCUIT
data latch circuit used temporarily store display data which released grayscale control circuit. display data this circuit updated synchronization with "Display ON/OFF" "Reverse Display ON/OFF" instructions control data this circuit, does change data DDRAM.
Ver.2004-08-05
NJU6854
COMMON DRIVERS SEGMENT DRIVERS
includes 132-common drivers 396-segment drivers. common drivers generate driving waveforms formed VSSH levels. segment drivers generate waveforms formed VSSH levels.
SEGC
SEGB
SEGA
COMA0 COMA1 COMA2
SEGC
SEGB
SEGA
COMA0
COMA0 COMA1 COMA2 COMA2 COMA1
SEGA SEGC SEGB SEGA
SEGB
COMA0 COMA1 COMA2 SEGC
Driving Waveforms (1/132Duty)
Ver.2004-08-05
NJU6854
OSCILLATOR
oscillator consists resistor capacitor, generates internal clocks display timing generator voltage booster. Through Oscillation Control register(CR), oscillating signal generated using internal resistor external resistor. Besides, external clock used too. using internal resistor, ground OSCI keep OSCO open. Frequency adjusted divided using Frequency Control register(MDIV). using external resistor, connect OSCI OSCO with resistor. using external clock, input duty signal OSCI pin.
(10) POWER SUPPLY
internal power supply organized into voltage converter voltage booster. voltage converter consists reference voltage generator with temperature compensation circuit, voltage regulator with control bias voltage generator. Furthermore configuration power supply arranged setting Power Control register(TCBI) Power Control register (POW2). possible part internal power supply with external supply, shown Table
Table Configuration Power Supply
AMPON VGOFF DCON VBON Voltage Booster DISABLE Voltage Converter Voltage Regulator (VREG output) DISABLE ENABLE DISABLE DISABLE ENABLE ENABLE ENALBLE DISABLE ENABLE Reference Voltage Generator (VBA output) DISABLE DISABLE DISABLE ENABLE DISABLE DISABLE ENABLE ENABLE ENABLE Bias Generator DISABLE External Power Supply VOUT, supplied VOUT, VREF supplied VOUT, VREG supplied VOUT supplied VREF supplied VREG supplied Note
NOTE1) bias voltages externally supplied, C1±, C2±, C3±, C4±, C5±, VREF, VREG open. NOTE2) VOUT VREF externally supplied, C1±, C2±, C3±, C4±, open. NOTE3) VOUT VREG externally supplied, C1±, C2±, C3±, C4±, open. NOTE4) VOUT externally supplied, C1±, C2±, C3±, open. NOTE5) VREF externally supplied. NOTE6) VREG externally supplied
Ver.2004-08-05
NJU6854
(10-1) Voltage Booster
internal voltage booster generates 6xVEE voltage. boost level selected from 2x~6x setting Boost Level register(GVU). boost voltage VOUT must exceed 18.0V, otherwise voltage stress cause permanent damage LSI.
VOUT=18.0V VOUT=9V
VEE=3V VSSH=0V 3-time boost
VEE=3V VSSH=0V 6-time boost
Boost Voltage 5-time Boost
6-time Boost C1C2+ C2C3+ C3C4+ C4C5+ C5VOUT VSSH
C1C2+ C2C3+ C3C4+ C4C5+ C5VOUT VSSH
4-time Boost
3-time Boost
2-time Boost
C1C2+ C2C3+ C3C4+ C4C5+ C5VOUT VSSH
C1C2+ C2C3+ C3C4+ C4C5+ C5VOUT VSSH
C1C2+ C2C3+ C3C4+ C4C5+ C5VOUT VSSH
External Capacitor Connection Voltage Booster
(10-2) Electrical Volume Register (EVR)
used fine-tune voltage optimize display contrast. value controlled steps setting Electrical Volume register(EVOL).
Ver.2004-08-05
NJU6854
(10-3) Voltage Converter (10-3-1) Voltage Regulator
voltage regulator consists operational amplifier with gain control EVR. VREF voltage multiplied obtain VREG voltage, gain control GSEL Boost Level register (GVU). When GSEL=0, boost level determined VU2~VU0 bits value. When GSEL=1, booster level determined RG2~RG0 value. relationship VREG driving voltage(V0) shown below:
available voltage range control VREG gain
VREG gain =00H =00H Volt =7FH
VREF=2.7V external reference VREF=1.9V internal reference
=7FH
6.45
Relationship VREG
Table VREG gain GSEL
GSEL
VREG Gain 6.45
Remark default VU[2:0] default RG[2:0]
VREG calculated following equation:
VREG VREF Boost Level)
Note) stabilize VREG, connect capacitor VREG pin.
Ver.2004-08-05
NJU6854
(10-3-2) Reference Voltage Generator
reference voltage generator outputs about 1.9V reference voltage. When using internal power supply, connect VREF. When using external power supply, input external power into VREF keep open. temperature compensating circuit built compensation coefficient selected from following shown levels setting TCV1~TVC0 bits Power Control register(TCBI).
reference voltage -0.24% -0.20% -0.13% -0.0%
Temperature Compensation
temperature
Table Temperature Coefficient Selection
TCV[1]
TCV[0]
Output 0.13 0.20 0.24
Remark Default setting
(10-3-3) Bias Voltage Generator
bias voltage generator consists buffer amplifiers bleeder resistors, bias ratio selected from1/5~1/12 through setting B2~B0 bits Power Control register(TCBI).
Ver.2004-08-05
NJU6854
(10-4) External Components Power Supply
Using External Power Supply
Only Using Internal Power Supply
VREF VREG
VREF VREG
NJU6854
VOUT External power circuit
VOUT
Reference guide values capacitor 0.47 0.47 0~0.1uF
NOTE1) grade capacitor recommended CA1-CA3. Make sure what best capacitor value particular application. NOTE2) Parasitic resistance power supply lines (VDD, VSS, VEE, VSSH, VOUT, reduces step-up efficiency voltage booster, have impact LSI's operation display quality. minimize this impact, sure shortest wires place capacitors close possible.
NJU6854
Ver.2004-08-05
NJU6854
Using Internal Power Supply without Reference Voltage Generator(1) Using Internal Power Supply without Reference Voltage Generator(2)
thermistor
VREF VREG
VREF VREG
NJU6854
VOUT
VOUT
Reference guide values capacitor 0.47 0.47 0~0.1uF
NOTE1) grade capacitor recommended CA1-CA3. Make sure what best capacitor value particular application. NOTE2) Parasitic resistance power supply lines (VDD, VSS, VEE, VSSH, VOUT, reduces step-up efficiency voltage booster, have impact LSI's operation display quality. minimize this impact, sure shortest wires place capacitors close possible.
Ver.2004-08-05
NJU6854
NJU6854
Using Internal Power Supply Without Voltage Booster
VREF VREG
External power circuit
VOUT
Reference guide values capacitor 0.47 0.47 0~0.1uF
NOTE1) grade capacitor recommended CA1-CA3. Make sure what best capacitor value particular application. NOTE2) Parasitic resistance power supply lines (VDD, VSS, VEE, VSSH, VOUT, reduces step-up efficiency voltage booster, have impact LSI's operation display quality. minimize this impact, sure shortest wires place capacitors close possible.
NJU6854
Ver.2004-08-05
NJU6854
(10-5) Power ON/OFF
protect from over current, following sequences must maintained turn power supply.
Using Internal Power Supply Power
First "VDD ON", next "Reset RESb", then "Internal power supply ON". sure execute "Display instruction later than completion this power sequence. Otherwise, unexpected pixels turned instantly.
Power
First "Reset RESb "HALT" instruction", next "VDD OFF". using different power sources VEE, must turned after reset "HALT". After that, turned off, waiting until bias voltages (V0~V4) drop below threshold level pixels.
Using External Power Supply Power
First "VDD ON", next "Reset RESb", then "External power supply ON". When using only external VOUT, first "VDD ON", next "Reset RESb", then "External VOUT ON", well. Power First "Reset RESb "HALT" instruction" isolate external bias voltages, next "VDD OFF". more safety, placing resistor series line VOUT line using only external VOUT) recommended. That resistance usually between 100.
VDD,
Rising Time Power Supply
Item Recommended Rising Time Applicable Power VDD, Note rising time time from 90%VEE
(10-6) Discharge Circuit
incorporates independently discharge circuits capacitors connected VOUT V1-V4. When setting DSI1 Discharge ON/OFF register (DISC) "1", executing reset instruction, capacitors V1-V4 discharged, same way, setting DSI2 resetting, capacitor VOUT discharged. sure turn internal external power supply during discharging, otherwise discharge circuit will function current load increase operating current.
Ver.2004-08-05
NJU6854
(10-7) Reset Function
reset function initializes following default status setting RESb "L". Usually connect RESb MPU's reset pin, that initialized simultaneously.
Table Default Status ITEM DDRAM address address DDRAM access increment mode length Initial display line Display ON/OFF Reverse display ON/OFF Display clock monitor Duty cycle ratio Vertical Blanking Area n-line Inversion ON/OFF Common scan direction Swap Electronic Volume Register(EVR) Internal Power Supply Display mode Bias ratio Colors Select Grayscale palette Aj[6:0] Grayscale palette Bj[6:0] Grayscale palette Cj[6:0] Extra palette PCX[6:0] output mode Discharge ON/OFF Initial value Undefined address increment 8bit line) OFF(Normal) 1/132 COMA0 COMA65 COMB0 COMB65 REF=0(Normal) OFF(Normal) Variable grayscale mode(64 grayscales) bias 65,536 colors Default value Default value Default value Default value Forward OFF(0)
Ver.2004-08-05
NJU6854
(11) INSTRUCTION TABLES
Table [2:0] 000B RA[3:0]
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Name
ADRH ADRL EADRH EADRL COLOR MDIV SSC1 SSC2 PCC1 PCC2
AIM1 VPC7 XEA7 YEA7 PWMM1 HST7 SSC17 SSC27 PCC17 PCC27
AIM0 VPC6 XEA6 YEA6 PWMM0 MDIV2 HCT6 HST6 SSC16 SSC26 PCC16 PCC26
VPC5 XEA5 YEA5 MDIV1 HCT5 HST5 SSC15 SSC25 PCC15 PCC25
IDSY VPC4 XEA4 YEA4 MODE1 MDIV0 HCT4 HST4 SSC14 SSC24 PCC14 PCC24
IDSX VPC3 FVC3 XEA3 YEA3 MODE0 HCT3 HST3 SSC13 SSC23 PCC13 PCC23
VPC2 FVC2 XEA2 YEA2 CRB2 HCT2 HST2 SSC12 SSC22 PCC12 PCC22
CRS1 VPC1 FVC1 XEA1 YEA1 CRB1 HCT1 HST1 SSC11 SSC21 PCC11 PCC21
CRS0 SWIF VPC0 FVC0 XEA0 YEA0 MODED CRB0 HCT0 HST0 SSC10 SSC20 PCC10 PCC20
REMARK
control Display data Configuration /Window Area ON/OFF /Increment Control Display Line Number Blank Line Number DDRAM address DDRAM address Window address Window address Display Mode/Grayscale Mode Frequency control Header Initial Display Line Scan Start Scan Start Partial Display Line Number1 Partial Display Line Number
Table1 [2:0] 001B RA[3:0]
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Name
TCBI EVOL POW2 DISPLAY ECONT DISC EDATA SSC3 PCC3
VGOFF GSEL BCKS TST0 LED27 SSC37 PCC37
VBON EVOL6 BCKG SWAP EN3PTL LED26 SSC36 PCC36
TCV1 EVOL5 PWMC1 ENLED LED25 SSC35 PCC35
TCV0 EVOL4 CKCONT SHIFT1 PWMC0 LED24 SSC34 PCC34
EVOL3 PBX3 AMPON BCK3 SHIFT0 PWMB1 LED13 LED23 SSC33 PCC33
EVOL2 PBX2 HALT BCK2 PWMB0 LED12 LED22 SSC32 PCC32
EVOL1 PBX1 DCON BCK1 PWMA1 LED11 DIS2 LED21 SSC31 PCC31
EVOL0 PBX0 BCK0 ON/OFF PWMA0 LED10 DIS1 LED20 SSC30 PCC30
REMARK
N-line Inversion Power Control Electronic Volume Display Timing Signal Monitor/Grayscale palette Power control Amplifier gain/ Booster Level Booster clock Display control Mode control Partial Display control Discharge control control signal Setting Instruction Table Scan Start Partial Display Line Number3
Ver.2004-08-05
NJU6854
Table2 [2:0] 010B RA[3:0]
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Name
PA10 PA11 PA12 PA13 PA14 PA15
PA06 PA16 PA26 PA36 PA46 PA56 PA66 PA76 PA86 PA96 PA106 PA116 PA126 PA136 PA146 PA156
PA05 PA15 PA25 PA35 PA45 PA55 PA65 PA75 PA85 PA95 PA105 PA115 PA125 PA135 PA145 PA155
PA04 PA14 PA24 PA34 PA44 PA54 PA64 PA74 PA84 PA94 PA104 PA114 PA124 PA134 PA144 PA154
PA03 PA13 PA23 PA33 PA43 PA53 PA63 PA73 PA83 PA93 PA103 PA113 PA123 PA133 PA143 PA153
PA02 PA12 PA22 PA32 PA42 PA52 PA62 PA72 PA82 PA92 PA102 PA112 PA122 PA132 PA142 PA152
PA01 PA11 PA21 PA31 PA41 PA51 PA61 PA71 PA81 PA91 PA101 PA111 PA121 PA131 PA141 PA151
PA00 PA10 PA20 PA30 PA40 PA50 PA60 PA70 PA80 PA90 PA100 PA110 PA120 PA130 PA140 PA150
REMARK
Grayscale palette (0/31) Grayscale palette (1/31) Grayscale palette (2/31) Grayscale palette (3/31) Grayscale palette (4/31) Grayscale palette (5/31) Grayscale palette (6/31) Grayscale palette (7/31) Grayscale palette (8/31) Grayscale palette (9/31) Grayscale palette (10/31) Grayscale palette (11/31) Grayscale palette (12/31) Grayscale palette (13/31) Grayscale palette (14/31) Grayscale palette (15/31)
Table3 [2:0] 011B RA[3:0]
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Name
PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31
PA166 PA176 PA186 PA196 PA206 PA216 PA226 PA236 PA246 PA256 PA266 PA276 PA286 PA296 PA306 PA316
PA165 PA175 PA185 PA195 PA205 PA215 PA225 PA235 PA245 PA255 PA265 PA275 PA285 PA295 PA305 PA315
PA164 PA174 PA184 PA194 PA204 PA214 PA224 PA234 PA244 PA254 PA264 PA274 PA284 PA294 PA304 PA314
PA163 PA173 PA183 PA193 PA203 PA213 PA223 PA233 PA243 PA253 PA263 PA273 PA283 PA293 PA303 PA313
PA162 PA172 PA182 PA192 PA202 PA212 PA222 PA232 PA242 PA252 PA262 PA272 PA282 PA292 PA302 PA312
PA161 PA171 PA181 PA191 PA201 PA211 PA221 PA231 PA241 PA251 PA261 PA271 PA281 PA291 PA301 PA311
PA160 PA170 PA180 PA190 PA200 PA210 PA220 PA230 PA240 PA250 PA260 PA270 PA280 PA290 PA300 PA310
REMARK
Grayscale palette (16/31) Grayscale palette (17/31) Grayscale palette (18/31) Grayscale palette (19/31) Grayscale palette (20/31) Grayscale palette (21/31) Grayscale palette (22/31) Grayscale palette (23/31) Grayscale palette (24/31) Grayscale palette (25/31) Grayscale palette (26/31) Grayscale palette (27/31) Grayscale palette (28/31) Grayscale palette (29/31) Grayscale palette (30/31) Grayscale palette (31/31)
Ver.2004-08-05
NJU6854
Table4 [2:0] 100B RA[3:0]
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Name
PB10 PB11 PB12 PB13 PB14 PB15
PB06 PB16 PB26 PB36 PB46 PB56 PB66 PB76 PB86 PB96 PB106 PB116 PB126 PB136 PB146 PB156
PB05 PB15 PB25 PB35 PB45 PB55 PB65 PB75 PB85 PB95 PB105 PB115 PB125 PB135 PB145 PB155
PB04 PB14 PB24 PB34 PB44 PB54 PB64 PB74 PB84 PB94 PB104 PB114 PB124 PB134 PB144 PB154
PB03 PB13 PB23 PB33 PB43 PB53 PB63 PB73 PB83 PB93 PB103 PB113 PB123 PB133 PB143 PB153
PB02 PB12 PB22 PB32 PB42 PB52 PB62 PB72 PB82 PB92 PB102 PB112 PB122 PB132 PB142 PB152
PB01 PB11 PB21 PB31 PB41 PB51 PB61 PB71 PB81 PB91 PB101 PB111 PB121 PB131 PB141 PB151
PB00 PB10 PB20 PB30 PB40 PB50 PB60 PB70 PB80 PB90 PB100 PB110 PB120 PB130 PB140 PB150
REMARK
Grayscale palette (0/31) Grayscale palette (1/31) Grayscale palette (2/31) Grayscale palette (3/31) Grayscale palette (4/31) Grayscale palette (5/31) Grayscale palette (6/31) Grayscale palette (7/31) Grayscale palette (8/31) Grayscale palette (9/31) Grayscale palette (10/31) Grayscale palette (11/31) Grayscale palette (12/31) Grayscale palette (13/31) Grayscale palette (14/31) Grayscale palette (15/31)
Table5 [2:0] 101B RA[3:0]
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Name
PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31
PB166 PB176 PB186 PB196 PB206 PB216 PB226 PB236 PB246 PB256 PB266 PB276 PB286 PB296 PB306 PB316
PB165 PB175 PB185 PB195 PB205 PB215 PB225 PB235 PB245 PB255 PB265 PB275 PB285 PB295 PB305 PB315
PB164 PB174 PB184 PB194 PB204 PB214 PB224 PB234 PB244 PB254 PB264 PB274 PB284 PB294 PB304 PB314
PB163 PB173 PB183 PB193 PB203 PB213 PB223 PB233 PB243 PB253 PB263 PB273 PB283 PB293 PB303 PB313
PB162 PB172 PB182 PB192 PB202 PB212 PB222 PB232 PB242 PB252 PB262 PB272 PB282 PB292 PB302 PB312
PB161 PB171 PB181 PB191 PB201 PB211 PB221 PB231 PB241 PB251 PB261 PB271 PB281 PB291 PB301 PB311
PB160 PB170 PB180 PB190 PB200 PB210 PB220 PB230 PB240 PB250 PB260 PB270 PB280 PB290 PB300 PB310
REMARK
Grayscale palette (16/31) Grayscale palette (17/31) Grayscale palette (18/31) Grayscale palette (19/31) Grayscale palette (20/31) Grayscale palette (21/31) Grayscale palette (22/31) Grayscale palette (23/31) Grayscale palette (24/31) Grayscale palette (25/31) Grayscale palette (26/31) Grayscale palette (27/31) Grayscale palette (28/31) Grayscale palette (29/31) Grayscale palette (30/31) Grayscale palette (31/31)
Ver.2004-08-05
NJU6854
Table6 [2:0] 110B RA[3:0]
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Name
PC10 PC11 PC12 PC13 PC14 PC15
PC06 PC16 PC26 PC36 PC46 PC56 PC66 PC76 PC86 PC96 PC106 PC116 PC126 PC136 PC146 PC156
PC05 PC15 PC25 PC35 PC45 PC55 PC65 PC75 PC85 PC95 PC105 PC115 PC125 PC135 PC145 PC155
PC04 PC14 PC24 PC34 PC44 PC54 PC64 PC74 PC84 PC94 PC104 PC114 PC124 PC134 PC144 PC154
PC03 PC13 PC23 PC33 PC43 PC53 PC63 PC73 PC83 PC93 PC103 PC113 PC123 PC133 PC143 PC153
PC02 PC12 PC22 PC32 PC42 PC52 PC62 PC72 PC82 PC92 PC102 PC112 PC122 PC132 PC142 PC152
PC01 PC11 PC21 PC31 PC41 PC51 PC61 PC71 PC81 PC91 PC101 PC111 PC121 PC131 PC141 PC151
PC00 PC10 PC20 PC30 PC40 PC50 PC60 PC70 PC80 PC90 PC100 PC110 PC120 PC130 PC140 PC150
REMARK
Grayscale palette (0/31) Grayscale palette (1/31) Grayscale palette (2/31) Grayscale palette (3/31) Grayscale palette (4/31) Grayscale palette (5/31) Grayscale palette (6/31) Grayscale palette (7/31) Grayscale palette (8/31) Grayscale palette (9/31) Grayscale palette (10/31) Grayscale palette (11/31) Grayscale palette (12/31) Grayscale palette (13/31) Grayscale palette (14/31) Grayscale palette (15/31)
Table7 [2:0] 111B RA[3:0]
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Name
PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31
PC166 PC176 PC186 PC196 PC206 PC216 PC226 PC236 PC246 PC256 PC266 PC276 PC286 PC296 PC306 PC316
PC165 PC175 PC185 PC195 PC205 PC215 PC225 PC235 PC245 PC255 PC265 PC275 PC285 PC295 PC305 PC315
PC164 PC174 PC184 PC194 PC204 PC214 PC224 PC234 PC244 PC254 PC264 PC274 PC284 PC294 PC304 PC314
PC163 PC173 PC183 PC193 PC203 PC213 PC223 PC233 PC243 PC253 PC263 PC273 PC283 PC293 PC303 PC313
PC162 PC172 PC182 PC192 PC202 PC212 PC222 PC232 PC242 PC252 PC262 PC272 PC282 PC292 PC302 PC312
PC161 PC171 PC181 PC191 PC201 PC211 PC221 PC231 PC241 PC251 PC261 PC271 PC281 PC291 PC301 PC311
PC160 PC170 PC180 PC190 PC200 PC210 PC220 PC230 PC240 PC250 PC260 PC270 PC280 PC290 PC300 PC310
REMARK
Grayscale palette (16/31) Grayscale palette (17/31) Grayscale palette (18/31) Grayscale palette (19/31) Grayscale palette (20/31) Grayscale palette (21/31) Grayscale palette (22/31) Grayscale palette (23/31) Grayscale palette (24/31) Grayscale palette (25/31) Grayscale palette (26/31) Grayscale palette (27/31) Grayscale palette (28/31) Grayscale palette (29/31) Grayscale palette (30/31) Grayscale palette (31/31)
Ver.2004-08-05
NJU6854
(12) INSTRUCTION DESCRIPTIONS
(12-1) 8-bit Access Mode
byte "0". Data instruction register transferred bytes, byte, D6~D4 used instruction table address, D3~D0 instruction register address. byte instruction data.
Instruction Register Address
(12-1-1) Instruction Register
Instruction Table Address data
access access
(Example) address DDRAM Step byte(X address)
Step
Table address
Register address
Pins setting
byte(X address)
Step byte(Y address)
Step
Table address
Register address
Pins setting
byte(Y address).
Ver.2004-08-05
NJU6854
setting byte "1", instruction data written registers successively. byte, D6~D4 used instruction table address(Table[2:0]) D3~D0 count number registers, from byte, data will automatically written successive registers.
Table address Count number(n) count count data address data address data address
(12-1-2) Auto-increment Instruction Register Address
count
counter number data written registers from address
(Example) Oscillator others. Step 8bit auto increment table address count number
Table address
count number
Pins setting
Step 8bit auto increment count
CRS1
CRS0
Step auto increment count
AIM1
AIM0
IDSY
IDSX
SWIF
Step auto increment count
VPC7
VPC6
VPC5
VPC4
VPC3
VPC2
VPC1
VPC0
Step auto increment count
FVC3
FVC2
FVC1
FVC0
Step auto increment count
Ver.2004-08-05
NJU6854
(12-2) 16-bit Access Mode (12-2-1) Instruction Register
to"0". Instruction table number, instruction register address instruction data will transferred 16-bit data. Instruction table number determined D14~D12, instruction register determined D11~D8, D7~D0 instruction data.
Table address Register address Instruction data
(Example) address DDRAM Step address setting.
Table address
Register address
data
Step address setting
Table address
Register address
data
setting byte "1", instruction data written registers successively. byte, only upper 8-bit data valid, D14~D12 used instruction table number(Table[2:0]) D11~D8 count number registers. From byte, data will automatically written successive registers.
Table address Count number(n) data address data address data address
(12-2-2) Auto Increment Instruction Register Address
data address data address data address
count number data written registers from address (Example) Oscillator Configuration control Step
Step
Table address
count number
data (don't care
AIM1
CRS1
CRS0
AIM0
IDSY
IDSX
SWIF
Step
VPC7
VPC6
VPC5
VPC4
VPC3
VPC2
VPC1
VPC0
FVC3
FVC2
FVC1
FVC0
Step
applicable)
Ver.2004-08-05
NJU6854
(12-3) Oscillation Control
Register Table0 [0H]
CRS1 CRS0
(default: {CRF, CRS1, CRS0} address: Setting Frequency
CRS1 CRS0 Function OSCI (730 kHz) OSC2 (170 kHz) OSC5 (external external source) Invalid OSC3 (1,200 kHz) OSC4 (285 kHz) Invalid Invalid
OSC5 mode, connect OSCI OSCO with resistor, input external clock signal OSCI.
(12-4) Display Data Assignment/ Window Area ONOFF/Increment Control
Register: Table [1H]
AIM1 AIM0 IDSY IDSX SWIF
(default: {AIM1, AIM0, VWR, IDSY, ISDX, WIN, UDS, SWIF} address: SWIF
SWIF length 8bit (Initial Value) 16bit
(ii) Assignment data DDRAM Access "0": lower 8-bit data corresponding lower 8-bit display data upper 8-bit data corresponding upper 8-bit display data "1": lower 8-bit data corresponding upper 8-bit display data upper 8-bit data corresponding lower 8-bit display data Access "0": data corresponding lower 8-bit display data data corresponding upper 8-bit display data "1": data corresponding upper 8-bit display data data corresponding lower 8-bit display data (iii) Window area Window area OFF(default) (iv) IDSX address auto increment/auto decrement IDSX auto increment IDSX auto decrement IDSY address auto increment/auto decrement IDSY auto increment IDSY auto decrement
Ver.2004-08-05
NJU6854
(vi) Setting direction data write /read DDRAM start from direction start from direction (vii) AIM[1:0]
AIM1 AIM0 Auto increment/decrement during data writing reading Auto increment/decrement during data writing Auto increment/decrement Prohibited
(12-5) Display Line Number
Register: TABLE0 [2H]
VPC7 VPC6 VPC5 VPC4 VPC3 VPC2 VPC1 VPC0
(default: VPC[7:0] 84H, address: VPC[7:0]: display line number (displayed pixel number direction). Setting within range 2~13202H~84H
VPC7 VPC6 VPC5 VPC4 Forbidden Forbidden VPC3 VPC2 VPC1 VPC0 Vertical Pixel Number Forbidden Forbidden
(12-6) Blank Line Number
Register TABLE0 [3H]
FVC3 FVC2 FVC1 FVC0
(default: FVC[3:0]=0H, address: FVC[3:0]: Blank line number(not displayed pixel number direction)
FVC3 FVC2 FVC1 FVC0 Vertical blanking Lines
Ver.2004-08-05
NJU6854
(12-7) Address
Register ADRH TABLE0 [4H]
(default: XA[7:0] address: address range from 83H.
(12-8) Address
Register ADRL TABLE0 [5H]
(default: YA[7:0] address: address range from 83H.
(12-9) Window Address
Register EADRH TABLE0 [6H]
XEA7 XEA6 XEA5 XEA4 XEA3 XEA2 XEA1 XEA0
(default: XEA[7:0] address: Setting address window area when window area access valid(WIN="1").
(12-10) Window Address
Register EADRL TABLE0 [7H]
YEA7 YEA6 YEA5 YEA4 YEA3 YEA2 YEA1 YEA0
(default: YEA[7:0] address: Setting address window area when window area access valid(WIN="1").
(12-11) Display Mode/Grayscale Mode
Register COLOR TABLE0 [8H]
PWMM1 PWMM0 MODE1 MODE0 MODED
(default: PWMM[1:0], MODE[1:0], MODED address: MODED Setting 65k-color 4k-color display mode
MODED Display Color Mode 65,536 Colors Mode (PWM 5bit FRC) 4,096 Colors(4bit only)
(ii) MODE[1:0]
assignment display data
MODE[1:0]
MODE1 MODE0
Input data
Remark
Note Note Note Invalid
Note 65,536 colors 5-6-5 data 4,096 colors 4-4-4 data 4,096 colors4-4-4 data, upper bits invalid
Ver.2004-08-05
NJU6854
(iii) PWMM[1:0] Setting grayscale mode through control.
PWMM1 PWMM0 Select grayscales Select grayscales Select grayscales Select grayscales Grayscale Mode mode grayscales mode from levels. mode grayscales mode from levels. mode from levels. mode grayscales mode from levels.
Using control (PWMM[1:0]) Frame rate control(FRC), following display mode selected.
MODED Display Mode 65,536 color mode 4,096 color mode control scan unavailable grayscales base grayscales selectable grayscales selectable control grayscales grayscales base base 32grayscales Forbidden selectable grayscales grayscales selectable selectable grayscales base grayscales selectable grayscales selectable
relationship among oscillating circuit, built-in clock frame frequency
Original source clock selection Internal oscillator resistor selection(0.7~1.3xR) CRF,CRS[1:0] register CRB[2:0] register
GCK(Source clock grayscale signal) signal generator Frequency dividing ratio selection (1/1~1/8) MDIV[2:0] register
BCKG
LP(Latch Pulse) signal generator Decided dividing rate(1/127,63,31,15) PWMM[1:0], MODED Duty Decided (PPC1+PPC2) (PPC1+PPC2+PPC3) 1/2~1/132
BCKG Selection
VPC,PPC1,PPC2,PPC3
Vertical blanking line Number inserted pulse(0~15)
FVC[3:0]
Source clock DCDC booster Booster clock making BCK[3:0]
FVC[3:0]
Booster clock
BLANK
CKCONT
CRB[2:0] CRS[1:0]
MDIV
MDIV[2:0]
1/127,63,31,15
PWMM[1:0]
1/duty
VPC, PPC1,PPC2,PPC3
BCKG
BCKG BCKS
BCKS
booster clock
BCK[3:0]
Block Diagram Oscillator
Frame Duty (duty blank)
Ver.2004-08-05
NJU6854
duty display mode
Display mode 65,536 color mode 4,096 color mode MODED PWMM=00 variable 1/63 1/63 control PWMM=01 PWMM=10 variable fixed 1/31 Forbidden 1/31 1/15 PWMM=11 variable 1/127 1/127
Frame frequency display mode
Usage Oscillator 1200 Display mode Grayscale mode PWMM[1:0] Duty Blank Equation
FLM=1200kHz/(1x127x(132+ 0))=72Hz Among 65,536 color Variable 1/132 undivided FLM=1200kHz/(1x127x(132+ 5))=69Hz FLM=285kHz/(1x31x(132+ 0))=70Hz Among 4,096 color Variable 1/132 undivided FLM=285kHz/(1x31x(132+10))=65Hz FLM=170kHz/(1x15x(132+ 0))=86Hz Among 4,096 color Fixed 1/132 undivided FLM=170kHz/(1x15x(132+15))=77Hz FLM=730kHz/(1x63x(132+ 0))=88Hz Among 65,536 color Variable 1/132 undivided FLM=730kHz/(1x63x(132+ 8))=83Hz NOTE): FLM: frame frequency fOSC (MDIV(1,2,3,4,5,6,7,8) PWMM(15,31,63,127) (Duty Blank))
Ver.2004-08-05
NJU6854
Colors Display Mode Display data grayscale palette.
Display data gray GS=X PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 Grayscale gray GS=1 PB10 PB10 PB10 PB11 PB11 PB11 PB12 PB12 PB12 PB13 PB13 PB13 PB14 PB14 PB14 PB15 PB15 PB15 PB16 PB16 PB16 PB17 PB17 PB17 PB18 PB18 PB18 PB19 PB19 PB19 PB20 PB20 PB20 PB21 PB21 PB21 PB22 PB22 PB22 PB23 PB23 PB23 PB24 PB24 PB24 PB25 PB25 PB25 PB26 PB26 PB26 PB27 PB27 PB27 PB28 PB28 PB28 PB29 PB29 PB29 PB30 PB30 PB30 PB31 PB31 GS=0 PB10 PB10 PB10 PB11 PB11 PB11 PB12 PB12 PB12 PB13 PB13 PB13 PB14 PB14 PB14 PB15 PB15 PB15 PB16 PB16 PB16 PB17 PB17 PB17 PB18 PB18 PB18 PB19 PB19 PB19 PB20 PB20 PB20 PB21 PB21 PB21 PB22 PB22 PB22 PB23 PB23 PB23 PB24 PB24 PB24 PB25 PB25 PB25 PB26 PB26 PB26 PB27 PB27 PB27 PB28 PB28 PB28 PB29 PB29 PB29 PB30 PB30 PB30 PB31 PB31 gray GS=X PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31
Note1) bits control Frame rate control(total bits display data), SEGBi realize 64-grayscale (32-grayscalex2) display. Note2) Real 64-grayscael realized setting bit(GS="0").
Ver.2004-08-05
NJU6854
Colors Display Mode Display data grayscale palette.
Display data gray GS=X PA11 PA13 PA15 PA17 PA19 PA21 PA23 PA25 PA27 PA29 PA31 Grayscale gray GS=X PB11 PB13 PB15 PB17 PB19 PB21 PB23 PB25 PB27 PB29 PB31 gray GS=X PC11 PC13 PC15 PC17 PC19 PC21 PC23 PC25 PC27 PC29 PC31
Note) Under colors display mode, invalid.
(12-12) Oscillating Frequency Adjustment/Frequency Dividing
Register MDIV TABLE0 [9H]
MDIV2 MDIV1 MDIV0 CRB2 CRB1 CRB0
(default: MDIV[2:0], CRB[2:0] address CRB[2:0] Frame frequency modified adjusting resistor oscillating circuit. Relationship between Resistance ratio
CRB2 CRB1 CRB0 Status Initial Resistance Ratio times Initial Resistance Ratio times Initial Resistance Ratio times Initial Resistance Ratio times Initial Resistance Ratio times Initial Resistance Ratio times Initial Resistance Ratio Forbidden
(ii) MDIV[2:0]
Oscillating Frequency external clock frequency divided.
MDIV2 MDIV1 MDIV0 Divide Ratio dividing dividing dividing dividing dividing dividing dividing dividing
Ver.2004-08-05
NJU6854
(12-13) Header
Register TABLE0 [AH]
HCT6 HCT5 HCT4 HCT3 HCT2 HCT1 HCT0
(default: [6:0] address:
small panel size(row number less than 132), this instruction used decide Header position specify available drivers. setting range from COMA0/COMB0 COMA65/COMB65. Refer "(13) Relationship Between Logic Number Physical Driver" details. Note that this instruction used specify scan start position, scan start position decided "Scan Start 1~3".
(132-VPC)/2
HCT6 HCT5 HCT4 HCT3 HCT2 HCT1 HCT0 Header COMA0/COMB0 COMA1/COMB1 COMA2/COMB2 COMA3/COMB3 COMA4/COMB4 COMA5/COMB5 COMA62/COMB62 COMA63/COMB63 COMA64/COMB64 COMA65/COMB65 Forbidden Forbidden
(12-14) Initial Display Line
Register TABLE0 [BH]
HST7 HST6 HST5 HST4 HST3 HST2 HST1 HST0
(default HST[7:0] address:
This instruction sets DDRAM address, addressed data will displayed scan start driver. available address range from 0~131.
HST7 HST6 HST5 HST4 HST3 HST2 HST1 HST0 address Forbidden Forbidden
Ver.2004-08-05
NJU6854
(12-15) Scan Start
Register SSC1 TABLE0 [CH]
SSC17 SSC16 SSC15 SSC14 SSC13 SSC12 SSC11 SSC10
(default SSC1[7:0] address:
Totally three partial area display screen once time. This instruction sets logical number scan start driver full screen display first partial display. Refer (13) Relationship between logical number physical driver details. available setting range SSC1 (VPC
(12-16) Scan Start
Register SSC2 TABLE0 [DH]
SSC27 SSC26 SSC25 SSC24 SSC23 SSC22 SSC21 SSC20
(default SSC2[7:0] address:
This instruction sets logical number scan start driver second partial display. Refer (13) Relationship between logical number physical driver details. available setting range SSC1+PCC1 SSC2 (VPC
(12-17) Line Number Partial Display
Register PCC1 TABLE0 [EH]
PCC17 PCC16 PCC15 PCC14 PCC13 PCC12 PCC11 PCC10
(default PCC1[7:0] address:
This instruction sets line number(DDRAM address range) first partial display. partial display mode, this instruction priority over Display Line Number(VPC) setting. PCC1+PCC2+PCC3 will display duty. available setting range PCC1 (VPC SSC1)
(12-18) Line Number Partial Display
Register PCC2 TABLE0 [FH]
PCC27 PCC26 PCC25 PCC24 PCC23 PCC22 PCC21 PCC20
(default PCC2[7:0] address:
This instruction sets line number(DDRAM address range) second partial display. partial display mode, this instruction priority over Display Line Number(VPC) setting. PCC1+PCC2+PCC3 will display duty. available setting range PCC2 (VPC SSC2).
(12-19) N-Line Inversion
Register TABLE1 [0H]
(default MC[7:0] address:
This instruction driving signal polarity signal) alternated every N(2=<N<=132) lines. Under default setting( MC[7:0]=0H), driving signal polarity alternates every frame.
Function Frame inversion (Default State) line inversion line inversion line Inversion Line Inversion prohibited prohibited.
Ver.2004-08-05
NJU6854
Frame Inversion (1/132 DUTY)
line line line 131st line132nd line line
(ii) Line Inversion
line line
line cycle line n-1th line line line
(12-20) Power Control
Register TCBI TABLE1 [1H]
VGOFF VBON TCV1 TCV0
(default: VGOFF, VBON, TCV[1:0] B[2:0] address: (i)VGOFF Voltage Regulator (VREG output) ON/OFF AMPON="1", Voltage Regulator Voltage Regulator (ii)VBON Reference Voltage Generator (VBA output) ON/OFF VBON Reference Voltage Circuit VBON AMPON="1" VGOFF="0", Reference Voltage Circuit (iii)TCV[1:0] Setting temperature compensation coefficient Reference Voltage Circuit. TCV[1] TCV[0] output remark Default setting 0.13 0.20 0.24
Ver.2004-08-05
NJU6854
(iv) B[2:0] Bias Ratio
Function Bias Bias Bias Bias Bias (Initial state) 1/10 Bias 1/11 Bias 1/12 Bias
(12-21) Electronic Volume Control
Register: EVOL TABLE1 [2H]
EVOL6 EVOL5 EVOL4 EVOL3 EVOL2 EVOL1 EVOL0
(default: EVOL[6:0] address: steps available
EVOL6 EVOL5 EVOL4 EVOL3 EVOL2 EVOL1 EVOL0 Output Voltage Lower Higher
VREG calculated from equation VREG VREF .(1) determined VU[2:0](boost level), RG[2:0] GSEL bits register) driving voltage calculated from equation VREG (VREG VREG) .(2) (electronic volume determined EVOL[6:0] bits EVOL register)
(12-22) Display Timing Signal Monitor/PBX Palette
Register TABLE1 [3H]
PBX3 PBX2 PBX1 PBX0
(default: MON, PBX[3:0] address: Setting FLM, signals output ON/OFF
Function FLM, signal output OFFdefault FLM, signal output
(ii) PBX[3:0] When GS="0", palette setting available. When GS="1", selected.
GS=1 PBX[3:0] register invalid (Note GS=0 PBX3 PBX2 PBX1 PBX0 Note Under colors mode palette selected data. used display grayscale between PB1.
Ver.2004-08-05
NJU6854
(12-23) Power Control
Register POW2 TABLE1 [5H]
CKCONT AMPON HALT DCON
(default: CKCONT, AMPON, HALT, DCON, address: "0": Default "1": Initialization
Note After initialization(RES="1"), turn "0". Note After initialization, least signal cycles needed wait execute next instruction.
(ii) DCON Setting voltage booster ON/OFF. DCON= "0": voltage booster DCON= "1": voltage booster (iii) HALT Setting power save mode ON/OFF HALT "0": power save mode OFF(default) HALT "1": power save mode Internal status under power save mode: Internal oscillator power supply halted state. COM/SEG outputs VSSH level voltage. External clock unacceptable. DDRAM data remained Instruction Register data remained (iv) AMPON Using together with VGOFF VBON bits Power control 1register (TCBI) voltage converter ON/OFF. AMPON voltage converter AMPON "1": voltage converter CKCONT Setting signal signal ON/OFF CKCONT "0": CKCONT "1":
Note) NJU6854 internal oscillator external clock signal generate signal. only used display clock, also used operating clock voltage booster. sure CKCONT="1" when voltage booster used(DCON= "1").
Ver.2004-08-05
NJU6854
(12-24) Booster Level/Amplifier Gain
Register TABLE1 [6H]
GSEL
(default: GSEL, RG[2:0] VU[2:0] address: GSEL Setting amplifier gain VREG GSEL Amplifier gain determined VU[2:0] bits same boost level. GSEL Amplifier gain determined RG[2:0] bits (ii)RG[2:0] When GSEL="1", relationship between RG[2:0] amplifier gain showed below.
GSEL GSEL Amplifier gain 6.45 Remark default VU[2:0] default RG[2:0]
(iii) VU[2:0] Setting boost level. when GSEL="0", also setting amplifier gain VREG.
Function Boost Times Boost Times Boost Times Boost Times Boost Times Boost Forbidden Forbidden
Ver.2004-08-05
NJU6854
(12-25) Voltage Booster Clock
Register TABLE1 [7H]
BCKS BCKG BCK3 BCK2 BCK1 BCK0
(default: BCKS, BCKG, BCK[3:0] address:
Note) NJU6854 internal oscillator external clock generate signal. only used display clock, also used operating clock voltage booster. sure CKCONT="1" when voltage booster used(DCON= "1").
BCK[3:0] Setting dividing ratio oscillating signal external clock generate
BCK3 BCK2 BCK1 BCK0 Function Dividing (There restriction) Dividing Dividing Dividing Dividing 1/12 Dividing 1/13 Dividing 1/14 Dividing 1/15 Dividing 1/16 Dividing
Note) When BCK[3:0]=[0000, MDIV[2:0]=[000] BCKS="1" settings prohibited.
(ii) BCKG When BCKG="1", MDIV output signal equally divided into time slots. (iii) BCKS Selecting divided clock signal. BCKS signal BCKS BCKG signal
Note) There trade-off relationship between voltage booster driving capability current consumption, optimal booster clock shall decided your module.
Ver.2004-08-05
NJU6854
(12-26) Display Control
Register Display TABLE1 [8H]
SWAP SHIFT1 SHIFT0 ON/OFF
(default: REF, SWAP, SHIFT[1:0], TBC, TEN, ON/OFF address: ON/OFF Display Control ON/OFF ON/OFF "0": Display ON/OFF "1": Display (ii) "0": Normal "1": Independent from DDRAM data, pixels forced OFF. (iii) TBC(TEN "1") pixels pixels (iv) SHIFT[1:0] Setting shift direction drivers' output. SWAP Switching corresponding relationship between DDRAM data palette This shall before DDRAM data writing. SWAP "0": Normal SWAP "1": SWAP (vi) Reversing shift direction drivers' output redirecting address. This shall before DDRAM data writing. "0": Normal "1": Opposite Direction
Ver.2004-08-05
NJU6854
(12-27) Control
Register TABLE1 [9H]
PWMC1 PWMC0 PWMB1 PWMB0 PWMA1 PWMA0
(default: PWMC[1:0], PWMB[1:0],PWMA[1:0] address: PWMC[1:0], PWMB[1:0], PWMA[1:0] Setting signals SEGA, SEGB, SEGC respectively. SEGAi (i=0~131)
PWMA1 PWMA0 Output Timing Forward Backward Forward Backward alternately Shift Phase
SEGBi (i=0~131)
PWMB1 PWMB0 Output Timing Forward Backward Forward Backward alternately Shift Phase
SEGCi (i=0~131)
PWMC1 PWMC0 Output Timing Forward Backward Forward Backward alternately Shift Phase
forward backward forward backward alternatively shift phase
Ver.2004-08-05
NJU6854
(12-28) Three Partial Display Areas/ Driver Control/REV
Register ECONT TABLE1 [AH]
TST0 EN3PTL ENLED LED13 LED12 LED11 LED10
(default: TST0, EN3PTL, ENLED, REV, LED1[3:0] address: TST0 maker testing, usually "0". (ii) EN3PTL When EN3PTL="1", three specified partial areas displayed through setting SSC1[7:0]~SSC3[7:0] PCC1[7:0]~PCC3[7:0]. setting EN3PTL="0", partial area displayed. (iii) ENLED When ENLED="1", data saved LED1[3:0] used control white through control port(LDAT, LSCK, LREQ, LRESB) ENLED LDAT, LSCK, LREQ, LRESB ports invalid (high impedance) ENLED LDAT, LSCK, LREQ, LRESB ports valid. (iv) LED1 [3:0] When ENLED="1", white control ports (LDAT, LSCK, LREQ, LRESB) valid, control signal output from LDAT, LSCK, LREQ LRESB LED10, LED11, LED12 LED13 respectively. Concerning white driver, please refer NJRC white controller series (NJU6051/52/53). Besides, above mentioned bits ports used general-purpose ports too.
Note) NJRC white driver, data state will changed according request pin. When request "L", data white driver input state, when request "H", data become output state. when LREQ NJU6854 "L", LDAT output signals, when LREQ "H", LDAT input state. LDAT, LSCK, LREQ LRESB used common ports, please attention this point. LSCK, LREQ LRESB pins used 3-bit general-purpose ports too.
Example connection with NJU6053
RSTb NJU6053 DATA LRESB LREQ LSCK LDAT NJU6854
Timing Sequence data sending
LRESb LREQ
LSCK LDAT
Ver.2004-08-05
NJU6854
Timing Sequence data receiving
LRESb LREQ LSCK LDAT
Follow Chart NJU6053 Operation
Initialization NJU6053 (LRESB=L->H) "0"-> LED13 ->LED13 Data Receiving Request Active (LREQ=H) LED12
Data Sending Request Active (LREQ=L) "0"-> LED12 Data Setting(LDAT=DATA(7)) Data(7th bit) LED10
Clock Setting (LSCK=L->H) LED11 LED11 Data sending Clock Setting (LSCK=L->H) LED11 LED11 Cycle times
Clock Setting(LSCK=L->H) ->LED11 LED11 DATA sent under same
Data Receiving
Data Setting (LDAT=DATA(0)) data(0 bit) LED10 Clock Setting (LSCK=L->H) LED11 LED11
EDATA Read
instruction data read, EDATA read
Without changing data DDRAM, pixel display state inverted "0": data="1" pixel (Normal) "1": data="0" pixel (Reversed)
Ver.2004-08-05
NJU6854
(12-29) Discharge ON/OFF
Register TABLE1 [BH]
DIS2 DIS1
(default: DIS[2:1] address: DIS1 DIS1="1", capacitors connected V0~V4 pins discharge. DIS1 "0": Discharge DIS1 "1": Discharge (ii) DIS2 DIS2="1", capacitor connected VOUT discharge DIS2 "0": discharge DIS2 "1": discharge
Vout
100k(typ)
5M(typ)
DIS2
DIS1
(12-30) Driver Data
Register EDATA TABLE1 [CH]
LED27 LED26 LED25 LED24 LED23 LED22 LED21 LED20
(default: LED2[7:0] address: (i)LED2[7:0] Data from NJRC white driver(NJU6051/52/53) saved this register.
(12-31) Instruction Table/Address
Register TABLE1 [DH]
(default: RA[6:0] address: RA[6:4] Instruction table selection
Table indicator
Ver.2004-08-05
NJU6854
RA[3:0] :Register address selection during direct access, increment number selection auto increment mode.
Direct access (address selection) Auto increment setting increment number
RSS: "1": increment number auto increment mode. "0": register address selection direct access
(12-32) Scan Start
Register SSC3 TABLE1 [EH]
SSC37 SSC36 SSC35 SSC34 SSC33 SSC32 SSC31 SSC30
(default: SSC3[7:0] address: This instruction sets logical number scan start driver third partial display, setting method just Scan Start This instruction used with normal display single partial display. When EN3PTL "1", setting valid. Range: SSC2 PCC2 SSC3 (VPC
(12-33) Line Number Partial Display
Register PCC3 TABLE1 [FH]
PCC37 PCC36 PCC35 PCC34 PCC33 PCC32 PCC31 PCC30
(default: PCC3[7:0] address: This instruction line number(DDRAM address range) third partial display area. partial display mode, this instruction priority over Display Line Number(VPC) setting. PCC1+PCC2+PCC3 will display duty. When EN3PTL "1", setting valid Range: PCC3 (VPC SSC3)
Ver.2004-08-05
NJU6854
(12-34) Grayscale Palette (PA0~PA31, PB0~PB31, PC0~PC31)
Register TABLE2 [0H]
PA06 PA05 PA04 PA03 PA02 PA01 PA00
(Initialization: PA0[6:0] Register Address:
Register TABLE2 [1H]
PA16 PA15 PA14 PA13 PA12 PA11 PA10
(Initialization: PA1[6:0] Register Address:
Register TABLE2 [2H]
PA26 PA25 PA24 PA23 PA22 PA21 PA20
(Initialization: PA2[6:0] Register Address:
Register TABLE2 [3H]
PA36 PA35 PA34 PA33 PA32 PA31 PA30
(Initialization: PA3[6:0] Register Address:
Register TABLE2 [4H]
PA46 PA45 PA44 PA43 PA42 PA41 PA40
(Initialization: PA4[6:0] 12H, Register Address:
Register TABLE2 [5H]
PA56 PA55 PA54 PA53 PA52 PA51 PA50
(Initialization: PA5[6:0] 16H, Register Address:
Register TABLE2 [6H]
PA66 PA65 PA64 PA63 PA62 PA61 PA60
(Initialization: PA6[6:0] 1AH, Register Address:
Register TABLE2 [7H]
PA76 PA75 PA74 PA73 PA72 PA71 PA70
(Initialization: PA7[6:0] 1EH, Register Address:
Register TABLE2 [8H]
PA86 PA85 PA84 PA83 PA82 PA81 PA80
(Initialization: PA8[6:0] 22H, Register Address:
Register TABLE2 [9H]
PA96 PA95 PA94 PA93 PA92 PA91 PA90
(Initialization: PA9[6:0] 26H, Register Address:
Register PA10 TABLE2 [AH]
PA106 PA105 PA104 PA103 PA102 PA101 PA100
(Initialization: PA10[6:0] 2AH, Register Address:
Ver.2004-08-05
NJU6854
Register PA11 TABLE2 [BH]
PA116 PA115 PA114 PA113 PA112 PA111 PA110
(Initialization: PA11[6:0] 2EH, Register Address:
Register PA12 TABLE2 [CH]
PA126 PA125 PA124 PA123 PA122 PA121 PA120
(Initialization: PA12[6:0] 32H, Register Address:
Register PA13 TABLE2 [DH]
PA136 PA135 PA134 PA133 PA132 PA131 PA130
(Initialization: PA13[6:0] 36H, Register Address:
Register PA14 TABLE2 [EH]
PA146 PA145 PA144 PA143 PA142 PA141 PA140
(Initialization: PA14[6:0] 3AH, Register Address:
Register PA15 TABLE2 [FH]
PA156 PA155 PA154 PA153 PA152 PA151 PA150
(Initialization: PA15[6:0] 3EH, Register Address:
Register PA16 TABLE3 [0H]
PA166 PA165 PA164 PA163 PA162 PA161 PA160
(Initialization: PA16[6:0] 42H, Register Address:
Register PA17 TABLE3 [1H]
PA176 PA175 PA174 PA173 PA172 PA171 PA170
(Initialization: PA17[6:0] 46H, Register Address:
Register PA18 TABLE3 [2H]
PA186 PA185 PA184 PA183 PA182 PA181 PA180
(Initialization: PA18[6:0] 4AH, Register Address:
Register PA19 TABLE3 [3H]
PA196 PA195 PA194 PA193 PA192 PA191 PA190
(Initialization: PA19[6:0] 4EH, Register Address:
Register PA20 TABLE3 [4H]
PA206 PA205 PA204 PA203 PA202 PA201 PA200
(Initialization: PA20[6:0] 52H, Register Address:
Register PA21 TABLE3 [5H]
PA216 PA215 PA214 PA213 PA212 PA211 PA210
(Initialization: PA21[6:0] 56H, Register Address:
Ver.2004-08-05
NJU6854
Register PA22 TABLE3 [6H]
PA226 PA225 PA224 PA223 PA222 PA221 PA220
Register PA23 TABLE3 [7H]
PA236
(Initialization: PA22[6:0] 5AH, Register Address:
PA235 PA234 PA233 PA232 PA231 PA230
(Initialization: PA23[6:0] 5EH, Register Address:
Register PA24 TABLE3 [8H]
PA246 PA245 PA244 PA243 PA242 PA241 PA240
(Initialization: PA24[6:0] 62H, Register Address:
Register PA25 TABLE3 [9H]
PA256 PA255 PA254 PA253 PA252 PA251 PA250
(Initialization: PA25[6:0] 66H, Register Address:
Register PA26 TABLE3 [AH]
PA266 PA265 PA264 PA263 PA262 PA261 PA260
(Initialization: PA26[6:0] 6AH, Register Address:
Register PA27 TABLE3 [BH]
PA276 PA275 PA274 PA273 PA272 PA271 PA270
(Initialization: PA27[6:0] 6EH, Register Address:
Register PA28 TABLE3 [CH]
PA286 PA285 PA284 PA283 PA282 PA281 PA280
(Initialization: PA28[6:0] 72H, Register Address:
Register PA29 TABLE3 [DH]
PA296 PA295 PA294 PA293 PA292 PA291 PA290
(Initialization: PA29[6:0] 76H, Register Address:
Register PA30 TABLE3 [EH]
PA306 PA305 PA304 PA303 PA302 PA301 PA300
(Initialization: PA30[6:0] 7AH, Register Address:
Register PA31 TABLE3 [FH]
PA316 PA315 PA314 PA313 PA312 PA311 PA310
(Initialization: PA31[6:0] 7FH, Register Address:
Register TABLE4 [0H]
PB06 PB05 PB04 PB03 PB02 PB01 PB00
(Initialization: PB0[6:0] Register Address:
Ver.2004-08-05
NJU6854
Register TABLE4 [1H]
PB16 PB15 PB14 PB13 PB12 PB11 PB10
(Initialization: PB1[6:0] Register Address:
Register TABLE4 [2H]
PB26 PB25 PB24 PB23 PB22 PB21 PB20
Register TABLE4 [3H]
PB36 PB35
(Initialization: PB2[6:0] Register Address:
PB34 PB33 PB32 PB31 PB30
(Initialization: PB3[6:0] Register Address:
Register TABLE4 [4H]
PB46 PB45 PB44 PB43 PB42 PB41 PB40
(Initialization: PB4[6:0] 12H, Register Address:
Register TABLE4 [5H]
PB56 PB55 PB54 PB53 PB52 PB51 PB50
(Initialization: PB5[6:0] 16H, Register Address:
Register TABLE4 [6H]
PB66 PB65 PB64 PB63 PB62 PB61 PB60
(Initialization: PB6[6:0] 1AH, Register Address:
Register TABLE4 [7H]
PB76 PB75 PB74 PB73 PB72 PB71 PB70
(Initialization: PB7[6:0] 1EH, Register Address:
Register TABLE4 [8H]
PB86 PB85 PB84 PB83 PB82 PB81 PB80
(Initialization: PB8[6:0] 22H, Register Address:
Register TABLE4 [9H]
PB96 PB95 PB94 PB93 PB92 PB91 PB90
(Initialization: PB9[6:0] 26H, Register Address:
Register PB10 TABLE4 [AH]
PB106 PB105 PB104 PB103 PB102 PB101 PB100
(Initialization: PB10[6:0] 2AH, Register Address:
Register PB11 TABLE4 [BH]
PB116 PB115 PB114 PB113 PB112 PB111 PB110
(Initialization: PB11[6:0] 2EH, Register Address:
Register PB12 TABLE4 [CH]
PB126 PB125 PB124 PB123 PB122 PB121 PB120
(Initialization: PB12[6:0] 32H, Register Address:
Ver.2004-08-05
NJU6854
Register PB13 TABLE4 [DH]
PB136 PB135 PB134 PB133 PB132 PB131 PB130
(Initialization: PB13[6:0] 36H, Register Address:
Register PB14 TABLE4 [EH]
PB146 PB145 PB144 PB143 PB142 PB141 PB140
Register PB15 TABLE4 [FH]
PB156
(Initialization: PB14[6:0] 3AH, Register Address:
PB155 PB154 PB153 PB152 PB151 PB150
(Initialization: PB15[6:0] 3EH, Register Address:
Register PB16 TABLE5 [0H]
PB166 PB165 PB164 PB163 PB162 PB161 PB160
(Initialization: PB16[6:0] 42H, Register Address:
Register PB17 TABLE5 [1H]
PB176 PB175 PB174 PB173 PB172 PB171 PB170
(Initialization: PB17[6:0] 46H, Register Address:
Register PB18 TABLE5 [2H]
PB186 PB185 PB184 PB183 PB182 PB181 PB180
(Initialization: PB18[6:0] 4AH, Register Address:
Register PB19 TABLE5 [3H]
PB196 PB195 PB194 PB193 PB192 PB191 PB190
(Initialization: PB19[6:0] 4EH, Register Address:
Register PB20 TABLE5 [4H]
PB206 PB205 PB204 PB203 PB202 PB201 PB200
(Initialization: PB20[6:0] 52H, Register Address:
Register PB21 TABLE5 [5H]
PB216 PB215 PB214 PB213 PB212 PB211 PB210
(Initialization: PB21[6:0] 56H, Register Address:
Register PB22 TABLE5 [6H]
PB226 PB225 PB224 PB223 PB222 PB221 PB220
(Initialization: PB22[6:0] 5AH, Register Address:
Register PB23 TABLE5 [7H]
PB236 PB235 PB234 PB233 PB232 PB231 PB230
(Initialization: PB23[6:0] 5EH, Register Address:
Ver.2004-08-05
NJU6854
Register PB24 TABLE5 [8H]
PB246 PB245 PB244 PB243 PB242 PB241 PB240
(Initialization: PB24[6:0] 62H, Register Address:
Register PB25 TABLE5 [9H]
PB256 PB255 PB254 PB253 PB252 PB251 PB250
(Initialization: PB25[6:0] 66H, Register Address:
Register PB26 TABLE5 [AH]
PB266 PB265 PB264 PB263 PB262 PB261 PB260
Register PB27 TABLE5 [BH]
PB276
(Initialization: PB26[6:0] 6AH, Register Address:
PB275 PB274 PB273 PB272 PB271 PB270
(Initialization: PB27[6:0] 6EH, Register Address:
Register PB28 TABLE5 [CH]
PB286 PB285 PB284 PB283 PB282 PB281 PB280
(Initialization: PB28[6:0] 72H, Register Address:
Register PB29 TABLE5 [DH]
PB296 PB295 PB294 PB293 PB292 PB291 PB290
(Initialization: PB29[6:0] 76H, Register Address:
Register PB30 TABLE5 [EH]
PB306 PB305 PB304 PB303 PB302 PB301 PB300
(Initialization: PB30[6:0] 7AH, Register Address:
Register PB31 TABLE5 [FH]
PB316 PB315 PB314 PB313 PB312 PB311 PB310
(Initialization: PB31[6:0] 7FH, Register Address:
Register TABLE6 [0H]
PC06 PC05 PC04 PC03 PC02 PC01 PC00
(Initialization: PC0[6:0] Register Address:
Register TABLE6 [1H]
PC16 PC15 PC14 PC13 PC12 PC11 PC10
(Initialization: PC1[6:0] Register Address:
Register TABLE6 [2H]
PC26 PC25 PC24 PC23 PC22 PC21 PC20
(Initialization: PC2[6:0] Register Address:
Ver.2004-08-05
NJU6854
Register TABLE6 [3H]
PC36 PC35 PC34 PC33 PC32 PC31 PC30
(Initialization: PC3[6:0] Register Address:
Register TABLE6 [4H]
PC46 PC45 PC44 PC43 PC42 PC41 PC40
(Initialization: PC4[6:0] 12H, Register Address:
Register TABLE6 [5H]
PC56 PC55 PC54 PC53 PC52 PC51 PC50
(Initialization: PC5[6:0] 16H, Register Address:
Register TABLE6 [6H]
PC66 PC65 PC64 PC63 PC62 PC61 PC60
Register TABLE6 [7H]
PC76 PC75
(Initialization: PC6[6:0] 1AH, Register Address:
PC74 PC73 PC72 PC71 PC70
(Initialization: PC7[6:0] 1EH, Register Address:
Register TABLE6 [8H]
PC86 PC85 PC84 PC83 PC82 PC81 PC80
(Initialization: PC8[6:0] 22H, Register Address:
Register TABLE6 [9H]
PC96 PC95 PC94 PC93 PC92 PC91 PC90
(Initialization: PC9[6:0] 26H, Register Address:
Register PC10 TABLE6 [AH]
PC106 PC105 PC104 PC103 PC102 PC101 PC100
(Initialization: PC10[6:0] 2AH, Register Address:
Register PC11 TABLE6 [BH]
PC116 PC115 PC114 PC113 PC112 PC111 PC110
(Initialization: PC11[6:0] 2EH, Register Address:
Register PC12 TABLE6 [CH]
PC126 PC125 PC124 PC123 PC122 PC121 PC120
(Initialization: PC12[6:0] 32H, Register Address:
Register PC13 TABLE6 [DH]
PC136 PC135 PC134 PC133 PC132 PC131 PC130
(Initialization: PC13[6:0] 36H, Register Address:
Register PC14 TABLE6 [EH]
PC146 PC145 PC144 PC143 PC142 PC141 PC140
(Initialization: PC14[6:0] 3AH, Register Address:
Ver.2004-08-05
NJU6854
Register PC15 TABLE6 [FH]
PC156 PC155 PC154 PC153 PC152 PC151 PC150
(Initialization: PC15[6:0] 3EH, Register Address:
Register PC16 TABLE7 [0H]
PC166 PC165 PC164 PC163 PC162 PC161 PC160
(Initialization: PC16[6:0] 42H, Register Address:
Register PC17 TABLE7 [1H]
PC176 PC175 PC174 PC173 PC172 PC171 PC170
(Initialization: PC17[6:0] 46H, Register Address:
Register PC18 TABLE7 [2H]
PC186 PC185 PC184 PC183 PC182 PC181 PC180
Register PC19 TABLE7 [3H]
PC196
(Initialization: PC18[6:0] 4AH, Register Address:
PC195 PC194 PC193 PC192 PC191 PC190
(Initialization: PC19[6:0] 4EH, Register Address:
Register PC20 TABLE7 [4H]
PC206 PC205 PC204 PC203 PC202 PC201 PC200
(Initialization: PC20[6:0] 52H, Register Address:
Register PC21 TABLE7 [5H]
PC216 PC215 PC214 PC213 PC212 PC211 PC210
(Initialization: PC21[6:0] 56H, Register Address:
Register PC22 TABLE7 [6H]
PC226 PC225 PC224 PC223 PC222 PC221 PC220
(Initialization: PC22[6:0] 5AH, Register Address:
Register PC23 TABLE7 [7H]
PC236 PC235 PC234 PC233 PC232 PC231 PC230
(Initialization: PC23[6:0] 5EH, Register Address:
Register PC24 TABLE7 [8H]
PC246 PC245 PC244 PC243 PC242 PC241 PC240
(Initialization: PC24[6:0] 62H, Register Address:
Register PC25 TABLE7 [9H]
PC256 PC255 PC254 PC253 PC252 PC251 PC250
(Initialization: PC25[6:0] 66H, Register Address:
Ver.2004-08-05
NJU6854
Register PC26 TABLE7 [AH]
PC266 PC265 PC264 PC263 PC262 PC261 PC260
(Initialization: PC26[6:0] 6AH, Register Address:
Register PC27 TABLE7 [BH]
PC276 PC275 PC274 PC273 PC272 PC271 PC270
(Initialization: PC27[6:0] 6EH, Register Address:
Register PC28 TABLE7 [CH]
PC286 PC285 PC284 PC283 PC282 PC281 PC280
(Initialization: PC28[6:0] 72H, Register Address:
Register PC29 TABLE7 [DH]
PC296 PC295 PC294 PC293 PC292 PC291 PC290
(Initialization: PC29[6:0] 76H, Register Address:
Register PC30 TABLE7 [EH]
PC306 PC305 PC304 PC303 PC302 PC301 PC300
(Initialization: PC30[6:0] 7AH, Register Address:
Register PC31 TABLE8 [FH]
PC316 PC315 PC314 PC313 PC312 PC311 PC310
(Initialization: PC31[6:0] 7FH, Register Address:
Ver.2004-08-05
NJU6854
65k-color Mode(32 Grayscale from Levels, PWM1=1, PWM0=1)
[Three groups palettes (j=0~31) available]
Palette 0000000 0000001 0000010 0000011 0000100 0000101 0000110 0000111 0001000 0001001 0001010 0001011 0001100 0001101 0001110 0001111 0010000 0010001 0010010 0010011 0010100 0010101 0010110 0010111 0011000 0011001 0011010 0011011 0011100 0011101 0011110 0011111 0100000 0100001 0100010 0100011 0100100 0100101 0100110 0100111 0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 0110110 0110111 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111 Grayscale level 0/127 1/127 2/127 3/127 4/127 5/127 6/127 7/127 8/127 9/127 10/127 11/127 12/127 13/127 14/127 15/127 16/127 17/127 18/127 19/127 20/127 21/127 22/127 23/127 24/127 25/127 26/127 27/127 28/127 29/127 30/127 31/127 32/127 33/127 34/127 35/127 36/127 37/127 38/127 39/127 40/127 41/127 42/127 43/127 44/127 45/127 46/127 47/127 48/127 49/127 50/127 51/127 52/127 53/127 54/127 55/127 56/127 57/127 58/127 59/127 60/127 61/127 62/127 63/127 Remarks(2) Palette initial value[6:0] (marking points default positions) Palette Grayscale level 1000000 64/127 1000001 65/127 1000010 66/127 1000011 67/127 1000100 68/127 1000101 69/127 1000110 70/127 1000111 71/127 1001000 72/127 1001001 73/127 1001010 74/127 1001011 75/127 1001100 76/127 1001101 77/127 1001110 78/127 1001111 79/127 1010000 80/127 1010001 81/127 1010010 82/127 1010011 83/127 1010100 84/127 1010101 85/127 1010110 86/127 1010111 87/127 1011000 88/127 1011001 89/127 1011010 90/127 1011011 91/127 1011100 92/127 1011101 93/127 1011110 94/127 1011111 95/127 1100000 96/127 1100001 97/127 1100010 98/127 1100011 99/127 1100100 100/127 1100101 101/127 1100110 102/127 1100111 103/127 1101000 104/127 1101001 105/127 1101010 106/127 1101011 107/127 1101100 108/127 1101101 109/127 1101110 110/127 1101111 111/127 1110000 112/127 1110001 113/127 1110010 114/127 1110011 115/127 1110100 116/127 1110101 117/127 1110110 118/127 1110111 119/127 1111000 120/127 1111001 121/127 1111010 122/127 1111011 123/127 1111100 124/127 1111101 125/127 1111110 126/127 1111111 127/127 Remarks(2)
Palette initial value[6:0]
Palette initial value [6:0](1)
Palette initial value[6:0]
Palette initial value[6:0]
Palette initial value[6:0]
Palette initial value[6:0]
Palette initial value[6:0]
Palette initial value[6:0]
Palette initial value[6:0]
Palette initial value[6:0]
Palette initial value[6:0]
Palette initial value[6:0]
Palette initial value[6:0]
Palette initial value[6:0]
Palette initial value[6:0]
Palette initial value[6:0]
Palette initial value[6:0]
Palette initial value[6:0]
Palette initial value[6:0]
Palette initial value[6:0]
Palette initial value[6:0]
Palette initial value[6:0]
Palette initial value[6:0]
Palette initial value[6:0]
Palette initial value[6:0]
Palette initial value[6:0]
Palette initial value[6:0]
Palette initial value[6:0]
Palette initial value[6:0]
Palette initial value[6:0]
Palette initial value[6:0]
Palette initial value[6:0]
Remark PBX[6:0] grayscale palette enable under `0'(defaults) setting. Remark Please refer description setting range, effective rule each grayscale palettes
Ver.2004-08-05
NJU6854
65k-color Mode(32 Grayscale from Levels, PWM1=0, PWM0=0) (marking points default positions) [Three groups palettes (j=0~31) available]
Palette 000000X 000001X 000010X 000011X 000100X 000101X 000110X 000111X 001000X 001001X 001010X 001011X 001100X 001101X 001110X 001111X 010000X 010001X 010010X 010011X 010100X 010101X 010110X 010111X 011000X 011001X 011010X 011011X 011100X 011101X 011110X 011111X Grayscale level 0/63 1/63 2/63 3/63 4/63 5/63 6/63 7/63 8/63 9/63 10/63 11/63 12/63 13/63 14/63 15/63 16/63 17/63 18/63 19/63 20/63 21/63 22/63 23/63 24/63 25/63 26/63 27/63 28/63 29/63 30/63 31/63 Remarks Palette initial value[6:1] Palette initial value[6:1] Palette initial value[6:1] Palette initial value[6:1] Palette initial value[6:1] Palette initial value[6:1] Palette initial value[6:1] Palette initial value[6:1] Palette initial value[6:1] Palette initial value[6:1] Palette initial value[6:1] Palette initial value[6:1] Palette initial value[6:1] Palette initial value[6:1] Palette initial value[6:1] Palette initial value[6:1] Palette initial value[6:1] Palette 100000X 100001X 100010X 100011X 100100X 100101X 100110X 100111X 101000X 101001X 101010X 101011X 101100X 101101X 101110X 101111X 110000X 110001X 110010X 110011X 110100X 110101X 110110X 110111X 111000X 111001X 111010X 111011X 111100X 111101X 111110X 111111X Grayscale level 32/63 33/63 34/63 35/63 36/63 37/63 38/63 39/63 40/63 41/63 42/63 43/63 44/63 45/63 46/63 47/63 48/63 49/63 50/63 51/63 52/63 53/63 54/63 55/63 56/63 57/63 58/63 59/63 60/63 61/63 62/63 63/63 Remarks Palette initial value[6:1] Palette initial value[6:1] Palette initial value[6:1] Palette initial value[6:1] Palette initial value[6:1] Palette initial value[6:1] Palette initial value[6:1] Palette initial value[6:1] Palette initial value[6:1] Palette initial value[6:1] Palette initial value[6:1] Palette initial value[6:1] Palette initial value][6:1] Palette initial value[6:1] Palette initial value[6:1] Palette initial value[6:1]
65k-color Mode(32 Grayscale from Levels, PWM1=0, PWM0=1) [Three groups palettes (j=0~31) available] (marking points default positions)
Palette 00000XX 00001XX 00010XX 00011XX 00100XX 00101XX 00110XX 00111XX 01000XX 01001XX 01010XX 01011XX 01100XX 01101XX 01110XX 01111XX Grayscale level 0/31 1/31 2/31 3/31 4/31 5/31 6/31 7/31 8/31 9/31 10/31 11/31 12/31 13/31 14/31 15/31 Remarks Palette initial value[6:2] Palette initial value[6:2] Palette initial value[6:2] Palette initial value[6:2] Palette initial value[6:2] Palette initial value[6:2] Palette initial value[6:2] Palette initial value[6:2] Palette initial value[6:2] Palette initial value[6:2] Palette initial value[6:2] Palette initial value[6:2] Palette initial value[6:2] Palette initial value[6:2] Palette initial value[6:2] Palette initial value[6:2] Palette 10000XX 10001XX 10010XX 10011XX 10100XX 10101XX 10110XX 10111XX 11000XX 11001XX 11010XX 11011XX 11100XX 11101XX 11110XX 11111XX Grayscale level 16/31 17/31 18/31 19/31 20/31 21/31 22/31 23/31 24/31 25/31 26/31 27/31 28/31 29/31 30/31 31/31 Remarks Palette initial value[6:2] Palette initial value[6:2] Palette initial value[6:2] Palette initial value[6:2] Palette initial value[6:2] Palette initial value[6:2] Palette initial value[6:2] Palette initial value[6:2] Palette initial value[6:2] Palette initial value[6:2] Palette initial value[6:2] Palette initial value[6:2] Palette initial value][6:2] Palette initial value[6:2] Palette initial value[6:2] Palette initial value[6:2]
Ver.2004-08-05
NJU6854
4k-color Mode(16 Grayscale from Levels, PWM1=1, PWM0=1) Only number palettes palette1 palette3 palette31)are effective under color mode. [Three groups palettes (j=1,3,5 .29, available] (marking points default positions)
Palette 0000000 0000001 0000010 0000011 0000100 0000101 0000110 0000111 0001000 0001001 0001010 0001011 0001100 0001101 0001110 0001111 0010000 0010001 0010010 0010011 0010100 0010101 0010110 0010111 0011000 0011001 0011010 0011011 0011100 0011101 0011110 0011111 0100000 0100001 0100010 0100011 0100100 0100101 0100110 0100111 0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 0110110 0110111 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111 Grayscale level 0/127 1/127 2/127 3/127 4/127 5/127 6/127 7/127 8/127 9/127 10/127 11/127 12/127 13/127 14/127 15/127 16/127 17/127 18/127 19/127 20/127 21/127 22/127 23/127 24/127 25/127 26/127 27/127 28/127 29/127 30/127 31/127 32/127 33/127 34/127 35/127 36/127 37/127 38/127 39/127 40/127 41/127 42/127 43/127 44/127 45/127 46/127 47/127 48/127 49/127 50/127 51/127 52/127 53/127 54/127 55/127 56/127 57/127 58/127 59/127 60/127 61/127 62/127 63/127 Remarks Palette 1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 1010000 1010001 1010010 1010011 1010100 1010101 1010110 1010111 1011000 1011001 1011010 1011011 1011100 1011101 1011110 1011111 1100000 1100001 1100010 1100011 1100100 1100101 1100110 1100111 1101000 1101001 1101010 1101011 1101100 1101101 1101110 1101111 1110000 1110001 1110010 1110011 1110100 1110101 1110110 1110111 1111000 1111001 1111010 1111011 1111100 1111101 1111110 1111111 Grayscale level 64/127 65/127 66/127 67/127 68/127 69/127 70/127 71/127 72/127 73/127 74/127 75/127 76/127 77/127 78/127 79/127 80/127 81/127 82/127 83/127 84/127 85/127 86/127 87/127 88/127 89/127 90/127 91/127 92/127 93/127 94/127 95/127 96/127 97/127 98/127 99/127 100/127 101/127 102/127 103/127 104/127 105/127 106/127 107/127 108/127 109/127 110/127 111/127 112/127 113/127 114/127 115/127 116/127 117/127 118/127 119/127 120/127 121/127 122/127 123/127 124/127 125/127 126/127 127/127 Remarks
Palette initial value[6:0]
Palette initial value[6:0]
Palette initial value[6:0]
Palette initial value[6:0]
Palette initial value[6:0]
Palette initial value[6:0]
Palette initial value[6:0]
Palette initial value[6:0]
Palette initial value[6:0]
Palette initial value[6:0]
Palette initial value[6:0]
Palette initial value[6:0]
Palette initial value[6:0]
Palette initial value[6:0]
Palette initial value[6:0]
Palette initial value[6:0]
Ver.2004-08-05
NJU6854
4k-color Mode(16 Grayscale from Levels, PWM1=0, PWM0=0)
[Three groups palettes (j=1,3,5 .29, available]
Palette 000000X 000001X 000010X 000011X 000100X 000101X 000110X 000111X 001000X 001001X 001010X 001011X 001100X 001101X 001110X 001111X 010000X 010001X 010010X 010011X 010100X 010101X 010110X 010111X 011000X 011001X 011010X 011011X 011100X 011101X 011110X 011111X Grayscale level 0/63 1/63 2/63 3/63 4/63 5/63 6/63 7/63 8/63 9/63 10/63 11/63 12/63 13/63 14/63 15/63 16/63 17/63 18/63 19/63 20/63 21/63 22/63 23/63 24/63 25/63 26/63 27/63 28/63 29/63 30/63 31/63 Remarks Palette 100000X 100001X 100010X 100011X 100100X 100101X 100110X 100111X 101000X 101001X 101010X 101011X 101100X 101101X 101110X 101111X 110000X 110001X 110010X 110011X 110100X 110101X 110110X 110111X 111000X 111001X 111010X 111011X 111100X 111101X 111110X 111111X (marking points default positions) Grayscale level Remarks 32/63 33/63 34/63 35/63 Palette initial value[6:1] 36/63 37/63 38/63 39/63 Palette initial value[6:1] 40/63 41/63 42/63 43/63 Palette initial value[6:1] 44/63 45/63 46/63 47/63 Palette initial value[6:1] 48/63 49/63 50/63 51/63 Palette initial value[6:1] 52/63 53/63 54/63 55/63 Palette initial value[6:1] 56/63 57/63 58/63 59/63 Palette initial value[6:1] 60/63 61/63 62/63 63/63 Palette initial value[6:
Other recent searches
STM-16 - STM-16 STM-16 Datasheet
SFF-8472 - SFF-8472 SFF-8472 Datasheet
LCP-2488D4MDR - LCP-2488D4MDR LCP-2488D4MDR Datasheet
SN74AHC574 - SN74AHC574 SN74AHC574 Datasheet
SN54AHC574 - SN54AHC574 SN54AHC574 Datasheet
P4092 - P4092 P4092 Datasheet
NDF9011 - NDF9011 NDF9011 Datasheet
ISM900 - ISM900 ISM900 Datasheet
L1382 - L1382 L1382 Datasheet
L1382 - L1382 L1382 Datasheet
INA145 - INA145 INA145 Datasheet
EN61036 - EN61036 EN61036 Datasheet
EN61268 - EN61268 EN61268 Datasheet
DTB113ZK - DTB113ZK DTB113ZK Datasheet
BZX79 - BZX79 BZX79 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
