DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR differenti
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ICS8735I-31
DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
differential 3.3V LVPECL outputs Selectable differential clock inputs CLKx, nCLKx pair accept following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL Output frequency range: 15.625MHz 350MHz Input frequency range: 15.625MHz 350MHz range: 250MHz 700MHz Programmable dividers allow following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, External feedback "zero delay" clock regeneration with configurable frequencies Cycle-to-cycle jitter: 60ps (maximum) Output skew: 35ps (maximum) Static phase offset: 55ps 125ps 3.3V supply voltage -40°C 85°C ambient operating temperature Lead-Free package fully RoHS compliant
GENERAL DESCRIPTION
ICS8735I-31 highly versatile Differential-to-3.3V LVPECL Clock Generator HiPerClockSmember HiPerClockSfamily High Perfor mance Clock Solutions from ICS. ICS8735I-31 fully integrated configured zero delay buffer, multiplier divider, output frequency range 15.625MHz 350MHz. reference divider, feedback divider output divider each programmable, thereby allowing following output-toinput frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. external feedback allows device achieve "zero delay" between input clock output clocks. PLL_SEL used bypass system test debug purposes. bypass mode, reference clock routed around into internal output dividers.
BLOCK DIAGRAM
PLL_SEL
ASSIGNMENT
PLL_SEL SEL3 VCCO VCCA
CLK0 nCLK0 CLK1 nCLK1 CLK_SEL FB_IN nFB_IN
÷16, ÷32, ÷64, ÷128
SEL0 SEL1 CLK0 nCLK0 CLK1 nCLK1 CLK_SEL
VCCO VCCO
8:1, 4:1, 2:1, 1:1, 1:2, 1:4,
ICS8735I-31
nFB_IN FB_IN SEL2 VCCO
SEL0 SEL1 SEL2 SEL3
32-Lead LQFP 1.4mm package body Package View
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DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
Type Description
TABLE DESCRIPTIONS
Number Name SEL0 SEL1 CLK0 nCLK0 CLK1 nCLK1 CLK_SEL Input Input Input Input Input Input Input Pulldown Determines output divider values Table LVCMOS interface levels. Pulldown Determines output divider values Table LVCMOS interface levels. Pulldown Non-inver ting differential clock input. Pullup Pullup Inver ting differential clock input. Pulldown Non-inver ting differential clock input. Inver ting differential clock input. Clock select input. When HIGH, selects CLK1, nCLK1. Pulldown When LOW, selects CLK0, nCLK0. LVCMOS interface levels. Active High Master Reset. When logic HIGH, internal dividers reset causing true outputs (Qx) inver outputs (nQx) Pulldown high. When logic LOW, internal dividers outputs enabled. LVCMOS interface levels Core supply pins. Pullup Feedback input phase detector regenerating clocks with "zero delay". Pulldown Feedback input phase detector regenerating clocks with "zero delay". Pulldown Determines output divider values Table LVCMOS interface levels. Negative supply pins. Differential output pair. LVPECL interface levels. Output supply pins. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Determines output divider values Table Pulldown LVCMOS interface levels. Analog supply pin. Selects between reference clock input dividers. When LOW, selects reference clock.When HIGH, selects PLL. Pullup LVCMOS interface levels.
nFB_IN FB_IN SEL2 nQ0, VCCO nQ1, nQ2, nQ3, nQ4, SEL3 VCCA PLL_SEL
Input Power Input Input Input Power Output Power Output Output Output Output Input Power Input
NOTE: Pullup Pulldown refer internal input resistors. Table Characteristics, typical values.
TABLE CHARACTERISTICS
Symbol RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical Maximum Units
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DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
Outputs PLL_SEL Enable Mode Q0:Q4, nQ0:nQ4
TABLE CONTROL INPUT FUNCTION TABLE
Inputs SEL3 SEL2 SEL1 SEL0 Reference Frequency Range (MHz) 62.5 31.25 87.5 15.625 43.75 62.5 31.25 87.5 62.5 62.5 31.25 87.5 15.625 43.75 31.25 87.5 15.625 43.75 15.625 43.75
TABLE BYPASS FUNCTION TABLE
Inputs SEL3
8735AYI-31
SEL2
SEL1
SEL0
Outputs PLL_SEL Bypass Mode Q0:Q4, nQ0:nQ4
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DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
4.6V -0.5V 0.5V 50mA 100mA 47.9°C/W lfpm) -65°C 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only. Functional operation product these conditions conditions beyond those listed Characteristics Characteristics implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, Inputs, Outputs, Continuous Current Surge Current Package Thermal Impedance, Storage Temperature, TSTG
TABLE POWER SUPPLY CHARACTERISTICS, VCCA VCCO 3.3V±5%, -40°C 85°C
Symbol VCCA VCCO ICCA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical Maximum 3.465 3.465 3.465 Units
TABLE LVCMOS/LVTTL CHARACTERISTICS, VCCA VCCO 3.3V±5%, -40°C 85°C
Symbol Parameter Input High Voltage Input Voltage Input High Current CLK_SEL, SEL0, SEL1, SEL2, SEL3 PLL_SEL CLK_SEL, SEL0, SEL1, SEL2, SEL3 PLL_SEL 3.465V 3.465V 3.465V 3.465V -150 Test Conditions Minimum -0.3 Typical Maximum Units
Input Current
TABLE DIFFERENTIAL CHARACTERISTICS, VCCA VCCO 3.3V±5%, -40°C 85°C
Symbol Parameter Input High Current Input Current CLK0, CLK1, FB_IN nCLK0, nCLK1, nFB_IN CLK0, CLK1, FB_IN nCLK0, nCLK1, nFB_IN Test Conditions 3.465V 3.465V 3.465V 3.465V -150 0.15 0.85 Minimum Typical Maximum Units
Peak-to-Peak Input Voltage
VCMR Common Mode Input Voltage; NOTE NOTE single ended applications, maximum input voltage CLKx, nCLKx 0.3V. NOTE Common mode voltage defined VIH.
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DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
Test Conditions Minimum VCCO VCCO Typical Maximum VCCO VCCO Units
TABLE LVPECL CHARACTERISTICS, VCCA VCCO 3.3V±5%, -40°C 85°C
Symbol Parameter VSWING Output High Voltage; NOTE Output Voltage; NOTE Peak-to-Peak Output Voltage Swing
NOTE Outputs terminated with VCCO
TABLE INPUT FREQUENCY CHARACTERISTICS, VCCA VCCO 3.3V±5%, -40°C 85°C
Symbol Parameter Input Frequency CLK0, nCLK0, CLK1, nCLK1 Test Conditions PLL_SEL PLL_SEL Minimum 15.625 Typical Maximum Units
TABLE CHARACTERISTICS, VCCA VCCO 3.3V±5%, -40°C 85°C
Symbol fMAX sk(o) jit(cc) Parameter Output Frequency Propagation Delay; NOTE Static Phase Offset; NOTE Output Skew; NOTE Cycle-to-Cycle Jitter NOTE Lock Time Output Rise/Fall Time PLL_SEL 350MHz PLL_SEL Test Conditions Minimum Typical Maximum +180 Units
Output Duty Cycle NOTE Measured from differential input crossing point differential output crossing point. NOTE Defined time difference between input reference clock averaged feedback input signal, when locked input reference frequency stable. NOTE Defined skew between outputs same supply voltage with equal load conditions. Measured output differential cross points. NOTE This parameter defined accordance with JEDEC Standard
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DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
VCCA, VCCO
SCOPE
LVPECL
nCLK0, nCLK1 CLK0, CLK1
Cross Points
-1.3V 0.165V
3.3V OUTPUT LOAD TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQ0:nQ4 Q0:Q4
tcycle
sk(o)
jit(cc) tcycle -tcycle
1000 Cycles
OUTPUT SKEW
CYCLE-TO-CYCLE JITTER
nCLK0, nCLK1 CLK0, CLK1 nFB_IN FB_IN
nCLK0, nCLK1 CLK0, CLK1 nQ0:nQ4 Q0:Q4
mean Static Phase Offset
(where random sample, mean average sampled cycles measured controlled edges)
PROPAGATION DELAY
Clock Outputs
STATIC PHASE OFFSET
nQ0:nQ4 Q0:Q4
Pulse Width
PERIOD
PERIOD
OUTPUT RISE/FALL TIME
8735AYI-31
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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tcycle
ICS8735I-31
DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR APPLICATION INFORMATION
WIRING DIFFERENTIAL INPUT ACCEPT SINGLE ENDED LEVELS
Figure shows differential input wired accept single ended levels. reference voltage V_REF VCC/2 generated bias resistors This bias circuit should located close possible input pin. ratio
might need adjusted position V_REF center input voltage swing. example, input clock swing only 2.5V 3.3V, V_REF should 1.25V R2/R1 0.609.
Single Ended Clock Input
CLKx
V_REF
nCLKx
0.1u
FIGURE SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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POWER SUPPLY FILTERING TECHNIQUES
high speed analog circuitry, power supply pins vulnerable random noise. ICS8735I-31 provides separate power supplies isolate high switching noise from outputs internal PLL. VCC, VCCA, VCCO should individually connected power supply plane through vias, bypass capacitors should used each pin. achieve optimum jitter performance, power supply isolation required. Figure illustrates resistor along with .01F bypass capacitor should connected each VCCA pin.
.01F .01F
3.3V
FIGURE POWER SUPPLY FILTERING
TERMINATION LVPECL OUTPUTS
clock layout topology shown below typical termination LVPECL outputs. different layouts mentioned recommended only guidelines. FOUT nFOUT impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors current path ground) current sources must used functionality. These outputs designed drive transmission lines. Matched impedance techniques should used maximize operating frequency minimize signal distortion. Figures show different layouts which recommended only guidelines. Other suitable clock layouts exist would recommended that board designers simulate guarantee compatibility across printed circuit clock component process variations.
3.3V
FOUT
FOUT
((VOH VOL) (VCC
FIGURE LVPECL OUTPUT TERMINATION
FIGURE LVPECL OUTPUT TERMINATION
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DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
here examples only. Please consult with vendor driver component confirm driver termination requirements. example Figure input termination applies HiPerClockS LVHSTL drivers. using LVHSTL driver from another vendor, their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
/nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL other differential signals. Both VSWING must meet VCMR input requirements. Figures show interface examples HiPerClockS CLK/nCLK input driven most common driver types. input interfaces suggested
3.3V 3.3V
3.3V 1.8V
nCLK LVHSTL HiPerClockS LVHSTL Driver
LVPECL
nCLK
HiPerClockS Input
HiPerClockS Input
FIGURE HIPERCLOCKS CLK/nCLK INPUT DRIVEN HIPERCLOCKS LVHSTL DRIVER
FIGURE HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER
3.3V 3.3V 3.3V nCLK LVPECL HiPerClockS Input
3.3V 3.3V LVDS_Driv
nCLK
Receiv
FIGURE HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER
FIGURE HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVDS DRIVER
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DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
depend selected component types, density components, density traces, stacking P.C. board.
LAYOUT GUIDELINE
schematic ICS8735I-31 layout example shown Figure ICS8735I-31 recommended board layout this example shown Figure This layout example used general guideline. layout actual system will
Space (i.e. intstalled)
CLK_SEL PLL_SEL SEL0 SEL1 SEL2 SEL3 PLL_SEL SEL3 VCCA
SEL[3:0] 0101, Divide
0.01u
(77.76 MHz)
VCCO
LVPECL_input
3.3V
(155.52 MHz)
SEL0 SEL1
PLL_SEL VCCA SEL3 VCCO
CLK_SEL 3.3V PECL Driv
nFB_IN FB_IN SEL2 VCCO
SEL0 SEL1 CLK0 nCLK0 CLK1 nCLK1 CLK_SEL
VCCO VCCO
Output Termination Example
Bypass capacitor located near power pins
(U1-9)
(U1-32)
8735-31
VCC=3.3V
0.1uF 0.1uF
VCCO=3.3V
SEL2
(U1-16)
0.1uF
VCCO
(U1-17)
(U1-24)
(U1-25)
0.1uF
0.1uF
0.1uF
FIGURE ICS8735I-31 LVPECL ZERO DELAY BUFFER SCHEMATIC EXAMPLE
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DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
trace trace delay might restricted available space board component location. While routing traces, clock signal traces should routed first should locked prior routing other signal traces. differential output traces should have same length. Avoid sharp angles clock trace. Sharp angle turns cause characteristic impedance change transmission lines. Keep clock traces same layer. Whenever possible, avoid placing vias clock traces. Placement vias traces affect trace characteristic impedance hence degrade signal integrity. prevent cross talk, avoid routing other signal traces parallel with clock traces. running parallel traces unavoidable, allow spearation least three trace widths between differential clock trace other signal trace. Make sure other signal traces routed between clock trace pair. matching termination resistors should located close receiver input pins possible.
following component footprints used this layout example: resistors capacitors size 0603.
POWER
GROUNDING
Place decoupling capacitors close possible power pins. space allows, placement decoupling capacitor component side preferred. This reduce unwanted inductance between decoupling capacitor power caused via. Maximize power ground sizes number vias capacitors. This reduce inductance between power ground planes component power ground pins. filter consisting C11, should placed close VCCA possible.
CLOCK TRACES
TERMINATION
Poor signal integrity degrade system performance cause system failure. synchronous high-speed digital systems, clock signal less tolerant poor signal integrity than other signals. ringing rising falling edge excessive ring back cause system failure. shape
VCCO
VCCA
Traces
FIGURE BOARD LAYOUT ICS8735I-31
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DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR POWER CONSIDERATIONS
This section provides information power dissipation junction temperature ICS8735I-31. Equations example calculations also provided.
Power Dissipation. total power dissipation ICS8735I-31 core power plus power dissipated load(s). following power dissipation 3.3V 3.465V, which gives worst case results. NOTE: Please refer Section details calculating power dissipated load.
Power (core)MAX VCC_MAX IEE_MAX 3.465V 150mA 519.75mW Power (outputs)MAX 30mW/Loaded Output pair outputs loaded, total power 30mW 150mW
Total Power_MAX (3.465V, with outputs switching) 519.75mW 150mW 669.75mW
Junction Temperature. Junction temperature, temperature junction bond wire bond directly affects reliability device. maximum recommended junction temperature HiPerClockSdevices 125°C.
equation follows: Pd_total Junction Temperature junction-to-ambient thermal resistance Pd_total Total device power dissipation (example calculation section above) Ambient Temperature order calculate junction temperature, appropriate junction-to-ambient thermal resistance must used. Assuming moderate flow linear feet minute multi-layer board, appropriate value 42.1°C/W Table below. Therefore, ambient temperature 85°C with outputs switching 85°C 0.670W 42.1°C/W 113.2°C. This well below limit 125°C. This calculation only example. will obviously vary depending number loaded outputs, supply voltage, flow, type board (single layer multi-layer).
Table Thermal Resistance 32-pin LQFP, Forced Convection
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W
55.9°C/W 42.1°C/W
50.1°C/W 39.4°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
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Calculations Equations.
purpose this section derive power dissipated into load. LVPECL output driver circuit termination shown Figure
ICS8735I-31
DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
VCCO
VOUT VCCO
FIGURE LVPECL DRIVER CIRCUIT
TERMINATION
calculate worst case power dissipation into load, following equations which assume load, termination voltage
logic high, VOUT
CCO_MAX
OH_MAX
CCO_MAX
0.9V
OH_MAX
0.9V 1.7V
logic low, VOUT
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
1.7V
Pd_H power dissipation when output drives high. Pd_L power dissipation when output drives low. Pd_H 2V))/R
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
[(2V
CCO_MAX
OH_MAX
))/R
CCO_MAX
OH_MAX
[(2V 0.9V)/50] 0.9V 19.8mW ))/R
Pd_L
OL_MAX
CCO_MAX
2V))/R
CCO_MAX
OL_MAX
[(2V
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
[(2V 1.7V)/50] 1.7V 10.2mW Total Power Dissipation output pair Pd_H Pd_L 30mW
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DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR RELIABILITY INFORMATION
TABLE JAVS. FLOW TABLE
LEAD LQFP
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W
55.9°C/W 42.1°C/W
50.1°C/W 39.4°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
TRANSISTOR COUNT
transistor count ICS8735I-31 2969
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DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
LEAD LQFP
PACKAGE OUTLINE SUFFIX
TABLE PACKAGE DIMENSIONS
JEDEC VARIATION DIMENSIONS MILLIMETERS SYMBOL 0.45 -0.05 1.35 0.30 0.09 MINIMUM NOMINAL -1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 -0.75 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
Reference Document: JEDEC Publication MS-026
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DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
Marking Package Lead LQFP Lead LQFP Lead "Lead-Free" LQFP Lead "Lead-Free" LQFP Shipping Packaging tray 1000 tape reel tray 1000 tape reel Temperature -40°C 85°C -40°C 85°C -40°C 85°C -40°C 85°C
TABLE ORDERING INFORMATION
Part/Order Number ICS8735AYI-31 ICS8735AYI-31T ICS8735AYI-31LF ICS8735AYI-31LFT
NOTE: Parts that ordered with "LF" suffix part number Pb-Free configuration RoHS compliant.
aforementioned trademark, HiPerClockSis trademark Integrated Circuit Systems, Inc. subsidiaries United States and/or other countries. While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial applications. other applications such those requiring extended temperature range, high reliability, other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 8735AYI-31
REV. APRIL 2005
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