FEMTOCLOCKSCRYSTAL-TO- LVPECL CLOCK GENERATOR FEATURES Diffe
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ICS843071I
FEMTOCLOCKSCRYSTAL-TO- LVPECL CLOCK GENERATOR
FEATURES
Differential LVPECL output Crystal oscillator interface, 18pF parallel resonant crystal (20.833MHz 28.3MHz) Output frequency range: 62.5MHz 170MHz range: 500MHz 680MHz phase jitter 150MHz, using 25MHz crystal (12KHz 20MHz): 0.67ps (typical) 3.3V 2.5V operating supply -40°C 85°C ambient operating temperature
GENERAL DESCRIPTION
ICS843071I Serial (SATA)/Serial Attached SCSI (SAS) Clock Generator HiPerClockSmember HiPerClocks family high performance devices from ICS. ICS843071I uses 18pF parallel resonant crystal over range 20.833MHz 28.3MHz. SATA/SAS applications, 25MHz crystal used either 75MHz 150MHz selected with FREQ_SEL pin. ICS843071I excellent <1ps phase jitter performance, over 12KHz 20MHz integration range. ICS843071I packaged small 8-pin TSSOP, making ideal systems with limited board space.
COMMON CONFIGURATION TABLE SERIAL ATA/SERIAL ATTACHED SCSI
Inputs Crystal Frequency (MHz) FREQ_SEL Multiplication Value Output Frequency (MHz)
BLOCK DIAGRAM
FREQ_SEL Pullup
ASSIGNMENT
FREQ_SEL
VCCA XTAL_OUT XTAL_IN FREQ_SEL
XTAL_IN
XTAL_OUT
Phase Detector
500MHz 680MHz
ICS843071I
8-Lead TSSOP 4.40mm 3.0mm 0.925mm package body Package View
(fixed)
Preliminary Information presented herein represents product prototyping pre-production. noted characteristics based initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves right change circuitry specifications without notice. 843071AGI REV. MARCH 2005
ICS843071I
FEMTOCLOCKSCRYSTAL-TO- LVPECL CLOCK GENERATOR
Type Power Input Power Input Pullup Description Analog supply pin. Crystal oscillator interface. XTAL_IN input, XTAL_OUT output. Negative supply pin. Frequency select pin. LVCMOS/LVTTL interface levels. Differential clock outputs. LVPECL interface levels. Core supply pin.
TABLE DESCRIPTIONS
Number Name VCCA XTAL_OUT, XTAL_IN FREQ_SEL nQ0,
Output Power
NOTE: Pullup refers internal input resistors. Table Characteristics, typical values.
TABLE CHARACTERISTICS
Symbol RPULLUP Parameter Input Capacitance Input Pullup Resistor Test Conditions Minimum Typical Maximum Units
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FEMTOCLOCKSCRYSTAL-TO- LVPECL CLOCK GENERATOR
4.6V -0.5V 10mA 15mA 101.7°C/W mps) -65°C 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only. Functional operation product these conditions conditions beyond those listed Characteristics Characteristics implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, Inputs, Outputs, (LVDS) Continuous Current Surge Current Package Thermal Impedance, Storage Temperature, TSTG
TABLE POWER SUPPLY CHARACTERISTICS, VCCA 3.3V±5%, -40°C 85°C
Symbol VCCA ICCA Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 Typical Maximum 3.465 3.465 Units
TABLE POWER SUPPLY CHARACTERISTICS, VCCA 2.5V±5%, -40°C 85°C
Symbol VCCA ICCA Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 2.375 2.375 Typical Maximum 2.625 2.625 Units
TABLE LVCMOS/LVTTL CHARACTERISTICS, VCCA 3.3V±5% 2.5V±5%, -40°C 85°C
Symbol Parameter Input High Voltage Input Voltage Input High Current Input Current FREQ_SEL FREQ_SEL Test Conditions 3.3V 2.5V 3.3V 2.5V 3.465V 2.625V 3.465V 2.625V, -150 Minimum -0.3 -0.3 Typical Maximum Units
NOTE Outputs terminated with VCC/2. Parameter Measurement Information Section, "Output Load Test Circuit" diagrams.
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FEMTOCLOCKSCRYSTAL-TO- LVPECL CLOCK GENERATOR
Test Conditions Minimum Typical Maximum Units
TABLE LVPECL CHARACTERISTICS, 3.3V±5% 2.5V±5%, -40°C 85°C
Symbol VSWING Parameter Output High Voltage; NOTE Output Voltage; NOTE Peak-to-Peak Output Voltage Swing
NOTE Outputs terminated with
TABLE CRYSTAL CHARACTERISTICS
Parameter Mode Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance 20.833 Test Conditions Minimum Typical Fundamental 28.3 Maximum Units
TABLE CHARACTERISTICS, VCCA 3.3V±5%, -40°C 85°C
Symbol fOUT Parameter Output Frequency Phase Jitter Random); NOTE Output Rise/Fall Time 150MHz Integration Range: 12KHz 20MHz 75MHz Integration Range: 12KHz 20MHz Test Conditions Minimum 62.5 0.67 0.60 Typical Maximum Units
Output Duty Cycle NOTE Please refer Phase Noise Plots following this section.
TABLE CHARACTERISTICS, VCCA 2.5V±5%, -40°C 85°C
Symbol fOUT Parameter Output Frequency Phase Jitter Random); NOTE Output Rise/Fall Time 150MHz Integration Range: 12KHz 20MHz 75MHz Integration Range: 12KHz 20MHz Test Conditions Minimum 62.5 0.78 0.75 Typical Maximum Units
Output Duty Cycle NOTE Please refer Phase Noise Plots following this section.
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FEMTOCLOCKSCRYSTAL-TO- LVPECL CLOCK GENERATOR
TYPICAL PHASE NOISE 75MHZ
-100 -110 -120 -130 -140 -150 -160 -170 -180 -190
Filter 75MHz
Phase Noise Jitter 12KHz 20MHz 0.60ps (typical)
NOISE POWER
Phase Noise Data
Phase Noise Result adding Filter data
100k 100M
TYPICAL PHASE NOISE 150MHZ
Filter 150MHz
Phase Noise Jitter 12KHz 20MHz 0.67ps (typical)
OFFSET FREQUENCY (HZ)
NOISE POWER
Phase Noise Data
-100 -110 -120 -130 -140 -150 -160 -170 -180 -190
Phase Noise Result adding Filter data
100k
100M
OFFSET FREQUENCY (HZ)
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FEMTOCLOCKSCRYSTAL-TO- LVPECL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
SCOPE
SCOPE
LVPECL
LVPECL
-1.3V 0.165V
-0.5V 0.125V
LVPECL 3.3V OUTPUT LOAD TEST CIRCUIT
LVPECL 2.5V OUTPUT LOAD TEST CIRCUIT
Clock Outputs
PERIOD
Pulse Width
PERIOD
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
Phase Noise Plot
Noise Power
Phase Noise Mask
Offset Frequency
Jitter Area Under Masked Phase Noise Plot
PHASE JITTER
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FEMTOCLOCKSCRYSTAL-TO- LVPECL CLOCK GENERATOR APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
high speed analog circuitry, power supply pins vulnerable random noise. ICS843071I provides separate power supplies isolate high switching noise from outputs internal PLL. VCCA should individually connected power supply plane through vias, bypass capacitors should used each pin. achieve optimum jitter performance, power supply isolation required. Figure illustrates resistor along with .01F bypass capacitor should connected each VCCA pin.
3.3V 2.5V .01F .01F
FIGURE POWER SUPPLY FILTERING
TERMINATION
2.5V LVPECL OUTPUT
ground level. Figure eliminated termination shown Figure
Figure Figure show examples termination 2.5V LVPECL driver. These terminations equivalent terminating 2.5V, very close
2.5V 2.5V VCC=2.5V 2,5V LVPECL Driv 62.5 62.5
2.5V VCC=2.5V 2,5V LVPECL Driv
FIGURE 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V VCC=2.5V 2,5V LVPECL Driv
FIGURE 2.5V LVPECL TERMINATION EXAMPLE
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FEMTOCLOCKSCRYSTAL-TO- LVPECL CLOCK GENERATOR
drive transmission lines. Matched impedance techniques should used maximize operating frequency minimize signal distortion. Figures show different layouts which recommended only guidelines. Other suitable clock layouts exist would recommended that board designers simulate guarantee compatibility across printed circuit clock component process variations.
TERMINATION 3.3V LVPECL OUTPUT
clock layout topology shown below typical termination LVPECL outputs. different layouts mentioned recommended only guidelines. FOUT nFOUT impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors current path ground) current sources must used functionality. These outputs designed
3.3V
FOUT
FOUT
(VOH
FIGURE LVPECL OUTPUT TERMINATION
FIGURE LVPECL OUTPUT TERMINATION
CRYSTAL INPUT INTERFACE
ICS843071I been characterized with 18pF parallel resonant crystals. capacitor values, shown Figure below were determined using 25MHz, 18pF parallel resonant crystal were chosen minimize error. optimum values slightly adjusted different board layouts.
XTAL_IN 18pF Parallel stal XTAL_OUT ICS84332 ICS843071I
Figure CRYSTAL INPUt INTERFACE
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ICS843071I
FEMTOCLOCKSCRYSTAL-TO- LVPECL CLOCK GENERATOR POWER CONSIDERATIONS
This section provides information power dissipation junction temperature ICS843071I. Equations example calculations also provided.
Power Dissipation. total power dissipation ICS843071I core power plus power dissipated load(s). following power dissipation 3.3V 3.465V, which gives worst case results. NOTE: Please refer Section details calculating power dissipated load.
Power (core)MAX VCC_MAX IEE_TYP 3.465V 58mA 200.97mW Power (outputs)MAX 30mW/Loaded Output pair
Total Power_MAX (3.465V, with outputs switching) 200.97mW 30mW 230.97mW
Junction Temperature. Junction temperature, temperature junction bond wire bond directly affects reliability device. maximum recommended junction temperature HiPerClockSdevices 125°C.
equation follows: Pd_total Junction Temperature Junction-to-Ambient Thermal Resistance Pd_total Total Device Power Dissipation (example calculation section above) Ambient Temperature order calculate junction temperature, appropriate junction-to-ambient thermal resistance must used. Assuming moderate flow meter second multi-layer board, appropriate value 90.5°C/W Table below. Therefore, ambient temperature 85°C with outputs switching 85°C 0.231W 90.5°C/W 106°C. This well below limit 125°C. This calculation only example. will obviously vary depending number loaded outputs, supply voltage, flow, type board (single layer multi-layer).
TABLE THERMAL RESISTANCE
8-PIN TSSOP, FORCED CONVECTION
Velocity (Meters Second)
Multi-Layer PCB, JEDEC Standard Test Boards 101.7°C/W
90.5°C/W
89.8°C/W
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FEMTOCLOCKSCRYSTAL-TO- LVPECL CLOCK GENERATOR
Calculations Equations. purpose this section derive power dissipated into load. LVPECL output driver circuit termination shown Figure
VOUT
FIGURE LVPECL DRIVER CIRCUIT
TERMINATION
calculate worst case power dissipation into load, following equations which assume load, termination voltage
logic high, VOUT
CCO_MAX
OH_MAX
CC_MAX
0.9V
OH_MAX
0.9V 1.7V
logic low, VOUT
CCO_MAX
OL_MAX
CC_MAX
OL_MAX
1.7V
Pd_H power dissipation when output drives high. Pd_L power dissipation when output drives low. Pd_H
OH_MAX
CC_MAX
2V))/R
CC_MAX
OH_MAX
[(2V
CC_MAX
OH_MAX
))/R
CC_MAX
OH_MAX
[(2V 0.9V)/50] 0.9V 19.8mW
Pd_L
OL_MAX
CC_MAX
2V))/R
CC_MAX
OL_MAX
[(2V
CC_MAX
OL_MAX
))/R
CC_MAX
OL_MAX
[(2V 1.7V)/50] 1.7V 10.2mW Total Power Dissipation output pair Pd_H Pd_L 30mW
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ICS843071I
FEMTOCLOCKSCRYSTAL-TO- LVPECL CLOCK GENERATOR RELIABILITY INFORMATION
TABLE
JAVS. FLOW TABLE LEAD TSSOP
Velocity (Linear Feet Minute)
90.5°C/W
89.8°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
101.7°C/W
TRANSISTOR COUNT
transistor count ICS843071I 1732
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FEMTOCLOCKSCRYSTAL-TO- LVPECL CLOCK GENERATOR
LEAD TSSOP
PACKAGE OUTLINE SUFFIX
TABLE PACKAGE DIMENSIONS
SYMBOL 0.45 -4.30 0.65 BASIC 0.75 0.10 -0.05 0.80 0.19 0.09 2.90 6.40 BASIC 4.50 Millimeters Minimum 1.20 0.15 1.05 0.30 0.20 3.10 Maximum
Reference Document: JEDEC Publication MO-153
843071AGI
REV. MARCH 2005
ICS843071I
FEMTOCLOCKSCRYSTAL-TO- LVPECL CLOCK GENERATOR
Marking 3071A 3071A Package Lead TSSOP Lead TSSOP Shipping Packaging tube 2500 tape reel Temperature -40°C 85°C -40°C 85°C
TABLE ORDERING INFORMATION
Part/Order Number ICS843071AGI ICS843071AGIT
aforementioned trademarks, HiPerClockSand FemtoClocksare trademark Integrated Circuit Systems, Inc. subsidiaries United States and/or other countries. While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial industrial applications. other applications such those requiring high reliability other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 843071AGI
REV. MARCH 2005
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