FEMTOCLOCKSCRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER FEAT

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FEMTOCLOCKSCRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER FEAT

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ICS843002I-01
FEMTOCLOCKSCRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
FEATURES
3.3V 2.5V LVPECL outputs Selectable crystal oscillator interface LVCMOS/LVTTL single-ended input Supports following input frequencies: 156.25MHz, 125MHz 62.5MHz range: 560MHz 680MHz phase jitter 156.25MHz, using 25MHz crystal (1.875MHz-20MHz): 0.55ps (typical) design target Output skew: 10ps (typical) Supply Voltage Modes Core/Outputs 3.3/3.3 2.5/2.5 -40°C 85°C ambient operating temperature
GENERAL DESCRIPTION
ICS843002I-01 output LVPECL synthesizer optimized generate Ethernet HiPerClockSreference clock frequencies member performance clock solutions from ICS. Using 25MHz 18pF parallel resonant crystal, following frequencies generated based frequency select pins (F_SEL[1:0]): 156.25MHz, 125MHz, 62.5MHz. ICS843002I-01 uses ICS' generation phase noise technology achieve lower typical phase jitter, easily meeting Ethernet jitter requirements. ICS843002I-01 packaged small 20-pin TSSOP package.
FREQUENCY SELECT FUNCTION TABLE
Inputs Divider F_SEL1 F_SEL0 Value Used Divider Value Output Frequency (25MHz Ref.) 156.25 62.5 Used
ASSIGNMENT
VCCO nPLL_SEL VCCA F_SEL0 VCCO nXTAL_SEL TEST_CLK XTAL_IN XTAL_OUT F_SEL1
BLOCK DIAGRAM
F_SEL[1:0] Pulldown nPLL_SEL Pulldown F_SEL[1:0] used
ICS843002I-01
20-Lead TSSOP 6.5mm 4.4mm 0.92mm package body Package View
TEST_CLK Pulldown
25MHz
XTAL_IN XTAL_OUT
Phase Detector
625MHz
(w/25MHz Reference)
nXTAL_SEL Pulldown
(fixed)
Pulldown
Preliminary Information presented herein represents product prototyping pre-production. noted characteristics based initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves right change circuitry specifications without notice. 843002AGI-01 REV. JUNE 2005
ICS843002I-01
FEMTOCLOCKSCRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
Type Description connect. Output supply pins. Differential output pair. LVPECL interface levels. Active HIGH Master Reset. When logic HIGH, internal dividers reset causing true outputs inver outputs Pulldown high. When logic LOW, internal dividers outputs enabled. LVCMOS/LVTTL interface levels. Selects between TEST_CLK input dividers. When Pulldown LOW, selects (PLL Enable). When HIGH, deselects reference clock (PLL Bypass). LVCMOS/LVTTL interface levels. Analog supply pin. Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. Core supply pin. Parallel resonant ystal interface. XTAL_OUT output, XTAL_IN input. Pulldown LVCMOS/LVTTL clock input. Selects between ystal TEST_CLK inputs Reference Pulldown source. Selects XTAL inputs when LOW. Selects TEST_CLK when HIGH. LVCMOS/LVTTL interface levels. Negative supply pins. Differential output pair. LVPECL interface levels. Output supply pins.
TABLE DESCRIPTIONS
Number Name VCCO Unused Power Ouput Input
nPLL_SEL VCCA F_SEL0, F_SEL1 XTAL_OUT, XTAL_IN TEST_CLK nXTAL_SEL nQ1, VCCO
Input Power Input Power Input Input Input Power Output Power
NOTE: Pulldown refer internal input resistors. Table Characteristics, typical values.
TABLE CHARACTERISTICS
Symbol RPULLDOWN Parameter Input Capacitance Input Pulldown Resistor Test Conditions Minimum Typical Maximum Units
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FEMTOCLOCKSCRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
4.6V -0.5V 0.5V 50mA 100mA 73.2°C/W lfpm) -65°C 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only. Functional operation product these conditions conditions beyond those listed Characteristics Characteristics implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, Inputs, Outputs, Continuous Current Surge Current Package Thermal Impedance, Storage Temperature, TSTG
TABLE POWER SUPPLY CHARACTERISTICS, VCCA VCCO 3.3V±10%, -40°C 85°C
Symbol VCCA VCCO ICCA ICCO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Core Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 2.97 2.97 2.97 Typical Maximum 3.63 3.63 3.63 Units
TABLE POWER SUPPLY CHARACTERISTICS, VCCA VCCO 2.5V±5%, -40°C 85°C
Symbol VCCA VCCO ICCA ICCO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Core Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 2.375 2.375 2.375 Typical Maximum 3.625 3.625 3.625 Units
TABLE LVCMOS LVTTL CHARACTERISTICS, VCCA VCCO 3.3V±10% 2.5V±5%, -40°C 85°C
Symbol Parameter Input High Voltage Input Voltage Input High Current Input Current TEST_CLK, nPLL_SEL, nXTAL_SEL TEST_CLK, nPLL_SEL, nXTAL_SEL 3.63V 3.63V, Test Conditions Minimum Typical -0.3 Maximum Units
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FEMTOCLOCKSCRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
Test Conditions Minimum VCCO VCCO Typical Maximum VCCO VCCO Units
TABLE LVPECL CHARACTERISTICS, VCCA VCCO 3.3V±10% 2.5V±10%, -40°C 85°C
Symbol VSWING Parameter Output High Voltage; NOTE Output Voltage; NOTE Peak-to-Peak Output Voltage Swing
NOTE Outputs terminated with VCCO
TABLE CRYSTAL CHARACTERISTICS
Parameter Mode Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level NOTE: Characterized using 18pF parallel resonant crystal. 22.4 Test Conditions Minimum Typical Maximum 27.2 Units Fundamental
TABLE CHARACTERISTICS, VCCA VCCO 3.3V±10%, -40°C 85°C
Symbol fOUT Parameter Output Frequency Output Skew; NOTE 156.25MHz, (1.875MHz 20MHz) Phase Jitter; NOTE Output Rise/Fall Time 125MHz, (1.875MHz 20MHz) 62.5MHz, (1.875MHz 20MHz) Test Conditions F_SEL[1,:0] F_SEL[1,:0] F_SEL[1,:0] Minimum 0.55 Typical Maximum Units
tsk(o)
Output Duty Cycle NOTE Defined skew between outputs same supply voltages with equal load conditions. Measured VCCO/2. NOTE This parameter defined accordance with JEDEC Standard NOTE Phase jitter dependent input source used.
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FEMTOCLOCKSCRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
Test Conditions F_SEL[1,:0] F_SEL[1,:0] F_SEL[1,:0] Minimum 156.25MHz, (1.875MHz 20MHz) 0.55 0.74 125MHz, (1.875MHz 20MHz) 62.5MHz, (1.875MHz 20MHz) Typical Maximum Units
TABLE CHARACTERISTICS, VCCA VCCO 2.5V±5%, -40°C 85°C
Symbol fOUT Parameter Output Frequency Output Skew; NOTE Phase Jitter; NOTE Output Rise/Fall Time
tsk(o)
Output Duty Cycle NOTE Defined skew between outputs same supply voltages with equal load conditions. Measured VCCO/2. NOTE This parameter defined accordance with JEDEC Standard NOTE Phase jitter dependent input source used.
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FEMTOCLOCKSTMCRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE 156.25MHZ
Gigabit Ethernet Filter 156.25MHz
Phase Noise Jitter 1.875MHz 20MHz 0.55ps (typical)
-100
NOISE POWER
Phase Noise Data
-110 -120 -130 -140 -150
-160 -170 -180 -190
Phase Noise Result adding Gigabit Ethernet Filter data
100k 100M
OFFSET FREQUENCY (HZ)
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FEMTOCLOCKSTMCRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
VCCA, VCCO
SCOPE
VCCA, VCCO
SCOPE
LVPECL
LVPECL
-1.3V 0.33V
-0.5V 0.125V
3.3V CORE/3.3V OUTPUT LOAD TEST CIRCUIT
2.5V CORE/2.5V OUTPUT LOAD TEST CIRCUIT
tsk(o)
nQ0, Q0,Q1
PERIOD
PERIOD
100%
OUTPUT SKEW
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
Phase Noise Plot
Noise Power
Phase Noise Mask
Clock Outputs
Offset Frequency
Jitter Area Under Masked Phase Noise Plot
PHASE JITTER
843002AGI-01
OUTPUT RISE/FALL TIME
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ICS843002I-01
FEMTOCLOCKSCRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
high speed analog circuitry, power supply pins vulnerable random noise. ICS843002I-01 provides separate power supplies isolate high switching noise from outputs internal PLL. VCC, VCCA, VCCO should individually connected power supply plane through vias, bypass capacitors should used each pin. achieve optimum jitter performance, power supply isolation required. Figure illustrates resistor along with 10µF .01µF bypass capacitor should connected each VCCA.
3.3V 2.5V .01µF VCCA .01µF 10µF
FIGURE POWER SUPPLY FILTERING
TERMINATION 3.3V LVPECL OUTPUT
clock layout topology shown below typical termination LVPECL outputs. different layouts mentioned recommended only guidelines. FOUT nFOUT impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors current path ground) current sources must used functionality. These outputs designed drive transmission lines. Matched impedance techniques should used maximize operating frequency minimize signal distortion. Figures show different layouts which recommended only guidelines. Other suitable clock layouts exist would recommended that board designers simulate guarantee compatibility across printed circuit clock component process variations.
3.3V
FOUT
FOUT
((VOH VOL) (VCC
FIGURE LVPECL OUTPUT TERMINATION
FIGURE LVPECL OUTPUT TERMINATION
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FEMTOCLOCKSCRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
ground level. Figure eliminated termination shown Figure
TERMINATION
2.5V LVPECL OUTPUT
Figure Figure show examples termination 2.5V LVPECL driver. These terminations equivalent terminating VCCO 2.5V, VCCO very close
2.5V 2.5V VCCO=2.5V 2,5V LVPECL Driv 62.5 62.5
2.5V VCCO=2.5V 2,5V LVPECL Driv
FIGURE 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V VCCO=2.5V 2,5V LVPECL Driv
FIGURE 2.5V LVPECL TERMINATION EXAMPLE
CRYSTAL INPUT INTERFACE
ICS843002I-01 been characterized with 18pF parallel resonant crystals. capacitor values shown Figure below were determined using 25MHz 18pF parallel resonant crystal were chosen minimize error.
XTAL_OUT 18pF Parallel Crystal XTAL_IN
ICS843002I-01
Figure CRYSTAL INPUt INTERFACE
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FEMTOCLOCKSCRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
parallel resonant 26.5625MHz crystal used. C1=27pF C2=33pF recommended frequency accuracy. different board layout, slightly adjusted optimizing frequency accuracy.
LAYOUT GUIDELINE
Figure shows schematic example ICS843002I-01. example LVEPCL termination shown this schematic. Additional LVPECL termination approaches shown LVPECL Termination Application Note. this example,
VCCA VCCO 0.1u
10uF
0.01u
Logic Control Input Examples
0.1u ICS843002-01
F_SEL0 VCCA nPLL_SEL VCCO
Logic Input
Logic Input
Install
VCC=3.3V
F_SEL1 XTAL_OUT XTAL_IN TEST_CLK nXTAL_SEL VCCO
VCCO=3.3V
VCCO 0.1u
Logic Input pins
Install
Logic Input pins
33pF
18pF 27pF
0.1u
ICS843002I-01
FIGURE ICS843002I-01 SCHEMATIC EXAMPLE
BOARD LAYOUT EXAMPLE
Figure shows example ICS843002I-01 P.C. board layout. crystal footprint shown this example allows installation either surface mount HC49S through-hole HC49 package. footprints other components this example
listed Table There should least decoupling capacitor power pin. decoupling capacitors should located close possible power pins. layout assumes that board clean analog power ground plane.
TABLE FOOTPRINT TABLE
Reference Size 0402 0805 0603
0603 NOTE: Table lists component sizes shown this layout example.
FIGURE ICS843002I-01 BOARD LAYOUT EXAMPLE
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FEMTOCLOCKSCRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS
This section provides information power dissipation junction temperature ICS843002I-01. Equations example calculations also provided.
Power Dissipation. total power dissipation ICS843002I-01 core power plus power dissipated load(s). following power dissipation 3.3V 3.63V, which gives worst case results. NOTE: Please refer Section details calculating power dissipated load.
Power (core)MAX VCC_MAX IEE_MAX 3.63V 115mA 417.45mW Power (outputs)MAX 30mW/Loaded Output pair outputs loaded, total power 30mW 60mW
Total Power_MAX (3.63V, with outputs switching) 417.5mW 60mW 477.5mW
Junction Temperature. Junction temperature, temperature junction bond wire bond directly affects reliability device. maximum recommended junction temperature HiPerClockSdevices 125°C.
equation follows: Pd_total Junction Temperature Junction-to-Ambient Thermal Resistance Pd_total Total Device Power Dissipation (example calculation section above) Ambient Temperature order calculate junction temperature, appropriate junction-to-ambient thermal resistance must used. Assuming moderate flow linear feet minute multi-layer board, appropriate value 66.6°C/W Table below. Therefore, ambient temperature 85°C with outputs switching 85°C 0.478W 66.6°C/W 116.8°C. This below limit 125°C. This calculation only example. will obviously vary depending number loaded outputs, supply voltage, flow, type board (single layer multi-layer).
TABLE THERMAL RESISTANCE
20-PIN TSSOP, FORCED CONVECTION
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 73.2°C/W
98.0°C/W 66.6°C/W
88.0°C/W 63.5°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
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Calculations Equations.
purpose this section derive power dissipated into load. LVPECL output driver circuit termination shown Figure
ICS843002I-01
FEMTOCLOCKSCRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
VCCO
VOUT VCCO
FIGURE LVPECL DRIVER CIRCUIT
TERMINATION
calculate worst case power dissipation into load, following equations which assume load, termination voltage
logic high, VOUT
OH_MAX
CCO_MAX
0.9V
(VCCO_MAX VOH_MAX) 0.9V logic low, VOUT
CCO_MAX
OL_MAX
CCO_MAX
1.7V
OL_MAX
1.7V
Pd_H power dissipation when output drives high. Pd_L power dissipation when output drives low. Pd_H 2V))/R
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
[(2V
CCO_MAX
OH_MAX
))/R
CCO_MAX
OH_MAX
[(2V 0.9V)/50] 0.9V 19.8mW ))/R
Pd_L
OL_MAX
CCO_MAX
2V))/R
CCO_MAX
OL_MAX
[(2V
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
[(2V 1.7V)/50] 1.7V 10.2mW Total Power Dissipation output pair Pd_H Pd_L 30mW
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FEMTOCLOCKSCRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION
TABLE
JAVS. FLOW TABLE LEAD TSSOP
Velocity (Linear Feet Minute)
98.0°C/W 66.6°C/W
88.0°C/W 63.5°C/W
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W 73.2°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
TRANSISTOR COUNT
transistor count ICS843002I-01 2955
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FEMTOCLOCKSCRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
LEAD TSSOP
PACKAGE OUTLINE SUFFIX
TABLE PACKAGE DIMENSIONS
SYMBOL 0.45 -4.30 0.65 BASIC 0.75 0.10 -0.05 0.80 0.19 0.09 6.40 6.40 BASIC 4.50 1.20 0.15 1.05 0.30 0.20 6.60 Millimeters
Reference Document: JEDEC Publication MO-153
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FEMTOCLOCKSTMCRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
Marking ICS43002AI01 ICS43002AI01 Package Lead TSSOP Lead TSSOP Count tube 2500 tape reel Temperature -40°C 85°C -40°C 85°C
TABLE ORDERING INFORMATION
Part/Order Number ICS843002AGI-01 ICS843002AGI-01T
aforementioned trademarks, HiPerClockSand FemtoClocksare trademark Integrated Circuit Systems, Inc. subsidiaries United States and/or other countries. While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial industrial applications. other applications such those requiring high reliability other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 843002AGI-01
REV. JUNE 2005

FEMTOCLOCKSCRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER FEAT

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