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FEMTOCLOCKSCRYSTAL-TO3.3V LVPECL CLOCK GENERATOR FEATURES di
Top Searches for this datasheetICS843011-01 FEMTOCLOCKSCRYSTAL-TO3.3V LVPECL CLOCK GENERATOR FEATURES differential 3.3V LVPECL output Crystal oscillator interface designed 26.5625MHz, 18pF parallel resonant crystal Output frequency: 106.25MHz 100MHz range: 560MHz 680MHz phase jitter 106.25MHz, using 26.5625MHz crystal (637kHz 10MHz): 0.56ps (typical) phase noise 106.25MHz Phase noise: Offset Noise Power 100Hz dBc/Hz 1KHz -122.3 dBc/Hz 10KHz -135.4 dBc/Hz 100KHz -135.2 dBc/Hz 3.3V operating supply 70°C ambient operating temperature GENERAL DESCRIPTION ICS843011-01 Fibre Channel Clock Generator member HiPerClocksHiPerClockSfamily high performance devices from ICS. ICS843011-01 uses 26.5625MHz crystal synthesize 106.25MHz 25MHz crystal synthesize 100MHz. ICS843011-01 excellent <1ps phase jitter performance, over 637kHz 10MHz integration range. ICS843011-01 packaged small 8-pin TSSOP, making ideal systems with limited board space. FREQUENCY TABLE Crystal (MHz) 26.5625 Output Frequency (MHz) 106.25 BLOCK DIAGRAM XTAL_IN ASSIGNMENT 637.5MHz 26.5625MHz Ref. XTAL_OUT Phase Detector VCCA XTAL_OUT XTAL_IN (fixed) ICS843011-01 8-Lead TSSOP 4.40mm 3.0mm 0.925mm package body Package View Preliminary Information presented herein represents product prototyping pre-production. noted characteristics based initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves right change circuitry specifications without notice. 843011AG-01 REV. APRIL 2005 ICS843011-01 FEMTOCLOCKSCRYSTAL-TO3.3V LVPECL CLOCK GENERATOR Type Power Input Power Description Analog supply pin. ystal oscillator interface. XTAL_IN input, XTAL_OUT output. Negative supply pin. connect. Core supply pin. Differential clock outputs. LVPECL interface levels. TABLE DESCRIPTIONS Number Name VCCA XTAL_OUT, XTAL_IN nQ0, Unused Power Output TABLE CHARACTERISTICS Symbol Parameter Input Capacitance Test Conditions Minimum Typical Maximum Units 843011AG-01 REV. APRIL 2005 ICS843011-01 FEMTOCLOCKSCRYSTAL-TO3.3V LVPECL CLOCK GENERATOR 4.6V -0.5V 0.5V 50mA 100mA 101.7°C/W mps) -65°C 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only. Functional operation product these conditions conditions beyond those listed Characteristics Characteristics implied. Exposure absolute maximum rating conditions extended periods affect product reliability. ABSOLUTE MAXIMUM RATINGS Supply Voltage, Inputs, Outputs, Continuous Current Surge Current Package Thermal Impedance, Storage Temperature, TSTG TABLE POWER SUPPLY CHARACTERISTICS, VCCA 3.3V±5%, 70°C Symbol VCCA Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Test Conditions Minimum 3.135 3.135 Typical Maximum 3.465 3.465 Units TABLE LVPECL CHARACTERISTICS, VCCA 3.3V±5%, 70°C Symbol VSWING Parameter Output High Voltage; NOTE Output Voltage; NOTE Peak-to-Peak Output Voltage Swing Test Conditions Minimum Typical Maximum Units NOTE Outputs terminated with TABLE CRYSTAL CHARACTERISTICS Parameter Mode Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level 23.33 Test Conditions Minimum Typical Fundamental 28.33 Maximum Units TABLE CHARACTERISTICS, VCCA 3.3V±5%, 70°C Symbol Parameter FOUT Output Frequency Phase Jitter (Random); NOTE Output Rise/Fall Time Output Duty Cycle Test Conditions 106.25MHz; Integration Range: 637kHz 10MHz 100MHz; Integration Range: 637kHz 10MHz Minimum 93.33 Typical Maximum 113.33 Units 0.56 0.54 843011AG-01 NOTE Please refer Phase Noise Plot. REV. APRIL 2005 ICS843011-01 FEMTOCLOCKSCRYSTAL-TO3.3V LVPECL CLOCK GENERATOR TYPICAL PHASE NOISE 100MHZ -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 Fibre Channel Filter 100MHz Phase Noise Jitter 637kHz 10MHz 0.54ps (typical) NOISE POWER Phase Noise Data Phase Noise Result adding Fibre Channel Filter data 100k 100M TYPICAL PHASE NOISE 106.25MHZ -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 OFFSET FREQUENCY (HZ) Fibre Channel Filter 106.25MHz Phase Noise Jitter 637kHz 10MHz 0.56ps (typical) NOISE POWER Phase Noise Data Phase Noise Result adding Fibre Channel Filter data 100k 100M OFFSET FREQUENCY (HZ) 843011AG-01 REV. APRIL 2005 ICS843011-01 FEMTOCLOCKSCRYSTAL-TO3.3V LVPECL CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION Phase Noise Plot Noise Power VCC, VCCA SCOPE LVPECL Phase Noise Mask Offset Frequency -1.3V 0.165V Jitter Area Under Masked Phase Noise Plot 3.3V OUTPUT LOAD TEST CIRCUIT PHASE JITTER Pulse Width PERIOD Clock Outputs PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD OUTPUT RISE/FALL TIME 843011AG-01 REV. APRIL 2005 ICS843011-01 FEMTOCLOCKSCRYSTAL-TO3.3V LVPECL CLOCK GENERATOR APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES high speed analog circuitry, power supply pins vulnerable random noise. ICS843011-01 provides separate power supplies isolate high switching noise from outputs internal PLL. VCCA should individually connected power supply plane through vias, bypass capacitors should used each pin. achieve optimum jitter performance, power supply isolation required. Figure illustrates resistor along with .01F bypass capacitor should connected each VCCA pin. 3.3V .01F .01F FIGURE POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE ICS843011-01 been characterized with 18pF parallel resonant crystals. capacitor values, shown Figure below were determined using 25MHz, 18pF parallel resonant crystal were chosen minimize error. optimum values slightly adjusted different board layouts. XTAL_OUT 18pF Parallel Crystal XTAL_IN Figure CRYSTAL INPUt INTERFACE 843011AG-01 REV. APRIL 2005 ICS843011-01 FEMTOCLOCKSCRYSTAL-TO3.3V LVPECL CLOCK GENERATOR drive transmission lines. Matched impedance techniques should used maximize operating frequency minimize signal distortion. Figures show different layouts which recommended only guidelines. Other suitable clock layouts exist would recommended that board designers simulate guarantee compatibility across printed circuit clock component process variations. TERMINATION 3.3V LVPECL OUTPUT clock layout topology shown below typical termination LVPECL outputs. different layouts mentioned recommended only guidelines. FOUT nFOUT impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors current path ground) current sources must used functionality. These outputs designed 3.3V FOUT FOUT ((VOH VOL) (VCC FIGURE LVPECL OUTPUT TERMINATION FIGURE LVPECL OUTPUT TERMINATION 843011AG-01 REV. APRIL 2005 ICS843011-01 FEMTOCLOCKSCRYSTAL-TO3.3V LVPECL CLOCK GENERATOR POWER CONSIDERATIONS This section provides information power dissipation junction temperature ICS843011-01. Equations example calculations also provided. Power Dissipation. total power dissipation ICS843011-01 core power plus power dissipated load(s). following power dissipation 3.3V 3.465V, which gives worst case results. NOTE: Please refer Section details calculating power dissipated load. Power (core)MAX VCC_MAX IEE_MAX 3.465V 55mA 190.57mW Power (outputs)MAX 30mW/Loaded Output pair Total Power_MAX (3.465V, with outputs switching) 190.6mW 30mW 220.6mW Junction Temperature. Junction temperature, temperature junction bond wire bond directly affects reliability device. maximum recommended junction temperature HiPerClockSdevices 125°C. equation follows: Pd_total Junction Temperature Junction-to-Ambient Thermal Resistance Pd_total Total Device Power Dissipation (example calculation section above) Ambient Temperature order calculate junction temperature, appropriate junction-to-ambient thermal resistance must used. Assuming moderate flow meter second multi-layer board, appropriate value 90.5°C/W Table below. Therefore, ambient temperature 70°C with outputs switching 70°C 0.221W 90.5°C/W 90°C. This well below limit 125°C. This calculation only example. will obviously vary depending number loaded outputs, supply voltage, flow, type board (single layer multi-layer). TABLE THERMAL RESISTANCE 8-PIN TSSOP, FORCED CONVECTION Velocity (Meters Second) Multi-Layer PCB, JEDEC Standard Test Boards 101.7°C/W 90.5°C/W 89.8°C/W 843011AG-01 REV. APRIL 2005 Calculations Equations. purpose this section derive power dissipated into load. LVPECL output driver circuit termination shown Figure ICS843011-01 FEMTOCLOCKSCRYSTAL-TO3.3V LVPECL CLOCK GENERATOR VOUT FIGURE LVPECL DRIVER CIRCUIT TERMINATION calculate worst case power dissipation into load, following equations which assume load, termination voltage logic high, VOUT CCO_MAX OH_MAX CC_MAX 0.9V OH_MAX 0.9V 1.7V logic low, VOUT CCO_MAX OL_MAX CC_MAX OL_MAX 1.7V Pd_H power dissipation when output drives high. Pd_L power dissipation when output drives low. Pd_H OH_MAX CC_MAX 2V))/R CC_MAX OH_MAX [(2V CC_MAX OH_MAX ))/R CC_MAX OH_MAX [(2V 0.9V)/50] 0.9V 19.8mW Pd_L OL_MAX CC_MAX 2V))/R CC_MAX OL_MAX [(2V CC_MAX OL_MAX ))/R CC_MAX OL_MAX [(2V 1.7V)/50] 1.7V 10.2mW Total Power Dissipation output pair Pd_H Pd_L 30mW 843011AG-01 REV. APRIL 2005 ICS843011-01 FEMTOCLOCKSCRYSTAL-TO3.3V LVPECL CLOCK GENERATOR RELIABILITY INFORMATION TABLE JAVS. FLOW TABLE LEAD TSSOP Velocity (Meters Second) Multi-Layer PCB, JEDEC Standard Test Boards 101.7°C/W 90.5°C/W 89.8°C/W TRANSISTOR COUNT transistor count ICS843011-01 1662 843011AG-01 REV. APRIL 2005 ICS843011-01 FEMTOCLOCKSCRYSTAL-TO3.3V LVPECL CLOCK GENERATOR PACKAGE OUTLINE SUFFIX LEAD TSSOP TABLE PACKAGE DIMENSIONS SYMBOL 0.45 -4.30 0.65 BASIC 0.75 0.10 -0.05 0.80 0.19 0.09 2.90 6.40 BASIC 4.50 Millimeters Minimum 1.20 0.15 1.05 0.30 0.20 3.10 Maximum Reference Document: JEDEC Publication MO-153 843011AG-01 REV. APRIL 2005 ICS843011-01 FEMTOCLOCKSCRYSTAL-TO3.3V LVPECL CLOCK GENERATOR Marking 11A01 11A01 Package Lead TSSOP Lead TSSOP Shipping Packaging tube 2500 tape reel Temperature 70°C 70°C TABLE ORDERING INFORMATION Part/Order Number ICS843011AM-01 ICS843011AM-01T aforementioned trademarks, HiPerClockSand FemtoClocksare trademark Integrated Circuit Systems, Inc. subsidiaries United States and/or other countries. While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial applications. other applications such those requiring extended temperature range, high reliability, other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 843011AG-01 REV. APRIL 2005 Other recent searchesTMS320C6000 - TMS320C6000 TMS320C6000 Datasheet PCI9050 - PCI9050 PCI9050 Datasheet PCI9052 - PCI9052 PCI9052 Datasheet PCI9050-to-HPI - PCI9050-to-HPI PCI9050-to-HPI Datasheet TMS320C64x - TMS320C64x TMS320C64x Datasheet REJ03C0368-0001 - REJ03C0368-0001 REJ03C0368-0001 Datasheet GL819 - GL819 GL819 Datasheet AN9663 - AN9663 AN9663 Datasheet 2SC5356 - 2SC5356 2SC5356 Datasheet
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