FEMTOCLOCKSMULTI-RATE LVPECL FREQUENCY SYNTHESIZER FEATURES

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FEMTOCLOCKSMULTI-RATE LVPECL FREQUENCY SYNTHESIZER FEATURES

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ICS843034-01
FEMTOCLOCKSMULTI-RATE LVPECL FREQUENCY SYNTHESIZER
FEATURES
Dual differential 3.3V LVPECL outputs which independently either 3.3V 2.5V Input Mux: differential input single-ended input crystal oscillator interfaces CLK, nCLK pair accept following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL TEST_CLK accepts LVCMOS LVTTL input levels Output frequency range: 30.625MHz 640MHz Crystal input frequency range: 12MHz 40MHz range: 490MHz 640MHz Parallel serial interface programming feedback divider output dividers phase jitter 106.25MHz, using 25.5MHz crystal (637kHz 5MHz): 0.61ps (typical) Supply voltage modes: LVPECL outputs (core/outputs): 3.3V/3.3V 3.3V/2.5V REF_CLK output (core/outputs): 3.3V/3.3V 3.3V/2.5V 70°C ambient operating temperature
GENERAL DESCRIPTION
ICS843034-01 general purpose, phase noise LVPECL synthesizer which HiPerClockSgenerate frequencies wide variety applications. ICS843034-01 input Multiplexer from which following inputs selected: differential input, single-ended input, crystal oscillators, thus making device ideal frequency translation generation. Each differential LVPECL output pair output divider which independently that different frequencies generated. Additionally, each LVPECL output pair dedicated power supply outputs 3.3V 2.5V. ICS843034-01 also supplies buffered copy reference clock crystal frequency single-ended REF_CLK which enabled disabled (disabled default). output frequency programmed using either serial parallel programming interface. ICS843034-01 excellent <1ps phase jitter performance over 637kHz 5MHz integration range, thus making suitable Fibre Channel, SONET, Ethernet/1Gb Ethernet applications. Example applications include systems which must support both rates. Fibre Channel, example, 25.5MHz crystal generate 159.375MHz reference clock, then switch 20.544MHz crystal generate 164.355MHz 66/64 FEC. Other applications could include suppor ting both Ether frequencies SONET frequencies application. When Ethernet frequencies needed, 25MHz crystal used when SONET frequencies needed, input switched select 38.88MHz Crystal.
ASSIGNMENT
OE_REF OE_A OE_B
48-Pin LQFP 1.4mm package body Package View
Preliminary Information presented herein represents product prototyping pre-production. noted characteristics based initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves right change circuitry specifications without notice.
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nCLK nP_LOAD VCO_SEL
ICS843034-01
XTAL_OUT1 XTAL_IN1 XTAL_OUT0 XTAL_IN0 TEST_CLK SEL1 SEL0 VCCA S_LOAD S_DATA S_CLOCK
P_DIV VCCO_REF REF_CLK VCCO_B nFOUTB0 FOUTB0 VCCO_A nFOUTA0 FOUTA0 TEST
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FEMTOCLOCKSMULTI-RATE LVPECL FREQUENCY SYNTHESIZER
BLOCK DIAGRAM
OE_A VCO_SEL XTAL_IN0 XTAL_OUT0
XTAL_IN1
XTAL_OUT1 nCLK TEST_CLK SEL1 SEL0 P_DIV OE_B
PHASE DETECTOR
FOUTA0 nFOUTA0 VCCO_A
VCCO_B FOUTB0 nFOUTB0
VCCO_REF REF_CLK
OE_REF S_LOAD S_DATA S_CLOCK nP_LOAD M8:M0 NA2:NA0 NB2:NB0
TEST
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FEMTOCLOCKSMULTI-RATE LVPECL FREQUENCY SYNTHESIZER
bits hardwired divider output divider specific default state that will automatically occur during power-up. TEST output when operating parallel input mode. relationship between frequency, crystal frequency divider defined follows: fVCO fxtal value required values through shown Table program Frequency Function Table. Valid values which will achieve lock 25MHz reference defined frequency defined follows: FOUT fVCO fxtal Serial operation occurs when nP_LOAD HIGH S_LOAD LOW. shift register loaded sampling S_DATA bits with rising edge S_CLOCK. contents shift register loaded into divider output divider when S_LOAD transitions from LOW-to-HIGH. divide output divide values latched HIGHto-LOW transition S_LOAD. S_LOAD held HIGH, data S_DATA input passed directly divider output divider each rising edge S_CLOCK. serial mode used program bits test bits internal registers determine state TEST output follows: TEST Output S_Data, Shift Register Output Output divider CMOS Fout
FUNCTIONAL DESCRIPTION
NOTE: functional description that follows describes operation using 25MHz crystal. Valid loop divider values different crystal input frequencies defined Input Frequency Characteristics, Table NOTE
ICS843034-01 features fully integrated therefore requires external components setting loop bandwidth. fundamental crystal used input onchip oscillator. output oscillator into phase detector. 25MHz crystal provides 25MHz phase detector reference frequency. operates over range 490MHz 640MHz. output divider also applied phase detector. phase detector divider force output frequency times reference frequency adjusting control voltage. Note that some values (either high low), will achieve lock. output scaled divider prior being sent each LVPECL output buffers. divider provides output duty cycle. ICS843034-01 supports either serial parallel programming modes program feedback divider output divider. input divider only changed using P_DIV pin. cannot changed from default setting using serial interface. Figure shows timing diagram each mode. parallel mode, nP_LOAD input initially LOW. data inputs passed directly divider both output dividers. LOW-to-HIGH transition nP_LOAD input, data latched dividers remain loaded until next transition nP_LOAD until serial event occurs. result,
SERIAL LOADING
S_CLOCK
S_DATA
S_LOAD
nP_LOAD
PARALLEL LOADING
M0:M8, P_DIV, NA0:NA2, NB0:NB2 nP_LOAD
S_LOAD
Time
FIGURE PARALLEL SERIAL LOAD OPERATIONS
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FEMTOCLOCKSMULTI-RATE LVPECL FREQUENCY SYNTHESIZER
Type Input Input Input Input Input Input Power Input Input Power Output Output Power Output Power Output Power Input Pullup/ Pulldown Pullup Description divider input. Data latched LOW-to-HIGH trnsition nP_LOAD Pulldown input. LVCMOS/LVTTL interfac levels. Pullup Determines output divider value defined Table Pulldown Function Table. LVCMOS/LVTTL interface levels. Output enable. Controls enabling disabling REF_CLK output. LVCMOS/LVTTL interface levels. Output enable. Controls enabling disabling FOUTA0, nFOUTA0 outputs. LVCMOS/LVTTL interface levels. Output enable. Controls enabling disabling FOUTB0, nFOUTB0 outputs. LVCMOS/LVTTL interface levels. Core supply pins.
TABLE DESCRIPTIONS
Number Name NB0, OE_REF OE_A OE_B NA0, TEST FOUTA0, nFOUTA0 VCCO_A FOUTB0, nFOUTB0 VCCO_B REF_CLK VCCO_REF P_DIV
Pulldown Pullup Pullup
Determines output divider value defined Table Pulldown Function Table. LVCMOS/LVTTL interface levels. Negative supply pins. Test output which ACTIVE serial mode operation. Output driven parallel mode. LVCMOS/LVTTL interface levels. Differential output synthesizer. LVPECL interface levels. Output supply FOUTA0, nFOUTA0. Differential output synthesizer. LVPECL interface levels. Output supply FOUTB0, nFOUTB0. Reference clock output. LVCMOS/LVTTL interface levels. Output supply REF_CLK. Input divide select. Float (default), LVCMOS/LVTTL interface levels. Active High Master Reset. When logic HIGH, forces internal dividers reset causing true outputs FOUTx inver outputs nFOUTx high. When logic LOW, internal dividers outputs enabled. Asser tion does affect loaded values. LVCMOS/LVTTL interface levels. Clocks serial data present S_DATA input into shift register rising edge S_CLOCK. LVCMOS/LVTTL interface levels. Shift register serial input. Data sampled rising edge S_CLOCK. LVCMOS/LVTTL interface levels. Controls transition data from shift register into dividers. LVCMOS/LVTTL interface levels. Analog supply pin.
Input
Pulldown
S_CLOCK S_DATA S_LOAD VCCA SEL0, SEL1 TEST_CLK XTAL_IN0, XTAL_OUT0 XTAL_IN1, XTAL_OUT1 nCLK
Input Input Input Power Input Input Input Input Input Input
Pulldown Pulldown Pulldown
Pulldown Clock select inputs. LVCMOS/LVTTL interface levels. Pulldown Test clock input. LVCMOS/LVTTL interface levels. ystal oscillator interface. ystal oscillator interface. Pulldown Non-inver ting differential clock input. Pullup/ Inver ting differential clock input.VCC/2 default when left floating. Pulldown
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ICS843034-01
FEMTOCLOCKSMULTI-RATE LVPECL FREQUENCY SYNTHESIZER
Type Input Description Parallel load input. Determines when data present M5:M0 loaded into divider, when data present NA2:NA0 Pulldown NB2:NB0 loaded into output dividers. LVCMOS/LVTTL interface levels. Determines whether synthesizer bypass mode. Pullup LVCMOS/LVTTL interface levels.
Number
Name nP_LOAD
VCO_SEL
Input Input Input
Pulldown divider inputs. Data latched LOW-to-HIGH transition nP_LOAD input. LVCMOS/LVTTL interface levels. Pullup
NOTE: Pullup Pulldown refer internal input resistors. Table Characteristics, typical values.
TABLE CHARACTERISTICS
Symbol RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Output Impedance Test Conditions Minimum Typical Maximum Units
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TABLE PARALLEL
SERIAL MODE FUNCTION TABLE
Inputs Conditions S_CLOCK S_DATA Data Data Data Data Reset. Forces outputs LOW. Data inputs passed directly divider output divider. TEST output forced LOW. Data latched into input registers remains loaded until next transition until serial event occurs. Serial input mode. Shift register loaded with data S_DATA each rising edge S_CLOCK. Contents shift register passed divider output divider. divider output divider values latched. Parallel serial input affect shift registers. S_DATA passed directly divider clocked.
nP_LOAD
Data Data
Data Data
S_LOAD
NOTE: HIGH Don't care Rising edge transition Falling edge transition
TABLE PROGRAMMABLE FREQUENCY FUNCTION TABLE (P_DIV FLOAT)
Frequency (MHz) Divide
NOTE These divide values resulting frequencies correspond crystal TEST_CLK input frequency 25MHz.
TABLE PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs *NX2
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*NX1
*NX0
Divider Value
Output Frequency (MHz) Minimum 163.33 122.5 81.67 61.25 30.625 Maximum 213.33 106.67
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*NOTE: denotes Bank Bank
ICS843034-01
FEMTOCLOCKSMULTI-RATE LVPECL FREQUENCY SYNTHESIZER
4.6V -0.5V 0.5V -0.5V VCCO 0.5V 50mA 100mA 47.9°C/W lfpm) -65°C 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only. Functional operation product these conditions conditions beyond those listed Characteristics Characteristics implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, Inputs, Outputs, (LVCMOS) Outputs, (LVPECL) Continuous Current Surge Current Package Thermal Impedance, Storage Temperature, TSTG
TABLE POWER SUPPLY CHARACTERISTICS, VCCA 3.3V±5%, VCCO_A VCCO_B 3.3V±5% 2.5V±5%, 70°C
Symbol VCCA VCCO_A, VCCO_B ICCA VCCO_REF Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current 3.135 REF_CLK Output Supply 2.375 Test Conditions Minimum 2.375 2.375 3.135 2.375 Typical 3.465 2.625 Maximum 3.465 3.465 3.465 2.625 Units
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Test Conditions Minimum Typical Maximum Units
TABLE LVCMOS/LVTTL CHARACTERISTICS, VCCA 3.3V±5%, VCCO_A VCCO_B 3.3V±5% 2.5V±5%,
70°C)
Symbol
Parameter VCO_SEL, SEL0, SEL1, OE_REF, OE_A, OE_B, S_LOAD, nP_LOAD, S_DATA, S_CLOCK, TEST_CLK, M0:M5, NX0:NX2 P_DIV VCO_SEL, SEL0, SEL1, OE_REF, OE_A, OE_B, S_LOAD, nP_LOAD, S_DATA, S_CLOCK, TEST_CLK, M0:M5, NX0:NX2 P_DIV TEST_CLK, P_DIV, SEL[1:0], S_CLOCK, S_DATA, S_LOAD, nP_LOAD, OE_REF NA2, NB2, M1:M4, M6:M8 NB0, NB1, NA0, NA1, OE_A, OE_B, VCO_SEL TEST_CLK, P_DIV, SEL[1:0], S_CLOCK, S_DATA, S_LOAD, nP_LOAD, OE_REF NA2, NB2, M1:M4, M6:M8 NB0, NB1, NA0, NA1, OE_A, OE_B, VCO_SEL
Input High Voltage
Input Voltage
-0.3
3.465V, 2.625V 3.465V, 2.625V 3.465V, 2.625V, 3.465V, 2.625V, VCCO 3.3V -150
Input High Current
Input Current
Output High Voltage
TEST; NOTE
VCCO 2.5V VCCO 1.8V 0.15V VCCO 3.3V
Output Voltage
TEST; NOTE
VCCO 2.5V VCCO 1.8V 0.15V
NOTE Output terminated with VCCO_REF/2.
TABLE DIFFERENTIAL CHARACTERISTICS, VCCA 3.3V±5%, VCCO_A VCCO_B 3.3V±5% 2.5V±5%, 70°C
Symbol Parameter Input High Current Input Current nCLK nCLK Test Conditions 3.465V 3.465V 3.465V 3.465V -150 0.15 0.85 Minimum Typical Maximum Units
Peak-to-Peak Input Voltage
VCMR Common Mode Input Voltage; NOTE NOTE single ended applications, maximum input voltage CLK, nCLK 0.3V. NOTE Common mode voltage defined VIH.
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Test Conditions Minimum VCCO VCCO Typical Maximum VCCO VCCO Units
TABLE LVPECL CHARACTERISTICS, VCCO_A VCCO_B 2.375V 3.465V, 70°C
Symbol VSWING Parameter Output High Voltage; NOTE Output Voltage; NOTE Peak-to-Peak Output Voltage Swing
NOTE Outputs terminated with VCCO_x
TABLE INPUT FREQUENCY CHARACTERISTICS, VCCA 3.3V±5%,
Symbol Parameter XTAL_IN0, XTAL_OUT0 Input Frequency XTAL_IN1, XTAL_OUT1 S_CLOCK Test Conditions
70°C
Minimum Typical Maximum Units
Rise Time S_CLOCK, S_DATA, S_LOAD NOTE: input ystal, CLK/nCLK TEST_CLK frequency range, value must operate within 490MHz 640MHz range. Using minimum input frequency 12MHz, valid values with input divider (P_DIV 00). Using maximum frequency 40MHz, valid values
TABLE CRYSTAL CHARACTERISTICS
Parameter Mode Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level Test Conditions Minimum Typical Maximum Units Fundamental
TABLE CHARACTERISTICS, VCCA VCCO_A VCCO_B 3.3V±5%, 70°C
Symbol Parameter FOUT Output Frequency Phase Jitter, (Random); NOTE Output Skew; NOTE Output Rise/Fall Time nP_LOAD Setup Time S_DATA S_CLOCK S_CLOCK S_LOAD nP_LOAD Hold Time S_DATA S_CLOCK S_CLOCK S_LOAD Output Duty Cycle Test Conditions Integration Range: 637kHz 5MHz Measured same Output Frequency Minimum 30.625 0.61 Typical Maximum Units
tsk(o)
Lock Time tLOCK Parameter Measurement Information section. NOTE Please refer Phase Noise Plot. NOTE Defined skew between outputs same supply voltage with equal load conditions. Measured output differential cross points. NOTE This parameter defined accordance with JEDEC Standard
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Test Conditions Integration Range: 637kHz 5MHz Minimum 30.625 0.71 Typical Maximum Units
TABLE CHARACTERISTICS, VCCA 3.3V±5%, VCCO_A VCCO_B 2.5V±5%, 70°C
Symbol Parameter FOUT Output Frequency Phase Jitter, (Random); NOTE Output Skew; NOTE Output Rise/Fall Time nP_LOAD Setup Time S_DATA S_CLOCK S_CLOCK S_LOAD nP_LOAD Hold Time S_DATA S_CLOCK S_CLOCK S_LOAD Output Duty Cycle
tsk(o)
Lock Time tLOCK Parameter Measurement Information section. NOTE Please refer Phase Noise Plot. NOTE Defined skew between outputs same supply voltage with equal load conditions. Measured output differential cross points. NOTE This parameter defined accordance with JEDEC Standard
TABLE CHARACTERISTICS, VCCA 3.3V±5%, VCCO_A 3.3V±5%, VCCO_B 2.5V±5%,TA 70°C
VCCA 3.3V±5%, VCCO_A 2.5V±5%, VCCO_B 3.3V±5%,TA 70°C
Symbol Parameter FOUT Output Frequency Phase Jitter, (Random); NOTE Output Skew; NOTE Output Rise/Fall Time nP_LOAD Setup Time S_DATA S_CLOCK S_CLOCK S_LOAD nP_LOAD Hold Time S_DATA S_CLOCK S_CLOCK S_LOAD Output Duty Cycle Test Conditions Integration Range: 637kHz 5MHz Minimum 0.71 Typical Maximum Units
tsk(o)
Lock Time tLOCK Parameter Measurement Information section. NOTE Please refer Phase Noise Plot. NOTE Defined skew between outputs same supply voltage with equal load conditions. Measured output differential cross points. NOTE This parameter defined accordance with JEDEC Standard
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TYPICAL PHASE NOISE 106.25MHZ
Filter 106.25MHz
Phase Jitter (Random) 637kHz 5MHz 0.61ps (typical)
NOISE POWER
-100 -110 -120 -130 -140 -150 -160 -170 -180 -190
Phase Noise Data
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Phase Noise Result adding Filter data
100k 100M
OFFSET FREQUENCY (HZ)
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PARAMETER MEASUREMENT INFORMATION
2.8V±0.04V
VCCA, VCCO_A, VCCO_B
SCOPE
VCCA VCCO_A, VCCO_B
SCOPE
LVPECL
LVPECL
-1.3V 0.165V
-0.5V 0.125V
3.3V CORE/3.3V OUTPUT LOAD TEST CIRCUIT FOUTA0/nFOUTA0, FOUTB0/nFOUTB0
3.3V CORE/2.5V OUTPUT LOAD TEST CIRCUIT FOUTA0/nFOUTA0, FOUTB0/nFOUTB0
1.65V±5%
2.05V±0.04V 1.25V±5%
VCCA, VCCO_REF
SCOPE
VCCA
SCOPE
VCCO_REF
LVCMOS
LVCMOS
-1.65V
-1.25V
3.3VCORE/3.3V REF_CLK OUTPUT LOAD TEST CIRCUIT
3.3V CORE/2.5V REF_CLK OUTPUT LOAD TEST CIRCUIT
VREF
nFOUTx FOUTx nFOUTy FOUTy
tsk(o)
contains 68.26% measurements contains 95.4% measurements contains 99.73% measurements contains 99.99366% measurements contains (100-1.973x10-7)% measurements
Reference Point
(Trigger Edge)
Histogram
Mean Period
(First edge after trigger)
PERIOD JITTER
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OUTPUT SKEW
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nFOUTA0 FOUTA0
PERIOD
Clock Outputs
100%
PERIOD
OUTPUT DUTY CYCLE/OUTPUT PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
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FEMTOCLOCKSMULTI-RATE LVPECL FREQUENCY SYNTHESIZER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
high speed analog circuitry, power supply pins vulnerable random noise. ICS843034-01 provides separate power supplies isolate high switching noise from outputs internal PLL. VCC, VCCA, VCCO_x should individually connected power supply plane through vias, bypass capacitors should used each pin. achieve optimum jitter performance, power supply isolation required. Figure illustrates resistor along with .01F bypass capacitor should connected each VCCA pin.
3.3V .01F VCCA .01F
FIGURE POWER SUPPLY FILTERING
WIRING DIFFERENTIAL INPUT ACCEPT SINGLE ENDED LVCMOS/LVTTL LEVELS
Figure shows differential input wired accept single ended levels. reference voltage V_REF VCC/2 generated bias resistors This bias circuit should located close possible input pin. ratio
might need adjusted position V_REF center input voltage swing. example, input clock swing only 2.5V 3.3V, V_REF should 1.25V R2/R1 0.609.
Single Ended Clock Input V_REF nCLK 0.1u
FIGURE SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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here examples only. Please consult with vendor driver component confirm driver termination requirements. example Figure input termination applies HiPerClockS LVHSTL drivers. using LVHSTL driver from another vendor, their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
/nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL other differential signals. Both VSWING must meet VCMR input requirements. Figures show interface examples HiPerClockS CLK/nCLK input driven most common driver types. input interfaces suggested
3.3V 3.3V 3.3V 1.8V nCLK LVHSTL HiPerClockS LVHSTL Driver LVPECL HiPerClockS Input nCLK HiPerClockS Input
FIGURE HIPERCLOCKS CLK/nCLK INPUT DRIVEN HIPERCLOCKS LVHSTL DRIVER
FIGURE HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER
3.3V 3.3V 3.3V nCLK LVPECL HiPerClockS Input
3.3V 3.3V LVDS_Driv
nCLK
Receiv
FIGURE HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER
FIGURE HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVDS DRIVER
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ground level. Figure eliminated termination shown Figure
TERMINATION
2.5V LVPECL OUTPUT
Figure Figure show examples termination 2.5V LVPECL driver. These terminations equivalent terminating 2.5V, very close
2.5V 2.5V VCCO=2.5V 2,5V LVPECL Driv 62.5 62.5
2.5V VCCO=2.5V 2,5V LVPECL Driv
FIGURE 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V VCCO=2.5V 2,5V LVPECL Driv
FIGURE 2.5V LVPECL TERMINATION EXAMPLE
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drive transmission lines. Matched impedance techniques should used maximize operating frequency minimize signal distortion. Figures show different layouts which recommended only guidelines. Other suitable clock layouts exist would recommended that board designers simulate guarantee compatibility across printed circuit clock component process variations.
TERMINATION
3.3V LVPECL OUTPUT
clock layout topology shown below typical termination LVPECL outputs. different layouts mentioned recommended only guidelines. FOUTx nFOUTx impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors current path ground) current sources must used functionality. These outputs designed
3.3V
FOUT
FOUT
((VOH VOL) (VCC
FIGURE LVPECL OUTPUT TERMINATION
FIGURE LVPECL OUTPUT TERMINATION
CRYSTAL INPUT INTERFACE
ICS843034-01 been characterized with 18pF parallel resonant crystals. capacitor values, shown Figure below were determined using 25MHz, 18pF parallel resonant crystal were chosen minimize error. optimum values slightly adjusted different board layouts.
XTAL_OUT 18pF Parallel Crystal XTAL_IN
ICS843034-01
ICS84332
Figure CRYSTAL INPUt INTERFACE
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This section provides information power dissipation junction temperature ICS843034-01. Equations example calculations also provided.
Power Dissipation. total power dissipation ICS843034-01 core power plus power dissipated load(s). following power dissipation 3.3V 3.465V, which gives worst case results. NOTE: Please refer Section details calculating power dissipated load.
Power (core)MAX VCC_MAX IEE_MAX 3.465V 185mA 641mW Power (outputs)MAX 30mW/Loaded Output pair outputs loaded, total power 30mW 60mW
Total Power_MAX (3.465V, with outputs switching) 641mW 60mW 701mW
Junction Temperature. Junction temperature, temperature junction bond wire bond directly affects reliability device. maximum recommended junction temperature HiPerClockSdevices 125°C.
equation follows: Pd_total Junction Temperature Junction-to-Ambient Thermal Resistance Pd_total Total Device Power Dissipation (example calculation section above) Ambient Temperature order calculate junction temperature, appropriate junction-to-ambient thermal resistance must used. Assuming moderate flow linear feet minute multi-layer board, appropriate value 42.1°C/W Table below. Therefore, ambient temperature 70°C with outputs switching 70°C 0.701W 42.1°C/W 99.5°C. This well below limit 125°C. This calculation only example. will obviously vary depending number loaded outputs, supply voltage, flow, type board (single layer multi-layer).
TABLE THERMAL RESISTANCE
48-PIN LQFP, FORCED CONVECTION
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W
55.9°C/W 42.1°C/W
50.1°C/W 39.4°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
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Calculations Equations.
purpose this section derive power dissipated into load. LVPECL output driver circuit termination shown Figure
ICS843034-01
FEMTOCLOCKSMULTI-RATE LVPECL FREQUENCY SYNTHESIZER
VCCO
VOUT VCCO
FIGURE LVPECL DRIVER CIRCUIT
TERMINATION
calculate worst case power dissipation into load, following equations which assume load, termination voltage
logic high, VOUT VOH_MAX VCCO_MAX 0.9V
CCO_MAX
OH_MAX
0.9V 1.7V
logic low, VOUT
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
1.7V
Pd_H power dissipation when output drives high. Pd_L power dissipation when output drives low. Pd_H 2V))/R
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
[(2V
CCO_MAX
OH_MAX
))/R
CCO_MAX
OH_MAX
[(2V 0.9V)/50] 0.9V 19.8mW ))/R
Pd_L
OL_MAX
CCO_MAX
2V))/R
CCO_MAX
OL_MAX
[(2V
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
[(2V 1.7V)/50] 1.7V 10.2mW Total Power Dissipation output pair Pd_H Pd_L 30mW
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TABLE JAVS. FLOW TABLE
LEAD LQFP
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W
55.9°C/W 42.1°C/W
50.1°C/W 39.4°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
TRANSISTOR COUNT
transistor count ICS843034-01 5084
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LEAD LQFP
PACKAGE OUTLINE SUFFIX
TABLE PACKAGE DIMENSIONS
JEDEC VARIATION DIMENSIONS MILLIMETERS SYMBOL 0.45 -0.05 1.35 0.17 0.09 MINIMUM NOMINAL -1.40 0.22 -9.00 BASIC 7.00 BASIC 5.50 Ref. 9.00 BASIC 7.00 BASIC 5.50 Ref. 0.50 BASIC 0.60 -0.75 0.08 1.60 0.15 1.45 0.27 0.20 MAXIMUM
Reference Document: JEDEC Publication MS-026
843034AY-01
REV. JUNE 2005
ICS843034-01
FEMTOCLOCKSMULTI-RATE LVPECL FREQUENCY SYNTHESIZER
Marking ICS843034A01 ICS843034A01 Package Lead LQFP Lead LQFP Shipping Packaging tray 1000 tape reel Temperature 70°C 70°C
TABLE ORDERING INFORMATION
Part/Order Number ICS843034AY-01 ICS843034AY-01T
aforementioned trademark, HiPerClockSand FEMTOCLOCKSis trademark Integrated Circuit Systems, Inc. subsidiaries United States and/or other countries. While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial applications. other applications such those requiring extended temperature range, high reliability, other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 843034AY-01
REV. JUNE 2005

FEMTOCLOCKSMULTI-RATE LVPECL FREQUENCY SYNTHESIZER FEATURES

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