350MHZ, JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER

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350MHZ, JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER

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ICS8431I-21
350MHZ, JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER
FEATURES
Fully integrated Differential 3.3V LVPECL output Crystal oscillator interface Output frequency range: 62.5MHz 350MHz Crystal input frequency range: 14MHz 25MHz range: 250MHz 700MHz Programmable loop divider generating variety output frequencies Spread Spectrum Clocking (SSC) fixed 1/2% modulation environments requiring ultra bypass modes supporting in-circuit testing on-chip functional block characterization Cycle-to-cycle jitter: 19ps (typical) 3.3V supply voltage -40°C 85°C ambient operating temperature Replaces ICS8431I-01
GENERAL DESCRIPTION
ICS8431I-21 general purpose clock frequency synthesizer IA64/32 application HiPerClockSmember HiPerClockSfamily High Performance Clock Solutions from ICS. operates frequency range 250MHz 700MHz providing output frequency range 62.5MHz 350MHz. output frequency programmed using parallel interface, through configuration logic, output divider control pin, DIV_SEL. Spread spectrum clocking programmed control inputs SSC_CTL0 SSC_CTL1.
Programmable features ICS8431I-21 support four operational modes. four modes spread spectrum clocking (SSC), non-spread spectrum clock test modes which controlled SSC_CTL[1:0] pins. Unlike other synthesizers, ICS8431I-21 immediately change spread-spectrum operation without having reset device. mode, output clock modulated order achieve reduction EMI. bypass test modes, disconnected source differential output allowing external source connected TEST_I/O pin. This useful in-circuit testing allows differential output driven lower frequency throughout system clock tree. other bypass mode, oscillator divider used source both Fout divide This useful characterizing oscillator internal dividers.
BLOCK DIAGRAM
XTAL_IN XTAL_OUT
ASSIGNMENT
SSC_CTL0 SSC_CTL1 TEST_I/O nP_LOAD XTAL_IN XTAL_OUT VCCA DIV_SEL VCCO FOUT nFOUT
PHASE DETECTOR FOUT nFOUT
ICS8431I-21
TEST_I/O Configuration Logic Control Logic
M0:M8
28-Lead SOIC 7.5mm 18.05mm 2.25mm package body Package View
nP_LOAD
SSC_CTL0
SSC_CTL1
DIV_SEL
Preliminary Information presented herein represents product prototyping pre-production. noted characteristics based initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves right change circuitry specifications without notice.
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ICS8431I-21
350MHZ, JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER
loop divider divider programmed using inputs through While nP_LOAD input held LOW, data present M0:M8 transparent divider. LOW-to-HIGH transition nP_LOAD, M0:M8 data latched into divider further changes M0:M8 inputs will seen divider until next transition nP_LOAD. relationship between frequency, crystal frequency divider defined follows: fxtal fVCO value required values M0:M8 programming shown Table Programmable Frequency Function Table. frequency defined follows: FOUT fVCO fxtal ICS8431I-21, output divider either DIV_SEL pin. input MHz, valid values which will achieve lock defined 511.
FUNCTIONAL DESCRIPTION
ICS8431I-21 features fully integrated therefore requires external components setting loop bandwidth. output oscillator divided prior phase detector. With 16MHz crystal this provides 1MHz reference frequency. operates over range 250MHz 700MHz. output divider also applied phase detector. phase detector divider force output frequency times reference frequency adjusting control voltage. Note that some values (either high low), will achieve lock. output scaled divider prior being sent LVPECL output buffer. divider provides output duty cycle. programmable features ICS8431I-21 support four output operational modes programmable divider output divider. four output operational modes spread spectrum clocking (SSC), non-spread spectrum clock test modes controlled SSC_CTL[1:0] pins.
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ICS8431I-21
350MHZ, JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER
Type Input Input Input Power Input Output Power Output Power Input Description
TABLE DESCRIPTIONS
Number Name M0-M6 M7-M8 CTL0, CTL1 TEST nFOUT, FOUT VCCO DIV_SEL
Pulldown divider inputs. Data latched LOW-to-HIGH transition nP_LOAD input. LVCMOS LVTTL pins interface levels. Pullup Pullup control pins. LVTTL LVCMOS interface levels. Negative supply pins. Connect pins board ground. Programmed defined Table Function Table. Core supply pin. Differential outputs synthesizer. 3.3V LVPECL interface levels. Output supply pin. Determines output divide value FOUT. Pulldown LVCMOS LVTTL interface levels. Active High Master Reset. When logic HIGH, internal dividers reset causing true output FOUT inver output Pulldown nFOUT high. When logic LOW, internal dividers outputs enabled. Asser tion does effect loaded values. LVCMOS LVTTL interface levels. Analog supply pin.
Input
VCCA XTAL_OUT, XTAL_IN
Power Unused
connect. Crystal oscillator interface. XTAL_IN input. Input XTAL_OUT output. Parallel load input. Determines when data present M8:M0 nP_LOAD Input Pulldown loaded into divider. LVTTL LVCMOS interface levels. NOTE: Pullup Pulldown refer internal input resistors. Table Characteristics, typical values.
TABLE CHARACTERISTICS
Symbol RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical Maximum Units
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ICS8431I-21
350MHZ, JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER
Outputs FOUT, nFOUT DIV_SEL0 DIV_SEL1 fXTAL fXTAL Test fXTAL fXTAL Test fXTAL TEST_I/O Operational Modes
TABLE CONTROL INPUT FUNCTION TABLE
Inputs SSC_CTL1 SSC_CTL0 TEST_I/O Source Internal External
Disabled Enabled Disabled Disabled
fXTAL bypass; oscillator, dividers test mode. NOTE Default SSC; Hi-Z Modulation Factor Percent Bypass Mode, NOTE Input (1MHz Test 200MHz) Hi-Z Modulation
fXTAL NOTE Used house debug characterization.
TABLE PROGRAMMABLE FREQUENCY FUNCTION TABLE (NOTE
Frequency (MHz) Count
NOTE Assumes 16MHz ystal.
TABLE FUNCTION TABLE
Inputs DIV_SEL Divider Value Output Frequency (MHz) Minimum 62.5 Maximum
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ICS8431I-21
350MHZ, JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER
4.6V -0.5V 0.5V 50mA 100mA 46.2°C/W lfpm) -65°C 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only. Functional operation product these conditions conditions beyond those listed Characteristics Characteristics implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, Inputs, Outputs, Continuous Current Surge Current Package Thermal Impedance, Storage Temperature, TSTG
TABLE POWER SUPPLY CHARACTERISTICS, VCCA VCCO 3.3V±5%, -40°C 85°C
Symbol VCCO VCCA ICCA Parameter Core Supply Voltage Output Supply Voltage Analog Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical Maximum 3.465 3.465 3.465 Units
TABLE LVCMOS LVTTL CHARACTERISTICS, VCCA VCCO 3.3V±5%, -40°C 85°C
Symbol Input Parameter M0:M8, SSC_CTL0, SSC_CTL1, High Voltage DIV_SEL, TEST_I/O, nP_LOAD M0:M8, SSC_CTL0, SSC_CTL1, Voltage DIV_SEL, TEST_I/O, nP_LOAD SSC_CTL0, SSC_CTL1, TEST_IO High Current M0:M6, DIV_SEL nP_LOAD, SSC_CTL0, SSC_CTL1, TEST_IO Current M0:M6, DIV_SEL nP_LOAD, Test Conditions Minimum Typical Maximum Units
Input
-0.3
3.465V 3.465V 3.465V, 3.465V, -150
Input
Input
TABLE LVPECL CHARACTERISTICS, VCCA VCCO 3.3V±5%, -40°C 85°C
Symbol VSWING Parameter Output High Voltage; NOTE Output Voltage; NOTE Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCCO VCCO Typical Maximum VCCO VCCO Units
NOTE Output terminated with VCCO Parameter Measurement Section, 3.3V Output Load Test Circuit.
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ICS8431I-21
350MHZ, JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER
Test Conditions Minimum Typical Maximum Units
TABLE CRYSTAL CHARACTERISTICS
Parameter Mode Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Fundamental
TABLE CHARACTERISTICS, VCCA VCCO 3.3V±5%, -40°C 85°C
Symbol FOUT Parameter Output Frequency Cycle-to-Cycle Jitter; NOTE Output Duty Cycle Output Rise/Fall Time Crystal Input Range; NOTE Modulation Frequency; NOTE Modulation Factor; NOTE Spectral Reduction; NOTE FOUT 200MHz FOUT 200MHz FOUT 200MHz FOUT 100MHz Test Conditions Minimum 62.5 33.33 Typical Maximum Units
it(cc)
Fxtal SSCred
Power-up Stable Clock Output tSTABLE Figures Parameter Measurement Information section. NOTE Jitter performance using XTAL inputs. NOTE Only valid within operating range. NOTE XTAL input, refer Application Note. NOTE Spread Spectrum clocking enabled. NOTE This parameter defined accordance with JEDEC Standard
8431AMI-21
REV. APRIL 2005
ICS8431I-21
350MHZ, JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
VCCA, VCCO
SCOPE
nFOUT FOUT
LVPECL
tcycle
jit(cc) tcycle -tcycle
1000 Cycles
-1.3V 0.165V
3.3V OUTPUT LOAD TEST CIRCUIT
CYCLE-TO-CYCLE JITTER
nFOUT Clock Outputs FOUT
Pulse Width
PERIOD
PERIOD
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
8431AMI-21
tcycle
REV. APRIL 2005
ICS8431I-21
350MHZ, JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
high speed analog circuitry, power supply pins vulnerable random noise. ICS8431I-21 provides separate power supplies isolate high switching noise from outputs internal PLL. VCC, VCCA, VCCO should individually connected power supply plane through vias, bypass capacitors should used each pin. achieve optimum jitter performance, better power supply isolation required. Figure illustrates along with .01F bypass capacitor should connected each VCCA pin.
3.3V .01F .01F
FIGURE POWER SUPPLY FILTERING
TERMINATION
LVPECL OUTPUTS
drive transmission lines. Matched impedance techniques should used maximize operating frequency minimize signal distortion. Figures show different layouts which recommended only guidelines. Other suitable clock layouts exist would recommended that board designers simulate guarantee compatibility across printed circuit clock component process variations.
clock layout topology shown below typical IA64/32 platforms. different layouts mentioned recommended only guidelines. FOUT nFOUT impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors current path ground) current sources must used functionality. These outputs designed
3.3V
FOUT
FOUT
((VOH VOL) (VCC
FIGURE LVPECL OUTPUT TERMINATION
FIGURE LVPECL OUTPUT TERMINATION
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Integrated Circuit Systems, Inc. CRYSTAL INPUT INTERFACE
ICS8431I-21 been characterized with 18pF parallel resonant crystals. capacitor values, shown Figure below were determined using 25MHz, 18pF parallel resonant crystal
ICS8431I-21
350MHZ, JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER
were chosen minimize error. optimum values slightly adjusted different board layouts.
XTAL_OUT 18pF Parallel Crystal XTAL_IN
Figure CRYSTAL INPUT INTERFACE
SPREAD SPECTRUM
Spread-spectrum clocking frequency modulation technique reduction. When spread-spectrum enabled, 30kHz triangle waveform used with 0.5% down-spread (+0.0% -0.5%) from nominal 200MHz clock frequency. example triangle frequency modulation profile shown Figure below. ramp profile expressed Fnom Nominal Clock Frequency Spread mode (200MHz with 16MHz Nominal Modulation Frequency (30kHz) Modulation Factor (0.5% down spread) fnom fnom when fnom fnom when ICS8431I-21 triangle modulation frequency deviation will exceed 0.6% down-spread from nominal clock frequency (+0.0% -0.5%). example amount down spread relative nominal clock frequency seen frequency domain, shown Figure ratio this width fundamental frequency typically 0.4%, will exceed 0.6%. resulting spectral reduction will greater than 7dB, shown Figure important note ICS8431I-21 minimum spectral reduction component-specific reduction, will necessarily same system reduction.
Fnom
Fnom
0.5/fm 1/fm
FIGURE TRIANGLE FREQUENCY MODULATION
8431AMI-21
FIGURE 200MHZ CLOCK OUTPUT
FREQUENCY DOMAIN
REV. APRIL 2005
SPREAD -SPECTRUM SPREAD PECTRUM
ICS8431I-21
350MHZ, JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER
Figure This layout example used general guideline. layout actual system will depend selected component types density P.C. board.
LAYOUT GUIDELINE
schematic ICS8431I-21 layout example used this layout guideline shown Figure ICS8431I-21 recommended board layout this example shown
Logic Input Examples
VCC=3.3V SP=Spare, installed
0.01uF SSC_CTL0 SSC_CTL1 TEST_IO nP_LOAD XTAL_IN XTAL_OUT VCCA DIV_SEL VCCO FOUT nFOUT 22pF 22pF VCCA 0.01uF 10uF
Logic Input
Logic Input
Logic Input pins
Logic Input pins
0.1uF
ICS8431I-21 ICS8431-21
0.1uF
FIGURE SCHEMATIC EXAMPLE
8431AMI-21
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following component footprints used this layout example: resistors capacitors size 0603.
ICS8431I-21
350MHZ, JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER
Avoid sharp angles clock trace. Sharp angle turns cause characteristic impedance change transmission lines. Keep clock traces same layer. Whenever possible, avoid placing vias clock traces. Placement vias traces affect trace characteristic impedance hence degrade signal integrity. prevent cross talk, avoid routing other signal traces parallel with clock traces. running parallel traces unavoidable, allow separation least three trace widths between differential clock trace other signal trace. Make sure other signal traces routed between clock trace pair. matching termination resistors should located close receiver input pins possible. matching termination resistors should located close receiver input pins possible. Other termination scheme also used shown example.
POWER
GROUNDING
Place decoupling capacitors close possible power pins. space allows, placment decoupling capacitor component side preferred. This reduce unwanted inductance between decoupling capacitor power generated via. Maximize power ground sizes number vias capacitors. This reduce inductance between power ground planes component power ground pins. filter consisting should placed close VCCA possible.
CLOCK TRACES
TERMINATION
Poor signal integrity degrade system performance cause system failure. synchronous high-speed digital systems, clock signal less tolerant poor signal integrity than other signals. ringing rising falling edge excessive ring back cause system failure. shape trace trace delay might restricted available space board component location. While routing traces, clock signal traces should routed first should locked prior routing other signal traces. output trace pair should have same length.
CRYSTAL
crystal should located close possible pins (XTAL_OUT) (XTAL_IN). trace length between should kept minimum avoid unwanted parasitic inductance capacitance. Other signal traces should routed near crystal traces.
ICS8431-21
Signals
Zo=50
Zo=50
FIGURE BOARD LAYOUT ICS8431I-21
8431AMI-21
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ICS8431I-21
350MHZ, JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS
This section provides information power dissipation junction temperature ICS8431I-21. Equations example calculations also provided.
Power Dissipation. total power dissipation ICS8431I-21 core power plus power dissipated load(s). following power dissipation 3.3V 3.465V, which gives worst case results. NOTE: Please refer Section details calculating power dissipated load.
Power (core)MAX VCC_MAX IEE_MAX 3.465V 155mA 537.1mW Power (outputs)MAX 30mW/Loaded Output pair outputs loaded, total power 30mW 30mW
Total Power_MAX (3.465V, with outputs switching) 537.1mW 30mW 567.1mW
Junction Temperature. Junction temperature, temperature junction bond wire bond directly affects reliability device. maximum recommended junction temperature HiPerClockSdevices 125°C.
equation follows: Pd_total Junction Temperature Junction-to-Ambient Thermal Resistance Pd_total Total Device Power Dissipation (example calculation section above) Ambient Temperature order calculate junction temperature, appropriate junction-to-ambient thermal resistance must used. Assuming moderate flow linear feet minute multi-layer board, appropriate value 39.7°C/W Table below. Therefore, ambient temperature 85°C with outputs switching 85°C 0.567W 39.7°C/W 107.5°C. This below limit 125°C. This calculation only example. will obviously vary depending number loaded outputs, supply voltage, flow, type board (single layer multi-layer).
Table THERMAL RESISTANCE
28-PIN SOIC, FORCED CONVECTION
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 76.2°C/W 46.2°C/W
60.8°C/W 39.7°C/W
53.2°C/W 36.8°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
8431AMI-21
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Calculations Equations.
purpose this section derive power dissipated into load. LVPECL output driver circuit termination shown Figure
ICS8431I-21
350MHZ, JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER
VCCO
VOUT VCCO
FIGURE LVPECL DRIVER CIRCUIT
TERMINATION
calculate worst case power dissipation into load, following equations which assume load, termination voltage
logic high, VOUT
CCO_MAX
OH_MAX
CCO_MAX
0.9V
OH_MAX
0.9V 1.7V
logic low, VOUT
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
1.7V
Pd_H power dissipation when output drives high. Pd_L power dissipation when output drives low. Pd_H
OH_MAX
CCO_MAX
2V))/R
CCO_MAX
OH_MAX
[(2V
CCO_MAX
OH_MAX
))/R
CCO_MAX
OH_MAX
[(2V 0.9V)/50] 0.9V 19.8mW Pd_L 2V))/R
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
[(2V
CCO_MAX
OL_MAX
))/R
CCO_MAX
OL_MAX
[(2V 1.7V)/50] 1.7V 10.2mW Total Power Dissipation output pair Pd_H Pd_L 30mW
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ICS8431I-21
350MHZ, JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION
TABLE JAVS. FLOW TABLE
LEAD SOIC
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 76.2°C/W 46.2°C/W
60.8°C/W 39.7°C/W
53.2°C/W 36.8°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
TRANSISTOR COUNT
transistor count ICS8431I-21 4790
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ICS8431I-21
350MHZ, JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER
LEAD SOIC
PACKAGE OUTLINE SUFFIX
TABLE PACKAGE DIMENSIONS
SYMBOL 10.00 0.25 0.40 -0.10 2.05 0.33 0.18 17.70 7.40 1.27 BASIC 10.65 0.75 1.27 Millimeters MINIMUM 2.65 -2.55 0.51 0.32 18.40 7.60 MAXIMUM
Reference Document: JEDEC Publication MS-013, MO-119
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REV. APRIL 2005
ICS8431I-21
350MHZ, JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER
Marking ICS8431AMI-21 ICS8431AMI-21 Package Lead SOIC Lead SOIC Shipping Packaging Tube 1000 tape reel Temperature -40°C 85°C -40°C 85°C
TABLE ORDERING INFORMATION
Part/Order Number ICS8431AMI-21 ICS8431AMI-21T
aforementioned trademark, HiPerClockSis trademark Integrated Circuit Systems, Inc. subsidiaries United States and/or other countries. While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial industrial applications. other applications such those requiring high reliability other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 8431AMI-21
REV. APRIL 2005

350MHZ, JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER

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