FEMTOCLOCKSTMCRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER FEATURES
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ICS844003I-01
FEMTOCLOCKSTMCRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
FEATURES
Three LVDS outputs banks, Bank with LVDS pair Bank with LVDS output pairs Using 19.53125MHz 25MHz crystal, output banks independently 625MHz, 312.5MHz, 156.25MHz 125MHz Selectable crystal oscillator interface LVCMOS/LVTTL single-ended input range: 490MHz 680MHz phase jitter 156.25MHz (1.875MHz 20MHz): 0.56ps (typical) 3.3V output supply mode -40°C 85°C ambient operating temperature
GENERAL DESCRIPTION
ICS844003I-01 differential output LVDS Synthesizer designed generate Ethernet referHiPerClockSence clock frequencies member HiPerClocksfamily high performance clock solutions from ICS. Using 19.53125MHz 25MHz, 18pF parallel resonant crystal, following frequencies generated based settings frequency select pins (DIV_SEL[A1:A0], DIV_SEL[B1:B0]): 625MHz, 312.5MHz, 156.25MHz, 125MHz. 844003I-01 output banks, Bank with differential LVDS output pair Bank with differential LVDS output pairs.
banks have their dedicated frequency select pins independently frequencies mentioned above. ICS844003I-01 uses ICS' generation phase noise technology achieve lower typical phase jitter, easily meeting Ethernet jitter requirements. ICS844003I-01 packaged small 24-pin TSSOP package.
ASSIGNMENT
DIV_SELB0 VCO_SEL VDDO_A nQA0 CLK_ENB CLK_ENA FB_DIV VDDA DIV_SELA0 DIV_SELB1 VDDO_B nQB0 nQB1 XTAL_SEL TEST_CLK XTAL_IN XTAL_OUT DIV_SELA1
BLOCK DIAGRAM
CLK_ENA Pullup DIV_SELA[1:0] Pullup VCO_SEL
Pullup
ICS844003I-01
24-Lead TSSOP 4.40mm 7.8mm 0.92mm package body Package View
(default)
TEST_CLK Pulldown
nQA0
XTAL_IN
XTAL_OUT XTAL_SEL Pullup
Phase Detector
FB_DIV (default)
(default)
nQB0 nQB1
FB_DIV Pulldown DIV_SELB[1:0] Pullup
Pulldown
CLK_ENB Pullup
Preliminary Information presented herein represents product prototyping pre-production. noted characteristics based initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves right change circuitry specifications without notice.
844003AGI-01
REV. 2005
ICS844003I-01
FEMTOCLOCKSTMCRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
Type Description Division select Bank Default HIGH. Pullup LVCMOS/LVTTL interface levels. Table select pin. When Low, bypassed crystal reference TEST_CLK (depending XTAL_SEL setting) passed directly Pullup output dividers. internal pullup resistor bypassed default. LVCMOS/LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, internal dividers reset causing true outputs inver outputs Pulldown high. When logic LOW, internal dividers outputs enabled. internal pulldown resistor power-up default state outputs dividers enabled. LVCMOS/LVTTL interface levels. Output supply Bank outputs. Differential output pair. LVDS interface levels. Synchronizing clock enable Bank outputs. Active High output enable. When logic HIGH, output pair Bank enabled. When logic LOW, outputs outputs HIGH. internal pullup resistor default power-up state output enabled. LVCMOS/LVTTL interface levels. Figure Synchronizing clock enable Bank outputs. Active High output enable. When logic HIGH, output pair Bank enabled. When logic LOW, output output HIGH. internal pullup resistor default power-up state output enabled. LVCMOS/LVTTL interface levels. Figure Feedback divide select. When (default), feedback divider ÷25. When HIGH, feedback divider ÷32. LVCMOS/LVTTL interface levels. Table Analog supply pin.
TABLE DESCRIPTIONS
Number Name DIV_SELB0, DIV_SELB1 VCO_SEL
Input
Input
Input
VDDO_A QA0, nQA0
Power Ouput
CLK_ENB
Input
Pullup
CLK_ENA
Input
Pullup
FB_DIV VDDA DIV_SELA0, DIV_SELA1 XTAL_OUT, XTAL_IN TEST_CLK
Input Power Power Input Power Input
Pulldown
Input
XTAL_SEL nQB1, nQB0,
Input Output Output
Core supply pin. Division select Bank Default HIGH. Pullup LVCMOS/LVTTL interface levels. Table Power supply ground. Parallel resonant crystal interface. XTAL_OUT output, XTAL_IN input. XTAL_IN also overdrive want overdrive crystal circuit with single-ended reference clock. Single-ended reference clock input. internal pulldown resistor Pulldown pull state default. leave floating using crystal interface. LVCMOS/LVTTL interface levels. Crystal select pin. Selects between single-ended TEST_CLK crystal interface. internal pullup resistor crystal interface selected Pullup default. LVCMOS/LVTTL interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels.
Power Output supply Bank outputs. VDDO_B NOTE: Pullup Pulldown refer internal input resistors. Table Characteristics, typical values.
TABLE CHARACTERISTICS
Symbol RPULLDOWN RPULLUP
844003AGI-01
Parameter Input Capacitance Input Pulldown Resistor Input Pullup Resistor
Test Conditions
Minimum
Typical
Maximum
Units
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FEMTOCLOCKSTMCRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
Multiplication Factor 12.5 12.500 8.333 6.25 6.25 6.25 10.667 QA0/nQA0 Output Frequency (MHz) 312.5 187.5 156.25 622.08 311.04 155.52
TABLE BANK FREQUENCY TABLE
Inputs Crystal Frequency (MHz) 22.5 19.44 19.44 15.625 18.75 19.44 18.75 15.625 FB_DIV DIV_SELA1 DIV_SELA0 Feedback Divider Bank Output Divider
TABLE BANK FREQUENCY TABLE
Inputs Crystal Frequency (MHz) 19.44 15.625 19.44 18.75 15.625 15.625 19.44 18.75 15.625
844003AGI-01
FB_DIV
DIV_SELB1
DIV_SELB0
Feedback Divider
Bank Output Divider
Multiplication Factor 12.5 12.5 6.25 6.25 6.25 3.125 3.125 3.125
QB0/nQB0 Output Frequency (MHz) 312.5 156.25 78.125 62.5 311.04 155.52 77.76 62.5
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Outputs (default) Inputs DIV_SELB1 DIV_SELB0 Outputs QBx, nQBx (default)
TABLE OUTPUT BANK CONFIGURATION SELECT FUNCTION TABLE
Inputs DIV_SELA1 DIV_SELA0
TABLE FEEDBACK DIVIDER CONFIGURATION SELECT FUNCTION TABLE
Inputs FB_DIV Feedback Divide
Disabled
Enabled
TEST_CLK
CLK_ENx
nQA0, nQB0:nQB1 QA0, QB0:QB1
FIGURE CLK_EN TIMING DIAGRAM
TABLE CLK_ENA SELECT FUNCTION TABLE
Inputs CLK_ENA Active Outputs nQA0 HIGH Active
TABLE CLK_ENB SELECT FUNCTION TABLE
Inputs CLK_ENB Active Outputs QB0:QB1 nQB0:nQB1 HIGH Active
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FEMTOCLOCKSTMCRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
4.6V -0.5V 0.5V 10mA 15mA 70°C/W lfpm) -65°C 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only. Functional operation product these conditions conditions beyond those listed Characteristics Characteristics implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, Inputs, Outputs, Continuous Current Surge Current Package Thermal Impedance, Storage Temperature, TSTG
TABLE POWER SUPPLY CHARACTERISTICS, VDDA VDDO_A VDDO_B 3.3V±5%, -40°C 85°C
Symbol VDDA VDDO_A, IDDA IDDO_A, Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical Maximum 3.465 3.465 3.465 Units
TABLE LVCMOS LVTTL CHARACTERISTICS, VDDA VDDO_A VDDO_B 3.3V±5%, -40°C 85°C
Symbol Parameter Input High Voltage Input Voltage Input High Current TEST_CLK, FB_DIV DIV_SELB0, DIV_SELB1, DIV_SELA0, DIV_SELA1, VCO_SEL, XTAL_SEL, CLK_ENA, CLK_ENB TEST_CLK, FB_DIV DIV_SELB0, DIV_SELB1, DIV_SELA0, DIV_SELA1, VCO_SEL, XTAL_SEL, CLK_ENA, CLK_ENB Test Conditions 3.3V 3.3V 3.465V 3.465V 3.465V, 3.465V, -150 Minimum -0.3 Typical Maximum Units
Input Current
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FEMTOCLOCKSTMCRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
Test Conditions Minimum Typical 1.35 Maximum Units
TABLE LVDS CHARACTERISTICS, VDDA VDDO_A VDDO_B 3.3V±5%, -40°C 85°C
Symbol Parameter Differential Output Voltage Magnitude Change Offset Voltage Magnitude Change
TABLE CRYSTAL CHARACTERISTICS
Parameter Mode Oscillation Frequency FB_DIV FB_DIV 19.6 15.313 Test Conditions Minimum Typical Fundamental 27.2 21.25 Maximum Units
Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level NOTE: Characterized using 18pF parallel resonant ystal.
TABLE CHARACTERISTICS, VDDA VDDO_A VDDO_B 3.3V±5%, -40°C 85°C
Symbol Parameter Test Conditions Output Divider Output Divider fOUT Output Frequency Range Output Divider Output Divider Output Divider Output Divider Minimum 163.33 122.5 61.25 Outputs Same Frequency Outputs Different Frequencies 625MHz (1.875MHz 20MHz) 312.5MHz (1.875MHz 20MHz) 156.25MHz (1.875MHz 20MHz) 125MHz (1.875MHz 20MHz) Output Rise/Fall Time 0.53 0.53 0.56 0.58 Typical Maximum 226.67 Units
tsk(b) tsk(o)
Bank Skew, NOTE Output Skew; NOTE
Phase Jitter (Random); NOTE
Output Duty Cycle NOTE Defined skew within bank outputs same voltages with equal load conditions. NOTE Defined skew between outputs same supply voltages with equal load conditions. Measured output differential cross points. NOTE Please refer Phase Noise Plots. NOTE This parameter defined accordance with JEDEC Standard
844003AGI-01
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FEMTOCLOCKSTMCRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE 156.25MHZ
10Gb Ethernet Filter 156.25MHz
Phase Jitter (Random) 1.875MHz 20MHz 0.56ps (typical)
NOISE POWER
-100 -110 -120 -130 -140 -150 -160 -170 -180 -190
Phase Noise Data
Phase Noise Result adding 10Gb Ethernet Filter data
100k 100M
OFFSET FREQUENCY (HZ)
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FEMTOCLOCKSTMCRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
Phase Noise Plot
Noise Power
SCOPE
Power Supply
Float
LVDS
Phase Noise Mask
Offset Frequency
Jitter Area Under Masked Phase Noise Plot
LVDS 3.3V OUTPUT LOAD TEST CIRCUIT
tsk(o)
PHASE JITTER
nQA0, nQB0, nQB1 QA0, QB0,
PERIOD
PERIOD
100%
OUTPUT SKEW
nQB0
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
Clock Outputs
nQB1
tsk(b)
BANK SKEW
OUTPUT RISE/FALL TIME
Input
LVDS
VOD/
Input
LVDS
VOS/
DIFFERENTIAL OUTPUT VOLTAGE SETUP
844003AGI-01
OFFSET VOLTAGE SETUP
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FEMTOCLOCKSTMCRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
high speed analog circuitry, power supply pins vulnerable random noise. ICS844003I-01 provides separate power supplies isolate high switching noise from outputs internal PLL. VDD, VDDA, VDDOx should individually connected power supply plane through vias, bypass capacitors should used each pin. achieve optimum jitter performance, power supply isolation required. Figure illustrates resistor along with .01F bypass capacitor should connected each VDDA pin.
3.3V .01F VDDA .01F
FIGURE POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
ICS844003I-01 been characterized with 18pF parallel resonant crystals. capacitor values shown Figure below were determined using 19.53125MHz 25MHz 18pF parallel resonant crystal were chosen minimize error.
XTAL_OUT 18pF Parallel Crystal XTAL_IN
ICS844003I-01
Figure CRYSTAL INPUt INTERFACE
844003AGI-01
REV. 2005
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FEMTOCLOCKSTMCRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
receiver input. multiple LVDS outputs buffer, only partial outputs used, recommended terminate unused outputs.
3.3V LVDS DRIVER TERMINATION
general LVDS interface shown Figure differential transmission line environment, LVDS drivers require matched load termination across near
3.3V 3.3V LVDS
Differential Transmission Line
FIGURE TYPICAL LVDS DRIVER TERMINATION
RELIABILITY INFORMATION
TABLE
JAVS. FLOW TABLE
LEAD TSSOP
Velocity (Meters Second)
Multi-Layer PCB, JEDEC Standard Test Boards 70°C/W
65°C/W
62°C/W
TRANSISTOR COUNT
transistor count ICS844003I-01 3537
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FEMTOCLOCKSTMCRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
LEAD TSSOP
PACKAGE OUTLINE SUFFIX
TABLE PACKAGE DIMENSIONS
SYMBOL 0.45 -4.30 0.65 BASIC 0.75 0.10 -0.05 0.80 0.19 0.09 7.70 6.40 BASIC 4.50 Millimeters Minimum 1.20 0.15 1.05 0.30 0.20 7.90 Maximum
Reference Document: JEDEC Publication MO-153
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REV. 2005
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FEMTOCLOCKSTMCRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
Marking ICS844003AI01 ICS844003AI01 Package Lead TSSOP Lead Shipping Packaging tube 2500 tape reel Temperature -40°C 85°C -40°C 85°C
TABLE ORDERING INFORMATION
Part/Order Number ICS844003AGI-01 ICS844003AGI-01T
aforementioned trademarks, HiPerClockSand FemtoClocksare trademark Integrated Circuit Systems, Inc. subsidiaries United States and/or other countries. While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial industrial applications. other applications such those requiring high reliability other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 844003AGI-01
REV. 2005
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