FEMTOCLOCKSTMCRYSTAL-TOLVDS FREQUENCY SYNTHESIZER FEATURES F
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ICS844004I-01
FEMTOCLOCKSTMCRYSTAL-TOLVDS FREQUENCY SYNTHESIZER
FEATURES
Four LVDS outputs Selectable crystal oscillator interface LVCMOS/LVTTL single-ended input Supports following output frequencies: 156.25MHz, 125MHz, 62.5MHz range: 560MHz 680MHz phase jitter 156.25MHz, using 25MHz crystal (1.875MHz 20MHz): 0.41ps (typical) Full 3.3V 2.5V supply modes -40°C 85°C ambient operating temperature
GENERAL DESCRIPTION
ICS844004I-01 output LVDS Synthesizer optimized generate Ethernet reference clock HiPerClockSfrequencies member HiPerClocks family high performance clock solutions from ICS. Using 25MHz 18pF parallel resonant crystal, following frequencies generated based frequency select pins (F_SEL[1:0]): 156.25MHz, 125MHz 62.5MHz. ICS844004I-01 uses ICS' generation phase noise technology achieve <1ps typical phase jitter, easily meeting Ethernet jitter requirements. ICS844004I-01 packaged small 24pin TSSOP package.
FREQUENCY SELECT FUNCTION TABLE
F_SEL1 F_SEL0 Divider Value Divider Value Used Divider Value 6.25 Output Frequency (25MHz Ref.) 156.5 62.5 Used
ASSIGNMENT
nPLL_SEL VDDA F_SEL0 F_SEL1 VDDO nXTAL_SEL TEST_CLK XTAL_IN XTAL_OUT
ICS844004I-01
BLOCK DIAGRAM
F_SEL[1:0] Pulldown nPLL_SEL Pulldown TEST_CLK Pulldown
25MHz
24-Lead TSSOP 4.40mm 7.8mm 0.92mm package body Package View
F_SEL[1:0]
XTAL_IN
XTAL_OUT nXTAL_SEL
Pulldown
Phase Detector
625MHz
(w/25MHz Reference)
used
(fixed)
Pulldown
Preliminary Information presented herein represents product prototyping pre-production. noted characteristics based initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves right change circuitry specifications without notice. 844004AGI-01 REV. JUNE 2005
ICS844004I-01
FEMTOCLOCKSTMCRYSTAL-TOLVDS FREQUENCY SYNTHESIZER
TABLE DESCRIPTIONS
Number Name nQ1, VDDO Type Output Power Ouput Input Description Differential output pair. LVDS interface levels. Output supply pins. Differential output pair. LVDS interface levels. Active HIGH Master Reset. When logic HIGH, internal dividers reset causing true outputs inver outputs Pulldown high. When logic LOW, internal dividers outputs enabled. LVCMOS/LVTTL interface levels. Selects between TEST_CLK input dividers. When Pulldown LOW, selects (PLL Enable). When HIGH, deselects reference clock (PLL Bypass). LVCMOS/LVTTL interface levels. connect. Analog supply pin. Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. Core supply pin. Parallel resonant ystal interface. XTAL_OUT output, XTAL_IN input. Power supply ground. Pulldown LVCMOS/LVTTL clock input. Selects between ystal TEST_CLK inputs Reference Pulldown source. Selects XTAL inputs when LOW. Selects TEST_CLK when HIGH. LVCMOS/LVTTL interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels.
nPLL_SEL VDDA F_SEL0, F_SEL1 XTAL_OUT, XTAL_IN TEST_CLK nXTAL_SEL nQ3,
Input Unused Power Input Power Input Power Input Input Output Output
NOTE: Pulldown refers internal input resistors. Table Characteristics, typical values.
TABLE CHARACTERISTICS
Symbol RPULLDOWN Parameter Input Capacitance Input Pulldown Resistor Test Conditions Minimum Typical Maximum Units
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4.6V -0.5V 0.5V 10mA 15mA 70°C/W lfpm) -65°C 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only. Functional operation product these conditions conditions beyond those listed Characteristics Characteristics implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, Inputs, Outputs, Continuous Current Surge Current Package Thermal Impedance, Storage Temperature, TSTG
TABLE POWER SUPPLY CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 85°C
Symbol VDDA VDDO IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical Maximum 3.465 3.465 3.465 Units
TABLE POWER SUPPLY CHARACTERISTICS, VDDA VDDO 2.5V±5%, -40°C 85°C
Symbol VDDA VDDO IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 2.375 2.375 2.375 Typical Maximum 2.625 2.625 2.625 Units
TABLE LVCMOS LVTTL CHARACTERISTICS, VDDA VDDO 3.3V±5% 2.5V±5%, -40°C 85°C
Symbol Parameter Input High Voltage Input Voltage Input High Current Input Current TEST_CLK, F_SEL0, F_SEL1, nPLL_SEL, nXTAL_SEL TEST_CLK, F_SEL0, F_SEL1, nPLL_SEL, nXTAL_SEL Test Conditions 3.3V 2.5V 3.3V 2.5V 3.465 2.5V 3.465V 2.5V, Minimum Typical -0.3 -0.3 Maximum Units
-150
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TABLE LVDS CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 85°C
Symbol Parameter Differential Output Voltage Magnitude Change Offset Voltage Magnitude Change Test Conditions Minimum Typical Maximum Units
TABLE LVDS CHARACTERISTICS, VDDA VDDO 2.5V±5%, -40°C 85°C
Symbol Parameter Differential Output Voltage Magnitude Change Offset Voltage Magnitude Change Test Conditions Minimum Typical Maximum Units
TABLE CRYSTAL CHARACTERISTICS
Parameter Mode Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level NOTE: Characterized using 18pF parallel resonant crystal. 22.4 Test Conditions Minimum Typical Maximum 27.2 Units Fundamental
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Test Conditions F_SEL[1:0] F_SEL[1:0] F_SEL[1:0] Minimum Typical 156.5 62.5 156.25MHz, (1.875MHz 20MHz) 0.41 0.44 0.47 125MHz, (1.875MHz 20MHz) 62.5MHz, (1.875MHz 20MHz) Maximum Units
TABLE CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 85°C
Symbol fOUT Parameter Output Frequency Output Skew; NOTE Phase Jitter (Random); NOTE Output Rise/Fall Time
tsk(o)
Output Duty Cycle NOTE Defined skew between outputs same supply voltages with equal load conditions. Measured VDDO/2. NOTE This parameter defined accordance with JEDEC Standard NOTE Please refer Phase Noise Plot.
TABLE CHARACTERISTICS, VDDA VDDO 2.5V±5%, -40°C 85°C
Symbol fOUT Parameter Output Frequency Output Skew; NOTE 156.25MHz, (1.875MHz 20MHz) Phase Jitter (Random); NOTE Output Rise/Fall Time 125MHz, (1.875MHz 20MHz) 62.5MHz, (1.875MHz 20MHz) Test Conditions F_SEL[1:0] F_SEL[1:0] F_SEL[1:0] Minimum Typical 156.5 62.5 0.41 0.44 0.47 Maximum Units
tsk(o)
Output Duty Cycle NOTE Defined skew between outputs same supply voltages with equal load conditions. Measured VDDO/2. NOTE This parameter defined accordance with JEDEC Standard NOTE Please refer Phase Noise Plot.
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PARAMETER MEASUREMENT INFORMATION
3.3V±5% POWER SUPPLY Float
SCOPE
2.5V±5% POWER SUPPLY Float
SCOPE
LVDS
LVDS
3.3V CORE/3.3V OUTPUT LOAD TEST CIRCUIT
2.5V CORE/2.5V OUTPUT LOAD TEST CIRCUIT
tsk(o)
TEST_CLK nQ0:nQ3 Q0:Q3
OUTPUT SKEW
PROPAGATION DELAY
Phase Noise Plot
Noise Power
nQ0:nQ3 Q0:Q3
PERIOD
Phase Noise Mask
Offset Frequency
PERIOD
100%
Jitter Area Under Masked Phase Noise Plot
PHASE JITTER
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OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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Clock Outputs
Input
LVDS
VOS/
OUTPUT RISE/FALL TIME
OFFSET VOLTAGE SETUP
Input
LVDS
VOD/
DIFFERENTIAL OUTPUT VOLTAGE SETUP
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APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
high speed analog circuitry, power supply pins vulnerable random noise. ICS844004I-01 provides separate power supplies isolate high switching noise from outputs internal PLL. VDD, VDDA, VDDO should individually connected power supply plane through vias, bypass capacitors should used each pin. achieve optimum jitter performance, power supply isolation required. Figure illustrates resistor along with 10µF .01F bypass capacitor should connected each VDDA.
3.3V 2.5V .01F .01F
FIGURE POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
ICS844004I-01 been characterized with 18pF parallel resonant crystals. capacitor values shown Figure below were determined using 26.5625MHz 18pF parallel resonant crystal were chosen minimize error.
XTAL_OUT 18pF Parallel Crystal XTAL_IN
ICS844004I-01
Figure CRYSTAL INPUt INTERFACE
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receiver input. multiple LVDS outputs buffer, only partial outputs used, recommended terminate un-used outputs.
3.3V, 2.5V LVDS DRIVER TERMINATION
general LVDS interface shown Figure differential transmission line environment, LVDS drivers require matched load termination across near
2.5V 3.3V LVDS_Driv
Differential Transmission Line
FIGURE TYPICAL LVDS DRIVER TERMINATION
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RELIABILITY INFORMATION
TABLE
JAVS. FLOW TABLE
LEAD TSSOP
Velocity (Meters Second)
Multi-Layer PCB, JEDEC Standard Test Boards 70°C/W
65°C/W
62°C/W
TRANSISTOR COUNT
transistor count ICS844004I-01 2914
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LEAD TSSOP
PACKAGE OUTLINE SUFFIX
TABLE PACKAGE DIMENSIONS
SYMBOL 0.45 -4.30 0.65 BASIC 0.75 0.10 -0.05 0.80 0.19 0.09 7.70 6.40 BASIC 4.50 Millimeters Minimum 1.20 0.15 1.05 0.30 0.20 7.90 Maximum
Reference Document: JEDEC Publication MO-153
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TABLE ORDERING INFORMATION
Part/Order Number ICS844004AGI-01 ICS844004AGI-01T Marking ICS844004AI01 ICS844004AI01 Package Lead TSSOP Lead TSSOP Shipping Packaging tube 2500 tape reel Temperature -40°C 85°C -40°C 85°C
aforementioned trademarks, HiPerClockSand FEMTOCLOCKSare trademarks Integrated Circuit Systems, Inc. subsidiaries United States and/or other countries. While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial industrial applications. other applications such those requiring high reliability other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 844004AGI-01
REV. JUNE 2005
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