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Voice/Melody/LCD Controller (ViewTalkSeries) GENERAL DESCRIPTION


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W53322/W53342
Voice/Melody/LCD Controller (ViewTalkSeries)
GENERAL DESCRIPTION FEATURES BLOCK DIAGRAM. DESCRIPTION FUNCTIONAL DESCRIPTION.
PART FUNCTION. Program Counter (PC) Stack Register (STACK). Program Memory (ROM). Data Memory (RAM). Special Rgister Special Register Pair(SR SRP). Accumulator (ACC). Arithmetic Logic Unit (ALU) Clock Generator. Dual-clock operation. Divider Watchdog Timer (WDT). Timer/Counter Interrupts. Hold Mode Operation Input/Output Ports Input Ports Output Port Reset Function. PART SPEECH MELODY FUNCTION SPEECH Function Melody Function PART FUNCTION pattern Mode Register (LCDM1 with SR=2AH). frame rate divider (LDIV with SR=12H).
ABSOLUTE MAXIMUM RATINGS CHARACTERISTICS
Publication Release Date: March 1999 -1Revision
W53322/W53342
TYPICAL APPLICATION CIRCUIT INSTRUCTION TABLE
SYMBOL DESCRIPTION COMPLETE INSTRUCTION TABLE 2.45
W53322/W53342
GENERAL DESCRIPTION
W53322/W53342 high-performance 4-bit microcontroller (µC) with built-in speech, melody 32*48/32*64 driver which includes internal pump circuit. 4-bit core contains dual clock source, 4-bit ALU, 8-bit timers, divider, Input output, interrupt sources 8-level subroutine nesting interrupt applications. Speech unit implemented with Winbond 60-sec Power Speech using ADPCM algorithm. Melody unit provides dual tone output store notes. Power reduction mode also built minimize power dissipation. ideal games, educational toys, remote controllers, watches, clocks other application's products which incorporate both display melody.
FEATURES
Operating voltage: 2.4volt 5.5volt Dual clock operating system -RC/Crystal (400 MHz) main clock 32.768 crystal oscillation circuit sub-oscillator Memory program 896x4/1024 general data (384x4/512x4 shared LCD) input/output pins -Ports input only: ports/8 pins -Input/output ports: ports/8 pins -Port output only: port pins mode -Hold function: operation (except 32kHz oscillator) -Stop mode function: operation (include 32kHz oscillator) Seven types interrupts -Five internal interrupts (Divider ,Timer Timer Speech, Melody) -Two external interrupts (Port Port built-in 14-bit clock frequency divider circuit built-in 8-bit programmable countdown timers -Timer internal clock frequencies (FOSC/4 FOSC/1024) selected -Timer built-in auto-reload function includes internal timer with FOSC, FOSC/64 8KHz clock source option TONE output function which used carrier output main clock 455kHz) Built-in 18/14-bit watchdog timer system reset mask code option Powerful instruction sets 8-level subroutine (including interrupt) nesting driver output common 48/64 segment 1/16 duty 1/32 duty, bias, internal pump circuit option special register Speech function -Provide 1.4M bits dedicated speech -With direct driving output speaker Publication Release Date: March 1999 -3Revision
W53322/W53342
-Maximum sections available Melody function -Provide kbits dedicated melody -Provide kinds beat, kinds tempo, pitch rang from -Tremolo, triple frequency kinds percussion available -With direct driving output speaker -Maximum scores available speech with melody available Multi-engine controller output current option Chip Board available
BLOCK DIAGRAM
SEG0 SEG63 COM0 COM31 VDD2 VDD3 DH1,
(1024*4)
DRIVER
VLCD PUMP CIRCUIT
TEST
PORT (16K*20) PORT
RA0~3
RB0~3
PORT Special Register
MLDH FLAG1 FLAG0 LUP2 RP0M SPCH LUP3 RP0H TONE SPC_busy
RD0~3
PORT
RC0~
STACK Levels)
PSR0 LUP0 LUP1 RP0L
PORT
LED1 LED2 ROSC PWM1 PWM2
SPC_busy
Speech 1.4M bits ROM)
Timer Bit)
Timer Bit)
Interrup Hold Mode Release
MLD_busy MLD_play
Dual Tone Melody (1K*22 ROM) VSS2 VDDP VSS1
Watch Timer (18/14 Bit)
Divider (14/10 Bit)
Timing Generator
XOUT X32I X32O
DESCRIPTION
W53322/W53342
SYMBOL XOUT X32I X32O
FUNCTION Input oscillator. connected crystal, connect resistor generate main system clock. Oscillator stopped when SCR.1 logic Output oscillator which connected another crystal pin. 32.768 crystal input pin. 32.768 crystal output pin. General Input/Output port specified register. output mode selected, register used specify CMOS/NMOS driving capability option. Initial state input mode. General Input/Output port specified register. output mode selected, register used specify CMOS/NMOS driving capability option. Initial state input mode. 4-bit schmitt input with internal pull high option specified register. Each independent interrupt capability specified PEFL special register. 4-bit schmitt input port with internal pull high option specified register. Each independent interrupt capability specified PEFH special register. Output port only. TONE special register logic System reset with internal pull-high resistor active low. Test pin. Connected normal use. Connect resistor generate speech melody clock source. Power source output. Synchronous LED1 output while speech play/melody active. Synchronous LED2 output only while speech play active. Speaker direct driving output while speech melody active. Speaker direct driving output while speech melody active. segment output pins. common signal output pins. alternating frequency fixed 64Hz. Connection terminals voltage doubler capacitor. Connect capacitor VSS1 double voltage output triple pump option enabled. Otherwise, VDD2 connects directly double pump option enabled. output internal pump circuit enabled. connects capacitor VSS. Triple voltage will output triple pump option enabled. Otherwise, double voltage will output double pump option enabled. input internal pump voltage disabled. COM/SEG output driving voltage. internal shunt resistor disabled, external resistors need supplied capacitor suggested stable voltage level. External variable resistor connects between VDD3 adjust maximun voltage level. Microcontroller Positive power supply (+). Negative power supply (-). Negative power supply (-).
RE0~RE3/TONE
TEST ROSC VDDP LED1 LED2 PWM1 PWM2 SEG0-SEG31/47/ COM0-COM31 DH1, VDD2 VDD3
VSS1 VSS2
Publication Release Date: March 1999 -5Revision
W53322/W53342
FUNCTIONAL DESCRIPTION
Four main units included W533X2. They 4bit power speech, dual tone melody 32/48/64 driver. 4bit modified from winbond W741C260 that many features enhanced such space, space addressing capability, more more instruction sets interrupt sources, controlling speech melody playing drive speaker directly separate three parts PART PARTB PART explain function more detailly.
PART FUNCTION
Program Counter (PC) Organized 14-bit binary counter (PC0 PC13), program counter generates addresses onchip containing program instructions. When jump subroutine call instructions interrupt initial reset conditions executed, address corresponding instruction will loaded into program counter. format used shown Table ITEM Initial Reset (DIV) (RC) (RD) (Reserved) (SPEECH) (MELODY) Instruction Subroutine Call Stack Register (STACK) stack register organized 14bits levels (first-in, last-out). When either call subroutine interrupt executed, program counter will pushed onto stack register automatically. call subroutine interrupt service subroutine, instruction must executed contents stack register into program counter. When stack register pushed over eighth level, contents first level will lost. other words, stack register maximun with subroutine nesting. Program Memory (ROM) Architecture read-only memory used store program codes addressed from 0000h~3FFFH. Location from 000H 0020H reserved interrupt service shown Figure instruction sets word, cycle. Lookup table function provided access code spaces. organization program memory shown Figure ADDRESS 0000H 0004H 0008H 000CH 0010H 0018H 001CH 0020H XXXXH XXXXH INTERRUPT PRIORITY
Table Interrup Address Assignment Priority
W53322/W53342
bits 0000H 0004H 0008H 000CH 0010H 16384 0014H address 0018H 001CH 0020H Reset start reserved SPEECH MELODY This area used store both instruction code look table data look-up table.
3FFFH
bits
Figure Program Memory Organization Look-Up Table Pointer Register(LUP3, LUP2, LUP1, LUP0 LUC) LUPC (Look-up table address Pointer Counter) symbol instruction used access data space. includes registers LUP3 (Look-Up table Pointer), LUP2, LUP1, LUP0, LUC(Look-Up table data Counter) LUP3~LUP0 store bits address access data word ROM, each word separated nibbles that counts from cyclical. instruction LUPn, write LUPC initial address pointer look-up table, reset register following equation described. LUPC=LUPC.13~LUPC.0 LUC.3~LUC.0 LUPC.13~LUPC.0 from 0000~3FFFH used word address uses select which nibble word data counts from cyclical. When LUPC incresased firstly increase LUP0 will inreased while counted from LUP1 increased LUP0 counted from then LUP3, LUP2 will follow same rule LUP1. will increased automatically while symbol @LUPC++ used. registers LUP3~LUP0 read/write user, register reald only. initial reset, registers 0000B. LUP.13 LUP.12 LUP.11 LUP.10 LUP.9 LUP.8 LUP2 LUP.4
LUP3
LUP.7 LUP.6 LUP.5 LUP1
LUP.3 LUP.2 LUP.1 LUP.0 LUP0
LUC.3 LUC.2 LUC.1 LUC.0
Publication Release Date: March 1999 -7Revision
W53322/W53342
Data Memory (RAM) Architecture static data memory (RAM) arranged maximun 512+(384/512) bits. data memory addressed directly indirectly. organization data memory shown Figure using W53322 example. first nibbles from 1FFH dedicated general data memory. Data memory from 200H 37FH/3FFH roles either dedicated pattern data memory Table mapping general data memory because they have same addressing capability 000H 1FFH. There data memory address point (RP0H+RP0M+RP0L) (RP1H+RP1M+RP1L) that programmer indirect addressing instruction such ACC, @RP0 @RP1, @RP0 move data between different data memory range ACC. also provide instruction between such @RP0, @LUPC that user move look-up table data general easily. instruction @RP0++, @LUPC++ also provides point counter incresaed automatically after instruction executed. Please refer instruction sets description more detail. first sixteen addresses (00H 3FH) data memory known page working registers. Only working register operate directly with immediate data. There special register WRPAGE from select working register page Working Register Page (WRPAGE with SR=30H) special register WRPAGE organized 4-bit counts from separate nibbles pages. Every page included nibbles. descriptions follows: WRPAGE
3~0: 0000~1011 Page Page Bit3~0: 1100~1111 inhibited. bits read/write user. initial reset, WRPAGE 0000B.
bits WRPAGE WRPAGE nibbles nibbles
address
WRPAGE
General
200H WRPAGE
WRPAGE 37FH WRPAGE bits
Figure Data Memory Organization Point Register (RP0L, RP0M, RP0H,, RP1L, RP1M, RP1L) There points that user uses access data easily direct indirect addressing. Point (RP0) organized RP0.9~RP0.0 that special registers used RP0L, RP0M RP0H. Point (RP1) same structure RP0, RP1L, RP1M RP1H needed.
W53322/W53342
RP0H
RP0.9 RP0.8 RP0.7 RP0.6 RP0.5 RP0.4 RP0.3 RP0.2 RP0.1 RP0.0 RP0M RP0L
RP1H
RP1.9 RP1.8 RP1.7 RP1.6 RP1.5 RP1.4 RP1.3 RP1.2 RP1.1 RP1.0 RP1M RP1L
bits RP0, read/written user. initial reset, data 0000B.
Special Rgister Special Register Pair(SR SRP)
There some special registers formatted register shown Table that chip operating condition depended special register value. Programmer such "MOV "CLR "SET command write suitable value control chip operatiing state. Some special register such HEF, write immediate data simultaneously Special Register Pair (SRP) command that format SRP, special register function will described detailly while close relation function introduced.
Publication Release Date: March 1999 -9Revision
W53322/W53342
Symbol -TM0L(w) TM0H(w) TM1L(w) TM1H(w) TMC1L(r) TMC1H(r) -EVFL(r,c) EVFH(r,c) HEFL(r/w,s/c) HEFH(r/w,s/c) IEFL(r/w,s/c) IEFH(r/w,s/c) HCFL(r) HCFH(r) LDIV(w) -PEFL(r/w,s/c) PEFH(r/w,s/c) RP0L(r/w) RP0M(r/w) RP1L(r/w) RP1M(r/w) RP0H(r/w) RP1H(r/w) MLDL(w) MLDH(w) SPCL(w) SPCH(w) CF(r,s/c) -FLAG0(r/w,s/c) FLAG1(c)
Function
assignment
nibble Timer high nibble Timer nibble Timer high nibble Timer nibble Timer high nibble Timer
TM0.3~TM0.0 TM0.7~TM0.4 TM1.3~TM1.0 TM1.7~TM1.4 TM1.3~TM1.0 TM1.7~TM1.4
Event Flag (set chip hardware interrupt occurred) Hold mode release Enable Flag Interrup Enable Flag Hold mode release Condition Flag (set hold mode released) Divider fundamental frequency Port Enable Flag hold mode release interrupt function address Pointer nibble address Pointer Middle nibble address Pointer nibble address Pointer Middle nobble address Pointer High nibble address Pointer High nibble MeLoDy score address nibble MeLoDy score address High nibble SPeeCh section address nibbel SPeeCh section address High nibbel Carrier Flag melody/speech busy play flag reset flag Divider/WatchDog
RD,RC,TM0,DIV TM1,SPEECH,MELODY,X RD,RC,TM0,DIV TM1,SPEECH,MELODY,X RD,RC,TM0,DIV TM1,SPEECH,MELODY,X RD,RC,TM0,DIV TM1,SPEECH,MELODY,X LDIV.3 LDIV.0 RC.3, RC.2, RC.1, RC.0 RD.3, RD.2, RD.1, RD.0 RP0.3~RP0.0 RP0.7~RP0.4 RP1.3~RP1.0 RP1.7~RP1.4 X,X, RP0.9,RP0.8 X,X, RP1.9,RP1.8 MLD.3~MLD.0 MLED1,MLED0, OSB,MLD.4 SPC.3~SPC.0 SPC.7~SPC.4 X,X,X,CF MLD_busy,SPC_busy,MLD_play, SPC_play X,DIVR,WDTR,X
W53322/W53342
MR2(r/w,s/c) MR3(w)
special register interrupt enable Mode register
X,X,X,INTEN Vlcd, FsENB, PWM1, PWM0 TM0EN,TM1EN,LCDEN,TONE WDTCK,TM0CK,TM1SR,TM1CK COM32B,BIAS7B,PUPV3B,INTSRB DIV5MB,FMRCB,FMEN,F32IN LUPC.3~LUPC.0 LUPC.7~LUPC.4 LUPC.11~LUPC.8 X,X,LUPC.13,LUPC.12 0000~1101H 0000~0100H RD_PH,RC_PH,RB_NM,RA_NM RC3EG~RC0EG RD3EG~RD0EG RA3IN~RA0IN RB3IN~RB0IN RA3~RA0 RB3~RB0 RC3~RC0 RD3~RD0 RE3~RE0
MR0(r/w,s/c) Mode Register timer MR1(w) Mode Register timer LCDM1(w) Mode register SCR(r/w,s/c) System Control Register LUP0(r/w) Look table address pointer first nibble LUP1(r/w) Look table address pointer nibble LUP2(r/w) Look table address pointer nibble LUP3(r/w) Look table address pointer nibble WRPAGE(r/w) Working Register PAGE register LUC(r) LUPC nibble counter PM0(r/w,s/c) Port Mode Register PSR0(r,clr-all) Port Status change Register PSR1(r,clr-all) Port Status chabge Register PM1(r/w,s/c) Port Mode select Register PM2(r/w,s/c) Port Mode select Register PORTA(r/w) PORT data PORTB(r/w) PORT data PORTC(r) PORT data PORTD(r) PORT data PORTE(w) PORT data 3D~3F -Note means "read, write, set, clear" separately) Note "clr-all means will clear simultaneously. Note means don't care Table Special Register address mapping
Accumulator (ACC)
accumulator (ACC) 4-bit register used hold results from transfer data between data memory, ports, special registers.
Arithmetic Logic Unit (ALU)
This circuit which performs arithmetic logic operations. provides following functions: Logic operations: ANL, XRL, Branch decisions: JB0, JB1, JB2, JB3, JNZ, JNC, DSKZ, DSKNZ, SKB0, SKB1, SKB2, SKB3, JNB0, JNB1, JNB2, JNB3, SKNB0, SKNB1, SKNB2, SKNB3 Shift operations: SHRC, RRC, SHLC, RLC, Binary additions/subtractions: ADDC, ADD, ADDU, SUB, SUBB, DEC, After above instructions executed, status carry flag (CF) zero signal (ZF) will influenced. will stored internal register, read executing MOVA Carrie Flag Register with SR=20H) register only stored signal state. Please refer instruction sets know signal status. Publication Release Date: March 1999 Revision
W53322/W53342
Clock Generator
W533X2 provides oscillation circuits- main-oscillator (FM) sub-oscillator (FS). (System Control Register) uses select clock operation condition. Either main-oscillator sub-clock system clock FOSC F32IN option (bit special register) main-oscillator starts oscillation FMEN (bit SCR) written Main-oscillator select crystal oscillation special register FMRCB (bit SCR) through external connections. crystal oscillator used, crystal ceramic resonator must connected between XOUT, capacitor must connected accurate frequency needed. oscillator range form MHz. ceramic resonator selected carrier output from RE3/TONE needed. oscillator used, resistor must connected between VDD. sub-oscillator must connected 32.768 crystal between X32I X32O. connection shown Figure machine cycle consists four-state system clock sequence with system clock.
RXIN Crystal (400K 4MHz XOUT Crystal X32O X32I
Figure Oscillator Configuration
Dual-clock operation
This operation mode dual-clock mode while FMEN enable, operation clock source should suboscillator clock (32768 only. Sub-clock used system clock initial reset such power reset active because special register 0001B. Programmer firstly needs write F32IN suitable value program start change system clock main-clock high frequency clock needed. exchange main-clock sub-clock operation performed resetting setting F32IN. F32IN reset clock source system clock generator main-oscillator clock; F32IN clock source system clock generator sub-oscillator clock. main-oscillator stop oscillating when FMEN reset When reset, must attention following: XX10B XX01B: Disable main-oscillator (FM) should done simultaneously with changing system clock source(FOSC) from FOSC should changed first from before main-oscillator (FM) disable. correct seqence XX10BXX11BXX01B. XX01B XX10B: Enabling main-oscillator should done simultaneously with changing from into main-oscillator (FM) should enabled first before delay subroutine called allow main-oscillator oscillate stably. FOSC changed from into correct sequence therefore XX01BXX11Bdelay subroutineXX10B. suggested delay ceramic resonator crystal. must remember that XX00B state which stopped FOSC come from inhibitive, because will induce system shutdown. organization dual-clock operation mode shown below.
W53322/W53342
SCR.0 (F32IN) XOUT SCR.1 (FMEN)
HOLD
Main Oscillator
enable
Fosc Fs(1)
System Clock Generator
type select SCR.2 (FMRCB)
(Fosc=Fs while initial reset)
Frequency Selector
X32O X32I
FLCD
Sub-oscillator
Divider
SCR.3 (DIV5MS)
INT0 HCF.0
Figure Dual Clock Operation Mode Control Diagram System Control Register (SCR with SR=2BH) register organized register SCR.3~SCR.0. function assignment shown following. DIV5MB FMRCB FMEN F32IN F32IN used FOSC input used FOSC input FMEN oscillation disable oscillation enable FMRCB type oscillation type XTAL oscillation DIV5MB Divider 0.5sec will overflow periodically Divider 0.125sec will overflow periodically. possible read/write, set/clear user. initial reset, 0001B.
Divider
There divider 14-bit/12bit binary up-counter designed generate periodic interrupts. divider incremented each clock (Fs). When overflow occurred, divider event flag (EVF.0 interrupt executed divider interrupt enable flag been (IEF.0 hold state terminated hold release enable flag been (HEF.0 There time periods (500mS that selected DIV5MB bit. When DIV5MB reset (default), period time selected; others DIV5MB select
Watchdog Timer (WDT)
watchdog timer (WDT) used prevent program from unknown errors. function enable mask option clock source Fosc/1024 Fosc/16384 WDTCK (bit special register) initial reset, WDTCK come from FOSC/1024. overflows occurred while chip operation under control will reset. contents reset instruction FLAG1, #0010B (CLR WDT). input clock Publication Release Date: March 1999 Revision
W53322/W53342
switched FOSC/16384 FOSC/1024) while WDTCK written normal operation, application program must reset WDT) before overflows. minimun overflow period 500mS when system clock (FOSC) clock input FOSC/1024. organization watchdog timer shown Figure
FLAG1 Register (FLAG1 with SR=23H) Divider watchdog counter reset FLAG1, instruction. Both instructions clear DIVR WDTR separately. descriptions following. FLAG1 DIVR WDTR DIVR influence Divider counter clear WDTR=0 influence Watchdog timer clear means don't care value cleared only. initial reset, FLAG1 0000B.
Divider
HEF.0 Fosc/16384 Fosc/4096 SCR.3 (DIV5MB) Hold mode release (HCF.0) EVF.0 IEF.0 Divider interrupt (INT0)
Fosc
Reset EVF,#01H FLAG1,#0100B (CLR DIV)
Fosc/16384 Fosc/1024 MR1.3 (WDTCK) Enable /Disable Mask Option
Overflow signal
System Reset
Reset FLAG1,#0010B (CLR WDT)
Figure Organization Divider Watchdog Timer
Timer/Counter
Timer (TM0) Timer (TM0) programmable 8-bit binary down-counter. specified value loaded into executing
W53322/W53342
TM0L(TM0H),R instructions. execute TM0L(TM0H),R instructions will stop down-counting processing down-counting, reset TM0EN option (bit special register) load specified value TM0. When TM0EN event flag (EVF.1) reset starts count. Timer stops operating generates underflow (EVF.1 while decrements FFH. interrupt executed Timer interrupt enable flag been (IEF.1 hold state terminated hold release enable flag been (HEF.1 Timer clock input select either FOSC/1024 FOSC/4 setting TM1CK (bit special register) resetting TM1CK organization Timer shown Figure Example: Timer clock input FOSC/4, then: Desired Time interval (preset value 1/FOSC Timer clock input FOSC/1024, then: Desired Time interval (preset value 1024 1/FOSC Preset value: Decimal number Timer preset value
MR1.2 (TM0CK) Fosc/1024 Fosc/4
Disable 8-Bit Binary Down Counter (Timer Enable
Reset EVF,#02H Reset TM0EN TM0L,R TM0H,R
HEF.1 Hold mode release (HCF.1) EVF.1 IEF.1 Timer interrupt (INT1)
MR0.3 (TM0EN) TM0H,R TM0L,R Reset EVF,#02H 3.Set TM0EN
Figure Organization Timer Timer (TM1) Timer (TM1) also programmable 8-bit binary down counter, shown Figure Timer used counter count external events output arbitrary frequency RE3/TONE pin. input clock source Timer internal sub-frequency/4 (32768/4) clock TM1SR option (bit special register). internal clock selected FOSC/64 FOSC TM1CK option (bit special register) initial reset, Timer clock input FOSC. external clock selected clock source Timer content Timer decreased falling edge RC.0. execute TM1L, TM1H,R instruction will load specified data auto-reload buffer disable down-counting (i.e. TM1EN reset TM1EN contents auto-reload buffer will loaded into down counter start counting reset event flag (EVF.7 When timer decrements FFH, will generate underflow (EVF.7 auto-reloaded with specified data, after which will continue count down. interrupt executed interrupt enable flag been (IEF.7 hold state terminated hold mode release enable flag (HEF.7 specified frequency Timer also output RE3/TONE TONE option bit(bit MR0). Example: Timer clock input then: Desired Timer interval (preset value Desired frequency RE3/TONE output (preset value (Hz) Preset value: Decimal number Timer preset value Publication Release Date: March 1999 Revision
W53322/W53342
TM1H,R TM1L,R
EVF.7 Reset INT7 accept EVF, #80H TM1EN
MR0.2 (TM1EN) 32768/4 clock Fosc/64 Fosc MR1.0 (TM1CK) MR1.1 (TM1SR) Enable
Auto-reload buffer bits 8-Bit Binary Down Counter (Timer
Underflow signal
circuit
Reset
TONE PORTE.3 RE3/TONE output MR0.0 (TONE)
Disable Reset TM1EN
TM1L, TM1H, Reset TM1EN
Figure Organization Timer example, when equals 32768 depending preset value TM1, RE3/TONE will output single tone signal tone frequency range from 16384 relation between tone frequency preset value shown Table Mode Register (MR0 with SR=28H) Mode Register organized 4-bit binary register (MR0.0 MR0.3) descriptions following: (Initial value=0000B) TM0EN TM1EN LCDEN TONE TONE data output PORTE.3. will TONE signal output generated from Timer LCDEN display display TM1EN Timer counting disable Timer counting enable TM0EN=0 Timer counting disable Timer counting enable User read/write set/clear bits. initial reset, 0000B. Mode Register (MR1 with SR=29H) Mode Register organized 4-bit binary register (MR1.0 MR1.3) descriptions following: (Initial value=0000B) WDTCK TM0CK TM1SR TM1CK TM1CK= internal Timer clock rate FOSC. internal Timer1 clock rate FOSC/64. TM1SR=0 Timer with internal clock source (depened TM1CK) Timer with sub-frequency/4 (32768/4) clock source TM0CK= internal Timer clock rate Fosc/4
W53322/W53342
internal Timer0 clock rate FoSC/1024 WDTCK= watchdog timer clock rate Fosc/1K watchdog timer clock rate FoSC/16K User read/write set/clear bits. initial reset, 0000B.
Tone frequency preset value frequency 131.07 138.84 146.28 156.03 165.49 174.30 184.09 195.04 207.39 221.40 234.05 248.24 Tone frequency 261.63 277.18 293.66 311.13 329.63 349.23 369.99 392.00 415.30 440.00 466.16 493.88
preset value frequency 260.06 277.69 292.57 309.13 327.68 372.36 390.09 420.10 443.81 442.81 468.11 496.48 Tone frequency 523.25 554.37 587.33 622.25 659.26 698.46 739.99 783.99 830.61 880.00 932.23 987.77
preset value frequency 528.51 564.96 585.14 630.15 655.36 712.34 744.72 780.19 819.20 862.84 910.22 963.76
130.81 138.59 146.83 155.56 164.81 174.61 185.00 196.00 207.65 220.00 233.08 246.94
Table TONE output with central tone A4(440HZ) Mode Register (MR3 with SR=27H) Mode Register organized 4-bit binary register (MR3.3 MR3.0) descriptions following: (Initial value=0000B) VLCD FsENB VLCD internal supplying voltage generated pump circuit. external supplying voltage. FsENB Enable 32768 crystal Disable 32768 crystal volumn control volumn control Note that port state will force MR3.2 low. means once port state, setting action this invalid.
Interrupts
W533X2 provides five internal interrupt sources (Divider, TM0, SPEECH, MELODY TM1) external interrupt source (port port RD). Vector addresses each interrupts located range program memory (ROM) addresses 004H 020H. flags IEF, PEF, used control interrupts. When hardware corresponding bits have been software, interrupt generated. When interrupt occurs, interrupts inhibited until IEF,#I instruction invoked. Publication Release Date: March 1999 Revision
W53322/W53342
interrupts also disabled executing instruction. When interrupt generated hold mode, hold mode will released momentarily interrupt subroutine will executed. After instruction executed interrupt subroutine, will enter hold mode again. control circuit diagram operation flow chart shown Figure Figure separately. Mode Register (MR2 with SR=26H) Mode Register organized 1-bit only register This INTEN uses disable/enable interrupt function. Instruction uses reset INTEN logic INTEN INTEN INTEN Disable interrupt process. Enable interrupt process which IEF.n means do't care. User read/write set/clear INTEN. initial reset, 0001B. Interrupt Enable Flag Register (IEF with SRP=07H) interrupt enable flag organized 8-bit binary register (IEF.0 IEF.7) that IEFL IEFH registers store IEF.0~IEF.3 IEF.4~IEF.7 separately. These bits used control interrupt conditions. controlled IEF, instruction with immediate data. course, IEFH, IEFL, instructions used with immediate data. When these interrupts accepted, corresponding event flag will reset hardware, other bits unaffected. interrupt subroutine, these interrupts will disable till instruction IEF, executed again. Therefore, enable these interrupts, instructions IEF, must executed again. Otherwise, these interrupts disable executing instruction. descriptions follows: Melody Speech IEFL
IEFH
IEF.0 Interrupt accepted overflow from Divider IEF.1 Interrupt accepted underflow from Timer IEF.2 Interrupt accepted signal change port IEF.3 Interrupt accepted signal change port IEF.4 Reserved IEF.5 Interrupt accepted speech play ending with SPC_busy falling edge IEF.6 Interrupt accepted melody play ending with MLD_busy falling edge IEF.7 Interrupt accepted underflow from Timer
bits read/write set/clear user.
W53322/W53342
Divider overflow IEF, Timer underflow EVF.1 EVF.0
Initial Reset Enable
IEF.0
IEF.1 EVF.2 IEF.2 EVF.3 IEF.3 EVF.5 IEF.5 Interrupt Process Circuit Interrupt Vector Generator
004H 008H 00CH 010H 018H 01CH 020H
Port state change
Port state change
SPC_busy falling edge
MLD_busy falling edge
EVF.6 IEF.6 EVF.7 IEF.7 Initial Reset EVF, instruction Disable
Timer underflow
instruction
Figure Interrupt Event Control Diagram
Publication Release Date: March 1999 Revision
W53322/W53342
Divider,TM0,State change port Speech, melody,
EVF.n
HOLD Mode?
Interrupt Enable?
Interrupt Enable?
IEF.n Flag Set? Reset EVF.n Flag Disable interrupt Execute Interrupt Service Routine
IEF.n Flag Set? Reset EVF.n Flag Disable interrupt Execute Interrupt Service Routine Disable interrupt
HEF.n Flag Set?
(Note)
(Note)
other EVF.m HEF.m
(PC+1)
HOLD
Note corresponding interrupt request signal will reset.
Figure Hold Mode Interrupt Operation Flow Chart
Hold Mode Operation
operations cease hold mode except oscillator timer, divider driver enters hold mode while HOLD instruction executed. hold mode released seven ways which timer underflow, timer underflow, divider overflow, speech playing finished, melody playing finished, port state changed port state changed. Before device enters hold mode, HEF, PEF, flags must define hold mode release conditions. more details, refer instruction sets Figure Event Flag Register (EVF with SRP=05H) event flag organized 8-bit binary EVF0 EVF7 that EVFL EVFH registers store EVF.0 EVF.3
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EVF.4 EVF.7 separately. hardware reset EVFL,#I EVFH,#I instruction occurrence interrupt. descriptions follows: Melody Speech EVFL
EVFH EVF.0 Overflow from Divider occurred. EVF.1 Underflow from Timer occurred. EVF.2 Statel change port occurred. EVF.3 State change port occurred. EVF.4 Reserved
EVF.5 Speech play ending with SPC_busy flag falling edge occurred. EVF.6 Speech play ending with SPC_busy flag falling edge occurred. EVF.7 Underflow from Timer occurred. bits read clear only user. Hold Mode Release Enable Flag Register (HEF with SRP=06H) hold mode release enable flag organized 8-bit binary register (HEF.0 HEF.7) that HEFL HEFH register store HEF.0~HEF.3 HEF.4~ HEF.7 separately. used control hold mode release conditions. controlled HEF, instruction with immediate data HEFH,#I HEFL,#I with immediate data. descriptions follows: HEFL
Melody Speech
HEFH
HEF.0 Overflow from Divider causes hold mode released. HEF.1 Underflow from Timer causes hold mode released. HEF.2 Statel change port causes hold mode released. HEF.3 Statel change port causes hold mode released HEF.5 Speech play ending with SPC_busy flag falling edge causes hold mode released HEF.6 Melody play ending with MLD_busy flag falling edge causes hold mode released HEF.7 Underflow from Timer causes hold mode released. bits read/write set/clear user
Hold mode release Condition Flag Register (HCFL, HCFH with SR=10H hold mode release condition flag organized 8-bit binary register (HCF0 HCF7) that HCFL HCFH registers store HCF.0~HCF.3 HCF.4~HCF.7 separately. hold mode been released, loaded Publication Release Date: March 1999 Revision
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hardware. read MOVA HCFL MOVA HCFH instructions. When bits "1," hold mode will released HOLD instruction invalid. reset EVFL/EVFH,#I (EVF.n When EVF.n HEF.n have been reset, corresponding reset simultaneously hardware. descriptions follows: Melody Speech HCFL
HCFH
HCF.0 Hold mode released overflow from Divider. HCF.1 Hold mode released underflow from Timer HCF.2 Hold mode released state change port HCF.3 Hold mode released state change port HCF.4 reserved HCF.5 Hold mode released speech play ending with SPC_busy falling edge HCF.6 Hold mode released melody play ending with MLD_busy falling edge HCF.7 Hold mode released underflow from Timer bits read only user set/clear chip hardware.
Input/Output Ports
Port consists pins port consists pins RB3. initial reset, input/output ports both input mode. When used output ports, CMOS NMOS open drain output type selected special register. Each port specified input output mode independently special registers. MOVA PORTA MOVA RORTB instructions operate input functions PORTA, PORTB, operate output functions. more details, refer instruction table Figure Port Mode Register (PM0 with SR=32H) port mode register organized 4-bit binary register (PM0.0 PM0.3). used determine structure input/output ports; controlled PM0, instruction. descriptions follows: RD_PH RC_PH RB_NM RA_NM
RA_NM port CMOS output type. port NMOS open drain output type. RB_NM port CMOS output type. port NMOS open drain output type. RC_PH port pull-high resistor disabled. port pull-high resistor enabled. RD_PH port pull-high resistor disabled. port pull-high resistor enabled. read/write set/clear user. initial reset, equal "0000" that port CMOS type input mode port disable pull-high resistor.
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Port Mode Register (PM1, with SR=36H, 37H) port mode registers organized 4-bit binary PM1.0 PM1.3 PM2.0~PM2.3. (PM2) used control input/output mode port (RB) (PM2) controlled PM1, (MOV PM2, instruction. descriptions follows: RA3IN RA2IN RA1IN RA0IN
RA0IN RA1IN RA2IN RA3IN
works output pin; RB.0 works input works output pin; RB.1 works input works output pin; RB.2 works input works output pin; RB.3 works input RB2IN RB1IN RB0IN
RB3IN
RB0IN works output pin; RB.0 works input RB1IN works output pin; RB.1 works input RB2IN works output pin; RB.2 works input RB3IN works output pin; RB.3 works input read/write set/clear user. initial reset, port input mode (PM1, 1111B).
Port Register (PORTA with SR=38H) This register stores current port state PORTA, PORTA instructions. When port input, register read only. Otherwise PORTA written during port output mode. PORTA
Port Register (PORTB with SR=39H) This register stores current port state PORTB, PORTB instructions. When port input, register read only. Otherwise PORTB writen during port output mode. PORTB
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Input/Output
RA_NM (PM0.0) RB_NM (PM0.1)
Output Buffer DATA
Enable
RAnIN RBnIN (PM1.n) (PM2.n)
PORTA, (MOV PORTB, instruction
Enable
MOVA PORTA (MOVA RORTB) instruction
Figure Architecture Input/Output Pins
Input Ports
Port consists pins RC3, port consists pins RD3. Each port port connected pull-up resistor, which controlled port mode register (PM0). When PEF, HEF, corresponding port set, statel change specified pins port will execute hold mode release interrupt subroutine. Port status register (PSR0, PSR1 record signal changing status port PSR0(PSR1) read cleared MOVA PSR0( MOVA PSR0 PSR0 PSR1) instructions. Refer Figure instruction sets more details. Port Enable Flag hold mode (PEFL, PEFH with SR=14H, 15H) port enable flag organized 8-bit binary register (PEF.0 PEF.7) that PEFL PEFH registers store PEF.0~PEF.3 PEF.4~PEF.7 separately. PEFL controls port status, PEFH responsible port status. Before port used release hold mode preform interrupt function, content must first. wirtten "1", function will enable. controlled PEF, instruction with immediate data. Both PEFH,#I PEFH,#I also used with immediate data. descriptions follows: PEFL
PEFH
PEF.0 State change release hold mode perform interrupt PEF.1 State change release hold mode perform interrupt PEF.2 State change release hold mode perform interrupt PEF.3 State change RC31 release hold mode perform interrupt PEF.4 State change release hold mode perform interrupt
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PEF.5 State change release hold mode perform interrupt PEF.6 State change release hold mode perform interrupt PEF.7 State change release hold mode perform interrupt
read/write set/clear user.
Port Status Register (PSR0, PSR1 with 34H, 35H) Port status register organized 4-bit binary PSR0.0 PSR0.3 PSR1.0 PSR1.3. PSR0 PSR1) will have chance PEF.n enable (RDn) input state changed. Then hold mode interupt will occurred. Refer Figure PSR0 (PSR1) read cleared MOVA PSR0 (MOVA PSR0 PSR0(CLR PSR0) instructions. descriptions follows:
PSR0 RC3EG RC2EG RC1EG RC0EG
input signal state changed input signal state isn't changed input signal state changed input signal state isn't changed input signal state changed input signal state isn't changed input signal state changed input signal state isn't changed
read only, clear 4bit simultaneously. initial reset PSR1 0000B
PSR1 RD3EG RD2EG RD1EG RD0EG
input signal state changed input signal state isn't changed input signal state changed input signal state isn't changed input signal state changed input signal state isn't changed input signal state changed input signal state isn't changed read only, clear 4bit simultaneously. initial reset PSR1 0000B Port Register (PORTC with SR=3AH) This register stores port current input state PORTC instructions. PORTC
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Port Register (PORTD with SR=3BH) This register stores port current input state PORTD instructions. PORTD
Output Port
When PORTE, instruction executed, data will output port output TONE from Timer TONE option Port Register (PORTE with SR=3CH) This register stores current Port output state PORTE, instructions. PORTE
DATA PM0.2 (PM0.3) RC.0 (RD.0) Signal change detector PEF.0 (PEF.4) (PSR1.0) PSR0.0
PM0.2 (PM0.3) RC.1 (RD.1) Signal change detector
PEF.1 (PEF.5)
(PSR1.1) PSR0.1
(EVF.3) EVF.2
HEF.2
(HEF.3)
HCF.2 (HCF.3)
IEF.2 (IEF.3)
PM0.2 (PM0.3) RC.2 (RD.2) Signal change detector
PEF.2 (PEF.6)
(PSR1.2) PSR0.2
(INT3) EVFL, #0100B (CLR EVFL, #1000B)
Reset
PM0.2 (PM0.3) PEF.3 (PEF.7) Signal change detector (PSR1.3) PSR0.3
RC.3 (RD.3)
Reset PEF, PSR0 (CLR PSR1)
Figure Architecture Input Ports (RD)
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Reset Function
W533X2 reset either power-on reset active pulse. initial reset state internal special register Input/Output shown Table Program Counter (PC) Input/output ports Output port ports output type ports pull-high resistors System Clock Input Timer input clock Timer input clock Input clock watchdog timer display Bias Duty Internal Pump Circuit Pump Voltage register register (INTEN flag) PM1,PM2 register Others Registers Table Default value initial Reset 0000B Input mode 0000B CMOS type Disable (32768HZ) FOSC/4 FOSC FOSC/1024 bias 1/32 duty Enable Triple pump 0001B 0001B 1111B 0000B
PART SPEECH MELODY FUNCTION
Both speech melody same clock source from ROSC these functions played same time. When speech melody playing, ROSC clock enable, otherwise clock disable power saving. Either speech synthesiaer melody sound tone output PWM1 PWM2 direct driving speaker. Speech coding select whether output will active. LED1 also active depended melody output Publication Release Date: March 1999 Revision
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volume. FLAG0 Register (FLAG0 with SR=22H) FLAG0 organized 4-bit register used control speech melody synthesizers. FLAG0.1~0 read/write set/clear user., FLAG0.3 FLAG0.2 set/clear chip hardware. initial reset, FLAG0 0000B. description following.
FLAG0
MLD_busy SPC_busy MLD_play SPC_play
SPC_paly Speech play disable Speech play enable. MLD_paly Melody play disbale. Melody play enable. SPC_busy Speech play finished Speech play processing MLD_busy Melody play finished. melody play processing
SPEECH Function
There 1.4M bits dedicated speech speech synthesizer, sepatated sections different voice maximun WINBOND ADPCM power speech coding system. needs write play section number SPCH, SPCL SPC_play option (bit FLAG0 special register) play speech voice Then SPC_busy (bit FLAG0) will changed from high keeps high till speech play ending. interrupt flag hold mode flag IEF.5, HEF.5, HCF.5 set, interrupt hold mode release will processed while SPC_busy falling edge occurred. circuit structure shown Figure SPC_play again, after section number been finished parallel serial previous SPC_play edge. There minimun instruction delay continuous SPC_play rising shown Figure output with frequency used drive external during speech playing. SPCH, SPCL will latched during SPC_play risng edge. speech synthesizer disabled when MLD_busy (bit FLAG0) melody synthesizer when SPC_busy SPC_play activate speech synthesizer. speech synthesizer receives rising edge SPC_play then plays voice section pointed SPC.7~SPC.0 pull voltage level SPC_busy logic SPC_busy cleared hardware when: speech synthesizer finishes tasks executes command; 2.the speech synthesizer receives rising edge SPC_play again content SPC.7~SPC.0 00H, which forces speech synthesizer into STANDBY mode whether tasks finished not.
Parallel serial Interface Section Num.
HEF.5 Hold mode release (HCF.5) IEF.5 EVF.5 Speech interrupt (INT5)
528X
Register
SPC_play (FLAG0.0 bit) rising edge
Tcyc
Reset EVFH,#0010B 3.MOV FLAG0,#0001B
SPCH,
SPCL,
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Figure Speech Circuit Diagram Speech Section Register (SPCL, SPCH with SR=1E, SPCH SPCL registers named SPC.7 ~SPC.0 define speech section that speech synthesizer required play. SPCH represents high nibble SPC.7 SPC.4 while SPCL represents nibble SPC.3 SPC.0 When speech synthesizer actived, plays voice section pointed SPC.7~SPC.0 with maximun sections (01h FFh). content register speech-play command becomes speech-stop command. SPC.7 SPC.6 SPC.5 SPC.4 SPC.3 SPC.2 SPC.1 SPCL SPC.0
SPCH
Melody Function
There notes bits note) dedicated dual tone melody code separated different scores maximun. controls dual tone melody same methodology speech playing. melody scores write MLDH, MLDL register. Then MLD_play enable high play melody, MLD_busy will changed from high keeps high till melody play ending. interrupt flag hold mode flag IEF.6, HEF.6, HCF.6 set, interrupt hold mode release will processed while MLD_busy falling edge occurred. MLDH, MLDL will latched during MLD_play User select melody play mode (bit MLDH). one-shot trigger mode (OSB=0) melody synthesizer receives rising edge MLD_play then plays score pointed MLD5~MLD.0 pull voltage level MLD_busy logic When melody synthesizer finishes tasks receives rising edge MLD_play with score number melody synthesizer enters standby mode MLD_busy pulled logic level-trig mode( OSB=1) melody synthesizer plays pointed score when MLD_busy pointed score repeatedly played MLD_busy pulled high until MLD_play cleared user.
enable
(MLED1,MLED0)
Score Address
HEF.6 Hold mode release (HCF.6) IEF.6 EVF.6 Speech interrupt (INT6)
MLD_play (FLAG0.1 bit)
Register
Melody
Reset EVFH,#0100B 3.MOV FLAG0,#0010B
MLDH,
MLDL,#I
Figure Melody Circuit Diagram Melody scores Register (MLDL, MLDH with SR=1CH, 1DH) register organized 4-bit registers, MLDH MLDL. MLDH represents high nibble MLED1, MLED0 OSB, MLD.4 while MLDL represents nibble MLD.3 MLD.0. MLD.4 MLD.0 performs 5-bit pointer scores, MLED1~0 control LED1 active type during melody playing. When melody synthesizer actived, plays score section pointed MLD.4 MLD.0 From score score 1FH, scores Publication Release Date: March 1999 Revision
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pointed register. When melody synthesizer one-shot trigger mode MLD.4 MLD.0 00H, melody-play command becomes melody-stop command. MLED1 MLED0 MLD.4 MLD.3 MLD.2 MLD.1 MLD.0 MLDH MLDL
MLD.4 MLD.0 melody score number with scores maximun. OSB=0 Melody play mode shot trgger Melody play mode level trigger MLED1~0: Selct LED1 output active type while melody playing. LED1 disable during melody playing LED1 will active during melody volume high than level LED1 will active during melody volume high than middle level LED1 will active during melody volume high than high level
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PART FUNCTION
W53322/W53342 directly drive panel with common output pins 48/64 segment output pins total 48/64 dots frame updating rate registers LCDM1 LCDM2 select different operating type such duty cycle, bias ratio, maximun pump voltage, internal shunt resistor enable pump voltage circuit instruction LCDM1, LCDM1, (where thelow address LCDM1, ACC. power saving issue, LCDEN (bit register) select panel controlled LCDON LCDOFF instructions. LCDON instruction turns display (even HOLD mode), LCDOFF instruction turns display off. initial reset, LCDM1 0000B that operating condition 1/32 duty, bias, triple pump voltage with internal shunt resistor, segments lit. When initial reset state ends, display turned automatically. circuit architecture shown Figure Many different application condition shown from Figure
Clock Generator Data
Instruction
LCDM1 Register
VDD2 VDD3
BIAS7B(LCDM1.2)
PUMP Voltage
PMPV3B (LCDM1.1) VLCDEXT (LCDM2.3) COM32B (LCDM1.3)
Data 32/48/64 bits)
LCDEN(MR0.1) INTSRB (LCDM1.0)
FLCD Shunt Resistor Commom Driver Segment Driver
COM0
SEG0 31/47/63
Figure Driver Circuit Diagram
pattern
Corresponding 48/64 drive output pins, there 384/512 data from 200H 37FH/3FFH named LCDR000H LCDR17FH/LCDR1FFH. fact, they also general purpose RAM, operatin instruction same area 00H~1FFH instructions such LCDR,#I, LCDR LCDR,WR LCDR, also available control data because LCDR will added 1FFH cross assembler automatically. When value data written turned Otherwise turnned data written "0". contents data (LCDR) sent SEG0~SEG47/SEG63 pins direct memory access. relation between data segment/common pins shown Table DATA LCDR000 RAM200 LCDR001 RAM201 LCDR002 RAM202 LCDR003 RAM203 OUTPUT BIT3 COM3 COM7 COM11 COM15 COM2 COM6 COM10 COM14 COM1 COM5 COM9 COM13 COM0 COM4 COM8 COM12
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LCDR004 RAM204 LCDR005 RAM205 LCDR006 RAM206 LCDR007 RAM207 LCDR008 RAM208 LCDR009 RAM209 LCDR00A RAM20A LCDR00B RAM20B LCDR00C RAM20C LCDR00D RAM20D LCDR00E RAM20E LCDR00F RAM20F LCDR1F8 RAM3F8 LCDR1F9 RAM3F9 LCDR1FA RAM3FA LCDR1FB RAM3FB LCDR1FC RAM3FC LCDR1FD RAM3FD LCDR1FE RAM3FE LCDR1FF RAM3FF
SEG0
COM19 COM23 COM27 COM31 COM3 COM7 COM11 COM15
COM18 COM22 COM26 COM30 COM2 COM6 COM10 COM14 COM18 COM22 COM26 COM30 COM2 COM6 COM10 COM14 COM18 COM22 COM26 COM30
COM17 COM21 COM25 COM29 COM1 COM5 COM9 COM13 COM17 COM21 COM25 COM29 COM1 COM5 COM9 COM13 COM17 COM21 COM25 COM29
COM16 COM20 COM24 COM28 COM0 COM4 COM8 COM12 COM16 COM20 COM24 COM28 COM0 COM4 COM8 COM12 COM16 COM20 COM24 COM28
SEG1
COM19 COM23 COM27 COM31
COM3 COM7 COM11 COM15
SEG63
COM19 COM23 COM27 COM31
Table5. W53342 mapping segment common output pins
Mode Register (LCDM1 with SR=2AH)
LCDM1 register organized LCDM1.0~LCDM1.3 that duty cycle, bias ratio pump voltage, internal shunt resistor selected instruction LCDM1, LCDM1, (where thelow address LCDM1, ACC. COM32B defines duty cycle BIAS7B controls bias ratio match characteristic panel. PMPV3B used choose COM/SEG output maximun voltage either doubler tripler when build-in voltage pump circuit enable. voltage tripler should enabled operating voltage, voltage doubler shoule enabled 4.5V operating voltage. INTSRB used select internal shunt reistoe V2~V6 output power. Please refer following application circuits. output waveforms five driving modes shown Figure
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Figure PMPV3B INTSRB
LCDM1 COM32B BIAS7B
INTSRB Internal shunt resistor available between V2~V6 External shunt resistor needed between ~V6. PMPV3B Triple pump voltage available (suggeset while VDD=3v) Double pump voltage available (suggest while VDD=4.5v) BIAS7B bias available suggeset common) bias available (suggest common) COM32B 1/32 duty, COM0~COM31 output available 1/16 duty, COM0~ COM15 output available write only. initial reset, LCDM1 0000B
frame rate divider (LDIV with SR=12H)
LDIV register used define frame rate driver. relationship between frame rate driver LDIV value FLCD 32768 [(LDIV+1)*64] LDIV value (default value), frame rate driver 64Hz. 1/16 duty while LCDM1 3=0), please LDIV, #1111B frame rate. Otherwise fame rate will 128HZ. LDIV LDIV.3 LDIV.2 LDIV.1 LDIV.0
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VDD3 VDD2
bias common (1/5 bias common) Triple pump voltage VDD=3 volt Enable internal pump voltage Enable internal shunt resistor C1=C2=C3=0.1uF
Figure Triple pump voltage internal shunt resistor
VDD3 VDD2
4.5V
bias common (1/5 bias common) Double pump voltage VDD=4.5 volt Enable internal pump voltage Enable internal shunt resistor C1=C3=0.1uF
Figure Double pump voltage internal shunt resistor
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VDD3 VDD2
bias common Triple pimp voltage VDD=3 volt Enable internal pump voltage Disable internal shunt resistor C1=C2=C3=0.1uF R=10K ~20K
Figure bias, Triple pump voltage external shunt resistor
VDD3 VDD2
bias common Triple pump voltage VDD=3 volt Enable internal pump voltage Disable internal V2~V6 shunt resistor C1=C2=C3=0.1uF R=10K ~20K
Figure bias, Triple pump voltage external shunt resistor
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External power source
(VLCD<3*VDD) VDD3 VDD2
bias common (1/5 bias common) External power VDD=3 volt Disable internal pump voltage Enable internal V2~V6 shunt resistor
Figure External voltage external shunt resistor VDD=3v
External power source
(VLCD<2*VDD) VDD3 VDD2
=4.5V
bias common (1/5 bias common) External power VDD=3 volt Disable internal pump voltage Enable internal V2~V6 shunt resistor
Figure External voltage external shunt resistor VDD=4.5v
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External power source
(VLCD<3*VDD) VDD3 VDD2
bias common External power VDD=3 volt Disable internal pump voltage Disable internal V2~V6 shunt resistor
Figure bias, External voltage external shunt resistor
External power source
(VLCD<3*VDD) VDD3 VDD2
bias common External power VDD=3 volt Disable internal pump voltage Disable internal V2~V6 shunt resistor
Figure bias, External voltage external shunt resistor
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Figure W53342 Common/Segment driving pattern
Accoding Figure pattern assignment, common, segment output waveform Figure bias, Figure bias.
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COM0
COM1
COM31
SEG0 (All OFF)
SEG1 (All
SEG10 (dot a,c,e
negative frame
postive frame frame rate
C31-S10 (dot
Figure bias, 1/32 duty driving waveform
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COM0
COM1
COM15
negative frame frame rate
positive frame frame rate
SEG0 (All OFF)
SEG1 (All
SEG10 (dot a,c,e
C0-S10 (dot
VLCD
-VLCD
Figure bias, 1/16 duty driving waveform
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ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage Ground Potential Applied Input/Output Voltage Power Dissipation Ambient Operating Temperature Storage Temperature VDD3 Input Voltage RATING -0.3 +7.0 -0.3 +7.0 +150 UNIT
Note: Exposure conditions beyond those listed under Absolute Maximum Ratings adversely affect life reliability device.
CHARACTERISTICS
(VDD-VSS 3.0V, MHz, 32.768 KHz, size 0.5mmm*0.5mm unless otherwise specified) PARAMETER SYM. CONDITIONS MIN. TYP. MAX. UNIT Voltage Current IOP1 Dual clock with crystal Load) Dual clock with type Single Clock, Hold Mode Current Iop2 Dual clock with crystal Load, OFF) Dual clock with type Single clock Stop Mode Current Iop3 Input Voltage 0.3*VDD Input High Voltage Port Output VABL Voltage Port Output High VABH -2.0 Voltage Port Sink Current 0.4V Port Source Current 2.4V Pull-up Resistor Port 1000 Pull-up Resistor RRES LED1/LED2 Sink Current ILED VO=1 volt PWM1/2 Source Current ISPH 2.4V CUR1~0=00 2.4V CUR1~0=01 2.4V CUR1~0=10 2.4V CUR1~0=11 -120
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PWM1/2 Sink Current
ISPL
Supply Current COM/SEG Resistor PARAMETER VDD2 output voltage
ILCD SYM. VDOB
VDD3 output Voltage
VTRI
VDD3 Input Voltage
VLCD
0.6V CUR1~0=00 0.6V CUR1~0=01 0.6V CUR1~0=10 0.6V CUR1~0=11 size 0.5mm*0.5mmm, Seg. CONDITIONS VLCDEXT=0 PMPV3B=0 VLCDEXT=0 PMPV3B=1 VLCDEXT=0 PMPV3B=0 VLCDEXT=0 PMPV3B=1 VLCDEXT=1
TYP.
MAX.
UNIT
MIN.
CHARATERISTICS
(VDD-VSS 3.0V, MHz, 32.768 KHz, unless otherwise specified) PARAMETER SYM. CONDITIONS MIN. TYP. MAX. UNIT Sub-clock Frequency Crystal type 32768 Main-clock Frequency type/Crystal type 4190 Frequency FOSC SCR.0=1 32768 SCR.0=0 4190 Instruction Cycle Time TCYC machine cycle 4/FOS Reset Active Width FOSC 32.768 Interrupt Active Width Main clock frequency
TIAW
FRXI
FOSC 32.768 RXIN =2.4 RXIN =1.2 RXIN =910 RXIN =160 f(3V) f(2.4V) f(3V) ROSC =1.2M f(3V) f(2.4V) f(3V) LDIV 0111b &1/32 duty LDIV= 1111b 1/16 duty
400K 800K 3.23
Frequency Deviation main-clock FRXIN =1MHz ROSC Frequency Frequency Deviation FROSC 3MHz Frame frequency
FROS
FLCD
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TYPICAL APPLICATION CIRCUIT
32com*64seg panel
COM0~31 SEG0~63 LED1 LED2
PWM1
VDDP
RC0~3 RD0~3 RA0~3 RB0~3 RE0~3 RESETB Battery
0.1uF
PWM2
VDD2 VDD3
VDDP
10uF
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0.1uF
1.2M
30pF
ROSC
X32IN 32.768kHz X32O VSS1 VSS2
0.1uF 0.1uF 0.1uF
30pF
0.1uF
Note 1.JP1 used select double triple pump. 2.R5=0 double pump active. 3.R3 optional. 4.LCD duty bias programmed registers
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INSTRUCTION TABLE
SYMBOL DESCRIPTION
SRP: ACC: ACC.n: R.n: RL.n: @P.n: LUPC: @LUPC: Working special register special register pair Accumulator Accumulator Memory (RAM) addressed direct address memory (RAM) addressed direct address Lower-half memory (RAM) addressed direct address lower-half memory (RAM) addressed direct address pointer RP0/RP1 Memory (RAM) addressed pointer RP0/RP1 Memory (RAM) addressed pointer RP0/RP1 pointer, look-up-table Memory (ROM) addressed pointer LUPC Constant parameter Branch jump address Carry Flag Zero Flag Program Counter
equal Exclusive Transfer direction, result
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COMPLETE INSTRUCTION TABLE
MNEMONIC FUNCTION FLAG AFFECTED CYCLE
Arithmetic Logic Operations
ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDCR ADDCR ADDCR ADDCR ADDCR ADDCR ADDR ADDR ADDR ADDR ADDR ADDR @RP0, @RP1, @RP0, @RP1, ACC, @RP0, @RP1, @RP0, @RP1, @RP0, @RP1, @RP0, @RP1, ACC, @RP0, @RP1, @RP0, @RP1, @RP0 @RP1 @RP0 @RP1 ACC, ACC, @RP0 @RP0 ACC, @RP1 @RP1 ACC, ACC, @RP0 @RP0 ACC, @RP1 @RP1 @RP0 @RP1 @RP0 @RP1 ACC, ACC, @RP0 @RP0 ACC, @RP1 @RP1 ACC, ACC, @RP0 @RP0 ACC, @RP1 @RP1
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ADDU ADDU ADDU ADDU ADDU ADDU ADDU ADDUR ADDUR ADDUR ADDUR ADDUR ADDUR SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBBR SUBBR SUBBR SUBBR SUBBR SUBBR
@RP0, @RP1, @RP0, @RP1, ACC, @RP0, @RP1, @RP0, @RP1, @RP0, @RP1, @RP0, @RP1, ACC, @RP0, @RP1, @RP0, @RP1, @RP0, @RP1, @RP0, @RP1,
@RP0 @RP1 @RP0 @RP1 ACC, ACC, @RP0 @RP0 ACC, @RP1 @RP1 ACC, ACC, @RP0 @RP0 ACC, @RP1 @RP1 @RP0 @RP1 @RP0 @RP1 ACC, ACC, @RP0 @RP0 ACC, @RP1 @RP1 ACC, ACC, @RP0 @RP0 ACC, @RP1 @RP1 @RP0 @RP1 @RP0 @RP1
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SUBR SUBR SUBR SUBR SUBR SUBR ANLR ANLR ANLR ANLR ANLR ANLR XRLR XRLR XRLR XRLR
ACC, @RP0, @RP1, @RP0, @RP1, @RP0, @RP1, @RP0, @RP1, ACC, @RP0, @RP1, @RP0, @RP1, @RP0, @RP1, @RP0, @RP1, ACC, @RP0, @RP1,
ACC, ACC, @RP0 @RP0 ACC, @RP1 @RP1 ACC, ACC, @RP0 @RP0 ACC, @RP1 @RP1 @RP0 @RP1 @RP0 @RP1 ACC, ACC, @RP0 @RP0 ACC, @RP1 @RP1 ACC, ACC, @RP0 @RP0 ACC, @RP1 @RP1 @RP0 @RP1 @RP0 @RP1 ACC, ACC, @RP0 @RP0 ACC, @RP1 @RP1 ACC,
Publication Release Date: March 1999 Revision
W53322/W53342
XRLR XRLR ORLR ORLR ORLR ORLR ORLR ORLR SKB0 SKB1 SKB2 SKB3 SKB0 SKB1 SKB2 SKB3 SKB0 SKB1 SKB2 SKB3 SKB0 SKB1 SKB2 SKB3 SKNB0 @RP0 @RP0 @RP0 @RP0 @RP1 @RP1 @RP1 @RP1
@RP0, @RP1, @RP0, @RP1, @RP0, @RP1, ACC, @RP0, @RP1, @RP0, @RP1,
ACC, @RP0 @RP0 ACC, @RP1 @RP1 @RP0 @RP1 @RP0 @RP1 ACC, ACC, @RP0 @RP0 ACC, @RP1 @RP1 ACC, ACC, @RP0 @RP0 ACC, @RP1 @RP1 @RP0.0 @RP0.1 @RP0.2 @RP0.3 @RP1.0 @RP1.1 @RP1.2 @RP1.3 ACC.0 ACC.1 ACC.2 ACC.3
W53322/W53342
SKNB1 SKNB2 SKNB3 SKNB0 SKNB1 SKNB2 SKNB3 SKNB0 SKNB1 SKNB2 SKNB3 SKNB0 SKNB1 SKNB2 SKNB3 SHLC
@RP0 @RP0 @RP0 @RP0 @RP1 @RP1 @RP1 @RP1
@RP0.0 @RP0.1 @RP0.2 @RP0.3 @RP1.0 @RP1.1 @RP1.2 @RP1.3 ACC.0 ACC.1 ACC.2 ACC.3 ACC.n, R.n-1; ACC.0, ACC.n, R.n+1; ACC.3, ACC.n, R.n-1; R.3; ACC.0, ACC.n, R.n+1; R.0; ACC.3, ACC.n, @RP0.n @RP0.n-1; ACC.0, @RP0.0 @RP0.3 ACC.n, @RP0.n @RP0.n+1; ACC.3, @RP0.3 @RP0.0 ACC.n, @RP0.n @RP0.n-1; @RP0.3; ACC.0, @RP0.0 ACC.n, @RP0.n @RP0.n+1; @RP0.0; ACC.3, @RP0.3
SHRC
SHLC
@RP0
SHRC
@RP0
@RP0
@RP0
Publication Release Date: March 1999 Revision
W53322/W53342
SHLC
@RP1
ACC.n, @RP1.n @RP1.n-1; ACC.0, @RP1.0 @RP1.3 ACC.n, @RP1.n @RP1.n+1; ACC.3, @RP1.3 @RP1.0 ACC.n, @RP1.n @RP1.n-1; @RP1.3; ACC.0, @RP1.0 ACC.n, @RP1.n @RP1.n+1; @RP1.0; ACC.3, @RP1.3 ACC.n (ACC.n-1); ACC.0 ACC.3 ACC.n (ACC.n+1); ACC.3 ACC.0 ACC.n (ACC.n-1); ACC.0 ACC.3 ACC.n (ACC.n+1); ACC.3 ACC.0 ACC, ACC, ACC, @RP0 @RP0 ACC, @RP0 @RP0 ACC, @RP1 @RP1 ACC, @RP1 @RP1 ACC, ACC, ACC, @RP0 @RP0 ACC, @RP0 @RP0 ACC, @RP1 @RP1
SHRC
@RP1
@RP1
@RP1
SHLC SHRC
DSKZ DSKNZ DSKZ DSKNZ DSKZ DSKNZ DSKZ DSKNZ
@RP0 @RP0 @RP1 @RP1 @RP0 @RP0 @RP1
W53322/W53342
@RP1
ACC, @RP1 @RP1
Branch
CALL JNB0 JNB1 JNB2 JNB3 STACK PC+1; PC13 PC13 PC13 PC13 PC13 PC13 PC13 ACC.0 PC13 ACC.1 PC13 ACC.2="1" PC13 ACC.3 PC13 ACC.0 PC13 ACC.1 PC13 ACC.2="0" PC13 ACC.3
SET/CLR Special Registers
HEFH, HEFH.0 HEFH.1 HEFH.2 HEFH.3 HEFL.0 HEFL.1 HEFL.2 HEFL.3 IEFH.0 IEFH.1 IEFH.2 IEFH.3
HEFL,
IEFH,
Publication Release Date: March 1999 Revision
W53322/W53342
IEFL,
IEFL.0 IEFL.1 IEFL.2 IEFL.3 PEFH.0 PEFH.1 PEFH.2 PEFH.3 PEFL.0 PEFL.1 PEFL.2 PEFL.3 carry flag
PEFH,
PEFL,
FLAG0,
FLAG0.3 FLAG0.2 FLAG0.1 FLAG0.0 MR0.0 MR0.1 MR0.2 MR0.3 MR2.0 MR2.1 MR2.2 MR2.3 SCR.0 SCR.1 SCR.2 SCR.3 PM0.0 PM0.1 PM0.2 PM0.3 PM2.0 PM2.1 PM2.2 PM2.3 PM1.0 PM1.1 PM1.2 PM1.3 EVFH.0 EVFH.1 EVFH.2 EVFH.3
MR0,
MR2,
SCR,
PM0,
PM2,
PM1,
EVFH,
W53322/W53342
EVFL,
EVFL.0 EVFL.1 EVFL.2 EVFL.3 HEFH.0 HEFH.1 HEFH.2 HEFH.3 HEFL.0 HEFL.1 HEFL.2 HEFL.3 IEFH.0 IEFH.1 IEFH.2 IEFH.3 IEFL.0 IEFL.1 IEFL.2 IEFL.3 PEFH.0 PEFH.1 PEFH.2 PEFH.3 PEFL.0 PEFL.1 PEFL.2 PEFL.3 clear carry flag
HEFH,
HEFL,
IEFH,
IEFL,
PEFH,
PEFL,
FLAG0,
FLAG0.3 FLAG0.2 cleared FLAG0.1= FLAG0.0 FLAG1.0 don't care, FLAG1.1 FLAG1.2 FLAG1.3 don't care, MR0.0 MR0.1 MR0.2 MR0.3 MR2.0 MR2.1 MR2.2 MR2.3
FLAG1,
MR0,
MR2,
Publication Release Date: March 1999 Revision
W53322/W53342
SCR,
SCR.0 SCR.1 SCR.2 SCR.3 PSR1.0 PSR1.1 PSR1.2 PSR1.3 PSR0.0 PSR0.1 PSR0.2 PSR0.3 PM0.0 PM0.1 PM0.2 PM0.3 PM2.0 PM2.1 PM2.2 PM2.3 PM1.0 PM1.1 PM1.2 PM1.3
PSR1
PSR0
PM0,
PM2,
PM1,
Data Move
MOVA MOVA MOVA MOVA MOVA MOVA @RP0, @RP0, @RP1, @RP1, ACC, @RP0 @RP1 ACC, ACC, ACC, @RP0 ACC, @RP0 @RP1 ACC, @RP1 @RP0 @RP1
W53322/W53342
MOVA MOVA MOVA MOVA MOVA MOVA MOVA MOVA MOVA MOVA LUPC
@RP0, @RP1, @RP0 @RP1 @RP0, @RP1, @RP1, @RP0 @RP0, @RP1 @RP1, @RP0 @RP0, @RP1 ACC, @LUPC @RP0, @LUPC @RP1, @LUPC @RP0++ @RP1++ @RP0++, @RP1++, @RP0++ @RP1++ @RP0++, @RP1++,
@RP0 @RP1 ACC, @RP0 ACC, @RP1 ACC, @RP0 ACC, @RP1 @RP1 @RP0 @RP0 @RP1 ACC, @RP1 @RP0 ACC, @RP0 @RP1 @LUPC @RP0 @LUPC @RP1 @LUPC @RP0 @RP1 @RP0 @RP1 ACC, @RP0 ACC, @RP1 ACC, @RP0 ACC, @RP1 LUPC LUPC
Publication Release Date: March 1999 Revision
W53322/W53342
@RP1++, @RP0++
@RP1 @RP0 RP0+1 RP1+1 @RP0 @RP1 RP0+1 RP1+1 ACC, @RP1 @RP0 RP0+1 RP1+1 ACC, @RP0 @RP1 RP0+1 RP1+1 @LUPC LUPC LUPC @RP0 @LUPC LUPC LUPC @RP1 @LUPC LUPC LUPC TM0H TM0H ACC, TM0H TM0H TM0L TM0L ACC, TM0L TM0L TM1H TM1H ACC, TM1H TM1H TM1L TM1L ACC, TM1L TM1L
@RP0++, @RP1++
MOVA @RP1++, @RP0++
MOVA @RP0++, @RP1++
@LUPC++ @RP0++, @LUPC++
@RP1++, @LUPC++
Special Register Write MOVA MOVA MOVA MOVA TM0H, TM0H, TM0H, TM0H, TM0L TM0L TM0L TM0L TM1H, TM1H, TM1H, TM1H, TM1L, TM1L, TM1L, TM1L,
W53322/W53342
MOVA MOVA MOVA MOVA MOVA MOVA MOVA MOVA
HEFH, HEFH, HEFH, HEFH, HEFL, HEFL, HEFL, HEFL, IEFH, IEFH, IEFH, IEFH, IEFL, IEFL, IEFL, IEFL, LDIV, LDIV, LDIV, LDIV, PEFH, PEFH, PEFH, PEFH, PEFL, PEFL, PEFL, PEFL, RP0M, RP0M, RP0M,
HEFH HEFH ACC, HEFH HEFH HEFL HEFL ACC, HEFL HEFL IEFH IEFH ACC, IEFH IEFH IEFL IEFL ACC, IEFL IEFL LDIV LDIV ACC, LDIV LDIV PEFH PEFH ACC, PEFH PEFH PEFL PEFL ACC, PEFL PEFL RP0M RP0M ACC, RP0M
Publication Release Date: March 1999 Revision
W53322/W53342
MOVA MOVA MOVA MOVA MOVA MOVA MOVA MOVA
RP0M, RP0L, RP0L, RP0L, RP0L, RP1M, RP1M, RP1M, RP1M, RP1L, RP1L, RP1L, RP1L, RP1H, RP1H, RP1H, RP1H, RP0H, RP0H, RP0H, RP0H, MLDH, MLDH, MLDH, MLDH, MLDL, MLDL, MLDL, MLDL, SPCH, SPCH, SPCH,
RP0M RP0L RP0L ACC, RP0L RP0L RP1M RP1M ACC, RP1M RP1M RP1L RP1L ACC, RP1L RP1L RP1H RP1H ACC, RP1H RP1H RP0H RP0H ACC, RP0H RP0H MLDH MLDH ACC, MLDH MLDH MLDL MLDL ACC, MLDL MLDL SPCH SPCH ACC, SPCH
W53322/W53342
MOVA
SPCH, SPCL, SPCL, SPCL, SPCL, FLAG0,
SPCH SPCL SPCL ACC, SPCL SPCL FLAG0 ACC, FLAG0.3 FLAG0.2 write-inhibited FLAG0 FLAG0.3 FLAG0.2 write-inhibited ACC, FLAG0 FLAG0.3 FLAG0.2 write-inhibited FLAG0 FLAG0.3 FLAG0.2 write-inhibited ACC, ACC, ACC, ACC, ACC,
FLAG0,
MOVA
FLAG0,
FLAG0,
MOVA MOVA MOVA MOVA MOVA
MR0, MR0, MR0, MR0, MR1, MR1, MR1, MR1, MR2, MR2, MR2, MR2, MR3, MR3, MR3, MR3, SCR, SCR, SCR,
Publication Release Date: March 1999 Revision
W53322/W53342
MOVA MOVA MOVA MOVA MOVA MOVA MOVA MOVA
SCR, LCDM1, LCDM1, LCDM1, LCDM1, LCDM2, LCDM2, LCDM2, LCDM2, LUP1, LUP1, LUP1, LUP1, LUP0, LUP0, LUP0, LUP0, LUP3, LUP3, LUP3, LUP3, LUP2, LUP2, LUP2, LUP2, WRPAGE, WRPAGE, WRPAGE, WRPAGE, RAMPAGE, RAMPAGE, RAMPAGE,
LCDM1 LCDM1 ACC, LCDM1 LCDM1 LCDM2 LCDM2 ACC, LCDM2 LCDM2 LUP1 LUP1 ACC, LUP1 LUP1 LUP0 LUP0 ACC, LUP0 LUP0 LUP3 LUP3 ACC, LUP3 LUP3 LUP2 LUP2 ACC, LUP2 LUP2 WRPAGE WRPAGE ACC, WRPAGE WRPAGE RAMPAGE RAMPAGE ACC, RAMPAGE
W53322/W53342
MOVA MOVA MOVA MOVA MOVA MOVA
RAMPAGE, PM0, PM0, PM0, PM0, PM2, PM2, PM2, PM2, PM1, PM1, PM1, PM1, PORTB, PORTB, PORTB, PORTB, PORTA, PORTA, PORTA, PORTA, PORTE, PORTE, PORTE, PORTE,
RAMPAGE ACC, ACC, ACC, PORTB PORTB ACC, PORTB PORTB PORTA PORTA ACC, PORTA PORTA PORTE PORTE ACC, PORTE PORTE
Special Register Read
MOVA MOVA TMC1H TMC1H TMC1L TMC1L EVFH TMC1H ACC, TMC1H TMC1L ACC, TMC1L EVFH
Publication Release Date: March 1999 Revision
W53322/W53342
MOVA MOVA MOVA MOVA MOVA MOVA MOVA MOVA MOVA MOVA MOVA MOVA MOVA MOVA MOVA MOVA
EVFH EVFL EVFL HEFH HEFH HEFL HEFL IEFH IEFH IEFL IEFL HCFH HCFH HCFL HCFL PEFH PEFH PEFL PEFL RP0M RP0M RP0L RP0L RP1M RP1M RP1L RP1L RP1H RP1H RP0H RP0H
ACC, EVFH EVFL ACC, EVFL HEFH ACC, HEFH HEFL ACC, HEFL IEFH ACC, IEFH IEFL ACC, IEFL HCFH ACC, HCFH HCFL ACC, HCFL PEFH ACC, PEFH PEFL ACC, PEFL RP0M ACC, RP0M RP0L ACC, RP0L RP1M ACC, RP1M RP1L ACC, RP1L RP1H ACC, RP1H RP0H ACC, RP0H
W53322/W53342
MOVA MOVA MOVA MOVA MOVA MOVA MOVA MOVA MOVA MOVA MOVA MOVA MOVA MOVA MOVA MOVA
FLAG0 FLAG0 LUP0 LUP0 LUP1 LUP1 LUP2 LUP2 LUP3 LUP3 WRPAGE WRPAGE RAMPAGE RAMPAGE PSR1 PSR1 PSR0 PSR0
ACC, FLAG0 ACC, FLAG0 ACC, ACC, ACC, LUP0 ACC, LUP0 LUP1 ACC, LUP1 LUP2 ACC, LUP2 LUP3 ACC, LUP3 ACC, WRPAGE ACC, WRPAGE RAMPAGE ACC, RAMPAGE ACC, PSR1 ACC, PSR1 PSR0 ACC, PSR0 ACC,
Publication Release Date: March 1999 Revision
W53322/W53342
MOVA MOVA MOVA MOVA MOVA
PORTB PORTB PORTA PORTA PORTD PORTD PORTC PORTC
ACC, PORTB ACC, PORTB PORTA ACC, PORTA PORTD ACC, PORTD PORTC ACC, PORTC
Special Register Pair Write
HEF, IEF,
Others
HOLD opperation Enter hold mode STACK
Pseudo Instruction
LCDON LCDOFF MR2.0 MR2.0 MR0.1 MR0.1 FLAG1.1 FLAG1.2
W53322/W53342
Headquarters
Creation III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5792697 http://www.winbond.com.tw/ Voice Fax-on-demand: 886-2-7197006
Winbond Electronics (H.K.) Ltd.
803, World Trade Square, Tower Rd., Kwun Tong, Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2730 Orchard Parkway, Jose, 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668
Taipei Office
11F, 115, Sec. Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502
Note: data specifications subject change without notice.
Publication Release Date: March 1999 Revision

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