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Quad Output Spread Spectrum Clock Generator MK1725 generates high


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MK1725
Quad Output Spread Spectrum Clock Generator
MK1725 generates high-quality, high-frequency spread spectrum clock outputs. designed replace spread spectrum clock generators buffer many digital consumer applications. Using ICS' patented Phase Locked Loop (PLL) techniques, device runs from lower frequency clock crystal input. MK1725 location table which provides maximum flexibility system designers. chip also power down which used reduce power.
Features
Packaged 16-pin TSSOP Available (lead) free package Replaces spread spectrum clock generator
buffer Input clock crystal frequency 20-34 Output frequency 20-136 Four spread spectrum clock outputs Duty cycle 45/55 Operating voltage Advanced, power CMOS process
Block Diagram
S3:0 PLL/Clock Synthesis Spread Spectrum Circuitry
CLK1:4
X1/ICLK 20-34 crystal clock Crystal Oscillator
Optional crystal capacitors.
PDTS
1725 Integrated Circuit Systems
Jose, 5126
Revision 021605 297-1
MK1725
Quad Output Spread Spectrum Clock Generator
Assignment
CLK1 CLK2 PDTS CLK4 CLK3
Output Selection Table
Multiplier TEST CLK1:4 Spread -0.5% 0.5% 0.25% -0.5% 0.5% 0.25% -0.5% 0.5% 0.25% TEST
(173 mil) TSSOP
Descriptions
Number
Name
CLK1 CLK2 CLK3
Type
Input Input Input Power Power Input Output Output Output
Connect crystal clock input. Select Determines frequency spread amount output clocks table above. Internal pull-down. Select Determines frequency spread amount output clocks table above. Internal pull-down. Connect +3.3V. Connect ground. Select Determines frequency spread amount output clocks table above. Internal pull-down. Clock output. Frequency spread amount determined table above. Weak internal pull-down when tri-state. Clock output. Frequency spread amount determined table above. Weak internal pull-down when tri-state. Clock output. Frequency spread amount determined table above. Weak internal pull-down when tri-state.
1725 grated Circu Systems
Race Stre Jose,
Revision 021605 7-120
MK1725
Quad Output Spread Spectrum Clock Generator
Number
Name
CLK4
Type
Output Power Power Input
Clock output. Frequency spread amount determined table above. Weak internal pull-down when tri-state. Connect ground. Connect +3.3V. Select Determines frequency spread amount output clocks table above. Internal pull-down. Power Down Tri-state. Powers down entire chip tri-states outputs when low. Internal pull-up resistor. Connect +3.3V. 20MHz-34MHz crystal input. Float clock input.
PDTS
Input Power Input
External Components
Decoupling Capacitor
with high performance mixed-signal MK1725 must isolated from system power supply noise perform optimally. decoupling capacitor 0.01µF must connected between each ground plane. capacitance, each crystal capacitor would [(18-6)
Layout Recommendations
optimum device performance lowest output phase noise, following guidelines should observed. 0.01µF decoupling capacitors should mounted component side board close possible. vias should used between decoupling capacitors pins. trace pins should kept short possible, should trace ground via. external crystal should mounted just next device with short traces. traces should routed next each other with minimum spaces, instead they should separated away from other traces. minimize series termination resistor needed) should placed close clock outputs. optimum layout with components same side board, minimizing vias through other signal layers. Other signal traces should routed away from MK1725. This includes signal traces just underneath device, layers adjacent ground plane layer used device.
Series Termination Resistor
Clock output traces over inch should series termination. series terminate trace commonly used trace impedance), place resistor series with clock line, close clock output possible. nominal impedance clock output
Crystal Load Capacitors
device crystal connections should include pads small capacitors from ground from ground. These capacitors used adjust stray capacitance board match nominally required crystal load capacitance. Because load capacitance only increased this trimming process, important keep stray capacitance minimum using very short traces (and vias) been crystal device. Crystal capacitors must connected from each pins ground. value these crystal caps should equal -6)*2. this equation, crystal load capacitance Example: crystal with load
1725 grated Circu Systems
Race Stre Jose,
Revision 021605 7-120
MK1725
Quad Output Spread Spectrum Clock Generator
Absolute Maximum Ratings
Stresses above ratings listed below cause permanent damage MK1725. These ratings, which standard values commercially rated parts, stress ratings only. Functional operation device these other conditions above those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect product reliability. Electrical parameters guaranteed only over recommended operating temperature range.
Item
Supply Voltage, Inputs Outputs Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature
Rating
-0.5 VDD+0.5 +70°C +150°C 125°C 260°C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature Power Supply Voltage (measured respect GND)
Min.
+3.135
Typ.
+3.3
Max.
+3.465
Units
Electrical Characteristics
Unless stated otherwise, ±5%, Ambient Temperature +70°C
Parameter
Operating Voltage Supply Current Input High Voltage Input Voltage Input High Voltage Input Voltage Output High Voltage Output High Voltage Output Voltage Short Circuit Current Input Capacitance Nominal Output Impedance Internal Pull-up Resistor Internal Pull-down Resistor
Symbol
ZOUT
Conditions
S3:0=[0100] Input selects Input selects ICLK ICLK Clock outputs
Min.
3.135
Typ.
Max.
3.465
Units
VDD/2+1 VDD/2-1 VDD-0.4
PDTS Clock outputs; S3:0
1725 grated Circu Systems
Race Stre Jose,
Revision 021605 7-120
MK1725
Quad Output Spread Spectrum Clock Generator
Electrical Characteristics
Unless stated otherwise, ±5%, Ambient Temperature +70°C
Parameter
Input Frequency Output Rise Time Output Fall Time Output Clock Duty Cycle
Symbol
Conditions
Crystal clock input 80%, Note 20%, Note VDD/2, Note modes VDD/2, Note mode
Min.
Typ.
Max. Units
Absolute Clock Period Jitter Modulation Frequency Output Output Skew Output Enable Time Output Disable Time Note Measured with load.
fmod
Cycle cycle, Note Non-spread modes PDTS high output spread profile stable PDTS tri-state
Thermal Characteristics
Parameter
Thermal Resistance Junction Ambient
Symbol
Conditions
Still flow flow
Min.
Typ.
Max. Units
°C/W °C/W °C/W °C/W
Thermal Resistance Junction Case
Marking Diagram
MK1725GL ###### YYWW
Notes: ###### code. YYWW last digits year week number that part assembled. denotes (lead) free package. Bottom marking: (origin). Origin country origin USA.
1725 grated Circu Systems
Race Stre Jose,
Revision 021605 7-120
MK1725
Quad Output Spread Spectrum Clock Generator
Package Outline Package Dimensions TSSOP, Mil. Narrow Body)
Package dimensions kept current with JEDEC Publication
Millimeters Symbol Inches
-1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 4.90 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 -0.10
-0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.193 0.201 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 -0.004
Ordering Information
Part Order Number
MK1725GLF MK1725GLFT
Marking
page
Shipping Packaging
Tubes Tape Reel
Package
16-pin TSSOP 16-pin TSSOP
Temperature
While information presented herein been checked both accuracy reliability, Integrated Circuit Systems (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial applications. other applications such those requiring extended temperature range, high reliability, other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments.
1725 grated Circu Systems
Race Stre Jose,
Revision 021605 7-120

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