175MHZ, FEMTOCLOCKSVCXO BASED SONET/SDH JITTER ATTENUATOR FEATURE

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175MHZ, FEMTOCLOCKSVCXO BASED SONET/SDH JITTER ATTENUATOR FEATURE

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ICS843002I-40
175MHZ, FEMTOCLOCKSVCXO BASED SONET/SDH JITTER ATTENUATOR
FEATURES
Differential LVPECL outputs Selectable CLKx, nCLKx differential input pairs CLKx, nCLKx pairs accept following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL single-ended LVCMOS LVTTL levels Maximum output frequency: 175MHz FemtoClock frequency range: 560MHz 700MHz phase jitter 155.52MHz, using 19.44MHz crystal (12kHz 20MHz): 0.81ps (typical) Full 3.3V mixed 3.3V core/2.5V output supply voltage -40°C 85°C ambient operating temperature
GENERAL DESCRIPTION
ICS843002I-40 member HiperClockSfamily high performance clock HiPerClockSsolutions from ICS. ICS843002I-40 based synchronous clock generator that optimized SONET/SDH line card applications where jitter attenuation frequency translation needed. device contains internal stages that cascaded series. first stage uses VCXO which optimized provide reference clock jitter attenuation jitter tolerant, provide stable reference clock stage (typically 19.44MHz). second stage provides additional frequency multiplication (x32), maintains output jitter using phase noise FemtoClock VCO. multiplication ratios selected from internal lookup tables using device input selection pins. device performance multiplication ratios optimized support non-FEC (non-Forward Error Correction) SONET/SDH applications with rates OC-48 (SONET) STM-16 (SDH). VCXO requires external, inexpensive pullable crystal. VCXO uses external passive loop filter components which used optimize loop bandwidth damping characteristics given line card application.
ASSIGNMENT
XTAL_OUT XTAL_IN R_SEL2 R_SEL1 R_SEL0 nCLK1 CLK1
ICS843002I-40 includes clock input ports. Each accept either single-ended differential input. Each input port also includes activity detector circuit, which reports input clock activity through LOR0 LOR1 logic output pins. input ports feed input selection mux. "Hitless switching" accomplished through proper filter tuning. Jitter transfer wander characteristics influenced loop filter tuning, phase transient performance influenced both loop filter tuning alignment error between reference clocks. Typical ICS843002I-40 configuration SONET/SDH Systems: VCXO 19.44MHz crystal Loop bandwidth: 50Hz 250Hz Input Reference clock frequency selections: 19.44MHz, 38.88MHz, 77.76MHz, 155.52MHz, 311.04MHz, 622.08MHz Output clock frequency selections: 19.44MHz, 77.76MHz, 155.52MHz, Hi-Z
ISET CLK0 nCLK0 CLK_SEL
QA_SEL1 QA_SEL0 QB_SEL1 QB_SEL0 VCCA
LOR0 LOR1 VCCO_LVCMOS VCCO_LVPECL
ICS843002I-40
32-Lead VFQFN 0.75mm package body Package View
Preliminary Information presented herein represents product prototyping pre-production. noted characteristics based initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves right change circuitry specifications without notice.
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BLOCK DIAGRAM
External Loop Components
19.44 Pullable xtal
ICS843002-40
VCCO_LVCMOS CLK1 nCLK1 LOR1
Activity Detector
ISET
Phase Detector
Divider
Divide
Charge Pump Loop Filter
VCXO
XTAL_OUT
19.44
CLK0 nCLK0 LOR0
Divide VCXO Jitter Attenuation
Activity Detector
XTAL_IN
VCCO_LVPECL
622.08
CLK_SEL
FemtoClock
Divider
QA_SEL1:0
R_SEL2:0
Divider
QB_SEL1:0
NOTE 19.44MHz VCXO crystal shown typical SONET/SDH device applications.
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Description Loop filter connection node pins. Charge pump current setting pin. Core power supply pin. Pulldown Pullup/ Pulldown Pulldown Pullup Pullup Non-inver ting differential clock input. Inver ting differential clock input. VCC/2 bias voltage when left floating. Input clock select. LVCMOS/LVTTL interface levels. Table LVPECL output divider control QA/nQA outputs. Table LVPECL output divider control QB/nQB outputs. Table Analog supply pin. Differential clock output pair. LVPECL interface levels. Negative supply pins. Differential clock output pair. LVPECL interface levels. Output power supply nQB. Power supply LOR0 LOR1. connect. Alarm output, loss reference CLK1. LVCMOS/LVTTL interface levels. Alarm output, loss reference CLK0. LVCMOS/LVTTL interface levels. Pullup/ Inver ting differential clock input. Pulldown VCC/2 bias voltage when left floating. Pulldown Non-inver ting differential clock input.
TABLE DESCRIPTIONS
Number Name LF1, ISET CLK0 nCLK0 CLK_SEL QA_SEL1, QA_SEL0 QB_SEL1, QB_SEL0 VCCA VCCO_LVPECL VCCO_LVCMOS LOR1 LOR0 nCLK1 Type Analog Input/Output Analog Input/Output Power Input Input Input Input Input Power Output Power Output Power Power Unused Output Output Input
CLK1 Input R_SEL0, R_SEL1, Input Pulldown Input divider selection. LVCMOS/LVTTL interface. Table R_SEL2 ystal oscillator interface. XTAL_OUT output. XTAL_OUT, Input XTAL_IN input. XTAL_IN NOTE: Pullup Pulldown refer internal input resistors. Table Characteristics, typical values.
TABLE CHARACTERISTICS
Symbol RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical Maximum Units
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TABLE INPUT REFERENCE SELECTION FUNCTION TABLE
Inputs CLK_SEL Input Selected CLK0 CLK1
TABLE INPUT REFERENCE DIVIDER SELECTION FUNCTION TABLE
Inputs R_SEL2:0 Divider Value State bypass VCXO bypass VCXO FemtoClockPLL's
TABLE OUTPUT DIVIDER SELECTION FUNCTION TABLE
Inputs Qx_SEL1:0 Output Divider Value State Output Hi-Z
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4.6V -0.5V 0.5V -0.5V VCCO 0.5V 50mA 100mA 34.8°C/W lfpm) -65°C 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only. Functional operation product these conditions conditions beyond those listed Characteristics Character-
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, Inputs, Outputs, (LVCMOS) Outputs, (LVPECL) Continuous Current Surge Current Package Thermal Impedance, Storage Temperature, TSTG
istics implied. Exposure absolute maximum rating
conditions extended periods affect product reliability.
TABLE POWER SUPPLY CHARACTERISTICS, VCCA 3.3V±5%, VCCO_LVCMOS, VCCO_LVPECL 3.3V±5% 2.5V±5%,
-40°C 85°C
Symbol VCCA VCCO_LVCMOS, VCCO_LVPECL ICCA
Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current
Test Conditions
Minimum 3.135 3.135 3.135 2.375
Typical
Maximum 3.465 3.465 3.465 2.625
Units
TABLE LVCMOS LVTTL CHARACTERISTICS, VCCA 3.3V±5%, VCCO_LVCMOS 3.3V±5% 2.5V±5%,
-40°C 85°C
Symbol
Parameter Input High Voltage Input Voltage Input High Current CLK_SEL, R_SEL0:2 QA_SEL0:1, QB_SEL0:1 CLK_SEL, R_SEL0:2 QA_SEL0:1, QB_SEL0:1
Test Conditions
Minimum -0.3
Typical
Maximum
Units
3.465V 3.465V 3.465V, 3.465V, VCCO_LVCMOS 3.3V VCCO_LVCMOS 2.5V VCCO_LVCMOS 3.3V 2.5V -150
Input Current
Output High Voltage Output Voltage
LOR0, LOR1; NOTE LOR0, LOR1; NOTE
NOTE Outputs terminated with VCCO_LVCMOS/2 .See Parameter Measurement Information Section, "Output Load Test Circuit".
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TABLE DIFFERENTIAL CHARACTERISTICS, VCCA 3.3V±5%, VCCO_LVPECL 3.3V±5% 2.5V±5%,
-40°C 85°C
Symbol
Parameter CLK0, CLK1 Input High Current nCLK0, nCLK1 CLK0, CLK1 Input Current nCLK0, nCLK1 Peak-to-Peak Input Voltage
Test Conditions 3.465V 3.465V 3.465V
Minimum
Typical
Maximum
Units
-150 0.15 0.85
VCMR Common Mode Input Voltage; NOTE NOTE Common mode voltage defined VIH. NOTE single ended applications, maximum input voltage CLKx, nCLKx 0.3V.
TABLE LVPECL CHARACTERISTICS, VCCA 3.3V±5%, VCCO_LVPECL 3.3V±5% 2.5V±5%, -40°C 85°C
Symbol Parameter Output High Voltage; NOTE Output Voltage; NOTE Test Conditions Minimum VCCO VCCO Typical Maximum VCCO VCCO Units
Peak-to-Peak Output Voltage Swing VSWING NOTE Outputs terminated with VCCO_LVPECL "Parameter Measurement Information" section, "Output Load Test Circuit".
TABLE CRYSTAL CHARACTERISTICS
Symbol CO/C1 Parameter Nominal Frequency Frequency Tolerance Frequency Stability Operating Temperature Range Load Capacitance Shunt Capacitance Pullability Ratio Equivalent Series Resistance Drive Level Mode Operation Fundamental Test Conditions Minimum Typical 19.44 ±TBD ±TBD Maximum Units
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Test Conditions 155.52MHz, Integration range: 12kHz 20MHz Minimum 19.44 0.81 Typical Maximum Units
TABLE CHARACTERISTICS, VCCA VCCO_LVCMOS, VCCO_LVPECL 3.3V±5%, -40°C 85°C
Symbol Parameter FOUT Output Frequency Phase Jitter, (Random); NOTE Output Skew; NOTE Output Rise/Fall Time
tsk(o)
Output Duty Cycle Parameter Measurement Information section. NOTE Please refer Phase Noise Plot. NOTE Defined skew between outputs same supply voltage with equal load conditions. Measured output differential cross points. NOTE This parameter defined accordance with JEDEC Standard
TABLE CHARACTERISTICS, VCCA 3.3V±5%, VCCO_LVCMOS, VCCO_LVPECL 2.5V±5%, -40°C 85°C
Symbol Parameter FOUT Output Frequency Phase Jitter, (Random); NOTE Output Skew; NOTE Output Rise/Fall Time Test Conditions 155.52 MHz, Integration range: 12kHz 20MHz Minimum 19.44 0.83 Typical Maximum Units
tsk(o)
Output Duty Cycle Parameter Measurement Information section. NOTE Please refer Phase Noise Plot. NOTE Defined skew between outputs same supply voltage with equal load conditions. Measured output differential cross points. NOTE This parameter defined accordance with JEDEC Standard
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TYPICAL PHASE NOISE 155.52MHZ
-100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100k 100M
Filter
155.52MHz
Phase Jitter (Random) 12kHz 20MHz 0.81ps (typical)
NOISE POWER
Phase Noise Data
Phase Noise Result adding Filter data OFFSET FREQUENCY (HZ)
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PARAMETER MEASUREMENT INFORMATION
2.8V±0.04V
VCCA, VCCO_LVPECL
SCOPE
VCCA VCCO_LVPECL
SCOPE
LVPECL
LVPECL
-1.3V 0.165V
-0.5V 0.125V
3.3V CORE/3.3V LVPECL OUTPUT LOAD TEST CIRCUIT
3.3V CORE/2.5V LVPECL OUTPUT LOAD TEST CIRCUIT
Phase Noise Plot
Noise Power
nCLK0, nCLK1
Phase Noise Mask
nCLK0, nCLK1
Cross Points
Offset Frequency
Jitter Area Under Masked Phase Noise Plot
DIFFERENTIAL INPUT LEVEL
tsk(o)
PHASE JITTER
nQA,
PERIOD
PERIOD
100%
OUTPUT SKEW
OUTPUT DUTY CYCLE/PULSE WIDTH/tPERIOD
Clock Outputs
OUTPUT RISE/FALL TIME
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175MHZ, FEMTOCLOCKSVCXO BASED SONET/SDH JITTER ATTENUATOR APPLICATION INFORMATION
DESCRIPTION STAGES
ICS843002I-40 stage device, VCXO followed phase noise FemtoClock PLL. VCXO uses external pullable crystal which pulled ±100ppm VCXO circuitry phase lock input reference frequency. FemtoClock wide bandwidth (about 800kHz) which means will phase track VCXO PLL. Most reference clock jitter attenuation needs accomplished VCXO PLL. using bypass FemtoClock mode (Table 3B), selected input reference clock passed directly FemtoClock which will multiply higher frequency. second mode, VCXO FemtoClock bypass, routes selected input refrence directly LVPECL output dividers.
SETTING VCXO LOOP RESPONSE
VCXO loop response determined both fixed device characteristics other characteristics user. This includes values RSET shown External VCXO Components figure this page. VCXO loop bandwidth approximated (VCXO PLL)
WHERE: Value resistor loop filter Ohms Charge pump current amps (see table page VCXO Gain Hz/V above equation calculates "normalized" loop bandwidth (denoted "NBW") which approximately equal bandwidth. does take into account effects damping factor second pole imposed does, however, provide useful approximation filter performance. prevent jitter clock output modulation VCXO phase detector frequency, following general rule should observed: (VCXO PLL) (Phase Detector)
VCXO LOOP RESPONSE CONSIDERATIONS
Loop response characteristics VCXO affected VCXO feedback divider value (bandwidth damping factor), external loop filter components (bandwidth, damping factor, frequency response). practical range VCXO bandwidth from about 10Hz about 1kHz. setting VCXO bandwidth damping factor covered later this document. based bandwidth calculator also under development. assistance with loop bandwidth suggestions value calculation, please contact applications.
(Phase Detector) Input Frequency Divider loop damping factor determined (VCLK)
WHERE: Value capacitor loop filter Farads
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establishes second pole VCXO loop filter. higher damping factors calculate value based value that would used damping factor This will minimize baseband peaking loop instability that lead output jitter. also dampens VCXO input voltage modulation charge pump correction pulses. value that will result increased output phase noise phase detector frequency this. extreme cases where input jitter high, charge pump current high, small, VCXO input voltage supply ground rail resulting nonlinear loop response. best value filter response software under development from (please refer following section). should increased value until just starts affecting passband peak.
EXTERNAL VCXO COMPONENTS
general, loop damping factor should greater ensure output stability. higher damping factor will create less peaking passband. higher damping factor also increase lock time output clock jitter when there excess digital noise system application, reduced ability respond therefore compensate phase noise ingress.
ISET
RSET
LOOP FILTER RESPONSE SOFTWARE
Online tools calculate loop filter response (coming soon) www.icst.com. Contact your local sales representative tool cannot found this product.
external crystal devices loop filter components should kept close device. Loop filter crystal connection traces should kept short well separated from each other from other signal traces. Other signal traces should underneath device, loop filter crystal components.
NOTES EXTERNAL CRYSTAL LOAD CAPACITORS
loop filter schematic diagram, capacitors shown between pins ground between pins ground. These optional crystal load capacitors which used center tune external pullable crystal (the crystal frequency only lowered adding capacitance, cannot raised). Note that addition external load capacitors will decrease crystal pull range Kvco value.
NOTES SETTING VALUE
another general rule, following relationship should maintained between components loop filter:
LOSS REFERENCE INDICATOR (LOR0
LOR1) OUTPUT PINS.
"edge"). output will otherwise low. activity monitor does flag excessive reference transitions phase detector observation interval error. monitor only distinguishes between transitions occurring transitions occurring.
LOR0 LOR1 pins controlled internal clock activity monitor circuits. clock activity monitor circuits clocked VCXO phase detector feedback clock. output asserted high there three consecutive feedback clock edges without reference clock edges both cases, either negative positive transition counted
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seen loop bandwidth damping factor equations using filter response software available from ICS, increasing charge pump current (ICP) increases both bandwidth damping factor.
NOTES SETTING CHARGE PUMP CURRENT
recommended range charge pump current 300A. Below 50A, loop filter charge leakage, capacitor leakage, become problem. This loop filter leakage cause locking problems, output clock cycle slips, frequency phase noise.
CHARGE PUMP CURRENT, EXAMPLE SETTINGS
RSET 17.6k 8.8k 4.4k 2.2k Charge Pump Current (ICP) 62.5µA 125µA 250µA 500µA
1E-3
ICP, Amps
100E-6
10E-6 RSET,
100k
FIGURE CHARGE PUMP CURRENT
VALUE
RSET (EXTERNAL
RESISTOR)
GRAPH
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3.3V .01F VCCA .01F
POWER SUPPLY FILTERING TECHNIQUES
high speed analog circuitry, power supply pins vulnerable random noise. ICS843002I-40 provides separate power supplies isolate high switching noise from outputs internal PLL. VCC, VCCA, VCCO_X should individually connected power supply plane through vias, bypass capacitors should used each pin. achieve optimum jitter performance, power supply isolation required. Figure illustrates resistor along with .01F bypass capacitor should connected each VCCA pin.
FIGURE POWER SUPPLY FILTERING
TERMINATION
2.5V LVPECL OUTPUT
ground level. Figure eliminated termination shown Figure
Figure Figure show examples termination 2.5V LVPECL driver. These terminations equivalent terminating 2.5V, very close
2.5V
2.5V 2.5V VCC=2.5V 2,5V LVPECL Driv 62.5 62.5
VCC=2.5V 2,5V LVPECL Driv
FIGURE 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V VCC=2.5V 2,5V LVPECL Driv
FIGURE 2.5V LVPECL TERMINATION EXAMPLE
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drive transmission lines. Matched impedance techniques should used maximize operating frequency minimize signal distortion. Figures show different layouts which recommended only guidelines. Other suitable clock layouts exist would recommended that board designers simulate guarantee compatibility across printed circuit clock component process variations.
TERMINATION 3.3V LVPECL OUTPUTS
clock layout topology shown below typical termination LVPECL outputs. different layouts mentioned recommended only guidelines. FOUT nFOUT impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors current path ground) current sources must used functionality. These outputs designed
3.3V
FOUT
((VOH VOL) (VCC
FOUT
FIGURE LVPECL OUTPUT TERMINATION
FIGURE LVPECL OUTPUT TERMINATION
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here examples only. Please consult with vendor driver component confirm driver termination requirements. example Figure input termination applies HiPerClockS LVHSTL drivers. using LVHSTL driver from another vendor, their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
/nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL other differential signals. Both VSWING must meet VCMR input requirements. Figures show interface examples HiPerClockS CLK/nCLK input driven most common driver types. input interfaces suggested
3.3V 3.3V 3.3V 1.8V nCLK LVHSTL HiPerClockS LVHSTL Driver LVPECL HiPerClockS Input nCLK HiPerClockS Input
FIGURE HIPERCLOCKS CLK/nCLK INPUT DRIVEN HIPERCLOCKS LVHSTL DRIVER
FIGURE HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER
3.3V 3.3V 3.3V nCLK LVPECL HiPerClockS Input
3.3V 3.3V LVDS_Driv
nCLK
Receiv
FIGURE HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER
FIGURE HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVDS DRIVER
3.3V 3.3V 3.3V LVPECL nCLK HiPerClockS Input
R5,R6 locate near driver pin.
FIGURE HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH COUPLE
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capacitance, this resistor acts pass signal filter. typical value this optional series filter resistor 100. This will lower both amplitude edge rate clock input signal. case very short clock trace series termination resistor needed.
SINGLE ENDED CLOCK INPUT INTERFACE
When using LVCMOS LVTTL clock driver, clock input connected CLKx (CLK0 CLK1) input pin. nCLKx (nCLK0 nCLK1) left unconnected. help reduce interference with internal circuits, external resistor placed series with clock signal right near CLKx input pin. Combined with input
Series Termination LVTTL LVCMOS
Optional Series Filter Resistor
3.3V CLKx nCLKx
3.3V nCLK
connection)
Differential Input Stage
External Circuitry
Internal Device Circuitry
FIGURE SINGLE-ENDED CLOCK INPUT INTERFACE
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This section provides information power dissipation junction temperature ICS843002I-40. Equations example calculations also provided.
Power Dissipation. total power dissipation ICS843002I-40 core power plus power dissipated load(s). following power dissipation 3.3V 3.465V, which gives worst case results. NOTE: Please refer Section details calculating power dissipated load.
Power (core)MAX VCC_MAX IEE_MAX 3.465V 175mA 606.375mW Power (outputs)MAX 30mW/Loaded Output pair outputs loaded, total power 30mW 120mW
Total Power_MAX (3.465V, with outputs switching) 606.375mW 60mW 666.38mW
Junction Temperature. Junction temperature, temperature junction bond wire bond directly affects reliability device. maximum recommended junction temperature HiPerClockSdevices 125°C.
equation follows: Pd_total Junction Temperature Junction-to-Ambient Thermal Resistance Pd_total Total Device Power Dissipation (example calculation section above) Ambient Temperature order calculate junction temperature, appropriate junction-to-ambient thermal resistance must used. Assuming flow linear feet minute multi-layer board, appropriate value 34.8°C/W Table below. Therefore, ambient temperature 85°C with outputs switching 85°C 0.666W 34.8°C/W 108.2°C. This well below limit 125°C. This calculation only example. will obviously vary depending number loaded outputs, supply voltage, flow, type board (single layer multi-layer).
TABLE THERMAL RESISTANCE
32-PIN VFQFN, FORCED CONVECTION
Flow (Linear Feet Minute)
Multi-Layer PCB, JEDEC Standard Test Boards 34.8°C/W
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Calculations Equations.
purpose this section derive power dissipated into load. LVPECL output driver circuit termination shown Figure
ICS843002I-40
175MHZ, FEMTOCLOCKSVCXO BASED SONET/SDH JITTER ATTENUATOR
VCCO
VOUT VCCO
FIGURE LVPECL DRIVER CIRCUIT
TERMINATION
calculate worst case power dissipation into load, following equations which assume load, termination voltage
logic high, VOUT VOH_MAX VCCO_MAX 0.9V
CCO_MAX
OH_MAX
0.9V 1.7V
logic low, VOUT
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
1.7V
Pd_H power dissipation when output drives high. Pd_L power dissipation when output drives low. Pd_H 2V))/R
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
[(2V
CCO_MAX
OH_MAX
))/R
CCO_MAX
OH_MAX
[(2V 0.9V)/50) 0.9V 19.8mW
Pd_L
OL_MAX
CCO_MAX
2V))/R
CCO_MAX
OL_MAX
[(2V
CCO_MAX
OL_MAX
))/R
CCO_MAX
OL_MAX
[(2V 1.7V)/50) 1.7V 10.2mW Total Power Dissipation output pair Pd_H Pd_L 30mW
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TABLE JAVS. FLOW TABLE
LEAD VFQFN
Flow (Linear Feet Minute)
Multi-Layer PCB, JEDEC Standard Test Boards 34.8°C/W
TRANSISTOR COUNT
transistor count ICS843002I-40 5536
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LEAD VFQFN
PACKAGE OUTLINE SUFFIX
TABLE PACKAGE DIMENSIONS
JEDEC VARIATION DIMENSIONS MILLIMETERS VHHD-2 SYMBOL 0.30 1.25 1.25 5.00 BASIC 2.25 5.00 BASIC 2.25 0.50 BASIC 0.40 0.50 3.25 3.25 0.18 0.80 MINIMUM NOMINAL -0.25 Ref. 0.25 0.30 1.00 0.05 MAXIMUM
Reference Document: JEDEC Publication MO-220
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Marking ICS43002A40 ICS43002A40 Package Lead VFQFN Lead VFQFN Shipping Packaging tray 2500 tape reel Temperature -40°C 85°C -40°C 85°C
TABLE ORDERING INFORMATION
Part/Order Number ICS843002AKI-40 ICS843002AKI-40T
aforementioned trademarks, HiPerClockS FEMTOCLOCKS trademarks Integrated Circuit Systems, Inc. subsidiaries United States and/or other countries. While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial industrial applications. other applications such those requiring high reliability other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 843002AKI-40
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175MHZ, FEMTOCLOCKSVCXO BASED SONET/SDH JITTER ATTENUATOR FEATURE

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