SCES547A FEBRUARY 2004 REVISED JUNE 2005 Available Texas Instrume

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SCES547A FEBRUARY 2004 REVISED JUNE 2005 Available Texas Instrume

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SN74LVC2G132 DUAL 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS
SCES547A FEBRUARY 2004 REVISED JUNE 2005
Available Texas Instruments NanoStarand NanoFreePackages Supports Operation Inputs Accept Voltages Power Consumption, 10-µA ±24-mA Output Drive Typical VOLP (Output Ground Bounce) <0.8 25°C Typical VOHV (Output Undershoot) 25°C Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds JESD Class Protection Exceeds JESD 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)
PACKAGE (TOP VIEW)
PACKAGE (BOTTOM VIEW)
DESCRIPTION/ORDERING INFORMATION
This dual 2-input NAND gate with Schmitt-trigger inputs designed 1.65-V 5.5-V operation. SN74LVC2G132 contains inverters performs Boolean function positive logic. device functions independent inverters, because Schmitt action, different input threshold levels positive-going (VT+) negative-going (VT-) signals. NanoStarand NanoFreepackage technology major breakthrough packaging concepts, using package. This device triggered from slowest input ramps still give clean jitter-free output signals. ORDERING INFORMATION
PACKAGE NanoStar- WCSP (DSBGA) 0.23-mm Large Bump NanoFree- WCSP (DSBGA) 0.23-mm Large Bump (Pb-free) SSOP VSSOP Reel 3000 SN74LVC2G132YZPR Reel 3000 Reel 3000 Reel SN74LVC2G132DCTR SN74LVC2G132DCUR SN74LVC2G132DCUT C3B_ C3B_ ORDERABLE PART NUMBER SN74LVC2G132YEPR _D5_ TOP-SIDE MARKING
-40°C 85°C
Package drawings, standard packing quantities, thermal data, symbolization, design guidelines available www.ti.com/sc/package. DCT: actual top-side marking three additional characters that designate year, month, assembly/test site. DCU: actual top-side marking additional character that designates assembly/test site. YEP/YZP: actual top-side marking three preceding characters denote year, month, sequence code, following character designate assembly/test site. identifier indicates solder-bump composition SnPb, Pb-free).
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. NanoStar, NanoFree trademarks Texas Instruments.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 2004-2005, Texas Instruments Incorporated
SN74LVC2G132 DUAL 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS
SCES547A FEBRUARY 2004 REVISED JUNE 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
This device fully specified partial-power-down applications using Ioff. Ioff circuitry disables outputs, preventing damaging current backflow through device when powered down. FUNCTION TABLE (EACH GATE)
INPUTS OUTPUT
LOGIC DIAGRAM (POSITIVE LOGIC)
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Supply voltage range Input voltage range Voltage range applied output high-impedance power-off state Voltage range applied output high state Input clamp current Output clamp current Continuous output current Continuous current through package Tstg Package thermal impedance Storage temperature range package YEP/YZP package -0.5 -0.5 -0.5 -0.5 ±100 °C/W UNIT
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. input output negative-voltage ratings exceeded input output current ratings observed. value provided recommended operating conditions table. package thermal impedance calculated accordance with JESD 51-7
SN74LVC2G132 DUAL 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS
SCES547A FEBRUARY 2004 REVISED JUNE 2005
Recommended Operating Conditions
Supply voltage Input voltage Output voltage
Operating Data retention only 1.65 1.65 High-level output current 1.65 Low-level output current Operating free-air temperature
UNIT
unused inputs device must held ensure proper device operation. Refer application report, Implications Slow Floating CMOS Inputs, literature number SCBA004.
SN74LVC2G132 DUAL 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS
SCES547A FEBRUARY 2004 REVISED JUNE 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS 1.65 Positive-going input threshold voltage 1.65 Negative-going input threshold voltage 1.65 Hysteresis (VT+ VT-) -100 Ioff inputs GND, typical values 25°C. input Other inputs 1.65 1.65 1.65 1.65 1.65 1.65 0.79 1.11 2.16 2.61 0.39 0.58 0.84 1.41 1.87 0.37 0.48 0.56 0.71 0.71 0.45 0.55 0.55 1.16 1.56 1.87 2.74 3.33 0.62 0.87 1.14 1.79 2.29 0.62 0.77 0.87 1.04 1.11 UNIT
SN74LVC2G132 DUAL 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS
SCES547A FEBRUARY 2004 REVISED JUNE 2005
Switching Characteristics
over recommended operating free-air temperature range, (unless otherwise noted) (see Figure
PARAMETER FROM (INPUT) (OUTPUT) 0.15 UNIT
Switching Characteristics
over recommended operating free-air temperature range, (unless otherwise noted) (see Figure
PARAMETER FROM (INPUT) (OUTPUT) 0.15 UNIT
Operating Characteristics
25°C
PARAMETER Power dissipation capacitance TEST CONDITIONS UNIT
SN74LVC2G132 DUAL 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS
SCES547A FEBRUARY 2004 REVISED JUNE 2005
PARAMETER MEASUREMENT INFORMATION
VLOAD From Output Under Test (see Note Open TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD
LOAD CIRCUIT INPUTS 0.15 tr/tf VCC/2 VCC/2 VCC/2 VLOAD 0.15 0.15 Timing Input Input VOLTAGE WAVEFORMS PULSE DURATION Input tPLH Output tPHL tPHL tPLH Output VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING NONINVERTING OUTPUTS Output Waveform (see Note Output Control tPZL Output Waveform VLOAD (see Note tPZH VOLTAGE WAVEFORMS SETUP HOLD TIMES tPLZ VLOAD/2 tPHZ Data Input
VOLTAGE WAVEFORMS ENABLE DISABLE TIMES LOW- HIGH-LEVEL ENABLING
NOTES: includes probe capacitance. Waveform output with internal conditions such that output low, except when disabled output control. Waveform output with internal conditions such that output high, except when disabled output control. input pulses supplied generators having following characteristics: MHz, outputs measured time, with transition measurement. tPLZ tPHZ same tdis. tPZL tPZH same ten. tPLH tPHL same tpd. parameters waveforms applicable devices.
Figure Load Circuit Voltage Waveforms
SN74LVC2G132 DUAL 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS
SCES547A FEBRUARY 2004 REVISED JUNE 2005
PARAMETER MEASUREMENT INFORMATION
VLOAD From Output Under Test (see Note Open TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD
LOAD CIRCUIT INPUTS 0.15 tr/tf VCC/2 VCC/2 VCC/2 VLOAD 0.15 0.15 Timing Input Input VOLTAGE WAVEFORMS PULSE DURATION Input tPLH Output tPHL tPHL tPLH Output VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING NONINVERTING OUTPUTS Output Waveform (see Note Output Control tPZL Output Waveform VLOAD (see Note tPZH VOLTAGE WAVEFORMS SETUP HOLD TIMES tPLZ VLOAD/2 tPHZ Data Input
VOLTAGE WAVEFORMS ENABLE DISABLE TIMES LOW- HIGH-LEVEL ENABLING
NOTES: includes probe capacitance. Waveform output with internal conditions such that output low, except when disabled output control. Waveform output with internal conditions such that output high, except when disabled output control. input pulses supplied generators having following characteristics: MHz, outputs measured time, with transition measurement. tPLZ tPHZ same tdis. tPZL tPZH same ten. tPLH tPHL same tpd. parameters waveforms applicable devices.
Figure Load Circuit Voltage Waveforms
PACKAGE OPTION ADDENDUM
6-Jun-2005
PACKAGING INFORMATION
Orderable Device 74LVC2G132DCURE4 74LVC2G132DCUTE4 SN74LVC2G132DCTR SN74LVC2G132DCUR SN74LVC2G132DCUT SN74LVC2G132YEPR SN74LVC2G132YZPR
Status ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Package Type WCSP WCSP
Package Drawing
Pins Package Plan 3000 3000 3000 3000 3000 Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS)
Lead/Ball Finish NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU SNPB SNAGCU
Peak Temp Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan planned eco-friendly classification: Pb-Free (RoHS) Green (RoHS Sb/Br) please check latest availability information additional product content details. TBD: Pb-Free/Green conversion plan been defined. Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Green (RoHS Sb/Br): defines "Green" mean Pb-Free (RoHS compatible), free Bromine (Br) Antimony (Sb) based flame retardants exceed 0.1% weight homogeneous material)
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDEC industry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
MECHANICAL DATA
MPDS049B 1999 REVISED OCTOBER 2002
(R-PDSO-G8)
0,30 0,15
PLASTIC SMALL-OUTLINE PACKAGE
0,65
0,13
0,15 2,90 2,70 4,25 3,75
INDEX AREA
0,10 0,00 NOTES: linear dimensions millimeters. This drawing subject change without notice. Body dimensions include mold flash protrusion Falls within JEDEC MO-187 variation
3,15 2,75
Gage Plane 0,25 0,60 0,20
1,30
Seating Plane 0,10 4188781/C 09/02
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SCES547A FEBRUARY 2004 REVISED JUNE 2005 Available Texas Instrume

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