M5M28F101AFP,J,VP,RV-85,-10 M5M28F101AFP,J,VP,RV-85,-10 1048576-B

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M5M28F101AFP,J,VP,RV-85,-10 M5M28F101AFP,J,VP,RV-85,-10 1048576-B

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MITSUBISHI LSIs MITSUBISHI LSIs
M5M28F101AFP,J,VP,RV-85,-10 M5M28F101AFP,J,VP,RV-85,-10
1048576-BIT (131072-WORD 8-BIT) CMOS FLASH MEMORY 1048576-BIT (131072-WORD 8-BIT) CMOS FLASH MEMORY
MITSUBISHI M5M28F101A high-speed 1048576-bit CMOS Flash Memories. This suitable applications with microprocessor micro-controller where on-board reprogramming required. M5M28F101A fabricated N-channel double polysilicon gate memory CMOS technology peripheral circuits, available 32pin plastic molded packages.
CONFIGURATION (TOP VIEW)
FEATURES
Speed item (max.) Speed item .100 (max.) Power supply voltage 5V±0.5V Write erase voltage 12V±0.6V Byte program Chip erase Auto program Auto erase Program/erase operation controlled software command Program/erase pulse controlled embedded timer 10000 program/erase cycles Tri-state output buffer TTL-compatible input output read write mode Contained device-identifier code Incorporated data-protection Available packaging Surface Mount
ADDRESS INPUTS
DATA INPUTS/ OUTPUTS
WRITE ENABLE INPUT ADDRESS INPUTS OUTPUT INPUT ENABLE ADDRESS INPUT CHIP ENABLE INPUT
DATA INPUTS/ OUTPUTS
Outline 525mil 32pin (32P2M-A)
APPLICATION
Micro-computer system peripheral equipment
M5M28F101AFP
M5M28F101AJ
Outline 32pin PLCC (32P0)
M5M28F101AVP
M5M28F101ARV
Outline 32pin TSOP type-I (8x20mm) 32P3H-E (normal bend)
Outline 32pin TSOP type-I (8x20mm) 32P3H-F (reverse bend)
CONNECTION
(970407)
MITSUBISHI LSIs
M5M28F101AFP,J,VP,RV-85,-10
1048576-BIT (131072-WORD 8-BIT) CMOS FLASH MEMORY
BLOCK DIAGRAM
ADDRESS INPUTS X-DECODER 131072 WORD CELL MATRIX PROGRAM VOLTAGE ERASE VOLTAGE
(5V, 12V) (5V) (0V)
VERIFY VOLTAGE TIMER CONTROL CIRCUITS COMMAND LATCH CHIP ENABLE OUTPUT ENABLE CIRCUITS OUTPUT SENSE OUTPUT BUFFERS Y-DECODER Y-GATE
CHIP ENABLE INPUT OUTPUT ENABLE INPUT
WRITE ENABLE INPUT
DATA INPUTS/OUTPUTS
FUNCTION
M5M28F101A Read-only mode Read-write mode applying voltage PPH, respectively, pin. Read-only mode, three operation modes, Read, Out-put disable Stand-by accessible. While, Read-Write mode, four operation modes, Read, Output disable, Stand-by Write functional. Read terminals read mode (low level). level input address signals address inputs (A0~A16) make data contents designated address location available data input/output(D0~D7). Output Disable When high level, output from devices disabled. Data input/output high-impedance (High-Z) state. Stand-by When high level, devices stand-by mode power consumption substantially reduced. Data input/output high-impedance (High-Z) state. Write Software command accomplishes program erase operations command latch device, when high voltage supplied VPP. contents latch serve input internal controller. controller output dictates function device. command latch written bringing level, while level high level. Addresses latched falling edge while data latched rising edge Standard micro-processor write timings used.
DATA PROTECTION
Power Supply Voltage When power supply voltage (Vcc) less than 2.5V, device ignores signal. Write Inhibit cases, below, write mode set. When terminated level. From each mode beginning through finish after rising edge program, auto-program, erase, autoerase. Over-erase Protection Just after powering erase command inputted, erase operation executed. Once byte-program performed verified data erase-verify mode, successive command input erase will accepted. Because this, applicable case multi-chip erasing simultaneously.
(970407)
MITSUBISHI LSIs
M5M28F101AFP,J,VP,RV-85,-10
1048576-BIT (131072-WORD 8-BIT) CMOS FLASH MEMORY
SOFTWARE COMMAND
When (VPP PPL), contents command latch fixed 00H, device read-only mode. When high VPPH), device enters read/write mode. device operations selected writing specific software command into command latch. Read Command device read mode after writing Read Command (00H) command latch. device continues read mode until other commands written. When powers-up high voltage (VPP PPH), default contents command latch 00H. ensured that false alteration memory data does occur during power transition. Program Command Program Command command byte-program, program initiated twice write cycles. Program Command (40H) written command latch first write cycle, address data programmed latched second write cycle. Then address data latched falling edge rising edge pulse, respectively. byte- program operation initiated rising edge second write cycle, terminates controlled internal timer. Program Verify Command Following byte program, programmed byte must verified. program-verify initiated writing Program Verify Command (C0H) command latch. After writing Program Verify Command, programmed data verified read mode. Then address information needed. Auto Program Command Auto Program Command command automated program program-verify byte, Auto Program initiated twice write cycles. Auto Program Command (10H 50H) written command latch first write cycle, address data programmed latched second write cycle. Then address data latched falling edge rising edge pulse, respectively. program operation initiated rising edge second write cycle, program-verify begin automatically. necessary program-verify mode after this. complete Auto Program indicated data polling. Data polling indication complete Auto Program. During Auto Program, WE=V CE=OE=VIL data D0~D7 inverse written datum. When Auto Program completed, written datum will output. necessary address written byte during data polling. Erase Command Erase Command command chip-erase, chip-erase initiated writing twice Erase Command (20H) consecutively command latch. erase operation initiated with rising edge pulse terminates 9.5ms, controlled internal timer. This two-step sequence chip-erase prevents from erasing accidentally. Erase Verify Command Following each erase, bytes must verified. erase verify initiated writing Erase Verify Command (A0H) command latch, while address verified latched falling edge pulse. erase verify command must written command latch each address latched before each byte verified. operation continues each byte until byte erased, last address accessed. Auto Erase Command Auto Erase Command command automated erase erase-verify bytes, Auto Erase initiated twice Erase Command (30H) consecutively command latch. First, preprogram operation initiated rising edge second write cycle, byte become zero data. Second, erase erase-verify begin, automatically. necessary preprogram erase-verify mode. complete Auto Erase indicated status polling. Status polling indication complete Auto Erase. During Auto Erase, WE=VIH CE=OE=VIL data "0". When Auto Erase completed, data "1". (D0~D7 "FFH". Reset Command Reset Command command safely abort erase program sequences. Following erase program command first write cycle, operation aborted safely writing consecutive Reset Commands (FFH). Then device enters read mode without altering memory contents. Read Device Identifier Code Device Identifier operation initiated writing into command latch. Following command write, manufacturer code (1CH) device code (D9H) read from address00000H 00001H, respectively. M5M28F101A supported with Common Device Identifier Code MITSUBISHI Flash memory (x8) family. Common Device Identifier operation initiated writing into command latch. Under this case, following command write, manufacturer code (1CH) device code (D0H) read from address-00000H 00001H, respectively. Additionally, Common Device Identifier operation initiated rising high voltage PROM programmers.
(970407)
MITSUBISHI LSIs
M5M28F101AFP,J,VP,RV-85,-10
1048576-BIT (131072-WORD 8-BIT) CMOS FLASH MEMORY
MODE SELECTION
Mode Read-Only Pins Read Output disable Stand Read Output disable Stand Write VPPL VPPL VPPL VPPH VPPH VPPH VPPH Data Data Hi-Z Hi-Z Data Hi-Z Hi-Z Data
Read/Write
Note
ABSOLUTE MAXIMUM RATINGS
Symbol Topr Tstg Parameter input output voltage except VPP/A9 supply voltage supply voltage Operating temperature Storage temperature Conditions With respect Ground Ratings -0.6~7 -0.6~14.0 -0.6~13.5 -10~80 -65~125 Unit
SOFTWARE COMMAND DEFINITION
Command Read Program (Byte Program) Program verify Auto Program Erase (Chip Erase) Erase verify Auto Erase Reset Read device identifier code Read common device identifier code Mode Write Write Write Write Write Write Write Write Write Write First cycle Address Verify address Data Mode Write Read Write Write Read Write Write Read Read Second cycle Address Data Program Program Data Address Program Address Verify Data Program Data Verify Data DDI1 DDI2
Note Write read mode defined mode selection table. Address Device Identifier 00000H manufacturer code, 00001H device code. DDI1 Data Device Identifier manufacturer code, device code. DDI2 Data Common Device Identifier manufacturer code, device code.
COMMON DEVICE IDENTIFIER CODE (not software command)
Code Manufacturer Code Device Code Pins Hex. Data
Note 11.5V~13.0V A1~A8, A10~A16, VIL, 5V±0.5V
CAPACITANCE
Symbol COUT Parameter Input capacitance (Address, Output capacitance Test conditions 25°C, 1MHz, Vout Limits Unit
(970407)
MITSUBISHI LSIs
M5M28F101AFP,J,VP,RV-85,-10
1048576-BIT (131072-WORD 8-BIT) CMOS FLASH MEMORY
ELECTRICAL CHARACTERISTICS 0~70°C, 5V±0.5V, unless otherwise noted)
Symbol ISB1 ISB2 ICC1 ICC2 ICC3 IPP1 IPP2 IPP3 VOH1 VOH2 VPPL VPPH Parameter Input leakage current Output leakage current stand-by current active read current program current erase current read current program current erase current Input voltage Input high voltage Output voltage Output high voltage voltage during read-only mode voltage during read/write mode Test conditions 0VVINVCC 0VVOUTVCC 5.5V, 5.5V, VCC±0.2V
5.5V, VIL, 11.8MHz, IOUT
Limits
VPPH VPPH 0VVPPVCC VCC<VPP6.5V VPPH VPPH VPPH 5.8mA -2.5mA -100µA
Vcc-0.4
Vcc+0.5
Unit
0.45
11.4
12.0
12.6
ELECTRICAL CHARACTERISTICS 0~70°C, 5V±0.5V, unless otherwise noted) Read-Only Mode
Symbol (AD) (CE) (OE) tCLZ tOLZ tWRR tAVAV tAVQV tELQV tGLQV tELQX tGLQX tGHQZ tWHGL Parameter Read cycle time Address access time Chip enable access time Output enable access time Chip enable output Output enable output Output enable high output Output hold from addresses Write recovery time before read Limits M5M28F101A-85 M5M28F101A-10 Unit
Note must applied simultaneously before removed simultaneously after VPP. Timing measurements made under WAVEFORMS READ OPERATIONS.
(970407)
MITSUBISHI LSIs
M5M28F101AFP,J,VP,RV-85,-10
1048576-BIT (131072-WORD 8-BIT) CMOS FLASH MEMORY
Read/Write Mode
Symbol tWRR tRRW tWPH tOEH tDAEC tDAP tVSC tOWP tOWS tOWH tOAS tOAH tODS tODH tAVAV tAVWL tWLAX tDVWH tWHDX tWHGL tGHWL tELWL tWHEH tWLWH tWHWL tWHWL1 tWHWL2 Parameter Write cycle time Address set-up time Address hold time Data set-up time Data hold time Write recovery time before read Read recovery time before write Chip enable set-up time Chip enable hold time Write pulse width Write pulse width high Duration program operation Duration erase operation Output enable hold time before status data polling Duration auto erase operation Duration auto program operation set-up time chip enable Write pulse width (optional write) Write enable set-up time (optional write) Write enable hold time (optional write) Address set-up time (optional write) Address hold time (optional write) Data set-up time (optional write) Data hold time (optional write) Limits
M5M28F101A-85 M5M28F101A-10
Unit
tVPEH
12.5
12.5
Note Read timing parameters during read/write mode same during read-only mode. must applied simultaneously before removed simultaneously after VPP.
WAVEFORMS READ OPERATIONS
TEST CONDITIONS CHARACTERISTICS Input voltage 0.45V, 2.4V Input rise fall times 10ns Reference voltage timing measurement 1.5V Output load 1TTL gate 100pF)
1.3V 1N914
ADDREVIL SSES DATA 5.0V HIGH-Z tWRR
ADDRESS VALID
(CE)
(OE) tOLZ tCLZ (AD)
HIGH-Z
3.3k
OUTPUT VALID
100pF
(970407)
MITSUBISHI LSIs
M5M28F101AFP,J,VP,RV-85,-10
1048576-BIT (131072-WORD 8-BIT) CMOS FLASH MEMORY
WAVEFORMS PROGRAM OPERATIONS
PROGRAM PROGRAM VERIFY
ADDRESSES DATA 5.0V 0.0V OPTIONAL WRITE tOWP VPPH VPPL tOWS tVSC tOAS tOWH tOAH
COMMAND
tRRW
tWPH
tWRR (OE)
COMMAND
(CE)
DATA
DATA VERIFIED
tODH tODS
WAVEFORMS ERASE OPERATIONS
ERASE ERASE VERIFY
ADDRESSES DATA 5.0V 0.0V VPPH VPPL tVSC
COMMAND
tRRW
tWPH
tWRR (OE)
COMMAND
(CE)
COMMAND
DATA VERIFIED
(970407)
MITSUBISHI LSIs
M5M28F101AFP,J,VP,RV-85,-10
1048576-BIT (131072-WORD 8-BIT) CMOS FLASH MEMORY
WAVEFORMS AUTO PROGRAM OPERATION
PROGRAM DATA POLLING
ADDRESSES DATA 5.0V 0.0V VPPH VPPL tVSC tRRW tWPH
ADDRESS VALID
ADDRESS VALID
ADDRESS VALID
(AD)
tOEH
(CE)
(OE) tDAP
DATA
OUTPUT
COMMAND
OUTPUT
WAVEFORMS AUTO CHIP ERASE OPERATION
ERASE STATUS POLLING
ADDRESSES
tWPH tOEH tDAEC
COMMAND
(CE)
tRRW
(OE)
COMMAND
D7OUTPUT
DATA
/(FFH)
D7OUTPUT (D0~D7)OUTPUT
5.0V 0.0V tVSC
VPPH VPPL
(970407)
MITSUBISHI LSIs
M5M28F101AFP,J,VP,RV-85,-10
1048576-BIT (131072-WORD 8-BIT) CMOS FLASH MEMORY
PROGRAMMING ERASE ALGORITHM FLOW CHART
PROGRAM
START VPPH ADDR FIRST LOCATION WRITE PROGRAM COMMAND WRITE PROGRAM DATA DURATION 10µs X=X+1 WRITE ERASE COMMAND WRITE PROGRAMVERIFY COMMAND DURATION WRITE ERASE COMMAND DURATION 9.5ms X=X+1 WRITE ERASE-VERIFY COMMAND DURATION FAIL VERIFY BYTE? PASS PASS VERIFY BYTE? FAIL 1000? BYTES 00H? PROGRAM BYTES ADDR FIRST LOCATION INPUT DATA
ERASE
START VPPH INPUT DATA
ADDR LAST ADDR? FAIL VERIFY BYTE? PASS PASS VERIFY BYTE? FAIL
WRITE READ COMMAND VPPL ADDR DEVICE PASSED DEVICE FAILED
LAST ADDR?
WRITE READ COMMAND VPPL DEVICE PASSED (Erase Complete) DEVICE FAILED
(970407)
MITSUBISHI LSIs
M5M28F101AFP,J,VP,RV-85,-10
1048576-BIT (131072-WORD 8-BIT) CMOS FLASH MEMORY
AUTO PROGRAM AUTO ERASE OPERATION AUTO PROGRAM
START 5.0V, VPPH WRITE AUTO PROGRAM SETUP COMMAND WRITE AUTO PROGRAM ADDRESS DATA DATA POLLING INPUT DATA
AUTO ERASE
START 5.0V, VPPH WRITE AUTOERASE SETUP COMMAND WRITE AUTOERASE COMMAND STATUS POLLING ERASURE COMPLETE INPUT DATA
INCREMENT ADDR
LAST ADDR? PROGRAMMING COMPLETE
(970407)

M5M28F101AFP,J,VP,RV-85,-10 M5M28F101AFP,J,VP,RV-85,-10 1048576-B

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