Features Phase-locked loop (PLL) device synthesizes output clock

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Features Phase-locked loop (PLL) device synthesizes output clock

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FS6128-04/FS6128-04g Clock Generator With VCXO
Features
Phase-locked loop (PLL) device synthesizes output clock frequency from crystal oscillator external reference clock On-chip tunable voltage-controlled crystal oscillator (VCXO) allows precise system frequency tuning Typically used generation MPEG-2 decoder clock 3.3V supply voltage
Very phase noise with "pullable" 14pF crystals external padding capacitors required Small circuit board footprint (8-pin 0.150" SOIC) Custom frequency selections available contact your local AMIS Sales Representative more information
Description
FS6128 monolithic CMOS clock generator designed minimize cost component count digital video/audio systems. core FS6128 circuitry that implements voltage-controlled crystal oscillator (VCXO) when external resonator (nominally 13.5MHz) attached. VCXO allows device frequencies precisely adjusted systems that have frequency matching requirements, such digital satellite receivers. high-resolution phase-locked loop generates output clock (CLK) through post-divider. frequency ratiometrically derived from VCXO frequency. locking frequency other system reference frequencies eliminate unpredictable artifacts video systems reduce electromagnetic interference (EMI) frequency harmonic stacking.
Table Crystal Output Frequencies Device FS6128-04 fXIN (MHz) 13.500 (MHz) 27.000
Note: Contact AMIS custom frequencies.
Figure Configuration
Figure Block Diagram
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FS6128-04/FS6128-04g Clock Generator With VCXO
Table Descriptions Type Name XTUNE XOUT Description VCXO Feedback Power Supply (+3.3V) VCXO Tune Ground Clock Output Connection Ground VCXO Drive
Key: Analog Input; Analog Output; Digital Input; Input With Internal PullUp; Input With Internal Pull-Down; Digital Input/Output; DI-3 Three-Level Digital Input, Digital Output; Power/Ground; Active
Functional Block Diagram
Voltage-Controlled Crystal Oscillator (VCXO)
VCXO provides tunable, low-jitter frequency reference rest FS6128 system components. Loading capacitance crystal internal FS6128. external components (other than resonator itself) required operation VCXO. Continuous fine-tuning VCXO frequency accomplished varying voltage XTUNE pin. value this voltage controls effective capacitance presented crystal. actual amount that this load capacitance change will alter oscillator frequency depends characteristics crystal well oscillator circuit itself. important that crystal load capacitance specified correctly "center" tuning range. Table simple formula obtain "pulling" capability crystal oscillator
EXAMPLE: crystal with following parameters used: 0.025pF 6pF. Using minimum maximum 10pF, 20pF, tuning range (peak-to-peak)
Phase-Locked Loop (PLL)
on-chip standard frequency- phaselocked loop architecture. multiplies reference oscillator frequency desired output frequency ratio integers. frequency multiplication exact with zero synthesis error (unless otherwise specified).
where: shunt holder) capacitance crystal motional capacitance crystal extremes (minimum maximum) applied load capacitance presented FS6128.
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FS6128-04/FS6128-04g Clock Generator With VCXO
Electrical Specifications
Table Absolute Maximum Ratings Parameter Supply Voltage (VSS ground) Input Voltage, Output Voltage, Input Clamp Current, VDD) Output Clamp Current, VDD) Storage Temperature Range (non-condensing) Ambient Temperature Range, Under Bias Junction Temperature Reflow Solder Profile Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7) Symbol VSS-0.5 VSS-0.5 VSS-0.5
VDD+0.5 VDD+0.5
Units IPC/JEDEC J-STD-020B
Note: Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. These conditions represent stress rating only functional operation device these other conditions above operational limits noted this specification implied. Exposure maximum rating conditions extended conditions affect device performance, functionality reliability.
Table Operating Conditions Parameter Supply Voltage Ambient Operating Temperature Range Crystal Resonator Frequency Table Electrical Specifications Symbol fXTAL
CAUTION: ELECTROSTATIC SENSITIVE DEVICE Permanent damage resulting loss functionality performance occur this device subjected highenergy electrostatic discharge.
Conditions/Descriptions 3.3V Fundamental Mode
Typ. 13.5
Units
Parameter Symbol Conditions/Descriptions Typ. Overall Supply Current, Dynamic, With Loaded Outputs fXTAL 13.5MHz; 10pF, 3.6V Supply Current, Static 3.6V Voltage-Controlled Crystal Oscillator (contact factory approved crystal sources other application assistance) Crystal Loading Capacitance Center Order crystal this capacitance (parallel CL(xtal) Tuning Voltage load) desired center frequency Specified motional capacitance Crystal Resonator Motional Capacitance crystal will affect pullability (see text) XTUNE Effective Range Synthesized Load Capacitance Min. @V(XTUNE)=minimum value Synthesized Load Capacitance Max. @V(XTUNE)=maximum value fXTAL 13.5MHz; CL(xtal) 14pF; VCXO Tuning Range C1(xtal) 25fF (peak-to-peak) Note: positive change XTUNE VCXO Tuning Characteristic positive change VCXO frequency Crystal Drive Level RXTAL=20; 20pF Clock Output (CLK) High-Level Output Source Current 2.0V Low-Level Output Sink Current 0.4V 0.1VDD; output driving high Output Impedance 0.1VDD; output driving Short Circuit Source Current IOSH shorted 30s, Short Circuit Sink Current IOSL 3.3V; shorted 30s,
Units
ppm/V
Note: Unless otherwise stated 3.3V ±10% load output ambient temperature range 70°C. Parameters denoted with asterisk represent nominal characterization data
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production tested specific limits. Where given, characterization data from typical. Negative currents indicate current flows device.
FS6128-04/FS6128-04g Clock Generator With VCXO
Table Timing Specifications
Parameter Overall Symbol Conditions/Descriptions Typ.
Units
VCXO Stabilization Time Stabilization Time Synthesis Error Clock Output (CLK) Duty Cycle Jitter, Period (peak-peak) Jitter, Long Term (y() Rise Time Fall Time
tVCXOSTB tPLLSTB
From power valid From VCXO stable (Unless otherwise noted frequency table) Ratio high pulse width measured from rising edge next falling edge VDD/2) clock period From rising edge next rising edge VDD/2, =10pF From 0-500µs VDD/2, 10pF compared ideal clock source 3.3V; 0.3V 3.0V; 10pF 3.3V; 3.0V 0.3V; 10pF
tj(P) tj(LT)
Note: Unless otherwise stated, 3.3V ±10%, load output, ambient temperature range 70°C. Parameters denoted with asterisk represent nominal
characterization data production tested specific limits. Where given, characterization data from typical.
Package Information Both `Green' `Non-Green'
Table 8-pin SOIC (0.150") Package Dimensions
Table 8-pin SOIC (0.150") Package Characteristics
Parameter Symbol Conditions/Descriptions Typ. Units
Thermal Impedance, Junction Free-Air 8-pin 0.150" SOIC Lead Inductance, Self Lead Inductance, Mutual Lead Capacitance, Bulk
flow Corner lead Center lead lead adjacent lead lead
0.27
°C/W
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FS6128-04/FS6128-04g Clock Generator With VCXO
Ordering Information
Table Device Ordering Codes Operating Temperature Range 70°C (Commercial) 70°C (Commercial)
Ordering Code 11640-825 11640-892
Device Number FS6128-04 FS6128-04g
Package Type 8-pin (0.150") SOIC (Small Outline Package) 8-pin (0.150") SOIC (Small Outline Package) `Green'or Lead-Free Packaging
Shipping Configuration Tape Reel Tape Reel
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Features Phase-locked loop (PLL) device synthesizes output clock

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