Master fully compliant Philips specification. design fully synchronous

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Master fully compliant Philips specification. design fully synchronous

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IPIC-100A
Master fully compliant Philips specification. design fully synchronous. supports standard clock rates 100kHz 400kHz which derived from reference supplied externally. I.e. clock rate independant clock easily changed changing reference clock. core been optimized minimum resource requirements does support multimaster target operation Core delivered full source code including testbench, documentation programming examples. host interface simple 8bit which uses separate read/write data busses does internal tristate buffers.
Din(7:0) Dout(7:0) a(3:0) write strobe
SDA_out SDA_in
Controller
clk_8M
Example ressource requirements Device Resources Xilinx Spartan2 (xc2s15) Slices Altera ACEX (EP1k10) Logic Elements QuickLogic 4036) Logic Cells
Used Comments
Flip-Flops Slice
Flip-Flop Logic Element Flip-Flop Logic Cell
IPIC-100A
description:
Signal Din(7:0) Dout(7:0) A(3:0) write strobe SDA_out SDA_in clk_8M
Direction
Description Asynchronous reset input Main Clock Input inputs except sync'ed this clock Write data input Read data output Chip select Register address inputs Write strobe: high writes, reads Interrupt Strobe: indicates valid cycle Transfer acknowledge Serial data output Serial data input Serial clockt Reference clock (8MHz)
Data input output combined bidiretional signal cell target device.
Ordering Information Description
Master
Order
1800-IPIC-0100A-000000

Master fully compliant Philips specification. design fully synchronous

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